/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf -i ../../../trunk/examples/svcomp/loops-crafted-1/nested3-2.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 22:19:03,064 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 22:19:03,065 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 22:19:03,122 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-04-27 22:19:03,122 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-04-27 22:19:03,123 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-04-27 22:19:03,125 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-04-27 22:19:03,126 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-04-27 22:19:03,127 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-04-27 22:19:03,128 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-04-27 22:19:03,128 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-04-27 22:19:03,129 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-04-27 22:19:03,129 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-27 22:19:03,130 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-27 22:19:03,130 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-27 22:19:03,131 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-27 22:19:03,131 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-27 22:19:03,132 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-27 22:19:03,133 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-27 22:19:03,134 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-27 22:19:03,135 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-27 22:19:03,140 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-27 22:19:03,142 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-27 22:19:03,144 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-27 22:19:03,148 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-27 22:19:03,153 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-27 22:19:03,157 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 22:19:03,158 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 22:19:03,161 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 22:19:03,162 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf [2022-04-27 22:19:03,183 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 22:19:03,184 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 22:19:03,185 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-04-27 22:19:03,185 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-04-27 22:19:03,185 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-04-27 22:19:03,185 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-04-27 22:19:03,185 INFO L138 SettingsManager]: * Use SBE=true [2022-04-27 22:19:03,186 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 22:19:03,186 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 22:19:03,186 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 22:19:03,186 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 22:19:03,186 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 22:19:03,187 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 22:19:03,187 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 22:19:03,187 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 22:19:03,187 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 22:19:03,187 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 22:19:03,187 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 22:19:03,187 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 22:19:03,187 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 22:19:03,187 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 22:19:03,187 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-04-27 22:19:03,187 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-04-27 22:19:03,188 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 22:19:03,188 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-04-27 22:19:03,188 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-04-27 22:19:03,188 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-04-27 22:19:03,188 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-04-27 22:19:03,189 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 22:19:03,189 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_QVASR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 22:19:03,365 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 22:19:03,380 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 22:19:03,382 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 22:19:03,382 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 22:19:03,383 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 22:19:03,384 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops-crafted-1/nested3-2.c [2022-04-27 22:19:03,424 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/aa51910c9/abc098640a8744acb27f7a3d08844b9a/FLAGd514ee8bf [2022-04-27 22:19:03,774 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 22:19:03,775 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/nested3-2.c [2022-04-27 22:19:03,778 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/aa51910c9/abc098640a8744acb27f7a3d08844b9a/FLAGd514ee8bf [2022-04-27 22:19:04,213 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/aa51910c9/abc098640a8744acb27f7a3d08844b9a [2022-04-27 22:19:04,215 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 22:19:04,216 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 22:19:04,217 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 22:19:04,217 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 22:19:04,219 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 22:19:04,220 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 10:19:04" (1/1) ... [2022-04-27 22:19:04,221 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@49679fb5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 10:19:04, skipping insertion in model container [2022-04-27 22:19:04,221 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 10:19:04" (1/1) ... [2022-04-27 22:19:04,225 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 22:19:04,233 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 22:19:04,359 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/nested3-2.c[321,334] [2022-04-27 22:19:04,368 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 22:19:04,374 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 22:19:04,381 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/nested3-2.c[321,334] [2022-04-27 22:19:04,384 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 22:19:04,394 INFO L208 MainTranslator]: Completed translation [2022-04-27 22:19:04,394 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 10:19:04 WrapperNode [2022-04-27 22:19:04,394 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 22:19:04,395 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 22:19:04,395 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 22:19:04,395 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 22:19:04,402 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 10:19:04" (1/1) ... [2022-04-27 22:19:04,402 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 10:19:04" (1/1) ... [2022-04-27 22:19:04,406 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 10:19:04" (1/1) ... [2022-04-27 22:19:04,406 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 10:19:04" (1/1) ... [2022-04-27 22:19:04,409 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 10:19:04" (1/1) ... [2022-04-27 22:19:04,414 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 10:19:04" (1/1) ... [2022-04-27 22:19:04,414 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 10:19:04" (1/1) ... [2022-04-27 22:19:04,415 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 22:19:04,416 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 22:19:04,416 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 22:19:04,416 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 22:19:04,421 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 10:19:04" (1/1) ... [2022-04-27 22:19:04,430 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 22:19:04,436 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 22:19:04,448 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 22:19:04,477 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 22:19:04,478 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 22:19:04,478 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 22:19:04,478 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 22:19:04,478 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 22:19:04,479 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 22:19:04,479 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 22:19:04,479 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 22:19:04,479 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 22:19:04,480 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 22:19:04,480 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 22:19:04,480 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 22:19:04,480 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 22:19:04,480 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 22:19:04,480 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 22:19:04,480 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 22:19:04,480 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 22:19:04,467 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 22:19:04,529 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 22:19:04,530 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 22:19:04,642 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 22:19:04,647 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 22:19:04,647 INFO L299 CfgBuilder]: Removed 3 assume(true) statements. [2022-04-27 22:19:04,648 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 10:19:04 BoogieIcfgContainer [2022-04-27 22:19:04,648 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 22:19:04,649 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 22:19:04,649 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 22:19:04,649 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 22:19:04,651 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 10:19:04" (1/1) ... [2022-04-27 22:19:04,652 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_QVASR [2022-04-27 22:19:04,667 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 10:19:04 BasicIcfg [2022-04-27 22:19:04,668 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 22:19:04,669 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 22:19:04,669 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 22:19:04,685 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 22:19:04,685 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 10:19:04" (1/4) ... [2022-04-27 22:19:04,686 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7962c17a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 10:19:04, skipping insertion in model container [2022-04-27 22:19:04,686 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 10:19:04" (2/4) ... [2022-04-27 22:19:04,686 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7962c17a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 10:19:04, skipping insertion in model container [2022-04-27 22:19:04,686 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 10:19:04" (3/4) ... [2022-04-27 22:19:04,686 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7962c17a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 10:19:04, skipping insertion in model container [2022-04-27 22:19:04,687 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 10:19:04" (4/4) ... [2022-04-27 22:19:04,687 INFO L111 eAbstractionObserver]: Analyzing ICFG nested3-2.cqvasr [2022-04-27 22:19:04,696 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-04-27 22:19:04,697 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 22:19:04,747 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 22:19:04,751 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@10a6781f, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@3c0312d4 [2022-04-27 22:19:04,752 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 22:19:04,757 INFO L276 IsEmpty]: Start isEmpty. Operand has 25 states, 15 states have (on average 1.5333333333333334) internal successors, (23), 16 states have internal predecessors, (23), 5 states have call successors, (5), 3 states have call predecessors, (5), 3 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 22:19:04,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-04-27 22:19:04,763 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 22:19:04,763 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 22:19:04,763 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 22:19:04,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 22:19:04,772 INFO L85 PathProgramCache]: Analyzing trace with hash 1301415802, now seen corresponding path program 1 times [2022-04-27 22:19:04,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 22:19:04,778 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438496253] [2022-04-27 22:19:04,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 22:19:04,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 22:19:04,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:04,948 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 22:19:04,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:04,967 INFO L290 TraceCheckUtils]: 0: Hoare triple {33#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {28#true} is VALID [2022-04-27 22:19:04,968 INFO L290 TraceCheckUtils]: 1: Hoare triple {28#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-27 22:19:04,968 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {28#true} {28#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-27 22:19:04,972 INFO L272 TraceCheckUtils]: 0: Hoare triple {28#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {33#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 22:19:04,973 INFO L290 TraceCheckUtils]: 1: Hoare triple {33#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {28#true} is VALID [2022-04-27 22:19:04,973 INFO L290 TraceCheckUtils]: 2: Hoare triple {28#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-27 22:19:04,973 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {28#true} {28#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-27 22:19:04,974 INFO L272 TraceCheckUtils]: 4: Hoare triple {28#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-27 22:19:04,974 INFO L290 TraceCheckUtils]: 5: Hoare triple {28#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {28#true} is VALID [2022-04-27 22:19:04,976 INFO L290 TraceCheckUtils]: 6: Hoare triple {28#true} [78] L19-2-->L19-3: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-27 22:19:04,976 INFO L272 TraceCheckUtils]: 7: Hoare triple {29#false} [81] L19-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_7 2) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_3|) InVars {main_~x~0=v_main_~x~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_3|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {29#false} is VALID [2022-04-27 22:19:04,977 INFO L290 TraceCheckUtils]: 8: Hoare triple {29#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {29#false} is VALID [2022-04-27 22:19:04,977 INFO L290 TraceCheckUtils]: 9: Hoare triple {29#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-27 22:19:04,978 INFO L290 TraceCheckUtils]: 10: Hoare triple {29#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-27 22:19:04,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:04,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 22:19:04,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [438496253] [2022-04-27 22:19:04,979 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [438496253] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 22:19:04,979 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 22:19:04,979 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 22:19:04,980 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101651633] [2022-04-27 22:19:04,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 22:19:04,984 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-27 22:19:04,986 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 22:19:04,988 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,003 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 11 edges. 11 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:05,004 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 22:19:05,004 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 22:19:05,031 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 22:19:05,032 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 22:19:05,035 INFO L87 Difference]: Start difference. First operand has 25 states, 15 states have (on average 1.5333333333333334) internal successors, (23), 16 states have internal predecessors, (23), 5 states have call successors, (5), 3 states have call predecessors, (5), 3 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:05,135 INFO L93 Difference]: Finished difference Result 44 states and 63 transitions. [2022-04-27 22:19:05,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 22:19:05,135 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-27 22:19:05,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 22:19:05,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 63 transitions. [2022-04-27 22:19:05,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 63 transitions. [2022-04-27 22:19:05,172 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 63 transitions. [2022-04-27 22:19:05,251 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 63 edges. 63 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:05,260 INFO L225 Difference]: With dead ends: 44 [2022-04-27 22:19:05,261 INFO L226 Difference]: Without dead ends: 20 [2022-04-27 22:19:05,263 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 22:19:05,267 INFO L413 NwaCegarLoop]: 26 mSDtfsCounter, 16 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 5 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 19 SdHoareTripleChecker+Valid, 29 SdHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 5 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 22:19:05,270 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [19 Valid, 29 Invalid, 9 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 5 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 22:19:05,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2022-04-27 22:19:05,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2022-04-27 22:19:05,289 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 22:19:05,290 INFO L82 GeneralOperation]: Start isEquivalent. First operand 20 states. Second operand has 20 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 13 states have internal predecessors, (16), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,290 INFO L74 IsIncluded]: Start isIncluded. First operand 20 states. Second operand has 20 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 13 states have internal predecessors, (16), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,291 INFO L87 Difference]: Start difference. First operand 20 states. Second operand has 20 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 13 states have internal predecessors, (16), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:05,299 INFO L93 Difference]: Finished difference Result 20 states and 24 transitions. [2022-04-27 22:19:05,299 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2022-04-27 22:19:05,299 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:05,299 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:05,300 INFO L74 IsIncluded]: Start isIncluded. First operand has 20 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 13 states have internal predecessors, (16), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 20 states. [2022-04-27 22:19:05,300 INFO L87 Difference]: Start difference. First operand has 20 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 13 states have internal predecessors, (16), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 20 states. [2022-04-27 22:19:05,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:05,304 INFO L93 Difference]: Finished difference Result 20 states and 24 transitions. [2022-04-27 22:19:05,304 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2022-04-27 22:19:05,304 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:05,304 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:05,304 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 22:19:05,304 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 22:19:05,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 13 states have internal predecessors, (16), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2022-04-27 22:19:05,308 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 11 [2022-04-27 22:19:05,309 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 22:19:05,309 INFO L495 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2022-04-27 22:19:05,310 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,313 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2022-04-27 22:19:05,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-04-27 22:19:05,317 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 22:19:05,317 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 22:19:05,317 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 22:19:05,317 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 22:19:05,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 22:19:05,318 INFO L85 PathProgramCache]: Analyzing trace with hash 1302339323, now seen corresponding path program 1 times [2022-04-27 22:19:05,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 22:19:05,318 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23251359] [2022-04-27 22:19:05,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 22:19:05,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 22:19:05,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:05,394 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 22:19:05,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:05,407 INFO L290 TraceCheckUtils]: 0: Hoare triple {175#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {169#true} is VALID [2022-04-27 22:19:05,407 INFO L290 TraceCheckUtils]: 1: Hoare triple {169#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 22:19:05,407 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {169#true} {169#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 22:19:05,409 INFO L272 TraceCheckUtils]: 0: Hoare triple {169#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {175#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 22:19:05,409 INFO L290 TraceCheckUtils]: 1: Hoare triple {175#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {169#true} is VALID [2022-04-27 22:19:05,409 INFO L290 TraceCheckUtils]: 2: Hoare triple {169#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 22:19:05,409 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {169#true} {169#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 22:19:05,409 INFO L272 TraceCheckUtils]: 4: Hoare triple {169#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 22:19:05,410 INFO L290 TraceCheckUtils]: 5: Hoare triple {169#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {174#(= main_~x~0 0)} is VALID [2022-04-27 22:19:05,410 INFO L290 TraceCheckUtils]: 6: Hoare triple {174#(= main_~x~0 0)} [79] L19-2-->L19-3: Formula: (not (< (mod v_main_~x~0_4 4294967296) 268435455)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4} AuxVars[] AssignedVars[] {170#false} is VALID [2022-04-27 22:19:05,410 INFO L272 TraceCheckUtils]: 7: Hoare triple {170#false} [81] L19-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_7 2) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_3|) InVars {main_~x~0=v_main_~x~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_3|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {170#false} is VALID [2022-04-27 22:19:05,410 INFO L290 TraceCheckUtils]: 8: Hoare triple {170#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {170#false} is VALID [2022-04-27 22:19:05,411 INFO L290 TraceCheckUtils]: 9: Hoare triple {170#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {170#false} is VALID [2022-04-27 22:19:05,411 INFO L290 TraceCheckUtils]: 10: Hoare triple {170#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {170#false} is VALID [2022-04-27 22:19:05,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:05,411 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 22:19:05,411 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23251359] [2022-04-27 22:19:05,411 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23251359] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 22:19:05,411 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 22:19:05,411 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-27 22:19:05,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2784344] [2022-04-27 22:19:05,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 22:19:05,412 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-27 22:19:05,413 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 22:19:05,413 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,422 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 11 edges. 11 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:05,422 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-27 22:19:05,422 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 22:19:05,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-27 22:19:05,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-27 22:19:05,423 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:05,525 INFO L93 Difference]: Finished difference Result 34 states and 42 transitions. [2022-04-27 22:19:05,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-27 22:19:05,525 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-27 22:19:05,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 22:19:05,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 42 transitions. [2022-04-27 22:19:05,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 42 transitions. [2022-04-27 22:19:05,533 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 42 transitions. [2022-04-27 22:19:05,563 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 42 edges. 42 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:05,566 INFO L225 Difference]: With dead ends: 34 [2022-04-27 22:19:05,566 INFO L226 Difference]: Without dead ends: 27 [2022-04-27 22:19:05,568 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-27 22:19:05,569 INFO L413 NwaCegarLoop]: 21 mSDtfsCounter, 25 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 25 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 28 SdHoareTripleChecker+Invalid, 36 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 25 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 22:19:05,570 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 28 Invalid, 36 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 25 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 22:19:05,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2022-04-27 22:19:05,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 21. [2022-04-27 22:19:05,575 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 22:19:05,576 INFO L82 GeneralOperation]: Start isEquivalent. First operand 27 states. Second operand has 21 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,577 INFO L74 IsIncluded]: Start isIncluded. First operand 27 states. Second operand has 21 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,577 INFO L87 Difference]: Start difference. First operand 27 states. Second operand has 21 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:05,581 INFO L93 Difference]: Finished difference Result 27 states and 35 transitions. [2022-04-27 22:19:05,581 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 35 transitions. [2022-04-27 22:19:05,582 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:05,582 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:05,582 INFO L74 IsIncluded]: Start isIncluded. First operand has 21 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 27 states. [2022-04-27 22:19:05,583 INFO L87 Difference]: Start difference. First operand has 21 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 27 states. [2022-04-27 22:19:05,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:05,585 INFO L93 Difference]: Finished difference Result 27 states and 35 transitions. [2022-04-27 22:19:05,585 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 35 transitions. [2022-04-27 22:19:05,585 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:05,585 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:05,585 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 22:19:05,585 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 22:19:05,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2022-04-27 22:19:05,589 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 11 [2022-04-27 22:19:05,589 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 22:19:05,589 INFO L495 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2022-04-27 22:19:05,589 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,589 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2022-04-27 22:19:05,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-04-27 22:19:05,591 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 22:19:05,591 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 22:19:05,591 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 22:19:05,591 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 22:19:05,592 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 22:19:05,592 INFO L85 PathProgramCache]: Analyzing trace with hash 1748313539, now seen corresponding path program 1 times [2022-04-27 22:19:05,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 22:19:05,593 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432849449] [2022-04-27 22:19:05,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 22:19:05,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 22:19:05,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:05,640 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 22:19:05,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:05,647 INFO L290 TraceCheckUtils]: 0: Hoare triple {325#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {319#true} is VALID [2022-04-27 22:19:05,647 INFO L290 TraceCheckUtils]: 1: Hoare triple {319#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {319#true} is VALID [2022-04-27 22:19:05,647 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {319#true} {319#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {319#true} is VALID [2022-04-27 22:19:05,649 INFO L272 TraceCheckUtils]: 0: Hoare triple {319#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {325#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 22:19:05,649 INFO L290 TraceCheckUtils]: 1: Hoare triple {325#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {319#true} is VALID [2022-04-27 22:19:05,649 INFO L290 TraceCheckUtils]: 2: Hoare triple {319#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {319#true} is VALID [2022-04-27 22:19:05,649 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {319#true} {319#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {319#true} is VALID [2022-04-27 22:19:05,649 INFO L272 TraceCheckUtils]: 4: Hoare triple {319#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {319#true} is VALID [2022-04-27 22:19:05,649 INFO L290 TraceCheckUtils]: 5: Hoare triple {319#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {319#true} is VALID [2022-04-27 22:19:05,650 INFO L290 TraceCheckUtils]: 6: Hoare triple {319#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {324#(= main_~y~0 0)} is VALID [2022-04-27 22:19:05,650 INFO L290 TraceCheckUtils]: 7: Hoare triple {324#(= main_~y~0 0)} [83] L22-2-->L22-3: Formula: (not (< (mod v_main_~y~0_6 4294967296) 268435455)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6} AuxVars[] AssignedVars[] {320#false} is VALID [2022-04-27 22:19:05,650 INFO L272 TraceCheckUtils]: 8: Hoare triple {320#false} [87] L22-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_2| (ite (= (mod v_main_~y~0_8 2) 0) 1 0)) InVars {main_~y~0=v_main_~y~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_2|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {320#false} is VALID [2022-04-27 22:19:05,651 INFO L290 TraceCheckUtils]: 9: Hoare triple {320#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {320#false} is VALID [2022-04-27 22:19:05,651 INFO L290 TraceCheckUtils]: 10: Hoare triple {320#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {320#false} is VALID [2022-04-27 22:19:05,651 INFO L290 TraceCheckUtils]: 11: Hoare triple {320#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {320#false} is VALID [2022-04-27 22:19:05,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:05,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 22:19:05,652 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432849449] [2022-04-27 22:19:05,652 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [432849449] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 22:19:05,652 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 22:19:05,652 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-27 22:19:05,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [944651601] [2022-04-27 22:19:05,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 22:19:05,652 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 12 [2022-04-27 22:19:05,653 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 22:19:05,653 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,660 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 12 edges. 12 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:05,660 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-27 22:19:05,660 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 22:19:05,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-27 22:19:05,661 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-27 22:19:05,661 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:05,739 INFO L93 Difference]: Finished difference Result 39 states and 50 transitions. [2022-04-27 22:19:05,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-27 22:19:05,739 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 12 [2022-04-27 22:19:05,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 22:19:05,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 50 transitions. [2022-04-27 22:19:05,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 50 transitions. [2022-04-27 22:19:05,742 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 50 transitions. [2022-04-27 22:19:05,784 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 50 edges. 50 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:05,785 INFO L225 Difference]: With dead ends: 39 [2022-04-27 22:19:05,785 INFO L226 Difference]: Without dead ends: 25 [2022-04-27 22:19:05,785 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-27 22:19:05,786 INFO L413 NwaCegarLoop]: 20 mSDtfsCounter, 21 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 23 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 23 SdHoareTripleChecker+Valid, 27 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 23 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 22:19:05,786 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [23 Valid, 27 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 23 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 22:19:05,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2022-04-27 22:19:05,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 22. [2022-04-27 22:19:05,789 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 22:19:05,789 INFO L82 GeneralOperation]: Start isEquivalent. First operand 25 states. Second operand has 22 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,790 INFO L74 IsIncluded]: Start isIncluded. First operand 25 states. Second operand has 22 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,790 INFO L87 Difference]: Start difference. First operand 25 states. Second operand has 22 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:05,791 INFO L93 Difference]: Finished difference Result 25 states and 31 transitions. [2022-04-27 22:19:05,791 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 31 transitions. [2022-04-27 22:19:05,792 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:05,792 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:05,792 INFO L74 IsIncluded]: Start isIncluded. First operand has 22 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 25 states. [2022-04-27 22:19:05,792 INFO L87 Difference]: Start difference. First operand has 22 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 25 states. [2022-04-27 22:19:05,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:05,793 INFO L93 Difference]: Finished difference Result 25 states and 31 transitions. [2022-04-27 22:19:05,793 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 31 transitions. [2022-04-27 22:19:05,794 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:05,794 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:05,794 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 22:19:05,794 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 22:19:05,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2022-04-27 22:19:05,795 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 12 [2022-04-27 22:19:05,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 22:19:05,796 INFO L495 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2022-04-27 22:19:05,796 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,796 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2022-04-27 22:19:05,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2022-04-27 22:19:05,796 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 22:19:05,796 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 22:19:05,796 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-04-27 22:19:05,797 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 22:19:05,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 22:19:05,797 INFO L85 PathProgramCache]: Analyzing trace with hash -1606116621, now seen corresponding path program 1 times [2022-04-27 22:19:05,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 22:19:05,797 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [100290519] [2022-04-27 22:19:05,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 22:19:05,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 22:19:05,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:05,852 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 22:19:05,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:05,863 INFO L290 TraceCheckUtils]: 0: Hoare triple {483#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {477#true} is VALID [2022-04-27 22:19:05,863 INFO L290 TraceCheckUtils]: 1: Hoare triple {477#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {477#true} is VALID [2022-04-27 22:19:05,863 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {477#true} {477#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {477#true} is VALID [2022-04-27 22:19:05,865 INFO L272 TraceCheckUtils]: 0: Hoare triple {477#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {483#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 22:19:05,865 INFO L290 TraceCheckUtils]: 1: Hoare triple {483#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {477#true} is VALID [2022-04-27 22:19:05,865 INFO L290 TraceCheckUtils]: 2: Hoare triple {477#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {477#true} is VALID [2022-04-27 22:19:05,865 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {477#true} {477#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {477#true} is VALID [2022-04-27 22:19:05,866 INFO L272 TraceCheckUtils]: 4: Hoare triple {477#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {477#true} is VALID [2022-04-27 22:19:05,866 INFO L290 TraceCheckUtils]: 5: Hoare triple {477#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {477#true} is VALID [2022-04-27 22:19:05,866 INFO L290 TraceCheckUtils]: 6: Hoare triple {477#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {477#true} is VALID [2022-04-27 22:19:05,869 INFO L290 TraceCheckUtils]: 7: Hoare triple {477#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {482#(= main_~z~0 0)} is VALID [2022-04-27 22:19:05,870 INFO L290 TraceCheckUtils]: 8: Hoare triple {482#(= main_~z~0 0)} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {478#false} is VALID [2022-04-27 22:19:05,870 INFO L272 TraceCheckUtils]: 9: Hoare triple {478#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {478#false} is VALID [2022-04-27 22:19:05,870 INFO L290 TraceCheckUtils]: 10: Hoare triple {478#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {478#false} is VALID [2022-04-27 22:19:05,870 INFO L290 TraceCheckUtils]: 11: Hoare triple {478#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {478#false} is VALID [2022-04-27 22:19:05,871 INFO L290 TraceCheckUtils]: 12: Hoare triple {478#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {478#false} is VALID [2022-04-27 22:19:05,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:05,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 22:19:05,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [100290519] [2022-04-27 22:19:05,871 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [100290519] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 22:19:05,871 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 22:19:05,871 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-27 22:19:05,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [907837073] [2022-04-27 22:19:05,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 22:19:05,872 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.25) internal successors, (9), 3 states have internal predecessors, (9), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 13 [2022-04-27 22:19:05,872 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 22:19:05,872 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 2.25) internal successors, (9), 3 states have internal predecessors, (9), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,882 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 13 edges. 13 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:05,883 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-27 22:19:05,883 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 22:19:05,883 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-27 22:19:05,883 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-27 22:19:05,884 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand has 4 states, 4 states have (on average 2.25) internal successors, (9), 3 states have internal predecessors, (9), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:05,962 INFO L93 Difference]: Finished difference Result 39 states and 48 transitions. [2022-04-27 22:19:05,962 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-27 22:19:05,962 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.25) internal successors, (9), 3 states have internal predecessors, (9), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 13 [2022-04-27 22:19:05,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 22:19:05,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.25) internal successors, (9), 3 states have internal predecessors, (9), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 46 transitions. [2022-04-27 22:19:05,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.25) internal successors, (9), 3 states have internal predecessors, (9), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:05,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 46 transitions. [2022-04-27 22:19:05,964 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 46 transitions. [2022-04-27 22:19:05,994 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 46 edges. 46 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:05,995 INFO L225 Difference]: With dead ends: 39 [2022-04-27 22:19:05,995 INFO L226 Difference]: Without dead ends: 24 [2022-04-27 22:19:05,995 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-27 22:19:05,996 INFO L413 NwaCegarLoop]: 21 mSDtfsCounter, 17 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 19 SdHoareTripleChecker+Valid, 28 SdHoareTripleChecker+Invalid, 27 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 22:19:05,996 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [19 Valid, 28 Invalid, 27 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 22:19:05,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2022-04-27 22:19:05,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 23. [2022-04-27 22:19:05,999 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 22:19:05,999 INFO L82 GeneralOperation]: Start isEquivalent. First operand 24 states. Second operand has 23 states, 15 states have (on average 1.2666666666666666) internal successors, (19), 16 states have internal predecessors, (19), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:05,999 INFO L74 IsIncluded]: Start isIncluded. First operand 24 states. Second operand has 23 states, 15 states have (on average 1.2666666666666666) internal successors, (19), 16 states have internal predecessors, (19), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:06,000 INFO L87 Difference]: Start difference. First operand 24 states. Second operand has 23 states, 15 states have (on average 1.2666666666666666) internal successors, (19), 16 states have internal predecessors, (19), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:06,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:06,001 INFO L93 Difference]: Finished difference Result 24 states and 28 transitions. [2022-04-27 22:19:06,001 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 28 transitions. [2022-04-27 22:19:06,001 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:06,001 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:06,001 INFO L74 IsIncluded]: Start isIncluded. First operand has 23 states, 15 states have (on average 1.2666666666666666) internal successors, (19), 16 states have internal predecessors, (19), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 24 states. [2022-04-27 22:19:06,001 INFO L87 Difference]: Start difference. First operand has 23 states, 15 states have (on average 1.2666666666666666) internal successors, (19), 16 states have internal predecessors, (19), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 24 states. [2022-04-27 22:19:06,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:06,002 INFO L93 Difference]: Finished difference Result 24 states and 28 transitions. [2022-04-27 22:19:06,002 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 28 transitions. [2022-04-27 22:19:06,003 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:06,003 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:06,003 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 22:19:06,003 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 22:19:06,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 15 states have (on average 1.2666666666666666) internal successors, (19), 16 states have internal predecessors, (19), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:06,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 27 transitions. [2022-04-27 22:19:06,004 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 27 transitions. Word has length 13 [2022-04-27 22:19:06,004 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 22:19:06,004 INFO L495 AbstractCegarLoop]: Abstraction has 23 states and 27 transitions. [2022-04-27 22:19:06,004 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.25) internal successors, (9), 3 states have internal predecessors, (9), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:06,004 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 27 transitions. [2022-04-27 22:19:06,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-04-27 22:19:06,004 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 22:19:06,004 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 22:19:06,005 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-04-27 22:19:06,005 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 22:19:06,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 22:19:06,005 INFO L85 PathProgramCache]: Analyzing trace with hash 1773342651, now seen corresponding path program 1 times [2022-04-27 22:19:06,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 22:19:06,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425008925] [2022-04-27 22:19:06,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 22:19:06,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 22:19:06,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:06,052 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 22:19:06,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:06,057 INFO L290 TraceCheckUtils]: 0: Hoare triple {643#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {636#true} is VALID [2022-04-27 22:19:06,057 INFO L290 TraceCheckUtils]: 1: Hoare triple {636#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,057 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {636#true} {636#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,058 INFO L272 TraceCheckUtils]: 0: Hoare triple {636#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 22:19:06,058 INFO L290 TraceCheckUtils]: 1: Hoare triple {643#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {636#true} is VALID [2022-04-27 22:19:06,058 INFO L290 TraceCheckUtils]: 2: Hoare triple {636#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,058 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {636#true} {636#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,058 INFO L272 TraceCheckUtils]: 4: Hoare triple {636#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,058 INFO L290 TraceCheckUtils]: 5: Hoare triple {636#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {636#true} is VALID [2022-04-27 22:19:06,059 INFO L290 TraceCheckUtils]: 6: Hoare triple {636#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {636#true} is VALID [2022-04-27 22:19:06,059 INFO L290 TraceCheckUtils]: 7: Hoare triple {636#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {641#(= main_~z~0 0)} is VALID [2022-04-27 22:19:06,059 INFO L290 TraceCheckUtils]: 8: Hoare triple {641#(= main_~z~0 0)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {642#(and (<= main_~z~0 1) (not (<= (+ (div main_~z~0 4294967296) 1) 0)))} is VALID [2022-04-27 22:19:06,060 INFO L290 TraceCheckUtils]: 9: Hoare triple {642#(and (<= main_~z~0 1) (not (<= (+ (div main_~z~0 4294967296) 1) 0)))} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {637#false} is VALID [2022-04-27 22:19:06,060 INFO L272 TraceCheckUtils]: 10: Hoare triple {637#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {637#false} is VALID [2022-04-27 22:19:06,060 INFO L290 TraceCheckUtils]: 11: Hoare triple {637#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {637#false} is VALID [2022-04-27 22:19:06,060 INFO L290 TraceCheckUtils]: 12: Hoare triple {637#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {637#false} is VALID [2022-04-27 22:19:06,060 INFO L290 TraceCheckUtils]: 13: Hoare triple {637#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {637#false} is VALID [2022-04-27 22:19:06,061 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:06,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 22:19:06,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425008925] [2022-04-27 22:19:06,061 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425008925] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 22:19:06,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [717065153] [2022-04-27 22:19:06,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 22:19:06,061 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 22:19:06,061 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 22:19:06,063 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 22:19:06,080 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 22:19:06,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:06,095 INFO L263 TraceCheckSpWp]: Trace formula consists of 66 conjuncts, 5 conjunts are in the unsatisfiable core [2022-04-27 22:19:06,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:06,103 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 22:19:06,167 INFO L272 TraceCheckUtils]: 0: Hoare triple {636#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,167 INFO L290 TraceCheckUtils]: 1: Hoare triple {636#true} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {636#true} is VALID [2022-04-27 22:19:06,168 INFO L290 TraceCheckUtils]: 2: Hoare triple {636#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,168 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {636#true} {636#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,168 INFO L272 TraceCheckUtils]: 4: Hoare triple {636#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,168 INFO L290 TraceCheckUtils]: 5: Hoare triple {636#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {636#true} is VALID [2022-04-27 22:19:06,168 INFO L290 TraceCheckUtils]: 6: Hoare triple {636#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {636#true} is VALID [2022-04-27 22:19:06,169 INFO L290 TraceCheckUtils]: 7: Hoare triple {636#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {641#(= main_~z~0 0)} is VALID [2022-04-27 22:19:06,169 INFO L290 TraceCheckUtils]: 8: Hoare triple {641#(= main_~z~0 0)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {671#(= main_~z~0 1)} is VALID [2022-04-27 22:19:06,169 INFO L290 TraceCheckUtils]: 9: Hoare triple {671#(= main_~z~0 1)} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {637#false} is VALID [2022-04-27 22:19:06,170 INFO L272 TraceCheckUtils]: 10: Hoare triple {637#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {637#false} is VALID [2022-04-27 22:19:06,170 INFO L290 TraceCheckUtils]: 11: Hoare triple {637#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {637#false} is VALID [2022-04-27 22:19:06,170 INFO L290 TraceCheckUtils]: 12: Hoare triple {637#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {637#false} is VALID [2022-04-27 22:19:06,170 INFO L290 TraceCheckUtils]: 13: Hoare triple {637#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {637#false} is VALID [2022-04-27 22:19:06,170 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:06,170 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 22:19:06,232 INFO L290 TraceCheckUtils]: 13: Hoare triple {637#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {637#false} is VALID [2022-04-27 22:19:06,232 INFO L290 TraceCheckUtils]: 12: Hoare triple {637#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {637#false} is VALID [2022-04-27 22:19:06,232 INFO L290 TraceCheckUtils]: 11: Hoare triple {637#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {637#false} is VALID [2022-04-27 22:19:06,233 INFO L272 TraceCheckUtils]: 10: Hoare triple {637#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {637#false} is VALID [2022-04-27 22:19:06,233 INFO L290 TraceCheckUtils]: 9: Hoare triple {699#(< (mod main_~z~0 4294967296) 268435455)} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {637#false} is VALID [2022-04-27 22:19:06,235 INFO L290 TraceCheckUtils]: 8: Hoare triple {703#(< (mod (+ main_~z~0 1) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {699#(< (mod main_~z~0 4294967296) 268435455)} is VALID [2022-04-27 22:19:06,236 INFO L290 TraceCheckUtils]: 7: Hoare triple {636#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {703#(< (mod (+ main_~z~0 1) 4294967296) 268435455)} is VALID [2022-04-27 22:19:06,236 INFO L290 TraceCheckUtils]: 6: Hoare triple {636#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {636#true} is VALID [2022-04-27 22:19:06,236 INFO L290 TraceCheckUtils]: 5: Hoare triple {636#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {636#true} is VALID [2022-04-27 22:19:06,236 INFO L272 TraceCheckUtils]: 4: Hoare triple {636#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,237 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {636#true} {636#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,237 INFO L290 TraceCheckUtils]: 2: Hoare triple {636#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,240 INFO L290 TraceCheckUtils]: 1: Hoare triple {636#true} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {636#true} is VALID [2022-04-27 22:19:06,240 INFO L272 TraceCheckUtils]: 0: Hoare triple {636#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {636#true} is VALID [2022-04-27 22:19:06,240 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:06,240 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [717065153] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 22:19:06,240 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 22:19:06,240 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 4] total 8 [2022-04-27 22:19:06,241 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315868400] [2022-04-27 22:19:06,241 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 22:19:06,241 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 14 [2022-04-27 22:19:06,241 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 22:19:06,242 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:06,263 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 21 edges. 21 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:06,263 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-27 22:19:06,263 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 22:19:06,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-27 22:19:06,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2022-04-27 22:19:06,264 INFO L87 Difference]: Start difference. First operand 23 states and 27 transitions. Second operand has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:06,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:06,436 INFO L93 Difference]: Finished difference Result 43 states and 54 transitions. [2022-04-27 22:19:06,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 22:19:06,436 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 14 [2022-04-27 22:19:06,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 22:19:06,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:06,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 51 transitions. [2022-04-27 22:19:06,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:06,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 51 transitions. [2022-04-27 22:19:06,439 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 51 transitions. [2022-04-27 22:19:06,477 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:06,478 INFO L225 Difference]: With dead ends: 43 [2022-04-27 22:19:06,478 INFO L226 Difference]: Without dead ends: 27 [2022-04-27 22:19:06,479 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=83, Unknown=0, NotChecked=0, Total=132 [2022-04-27 22:19:06,479 INFO L413 NwaCegarLoop]: 21 mSDtfsCounter, 19 mSDsluCounter, 12 mSDsCounter, 0 mSdLazyCounter, 44 mSolverCounterSat, 17 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 21 SdHoareTripleChecker+Valid, 33 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 17 IncrementalHoareTripleChecker+Valid, 44 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 22:19:06,479 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [21 Valid, 33 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [17 Valid, 44 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 22:19:06,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2022-04-27 22:19:06,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 26. [2022-04-27 22:19:06,484 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 22:19:06,485 INFO L82 GeneralOperation]: Start isEquivalent. First operand 27 states. Second operand has 26 states, 18 states have (on average 1.2222222222222223) internal successors, (22), 19 states have internal predecessors, (22), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:06,485 INFO L74 IsIncluded]: Start isIncluded. First operand 27 states. Second operand has 26 states, 18 states have (on average 1.2222222222222223) internal successors, (22), 19 states have internal predecessors, (22), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:06,485 INFO L87 Difference]: Start difference. First operand 27 states. Second operand has 26 states, 18 states have (on average 1.2222222222222223) internal successors, (22), 19 states have internal predecessors, (22), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:06,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:06,486 INFO L93 Difference]: Finished difference Result 27 states and 31 transitions. [2022-04-27 22:19:06,486 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 31 transitions. [2022-04-27 22:19:06,486 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:06,486 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:06,487 INFO L74 IsIncluded]: Start isIncluded. First operand has 26 states, 18 states have (on average 1.2222222222222223) internal successors, (22), 19 states have internal predecessors, (22), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 27 states. [2022-04-27 22:19:06,487 INFO L87 Difference]: Start difference. First operand has 26 states, 18 states have (on average 1.2222222222222223) internal successors, (22), 19 states have internal predecessors, (22), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 27 states. [2022-04-27 22:19:06,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:06,488 INFO L93 Difference]: Finished difference Result 27 states and 31 transitions. [2022-04-27 22:19:06,488 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 31 transitions. [2022-04-27 22:19:06,488 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:06,488 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:06,488 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 22:19:06,488 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 22:19:06,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 18 states have (on average 1.2222222222222223) internal successors, (22), 19 states have internal predecessors, (22), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:06,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 30 transitions. [2022-04-27 22:19:06,489 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 30 transitions. Word has length 14 [2022-04-27 22:19:06,489 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 22:19:06,489 INFO L495 AbstractCegarLoop]: Abstraction has 26 states and 30 transitions. [2022-04-27 22:19:06,489 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:06,489 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 30 transitions. [2022-04-27 22:19:06,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 22:19:06,489 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 22:19:06,490 INFO L195 NwaCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 22:19:06,506 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-27 22:19:06,703 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 22:19:06,704 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 22:19:06,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 22:19:06,704 INFO L85 PathProgramCache]: Analyzing trace with hash -1029731085, now seen corresponding path program 2 times [2022-04-27 22:19:06,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 22:19:06,704 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330742286] [2022-04-27 22:19:06,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 22:19:06,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 22:19:06,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:06,786 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 22:19:06,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:06,792 INFO L290 TraceCheckUtils]: 0: Hoare triple {916#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {906#true} is VALID [2022-04-27 22:19:06,792 INFO L290 TraceCheckUtils]: 1: Hoare triple {906#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:06,792 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {906#true} {906#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:06,793 INFO L272 TraceCheckUtils]: 0: Hoare triple {906#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {916#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 22:19:06,793 INFO L290 TraceCheckUtils]: 1: Hoare triple {916#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {906#true} is VALID [2022-04-27 22:19:06,793 INFO L290 TraceCheckUtils]: 2: Hoare triple {906#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:06,793 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {906#true} {906#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:06,793 INFO L272 TraceCheckUtils]: 4: Hoare triple {906#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:06,793 INFO L290 TraceCheckUtils]: 5: Hoare triple {906#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {906#true} is VALID [2022-04-27 22:19:06,793 INFO L290 TraceCheckUtils]: 6: Hoare triple {906#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {906#true} is VALID [2022-04-27 22:19:06,794 INFO L290 TraceCheckUtils]: 7: Hoare triple {906#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {911#(= main_~z~0 0)} is VALID [2022-04-27 22:19:06,794 INFO L290 TraceCheckUtils]: 8: Hoare triple {911#(= main_~z~0 0)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {912#(and (<= main_~z~0 1) (<= 1 main_~z~0))} is VALID [2022-04-27 22:19:06,795 INFO L290 TraceCheckUtils]: 9: Hoare triple {912#(and (<= main_~z~0 1) (<= 1 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {913#(and (<= main_~z~0 2) (<= 2 main_~z~0))} is VALID [2022-04-27 22:19:06,795 INFO L290 TraceCheckUtils]: 10: Hoare triple {913#(and (<= main_~z~0 2) (<= 2 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {914#(and (<= main_~z~0 3) (<= 3 main_~z~0))} is VALID [2022-04-27 22:19:06,797 INFO L290 TraceCheckUtils]: 11: Hoare triple {914#(and (<= main_~z~0 3) (<= 3 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {915#(and (not (<= (+ (div main_~z~0 4294967296) 1) 0)) (<= main_~z~0 4))} is VALID [2022-04-27 22:19:06,797 INFO L290 TraceCheckUtils]: 12: Hoare triple {915#(and (not (<= (+ (div main_~z~0 4294967296) 1) 0)) (<= main_~z~0 4))} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {907#false} is VALID [2022-04-27 22:19:06,797 INFO L272 TraceCheckUtils]: 13: Hoare triple {907#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {907#false} is VALID [2022-04-27 22:19:06,797 INFO L290 TraceCheckUtils]: 14: Hoare triple {907#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {907#false} is VALID [2022-04-27 22:19:06,798 INFO L290 TraceCheckUtils]: 15: Hoare triple {907#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {907#false} is VALID [2022-04-27 22:19:06,798 INFO L290 TraceCheckUtils]: 16: Hoare triple {907#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {907#false} is VALID [2022-04-27 22:19:06,798 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:06,798 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 22:19:06,798 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [330742286] [2022-04-27 22:19:06,798 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [330742286] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 22:19:06,798 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1358278203] [2022-04-27 22:19:06,798 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 22:19:06,798 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 22:19:06,798 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 22:19:06,799 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 22:19:06,800 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 22:19:06,828 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 22:19:06,828 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 22:19:06,829 INFO L263 TraceCheckSpWp]: Trace formula consists of 75 conjuncts, 11 conjunts are in the unsatisfiable core [2022-04-27 22:19:06,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:06,835 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 22:19:07,036 INFO L272 TraceCheckUtils]: 0: Hoare triple {906#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:07,036 INFO L290 TraceCheckUtils]: 1: Hoare triple {906#true} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {906#true} is VALID [2022-04-27 22:19:07,036 INFO L290 TraceCheckUtils]: 2: Hoare triple {906#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:07,037 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {906#true} {906#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:07,037 INFO L272 TraceCheckUtils]: 4: Hoare triple {906#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:07,037 INFO L290 TraceCheckUtils]: 5: Hoare triple {906#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {906#true} is VALID [2022-04-27 22:19:07,037 INFO L290 TraceCheckUtils]: 6: Hoare triple {906#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {906#true} is VALID [2022-04-27 22:19:07,037 INFO L290 TraceCheckUtils]: 7: Hoare triple {906#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {911#(= main_~z~0 0)} is VALID [2022-04-27 22:19:07,038 INFO L290 TraceCheckUtils]: 8: Hoare triple {911#(= main_~z~0 0)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {912#(and (<= main_~z~0 1) (<= 1 main_~z~0))} is VALID [2022-04-27 22:19:07,038 INFO L290 TraceCheckUtils]: 9: Hoare triple {912#(and (<= main_~z~0 1) (<= 1 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {913#(and (<= main_~z~0 2) (<= 2 main_~z~0))} is VALID [2022-04-27 22:19:07,039 INFO L290 TraceCheckUtils]: 10: Hoare triple {913#(and (<= main_~z~0 2) (<= 2 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {914#(and (<= main_~z~0 3) (<= 3 main_~z~0))} is VALID [2022-04-27 22:19:07,041 INFO L290 TraceCheckUtils]: 11: Hoare triple {914#(and (<= main_~z~0 3) (<= 3 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {953#(and (<= 4 main_~z~0) (<= main_~z~0 4))} is VALID [2022-04-27 22:19:07,041 INFO L290 TraceCheckUtils]: 12: Hoare triple {953#(and (<= 4 main_~z~0) (<= main_~z~0 4))} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {907#false} is VALID [2022-04-27 22:19:07,041 INFO L272 TraceCheckUtils]: 13: Hoare triple {907#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {907#false} is VALID [2022-04-27 22:19:07,041 INFO L290 TraceCheckUtils]: 14: Hoare triple {907#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {907#false} is VALID [2022-04-27 22:19:07,041 INFO L290 TraceCheckUtils]: 15: Hoare triple {907#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {907#false} is VALID [2022-04-27 22:19:07,042 INFO L290 TraceCheckUtils]: 16: Hoare triple {907#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {907#false} is VALID [2022-04-27 22:19:07,042 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:07,042 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 22:19:07,150 INFO L290 TraceCheckUtils]: 16: Hoare triple {907#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {907#false} is VALID [2022-04-27 22:19:07,150 INFO L290 TraceCheckUtils]: 15: Hoare triple {907#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {907#false} is VALID [2022-04-27 22:19:07,150 INFO L290 TraceCheckUtils]: 14: Hoare triple {907#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {907#false} is VALID [2022-04-27 22:19:07,150 INFO L272 TraceCheckUtils]: 13: Hoare triple {907#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {907#false} is VALID [2022-04-27 22:19:07,151 INFO L290 TraceCheckUtils]: 12: Hoare triple {981#(< (mod main_~z~0 4294967296) 268435455)} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {907#false} is VALID [2022-04-27 22:19:07,152 INFO L290 TraceCheckUtils]: 11: Hoare triple {985#(< (mod (+ main_~z~0 1) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {981#(< (mod main_~z~0 4294967296) 268435455)} is VALID [2022-04-27 22:19:07,152 INFO L290 TraceCheckUtils]: 10: Hoare triple {989#(< (mod (+ main_~z~0 2) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {985#(< (mod (+ main_~z~0 1) 4294967296) 268435455)} is VALID [2022-04-27 22:19:07,153 INFO L290 TraceCheckUtils]: 9: Hoare triple {993#(< (mod (+ main_~z~0 3) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {989#(< (mod (+ main_~z~0 2) 4294967296) 268435455)} is VALID [2022-04-27 22:19:07,154 INFO L290 TraceCheckUtils]: 8: Hoare triple {997#(< (mod (+ main_~z~0 4) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {993#(< (mod (+ main_~z~0 3) 4294967296) 268435455)} is VALID [2022-04-27 22:19:07,154 INFO L290 TraceCheckUtils]: 7: Hoare triple {906#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {997#(< (mod (+ main_~z~0 4) 4294967296) 268435455)} is VALID [2022-04-27 22:19:07,154 INFO L290 TraceCheckUtils]: 6: Hoare triple {906#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {906#true} is VALID [2022-04-27 22:19:07,155 INFO L290 TraceCheckUtils]: 5: Hoare triple {906#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {906#true} is VALID [2022-04-27 22:19:07,155 INFO L272 TraceCheckUtils]: 4: Hoare triple {906#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:07,155 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {906#true} {906#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:07,155 INFO L290 TraceCheckUtils]: 2: Hoare triple {906#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:07,155 INFO L290 TraceCheckUtils]: 1: Hoare triple {906#true} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {906#true} is VALID [2022-04-27 22:19:07,155 INFO L272 TraceCheckUtils]: 0: Hoare triple {906#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {906#true} is VALID [2022-04-27 22:19:07,155 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:07,155 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1358278203] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 22:19:07,156 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 22:19:07,156 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2022-04-27 22:19:07,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1236838281] [2022-04-27 22:19:07,156 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 22:19:07,156 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 22:19:07,156 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 22:19:07,157 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:07,174 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:07,175 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 22:19:07,175 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 22:19:07,175 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 22:19:07,175 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=122, Unknown=0, NotChecked=0, Total=182 [2022-04-27 22:19:07,175 INFO L87 Difference]: Start difference. First operand 26 states and 30 transitions. Second operand has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:07,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:07,697 INFO L93 Difference]: Finished difference Result 52 states and 66 transitions. [2022-04-27 22:19:07,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 22:19:07,697 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 22:19:07,697 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 22:19:07,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:07,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 60 transitions. [2022-04-27 22:19:07,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:07,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 60 transitions. [2022-04-27 22:19:07,700 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 60 transitions. [2022-04-27 22:19:07,761 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:07,762 INFO L225 Difference]: With dead ends: 52 [2022-04-27 22:19:07,762 INFO L226 Difference]: Without dead ends: 33 [2022-04-27 22:19:07,763 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 31 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 64 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=175, Invalid=377, Unknown=0, NotChecked=0, Total=552 [2022-04-27 22:19:07,763 INFO L413 NwaCegarLoop]: 21 mSDtfsCounter, 18 mSDsluCounter, 32 mSDsCounter, 0 mSdLazyCounter, 140 mSolverCounterSat, 27 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 53 SdHoareTripleChecker+Invalid, 167 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 27 IncrementalHoareTripleChecker+Valid, 140 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 22:19:07,763 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 53 Invalid, 167 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [27 Valid, 140 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 22:19:07,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2022-04-27 22:19:07,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 32. [2022-04-27 22:19:07,777 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 22:19:07,778 INFO L82 GeneralOperation]: Start isEquivalent. First operand 33 states. Second operand has 32 states, 24 states have (on average 1.1666666666666667) internal successors, (28), 25 states have internal predecessors, (28), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:07,778 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand has 32 states, 24 states have (on average 1.1666666666666667) internal successors, (28), 25 states have internal predecessors, (28), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:07,778 INFO L87 Difference]: Start difference. First operand 33 states. Second operand has 32 states, 24 states have (on average 1.1666666666666667) internal successors, (28), 25 states have internal predecessors, (28), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:07,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:07,779 INFO L93 Difference]: Finished difference Result 33 states and 37 transitions. [2022-04-27 22:19:07,779 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 37 transitions. [2022-04-27 22:19:07,779 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:07,779 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:07,779 INFO L74 IsIncluded]: Start isIncluded. First operand has 32 states, 24 states have (on average 1.1666666666666667) internal successors, (28), 25 states have internal predecessors, (28), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 33 states. [2022-04-27 22:19:07,780 INFO L87 Difference]: Start difference. First operand has 32 states, 24 states have (on average 1.1666666666666667) internal successors, (28), 25 states have internal predecessors, (28), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 33 states. [2022-04-27 22:19:07,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:07,780 INFO L93 Difference]: Finished difference Result 33 states and 37 transitions. [2022-04-27 22:19:07,781 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 37 transitions. [2022-04-27 22:19:07,781 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:07,781 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:07,781 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 22:19:07,781 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 22:19:07,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 24 states have (on average 1.1666666666666667) internal successors, (28), 25 states have internal predecessors, (28), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:07,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 36 transitions. [2022-04-27 22:19:07,782 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 36 transitions. Word has length 17 [2022-04-27 22:19:07,782 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 22:19:07,782 INFO L495 AbstractCegarLoop]: Abstraction has 32 states and 36 transitions. [2022-04-27 22:19:07,782 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:07,782 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 36 transitions. [2022-04-27 22:19:07,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2022-04-27 22:19:07,783 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 22:19:07,783 INFO L195 NwaCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 22:19:07,803 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2022-04-27 22:19:07,999 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable5 [2022-04-27 22:19:08,000 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 22:19:08,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 22:19:08,000 INFO L85 PathProgramCache]: Analyzing trace with hash -531163149, now seen corresponding path program 3 times [2022-04-27 22:19:08,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 22:19:08,000 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672190005] [2022-04-27 22:19:08,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 22:19:08,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 22:19:08,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:08,182 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 22:19:08,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:08,186 INFO L290 TraceCheckUtils]: 0: Hoare triple {1270#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1254#true} is VALID [2022-04-27 22:19:08,186 INFO L290 TraceCheckUtils]: 1: Hoare triple {1254#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,186 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1254#true} {1254#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,187 INFO L272 TraceCheckUtils]: 0: Hoare triple {1254#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1270#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 22:19:08,187 INFO L290 TraceCheckUtils]: 1: Hoare triple {1270#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1254#true} is VALID [2022-04-27 22:19:08,187 INFO L290 TraceCheckUtils]: 2: Hoare triple {1254#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,187 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1254#true} {1254#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,187 INFO L272 TraceCheckUtils]: 4: Hoare triple {1254#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,187 INFO L290 TraceCheckUtils]: 5: Hoare triple {1254#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {1254#true} is VALID [2022-04-27 22:19:08,187 INFO L290 TraceCheckUtils]: 6: Hoare triple {1254#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {1254#true} is VALID [2022-04-27 22:19:08,188 INFO L290 TraceCheckUtils]: 7: Hoare triple {1254#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {1259#(= main_~z~0 0)} is VALID [2022-04-27 22:19:08,188 INFO L290 TraceCheckUtils]: 8: Hoare triple {1259#(= main_~z~0 0)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1260#(and (<= main_~z~0 1) (<= 1 main_~z~0))} is VALID [2022-04-27 22:19:08,189 INFO L290 TraceCheckUtils]: 9: Hoare triple {1260#(and (<= main_~z~0 1) (<= 1 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1261#(and (<= main_~z~0 2) (<= 2 main_~z~0))} is VALID [2022-04-27 22:19:08,190 INFO L290 TraceCheckUtils]: 10: Hoare triple {1261#(and (<= main_~z~0 2) (<= 2 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1262#(and (<= main_~z~0 3) (<= 3 main_~z~0))} is VALID [2022-04-27 22:19:08,190 INFO L290 TraceCheckUtils]: 11: Hoare triple {1262#(and (<= main_~z~0 3) (<= 3 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1263#(and (<= 4 main_~z~0) (<= main_~z~0 4))} is VALID [2022-04-27 22:19:08,191 INFO L290 TraceCheckUtils]: 12: Hoare triple {1263#(and (<= 4 main_~z~0) (<= main_~z~0 4))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1264#(and (<= main_~z~0 5) (<= 5 main_~z~0))} is VALID [2022-04-27 22:19:08,191 INFO L290 TraceCheckUtils]: 13: Hoare triple {1264#(and (<= main_~z~0 5) (<= 5 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1265#(and (<= main_~z~0 6) (<= 6 main_~z~0))} is VALID [2022-04-27 22:19:08,192 INFO L290 TraceCheckUtils]: 14: Hoare triple {1265#(and (<= main_~z~0 6) (<= 6 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1266#(and (<= main_~z~0 7) (<= 7 main_~z~0))} is VALID [2022-04-27 22:19:08,192 INFO L290 TraceCheckUtils]: 15: Hoare triple {1266#(and (<= main_~z~0 7) (<= 7 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1267#(and (<= 8 main_~z~0) (<= main_~z~0 8))} is VALID [2022-04-27 22:19:08,193 INFO L290 TraceCheckUtils]: 16: Hoare triple {1267#(and (<= 8 main_~z~0) (<= main_~z~0 8))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1268#(and (<= 9 main_~z~0) (<= main_~z~0 9))} is VALID [2022-04-27 22:19:08,193 INFO L290 TraceCheckUtils]: 17: Hoare triple {1268#(and (<= 9 main_~z~0) (<= main_~z~0 9))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1269#(and (<= main_~z~0 10) (not (<= (+ (div main_~z~0 4294967296) 1) 0)))} is VALID [2022-04-27 22:19:08,194 INFO L290 TraceCheckUtils]: 18: Hoare triple {1269#(and (<= main_~z~0 10) (not (<= (+ (div main_~z~0 4294967296) 1) 0)))} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-27 22:19:08,194 INFO L272 TraceCheckUtils]: 19: Hoare triple {1255#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {1255#false} is VALID [2022-04-27 22:19:08,194 INFO L290 TraceCheckUtils]: 20: Hoare triple {1255#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1255#false} is VALID [2022-04-27 22:19:08,194 INFO L290 TraceCheckUtils]: 21: Hoare triple {1255#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-27 22:19:08,194 INFO L290 TraceCheckUtils]: 22: Hoare triple {1255#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-27 22:19:08,194 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:08,195 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 22:19:08,195 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1672190005] [2022-04-27 22:19:08,195 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1672190005] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 22:19:08,195 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1157313358] [2022-04-27 22:19:08,195 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-27 22:19:08,195 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 22:19:08,195 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 22:19:08,196 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 22:19:08,197 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 22:19:08,265 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-04-27 22:19:08,265 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 22:19:08,280 INFO L263 TraceCheckSpWp]: Trace formula consists of 93 conjuncts, 23 conjunts are in the unsatisfiable core [2022-04-27 22:19:08,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:08,285 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 22:19:08,537 INFO L272 TraceCheckUtils]: 0: Hoare triple {1254#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,538 INFO L290 TraceCheckUtils]: 1: Hoare triple {1254#true} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1254#true} is VALID [2022-04-27 22:19:08,538 INFO L290 TraceCheckUtils]: 2: Hoare triple {1254#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,538 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1254#true} {1254#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,538 INFO L272 TraceCheckUtils]: 4: Hoare triple {1254#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,538 INFO L290 TraceCheckUtils]: 5: Hoare triple {1254#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {1254#true} is VALID [2022-04-27 22:19:08,538 INFO L290 TraceCheckUtils]: 6: Hoare triple {1254#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {1254#true} is VALID [2022-04-27 22:19:08,540 INFO L290 TraceCheckUtils]: 7: Hoare triple {1254#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {1259#(= main_~z~0 0)} is VALID [2022-04-27 22:19:08,540 INFO L290 TraceCheckUtils]: 8: Hoare triple {1259#(= main_~z~0 0)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1260#(and (<= main_~z~0 1) (<= 1 main_~z~0))} is VALID [2022-04-27 22:19:08,541 INFO L290 TraceCheckUtils]: 9: Hoare triple {1260#(and (<= main_~z~0 1) (<= 1 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1261#(and (<= main_~z~0 2) (<= 2 main_~z~0))} is VALID [2022-04-27 22:19:08,541 INFO L290 TraceCheckUtils]: 10: Hoare triple {1261#(and (<= main_~z~0 2) (<= 2 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1262#(and (<= main_~z~0 3) (<= 3 main_~z~0))} is VALID [2022-04-27 22:19:08,542 INFO L290 TraceCheckUtils]: 11: Hoare triple {1262#(and (<= main_~z~0 3) (<= 3 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1263#(and (<= 4 main_~z~0) (<= main_~z~0 4))} is VALID [2022-04-27 22:19:08,542 INFO L290 TraceCheckUtils]: 12: Hoare triple {1263#(and (<= 4 main_~z~0) (<= main_~z~0 4))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1264#(and (<= main_~z~0 5) (<= 5 main_~z~0))} is VALID [2022-04-27 22:19:08,543 INFO L290 TraceCheckUtils]: 13: Hoare triple {1264#(and (<= main_~z~0 5) (<= 5 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1265#(and (<= main_~z~0 6) (<= 6 main_~z~0))} is VALID [2022-04-27 22:19:08,543 INFO L290 TraceCheckUtils]: 14: Hoare triple {1265#(and (<= main_~z~0 6) (<= 6 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1266#(and (<= main_~z~0 7) (<= 7 main_~z~0))} is VALID [2022-04-27 22:19:08,544 INFO L290 TraceCheckUtils]: 15: Hoare triple {1266#(and (<= main_~z~0 7) (<= 7 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1267#(and (<= 8 main_~z~0) (<= main_~z~0 8))} is VALID [2022-04-27 22:19:08,547 INFO L290 TraceCheckUtils]: 16: Hoare triple {1267#(and (<= 8 main_~z~0) (<= main_~z~0 8))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1268#(and (<= 9 main_~z~0) (<= main_~z~0 9))} is VALID [2022-04-27 22:19:08,547 INFO L290 TraceCheckUtils]: 17: Hoare triple {1268#(and (<= 9 main_~z~0) (<= main_~z~0 9))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1325#(and (<= main_~z~0 10) (<= 10 main_~z~0))} is VALID [2022-04-27 22:19:08,548 INFO L290 TraceCheckUtils]: 18: Hoare triple {1325#(and (<= main_~z~0 10) (<= 10 main_~z~0))} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-27 22:19:08,548 INFO L272 TraceCheckUtils]: 19: Hoare triple {1255#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {1255#false} is VALID [2022-04-27 22:19:08,548 INFO L290 TraceCheckUtils]: 20: Hoare triple {1255#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1255#false} is VALID [2022-04-27 22:19:08,548 INFO L290 TraceCheckUtils]: 21: Hoare triple {1255#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-27 22:19:08,548 INFO L290 TraceCheckUtils]: 22: Hoare triple {1255#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-27 22:19:08,549 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:08,549 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 22:19:08,835 INFO L290 TraceCheckUtils]: 22: Hoare triple {1255#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-27 22:19:08,835 INFO L290 TraceCheckUtils]: 21: Hoare triple {1255#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-27 22:19:08,835 INFO L290 TraceCheckUtils]: 20: Hoare triple {1255#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1255#false} is VALID [2022-04-27 22:19:08,835 INFO L272 TraceCheckUtils]: 19: Hoare triple {1255#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {1255#false} is VALID [2022-04-27 22:19:08,836 INFO L290 TraceCheckUtils]: 18: Hoare triple {1353#(< (mod main_~z~0 4294967296) 268435455)} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-27 22:19:08,836 INFO L290 TraceCheckUtils]: 17: Hoare triple {1357#(< (mod (+ main_~z~0 1) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1353#(< (mod main_~z~0 4294967296) 268435455)} is VALID [2022-04-27 22:19:08,837 INFO L290 TraceCheckUtils]: 16: Hoare triple {1361#(< (mod (+ main_~z~0 2) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1357#(< (mod (+ main_~z~0 1) 4294967296) 268435455)} is VALID [2022-04-27 22:19:08,837 INFO L290 TraceCheckUtils]: 15: Hoare triple {1365#(< (mod (+ main_~z~0 3) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1361#(< (mod (+ main_~z~0 2) 4294967296) 268435455)} is VALID [2022-04-27 22:19:08,838 INFO L290 TraceCheckUtils]: 14: Hoare triple {1369#(< (mod (+ main_~z~0 4) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1365#(< (mod (+ main_~z~0 3) 4294967296) 268435455)} is VALID [2022-04-27 22:19:08,839 INFO L290 TraceCheckUtils]: 13: Hoare triple {1373#(< (mod (+ 5 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1369#(< (mod (+ main_~z~0 4) 4294967296) 268435455)} is VALID [2022-04-27 22:19:08,839 INFO L290 TraceCheckUtils]: 12: Hoare triple {1377#(< (mod (+ main_~z~0 6) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1373#(< (mod (+ 5 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:19:08,840 INFO L290 TraceCheckUtils]: 11: Hoare triple {1381#(< (mod (+ 7 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1377#(< (mod (+ main_~z~0 6) 4294967296) 268435455)} is VALID [2022-04-27 22:19:08,840 INFO L290 TraceCheckUtils]: 10: Hoare triple {1385#(< (mod (+ main_~z~0 8) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1381#(< (mod (+ 7 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:19:08,841 INFO L290 TraceCheckUtils]: 9: Hoare triple {1389#(< (mod (+ main_~z~0 9) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1385#(< (mod (+ main_~z~0 8) 4294967296) 268435455)} is VALID [2022-04-27 22:19:08,843 INFO L290 TraceCheckUtils]: 8: Hoare triple {1393#(< (mod (+ main_~z~0 10) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1389#(< (mod (+ main_~z~0 9) 4294967296) 268435455)} is VALID [2022-04-27 22:19:08,844 INFO L290 TraceCheckUtils]: 7: Hoare triple {1254#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {1393#(< (mod (+ main_~z~0 10) 4294967296) 268435455)} is VALID [2022-04-27 22:19:08,844 INFO L290 TraceCheckUtils]: 6: Hoare triple {1254#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {1254#true} is VALID [2022-04-27 22:19:08,844 INFO L290 TraceCheckUtils]: 5: Hoare triple {1254#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {1254#true} is VALID [2022-04-27 22:19:08,844 INFO L272 TraceCheckUtils]: 4: Hoare triple {1254#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,844 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1254#true} {1254#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,844 INFO L290 TraceCheckUtils]: 2: Hoare triple {1254#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,844 INFO L290 TraceCheckUtils]: 1: Hoare triple {1254#true} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1254#true} is VALID [2022-04-27 22:19:08,844 INFO L272 TraceCheckUtils]: 0: Hoare triple {1254#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-27 22:19:08,845 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:08,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1157313358] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 22:19:08,845 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 22:19:08,845 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 26 [2022-04-27 22:19:08,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644611697] [2022-04-27 22:19:08,845 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 22:19:08,846 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 22:19:08,846 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 22:19:08,846 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:08,873 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:08,874 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-04-27 22:19:08,874 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 22:19:08,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-04-27 22:19:08,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=458, Unknown=0, NotChecked=0, Total=650 [2022-04-27 22:19:08,875 INFO L87 Difference]: Start difference. First operand 32 states and 36 transitions. Second operand has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:14,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:14,554 INFO L93 Difference]: Finished difference Result 70 states and 90 transitions. [2022-04-27 22:19:14,554 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-04-27 22:19:14,555 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 22:19:14,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 22:19:14,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:14,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 78 transitions. [2022-04-27 22:19:14,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:14,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 78 transitions. [2022-04-27 22:19:14,557 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 25 states and 78 transitions. [2022-04-27 22:19:14,657 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 78 edges. 78 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:14,658 INFO L225 Difference]: With dead ends: 70 [2022-04-27 22:19:14,658 INFO L226 Difference]: Without dead ends: 45 [2022-04-27 22:19:14,659 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 37 SyntacticMatches, 1 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 268 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=643, Invalid=1613, Unknown=0, NotChecked=0, Total=2256 [2022-04-27 22:19:14,660 INFO L413 NwaCegarLoop]: 21 mSDtfsCounter, 17 mSDsluCounter, 67 mSDsCounter, 0 mSdLazyCounter, 370 mSolverCounterSat, 46 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 19 SdHoareTripleChecker+Valid, 88 SdHoareTripleChecker+Invalid, 416 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 46 IncrementalHoareTripleChecker+Valid, 370 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-27 22:19:14,660 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [19 Valid, 88 Invalid, 416 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [46 Valid, 370 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-04-27 22:19:14,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2022-04-27 22:19:14,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 44. [2022-04-27 22:19:14,690 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 22:19:14,690 INFO L82 GeneralOperation]: Start isEquivalent. First operand 45 states. Second operand has 44 states, 36 states have (on average 1.1111111111111112) internal successors, (40), 37 states have internal predecessors, (40), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:14,690 INFO L74 IsIncluded]: Start isIncluded. First operand 45 states. Second operand has 44 states, 36 states have (on average 1.1111111111111112) internal successors, (40), 37 states have internal predecessors, (40), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:14,690 INFO L87 Difference]: Start difference. First operand 45 states. Second operand has 44 states, 36 states have (on average 1.1111111111111112) internal successors, (40), 37 states have internal predecessors, (40), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:14,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:14,691 INFO L93 Difference]: Finished difference Result 45 states and 49 transitions. [2022-04-27 22:19:14,691 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 49 transitions. [2022-04-27 22:19:14,692 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:14,692 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:14,692 INFO L74 IsIncluded]: Start isIncluded. First operand has 44 states, 36 states have (on average 1.1111111111111112) internal successors, (40), 37 states have internal predecessors, (40), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 45 states. [2022-04-27 22:19:14,692 INFO L87 Difference]: Start difference. First operand has 44 states, 36 states have (on average 1.1111111111111112) internal successors, (40), 37 states have internal predecessors, (40), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 45 states. [2022-04-27 22:19:14,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:19:14,693 INFO L93 Difference]: Finished difference Result 45 states and 49 transitions. [2022-04-27 22:19:14,693 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 49 transitions. [2022-04-27 22:19:14,693 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:19:14,693 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:19:14,693 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 22:19:14,693 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 22:19:14,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 36 states have (on average 1.1111111111111112) internal successors, (40), 37 states have internal predecessors, (40), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:19:14,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 48 transitions. [2022-04-27 22:19:14,695 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 48 transitions. Word has length 23 [2022-04-27 22:19:14,695 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 22:19:14,695 INFO L495 AbstractCegarLoop]: Abstraction has 44 states and 48 transitions. [2022-04-27 22:19:14,695 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:14,695 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 48 transitions. [2022-04-27 22:19:14,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2022-04-27 22:19:14,695 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 22:19:14,695 INFO L195 NwaCegarLoop]: trace histogram [22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 22:19:14,701 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-27 22:19:14,899 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 22:19:14,900 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 22:19:14,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 22:19:14,900 INFO L85 PathProgramCache]: Analyzing trace with hash 45706739, now seen corresponding path program 4 times [2022-04-27 22:19:14,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 22:19:14,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271869948] [2022-04-27 22:19:14,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 22:19:14,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 22:19:14,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:15,363 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 22:19:15,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:15,375 INFO L290 TraceCheckUtils]: 0: Hoare triple {1786#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1758#true} is VALID [2022-04-27 22:19:15,375 INFO L290 TraceCheckUtils]: 1: Hoare triple {1758#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:15,375 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1758#true} {1758#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:15,375 INFO L272 TraceCheckUtils]: 0: Hoare triple {1758#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1786#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 22:19:15,376 INFO L290 TraceCheckUtils]: 1: Hoare triple {1786#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1758#true} is VALID [2022-04-27 22:19:15,376 INFO L290 TraceCheckUtils]: 2: Hoare triple {1758#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:15,376 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1758#true} {1758#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:15,376 INFO L272 TraceCheckUtils]: 4: Hoare triple {1758#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:15,376 INFO L290 TraceCheckUtils]: 5: Hoare triple {1758#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {1758#true} is VALID [2022-04-27 22:19:15,376 INFO L290 TraceCheckUtils]: 6: Hoare triple {1758#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {1758#true} is VALID [2022-04-27 22:19:15,377 INFO L290 TraceCheckUtils]: 7: Hoare triple {1758#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {1763#(= main_~z~0 0)} is VALID [2022-04-27 22:19:15,378 INFO L290 TraceCheckUtils]: 8: Hoare triple {1763#(= main_~z~0 0)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1764#(and (<= main_~z~0 1) (<= 1 main_~z~0))} is VALID [2022-04-27 22:19:15,378 INFO L290 TraceCheckUtils]: 9: Hoare triple {1764#(and (<= main_~z~0 1) (<= 1 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1765#(and (<= main_~z~0 2) (<= 2 main_~z~0))} is VALID [2022-04-27 22:19:15,379 INFO L290 TraceCheckUtils]: 10: Hoare triple {1765#(and (<= main_~z~0 2) (<= 2 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1766#(and (<= main_~z~0 3) (<= 3 main_~z~0))} is VALID [2022-04-27 22:19:15,379 INFO L290 TraceCheckUtils]: 11: Hoare triple {1766#(and (<= main_~z~0 3) (<= 3 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1767#(and (<= 4 main_~z~0) (<= main_~z~0 4))} is VALID [2022-04-27 22:19:15,380 INFO L290 TraceCheckUtils]: 12: Hoare triple {1767#(and (<= 4 main_~z~0) (<= main_~z~0 4))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1768#(and (<= main_~z~0 5) (<= 5 main_~z~0))} is VALID [2022-04-27 22:19:15,380 INFO L290 TraceCheckUtils]: 13: Hoare triple {1768#(and (<= main_~z~0 5) (<= 5 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1769#(and (<= main_~z~0 6) (<= 6 main_~z~0))} is VALID [2022-04-27 22:19:15,381 INFO L290 TraceCheckUtils]: 14: Hoare triple {1769#(and (<= main_~z~0 6) (<= 6 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1770#(and (<= main_~z~0 7) (<= 7 main_~z~0))} is VALID [2022-04-27 22:19:15,383 INFO L290 TraceCheckUtils]: 15: Hoare triple {1770#(and (<= main_~z~0 7) (<= 7 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1771#(and (<= 8 main_~z~0) (<= main_~z~0 8))} is VALID [2022-04-27 22:19:15,383 INFO L290 TraceCheckUtils]: 16: Hoare triple {1771#(and (<= 8 main_~z~0) (<= main_~z~0 8))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1772#(and (<= 9 main_~z~0) (<= main_~z~0 9))} is VALID [2022-04-27 22:19:15,384 INFO L290 TraceCheckUtils]: 17: Hoare triple {1772#(and (<= 9 main_~z~0) (<= main_~z~0 9))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1773#(and (<= main_~z~0 10) (<= 10 main_~z~0))} is VALID [2022-04-27 22:19:15,385 INFO L290 TraceCheckUtils]: 18: Hoare triple {1773#(and (<= main_~z~0 10) (<= 10 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1774#(and (<= main_~z~0 11) (<= 11 main_~z~0))} is VALID [2022-04-27 22:19:15,385 INFO L290 TraceCheckUtils]: 19: Hoare triple {1774#(and (<= main_~z~0 11) (<= 11 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1775#(and (<= main_~z~0 12) (<= 12 main_~z~0))} is VALID [2022-04-27 22:19:15,386 INFO L290 TraceCheckUtils]: 20: Hoare triple {1775#(and (<= main_~z~0 12) (<= 12 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1776#(and (<= 13 main_~z~0) (<= main_~z~0 13))} is VALID [2022-04-27 22:19:15,386 INFO L290 TraceCheckUtils]: 21: Hoare triple {1776#(and (<= 13 main_~z~0) (<= main_~z~0 13))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1777#(and (<= 14 main_~z~0) (<= main_~z~0 14))} is VALID [2022-04-27 22:19:15,387 INFO L290 TraceCheckUtils]: 22: Hoare triple {1777#(and (<= 14 main_~z~0) (<= main_~z~0 14))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1778#(and (<= main_~z~0 15) (<= 15 main_~z~0))} is VALID [2022-04-27 22:19:15,387 INFO L290 TraceCheckUtils]: 23: Hoare triple {1778#(and (<= main_~z~0 15) (<= 15 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1779#(and (<= 16 main_~z~0) (<= main_~z~0 16))} is VALID [2022-04-27 22:19:15,388 INFO L290 TraceCheckUtils]: 24: Hoare triple {1779#(and (<= 16 main_~z~0) (<= main_~z~0 16))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1780#(and (<= 17 main_~z~0) (<= main_~z~0 17))} is VALID [2022-04-27 22:19:15,388 INFO L290 TraceCheckUtils]: 25: Hoare triple {1780#(and (<= 17 main_~z~0) (<= main_~z~0 17))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1781#(and (<= 18 main_~z~0) (<= main_~z~0 18))} is VALID [2022-04-27 22:19:15,389 INFO L290 TraceCheckUtils]: 26: Hoare triple {1781#(and (<= 18 main_~z~0) (<= main_~z~0 18))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1782#(and (<= 19 main_~z~0) (<= main_~z~0 19))} is VALID [2022-04-27 22:19:15,389 INFO L290 TraceCheckUtils]: 27: Hoare triple {1782#(and (<= 19 main_~z~0) (<= main_~z~0 19))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1783#(and (<= main_~z~0 20) (<= 20 main_~z~0))} is VALID [2022-04-27 22:19:15,390 INFO L290 TraceCheckUtils]: 28: Hoare triple {1783#(and (<= main_~z~0 20) (<= 20 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1784#(and (<= main_~z~0 21) (<= 21 main_~z~0))} is VALID [2022-04-27 22:19:15,390 INFO L290 TraceCheckUtils]: 29: Hoare triple {1784#(and (<= main_~z~0 21) (<= 21 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1785#(and (not (<= (+ (div main_~z~0 4294967296) 1) 0)) (<= main_~z~0 22))} is VALID [2022-04-27 22:19:15,391 INFO L290 TraceCheckUtils]: 30: Hoare triple {1785#(and (not (<= (+ (div main_~z~0 4294967296) 1) 0)) (<= main_~z~0 22))} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {1759#false} is VALID [2022-04-27 22:19:15,391 INFO L272 TraceCheckUtils]: 31: Hoare triple {1759#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {1759#false} is VALID [2022-04-27 22:19:15,391 INFO L290 TraceCheckUtils]: 32: Hoare triple {1759#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1759#false} is VALID [2022-04-27 22:19:15,391 INFO L290 TraceCheckUtils]: 33: Hoare triple {1759#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1759#false} is VALID [2022-04-27 22:19:15,391 INFO L290 TraceCheckUtils]: 34: Hoare triple {1759#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1759#false} is VALID [2022-04-27 22:19:15,392 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:15,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 22:19:15,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271869948] [2022-04-27 22:19:15,392 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [271869948] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 22:19:15,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1134841517] [2022-04-27 22:19:15,392 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-04-27 22:19:15,392 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 22:19:15,392 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 22:19:15,393 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 22:19:15,394 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 22:19:15,465 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-04-27 22:19:15,465 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 22:19:15,466 INFO L263 TraceCheckSpWp]: Trace formula consists of 129 conjuncts, 47 conjunts are in the unsatisfiable core [2022-04-27 22:19:15,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:19:15,475 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 22:19:15,843 INFO L272 TraceCheckUtils]: 0: Hoare triple {1758#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:15,843 INFO L290 TraceCheckUtils]: 1: Hoare triple {1758#true} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1758#true} is VALID [2022-04-27 22:19:15,843 INFO L290 TraceCheckUtils]: 2: Hoare triple {1758#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:15,843 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1758#true} {1758#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:15,843 INFO L272 TraceCheckUtils]: 4: Hoare triple {1758#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:15,843 INFO L290 TraceCheckUtils]: 5: Hoare triple {1758#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {1758#true} is VALID [2022-04-27 22:19:15,843 INFO L290 TraceCheckUtils]: 6: Hoare triple {1758#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {1758#true} is VALID [2022-04-27 22:19:15,844 INFO L290 TraceCheckUtils]: 7: Hoare triple {1758#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {1763#(= main_~z~0 0)} is VALID [2022-04-27 22:19:15,844 INFO L290 TraceCheckUtils]: 8: Hoare triple {1763#(= main_~z~0 0)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1764#(and (<= main_~z~0 1) (<= 1 main_~z~0))} is VALID [2022-04-27 22:19:15,845 INFO L290 TraceCheckUtils]: 9: Hoare triple {1764#(and (<= main_~z~0 1) (<= 1 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1765#(and (<= main_~z~0 2) (<= 2 main_~z~0))} is VALID [2022-04-27 22:19:15,845 INFO L290 TraceCheckUtils]: 10: Hoare triple {1765#(and (<= main_~z~0 2) (<= 2 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1766#(and (<= main_~z~0 3) (<= 3 main_~z~0))} is VALID [2022-04-27 22:19:15,846 INFO L290 TraceCheckUtils]: 11: Hoare triple {1766#(and (<= main_~z~0 3) (<= 3 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1767#(and (<= 4 main_~z~0) (<= main_~z~0 4))} is VALID [2022-04-27 22:19:15,846 INFO L290 TraceCheckUtils]: 12: Hoare triple {1767#(and (<= 4 main_~z~0) (<= main_~z~0 4))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1768#(and (<= main_~z~0 5) (<= 5 main_~z~0))} is VALID [2022-04-27 22:19:15,847 INFO L290 TraceCheckUtils]: 13: Hoare triple {1768#(and (<= main_~z~0 5) (<= 5 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1769#(and (<= main_~z~0 6) (<= 6 main_~z~0))} is VALID [2022-04-27 22:19:15,847 INFO L290 TraceCheckUtils]: 14: Hoare triple {1769#(and (<= main_~z~0 6) (<= 6 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1770#(and (<= main_~z~0 7) (<= 7 main_~z~0))} is VALID [2022-04-27 22:19:15,848 INFO L290 TraceCheckUtils]: 15: Hoare triple {1770#(and (<= main_~z~0 7) (<= 7 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1771#(and (<= 8 main_~z~0) (<= main_~z~0 8))} is VALID [2022-04-27 22:19:15,848 INFO L290 TraceCheckUtils]: 16: Hoare triple {1771#(and (<= 8 main_~z~0) (<= main_~z~0 8))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1772#(and (<= 9 main_~z~0) (<= main_~z~0 9))} is VALID [2022-04-27 22:19:15,849 INFO L290 TraceCheckUtils]: 17: Hoare triple {1772#(and (<= 9 main_~z~0) (<= main_~z~0 9))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1773#(and (<= main_~z~0 10) (<= 10 main_~z~0))} is VALID [2022-04-27 22:19:15,849 INFO L290 TraceCheckUtils]: 18: Hoare triple {1773#(and (<= main_~z~0 10) (<= 10 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1774#(and (<= main_~z~0 11) (<= 11 main_~z~0))} is VALID [2022-04-27 22:19:15,850 INFO L290 TraceCheckUtils]: 19: Hoare triple {1774#(and (<= main_~z~0 11) (<= 11 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1775#(and (<= main_~z~0 12) (<= 12 main_~z~0))} is VALID [2022-04-27 22:19:15,850 INFO L290 TraceCheckUtils]: 20: Hoare triple {1775#(and (<= main_~z~0 12) (<= 12 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1776#(and (<= 13 main_~z~0) (<= main_~z~0 13))} is VALID [2022-04-27 22:19:15,851 INFO L290 TraceCheckUtils]: 21: Hoare triple {1776#(and (<= 13 main_~z~0) (<= main_~z~0 13))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1777#(and (<= 14 main_~z~0) (<= main_~z~0 14))} is VALID [2022-04-27 22:19:15,851 INFO L290 TraceCheckUtils]: 22: Hoare triple {1777#(and (<= 14 main_~z~0) (<= main_~z~0 14))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1778#(and (<= main_~z~0 15) (<= 15 main_~z~0))} is VALID [2022-04-27 22:19:15,852 INFO L290 TraceCheckUtils]: 23: Hoare triple {1778#(and (<= main_~z~0 15) (<= 15 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1779#(and (<= 16 main_~z~0) (<= main_~z~0 16))} is VALID [2022-04-27 22:19:15,852 INFO L290 TraceCheckUtils]: 24: Hoare triple {1779#(and (<= 16 main_~z~0) (<= main_~z~0 16))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1780#(and (<= 17 main_~z~0) (<= main_~z~0 17))} is VALID [2022-04-27 22:19:15,853 INFO L290 TraceCheckUtils]: 25: Hoare triple {1780#(and (<= 17 main_~z~0) (<= main_~z~0 17))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1781#(and (<= 18 main_~z~0) (<= main_~z~0 18))} is VALID [2022-04-27 22:19:15,853 INFO L290 TraceCheckUtils]: 26: Hoare triple {1781#(and (<= 18 main_~z~0) (<= main_~z~0 18))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1782#(and (<= 19 main_~z~0) (<= main_~z~0 19))} is VALID [2022-04-27 22:19:15,854 INFO L290 TraceCheckUtils]: 27: Hoare triple {1782#(and (<= 19 main_~z~0) (<= main_~z~0 19))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1783#(and (<= main_~z~0 20) (<= 20 main_~z~0))} is VALID [2022-04-27 22:19:15,854 INFO L290 TraceCheckUtils]: 28: Hoare triple {1783#(and (<= main_~z~0 20) (<= 20 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1784#(and (<= main_~z~0 21) (<= 21 main_~z~0))} is VALID [2022-04-27 22:19:15,855 INFO L290 TraceCheckUtils]: 29: Hoare triple {1784#(and (<= main_~z~0 21) (<= 21 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1877#(and (<= 22 main_~z~0) (<= main_~z~0 22))} is VALID [2022-04-27 22:19:15,855 INFO L290 TraceCheckUtils]: 30: Hoare triple {1877#(and (<= 22 main_~z~0) (<= main_~z~0 22))} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {1759#false} is VALID [2022-04-27 22:19:15,855 INFO L272 TraceCheckUtils]: 31: Hoare triple {1759#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {1759#false} is VALID [2022-04-27 22:19:15,856 INFO L290 TraceCheckUtils]: 32: Hoare triple {1759#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1759#false} is VALID [2022-04-27 22:19:15,856 INFO L290 TraceCheckUtils]: 33: Hoare triple {1759#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1759#false} is VALID [2022-04-27 22:19:15,856 INFO L290 TraceCheckUtils]: 34: Hoare triple {1759#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1759#false} is VALID [2022-04-27 22:19:15,856 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:15,856 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 22:19:16,773 INFO L290 TraceCheckUtils]: 34: Hoare triple {1759#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1759#false} is VALID [2022-04-27 22:19:16,773 INFO L290 TraceCheckUtils]: 33: Hoare triple {1759#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1759#false} is VALID [2022-04-27 22:19:16,773 INFO L290 TraceCheckUtils]: 32: Hoare triple {1759#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1759#false} is VALID [2022-04-27 22:19:16,773 INFO L272 TraceCheckUtils]: 31: Hoare triple {1759#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {1759#false} is VALID [2022-04-27 22:19:16,774 INFO L290 TraceCheckUtils]: 30: Hoare triple {1905#(< (mod main_~z~0 4294967296) 268435455)} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {1759#false} is VALID [2022-04-27 22:19:16,774 INFO L290 TraceCheckUtils]: 29: Hoare triple {1909#(< (mod (+ main_~z~0 1) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1905#(< (mod main_~z~0 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,776 INFO L290 TraceCheckUtils]: 28: Hoare triple {1913#(< (mod (+ main_~z~0 2) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1909#(< (mod (+ main_~z~0 1) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,777 INFO L290 TraceCheckUtils]: 27: Hoare triple {1917#(< (mod (+ main_~z~0 3) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1913#(< (mod (+ main_~z~0 2) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,777 INFO L290 TraceCheckUtils]: 26: Hoare triple {1921#(< (mod (+ main_~z~0 4) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1917#(< (mod (+ main_~z~0 3) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,778 INFO L290 TraceCheckUtils]: 25: Hoare triple {1925#(< (mod (+ 5 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1921#(< (mod (+ main_~z~0 4) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,778 INFO L290 TraceCheckUtils]: 24: Hoare triple {1929#(< (mod (+ main_~z~0 6) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1925#(< (mod (+ 5 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,779 INFO L290 TraceCheckUtils]: 23: Hoare triple {1933#(< (mod (+ 7 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1929#(< (mod (+ main_~z~0 6) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,780 INFO L290 TraceCheckUtils]: 22: Hoare triple {1937#(< (mod (+ main_~z~0 8) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1933#(< (mod (+ 7 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,780 INFO L290 TraceCheckUtils]: 21: Hoare triple {1941#(< (mod (+ main_~z~0 9) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1937#(< (mod (+ main_~z~0 8) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,781 INFO L290 TraceCheckUtils]: 20: Hoare triple {1945#(< (mod (+ main_~z~0 10) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1941#(< (mod (+ main_~z~0 9) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,782 INFO L290 TraceCheckUtils]: 19: Hoare triple {1949#(< (mod (+ main_~z~0 11) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1945#(< (mod (+ main_~z~0 10) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,783 INFO L290 TraceCheckUtils]: 18: Hoare triple {1953#(< (mod (+ main_~z~0 12) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1949#(< (mod (+ main_~z~0 11) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,783 INFO L290 TraceCheckUtils]: 17: Hoare triple {1957#(< (mod (+ main_~z~0 13) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1953#(< (mod (+ main_~z~0 12) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,784 INFO L290 TraceCheckUtils]: 16: Hoare triple {1961#(< (mod (+ main_~z~0 14) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1957#(< (mod (+ main_~z~0 13) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,784 INFO L290 TraceCheckUtils]: 15: Hoare triple {1965#(< (mod (+ main_~z~0 15) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1961#(< (mod (+ main_~z~0 14) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,785 INFO L290 TraceCheckUtils]: 14: Hoare triple {1969#(< (mod (+ main_~z~0 16) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1965#(< (mod (+ main_~z~0 15) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,786 INFO L290 TraceCheckUtils]: 13: Hoare triple {1973#(< (mod (+ main_~z~0 17) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1969#(< (mod (+ main_~z~0 16) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,786 INFO L290 TraceCheckUtils]: 12: Hoare triple {1977#(< (mod (+ main_~z~0 18) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1973#(< (mod (+ main_~z~0 17) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,787 INFO L290 TraceCheckUtils]: 11: Hoare triple {1981#(< (mod (+ 19 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1977#(< (mod (+ main_~z~0 18) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,787 INFO L290 TraceCheckUtils]: 10: Hoare triple {1985#(< (mod (+ main_~z~0 20) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1981#(< (mod (+ 19 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,788 INFO L290 TraceCheckUtils]: 9: Hoare triple {1989#(< (mod (+ main_~z~0 21) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1985#(< (mod (+ main_~z~0 20) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,789 INFO L290 TraceCheckUtils]: 8: Hoare triple {1993#(< (mod (+ main_~z~0 22) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {1989#(< (mod (+ main_~z~0 21) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,789 INFO L290 TraceCheckUtils]: 7: Hoare triple {1758#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {1993#(< (mod (+ main_~z~0 22) 4294967296) 268435455)} is VALID [2022-04-27 22:19:16,789 INFO L290 TraceCheckUtils]: 6: Hoare triple {1758#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {1758#true} is VALID [2022-04-27 22:19:16,789 INFO L290 TraceCheckUtils]: 5: Hoare triple {1758#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {1758#true} is VALID [2022-04-27 22:19:16,789 INFO L272 TraceCheckUtils]: 4: Hoare triple {1758#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:16,789 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1758#true} {1758#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:16,789 INFO L290 TraceCheckUtils]: 2: Hoare triple {1758#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:16,790 INFO L290 TraceCheckUtils]: 1: Hoare triple {1758#true} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1758#true} is VALID [2022-04-27 22:19:16,790 INFO L272 TraceCheckUtils]: 0: Hoare triple {1758#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1758#true} is VALID [2022-04-27 22:19:16,790 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:19:16,790 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1134841517] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 22:19:16,790 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 22:19:16,790 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 25, 25] total 50 [2022-04-27 22:19:16,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769151136] [2022-04-27 22:19:16,791 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 22:19:16,791 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 35 [2022-04-27 22:19:16,791 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 22:19:16,792 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:19:16,829 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 63 edges. 63 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:19:16,830 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 50 states [2022-04-27 22:19:16,830 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 22:19:16,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2022-04-27 22:19:16,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=672, Invalid=1778, Unknown=0, NotChecked=0, Total=2450 [2022-04-27 22:19:16,831 INFO L87 Difference]: Start difference. First operand 44 states and 48 transitions. Second operand has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:21:03,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:21:03,980 INFO L93 Difference]: Finished difference Result 106 states and 138 transitions. [2022-04-27 22:21:03,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2022-04-27 22:21:03,981 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 35 [2022-04-27 22:21:03,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 22:21:03,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:21:03,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 114 transitions. [2022-04-27 22:21:03,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:21:03,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 114 transitions. [2022-04-27 22:21:03,984 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 49 states and 114 transitions. [2022-04-27 22:21:04,139 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 114 edges. 114 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:21:04,140 INFO L225 Difference]: With dead ends: 106 [2022-04-27 22:21:04,140 INFO L226 Difference]: Without dead ends: 69 [2022-04-27 22:21:04,142 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 49 SyntacticMatches, 1 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1111 ImplicationChecksByTransitivity, 106.2s TimeCoverageRelationStatistics Valid=2442, Invalid=6677, Unknown=1, NotChecked=0, Total=9120 [2022-04-27 22:21:04,142 INFO L413 NwaCegarLoop]: 21 mSDtfsCounter, 17 mSDsluCounter, 132 mSDsCounter, 0 mSdLazyCounter, 1034 mSolverCounterSat, 125 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 19 SdHoareTripleChecker+Valid, 153 SdHoareTripleChecker+Invalid, 1159 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 125 IncrementalHoareTripleChecker+Valid, 1034 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-04-27 22:21:04,142 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [19 Valid, 153 Invalid, 1159 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [125 Valid, 1034 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-04-27 22:21:04,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2022-04-27 22:21:04,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 68. [2022-04-27 22:21:04,221 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 22:21:04,221 INFO L82 GeneralOperation]: Start isEquivalent. First operand 69 states. Second operand has 68 states, 60 states have (on average 1.0666666666666667) internal successors, (64), 61 states have internal predecessors, (64), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:21:04,221 INFO L74 IsIncluded]: Start isIncluded. First operand 69 states. Second operand has 68 states, 60 states have (on average 1.0666666666666667) internal successors, (64), 61 states have internal predecessors, (64), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:21:04,222 INFO L87 Difference]: Start difference. First operand 69 states. Second operand has 68 states, 60 states have (on average 1.0666666666666667) internal successors, (64), 61 states have internal predecessors, (64), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:21:04,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:21:04,223 INFO L93 Difference]: Finished difference Result 69 states and 73 transitions. [2022-04-27 22:21:04,223 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 73 transitions. [2022-04-27 22:21:04,223 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:21:04,223 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:21:04,224 INFO L74 IsIncluded]: Start isIncluded. First operand has 68 states, 60 states have (on average 1.0666666666666667) internal successors, (64), 61 states have internal predecessors, (64), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 69 states. [2022-04-27 22:21:04,224 INFO L87 Difference]: Start difference. First operand has 68 states, 60 states have (on average 1.0666666666666667) internal successors, (64), 61 states have internal predecessors, (64), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand 69 states. [2022-04-27 22:21:04,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 22:21:04,225 INFO L93 Difference]: Finished difference Result 69 states and 73 transitions. [2022-04-27 22:21:04,225 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 73 transitions. [2022-04-27 22:21:04,225 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 22:21:04,225 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 22:21:04,225 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 22:21:04,225 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 22:21:04,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 60 states have (on average 1.0666666666666667) internal successors, (64), 61 states have internal predecessors, (64), 5 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 22:21:04,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 72 transitions. [2022-04-27 22:21:04,227 INFO L78 Accepts]: Start accepts. Automaton has 68 states and 72 transitions. Word has length 35 [2022-04-27 22:21:04,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 22:21:04,227 INFO L495 AbstractCegarLoop]: Abstraction has 68 states and 72 transitions. [2022-04-27 22:21:04,227 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:21:04,227 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 72 transitions. [2022-04-27 22:21:04,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2022-04-27 22:21:04,228 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 22:21:04,228 INFO L195 NwaCegarLoop]: trace histogram [46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 22:21:04,244 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-27 22:21:04,439 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 22:21:04,440 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 22:21:04,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 22:21:04,440 INFO L85 PathProgramCache]: Analyzing trace with hash 2089490931, now seen corresponding path program 5 times [2022-04-27 22:21:04,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 22:21:04,440 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550547322] [2022-04-27 22:21:04,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 22:21:04,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 22:21:04,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:21:05,592 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 22:21:05,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:21:05,598 INFO L290 TraceCheckUtils]: 0: Hoare triple {2626#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2574#true} is VALID [2022-04-27 22:21:05,598 INFO L290 TraceCheckUtils]: 1: Hoare triple {2574#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:05,598 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2574#true} {2574#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:05,599 INFO L272 TraceCheckUtils]: 0: Hoare triple {2574#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2626#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 22:21:05,599 INFO L290 TraceCheckUtils]: 1: Hoare triple {2626#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2574#true} is VALID [2022-04-27 22:21:05,599 INFO L290 TraceCheckUtils]: 2: Hoare triple {2574#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:05,599 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2574#true} {2574#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:05,599 INFO L272 TraceCheckUtils]: 4: Hoare triple {2574#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:05,599 INFO L290 TraceCheckUtils]: 5: Hoare triple {2574#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {2574#true} is VALID [2022-04-27 22:21:05,599 INFO L290 TraceCheckUtils]: 6: Hoare triple {2574#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {2574#true} is VALID [2022-04-27 22:21:05,600 INFO L290 TraceCheckUtils]: 7: Hoare triple {2574#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {2579#(= main_~z~0 0)} is VALID [2022-04-27 22:21:05,600 INFO L290 TraceCheckUtils]: 8: Hoare triple {2579#(= main_~z~0 0)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2580#(and (<= main_~z~0 1) (<= 1 main_~z~0))} is VALID [2022-04-27 22:21:05,600 INFO L290 TraceCheckUtils]: 9: Hoare triple {2580#(and (<= main_~z~0 1) (<= 1 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2581#(and (<= main_~z~0 2) (<= 2 main_~z~0))} is VALID [2022-04-27 22:21:05,601 INFO L290 TraceCheckUtils]: 10: Hoare triple {2581#(and (<= main_~z~0 2) (<= 2 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2582#(and (<= main_~z~0 3) (<= 3 main_~z~0))} is VALID [2022-04-27 22:21:05,601 INFO L290 TraceCheckUtils]: 11: Hoare triple {2582#(and (<= main_~z~0 3) (<= 3 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2583#(and (<= 4 main_~z~0) (<= main_~z~0 4))} is VALID [2022-04-27 22:21:05,602 INFO L290 TraceCheckUtils]: 12: Hoare triple {2583#(and (<= 4 main_~z~0) (<= main_~z~0 4))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2584#(and (<= main_~z~0 5) (<= 5 main_~z~0))} is VALID [2022-04-27 22:21:05,602 INFO L290 TraceCheckUtils]: 13: Hoare triple {2584#(and (<= main_~z~0 5) (<= 5 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2585#(and (<= main_~z~0 6) (<= 6 main_~z~0))} is VALID [2022-04-27 22:21:05,603 INFO L290 TraceCheckUtils]: 14: Hoare triple {2585#(and (<= main_~z~0 6) (<= 6 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2586#(and (<= main_~z~0 7) (<= 7 main_~z~0))} is VALID [2022-04-27 22:21:05,603 INFO L290 TraceCheckUtils]: 15: Hoare triple {2586#(and (<= main_~z~0 7) (<= 7 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2587#(and (<= 8 main_~z~0) (<= main_~z~0 8))} is VALID [2022-04-27 22:21:05,604 INFO L290 TraceCheckUtils]: 16: Hoare triple {2587#(and (<= 8 main_~z~0) (<= main_~z~0 8))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2588#(and (<= 9 main_~z~0) (<= main_~z~0 9))} is VALID [2022-04-27 22:21:05,604 INFO L290 TraceCheckUtils]: 17: Hoare triple {2588#(and (<= 9 main_~z~0) (<= main_~z~0 9))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2589#(and (<= main_~z~0 10) (<= 10 main_~z~0))} is VALID [2022-04-27 22:21:05,605 INFO L290 TraceCheckUtils]: 18: Hoare triple {2589#(and (<= main_~z~0 10) (<= 10 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2590#(and (<= main_~z~0 11) (<= 11 main_~z~0))} is VALID [2022-04-27 22:21:05,605 INFO L290 TraceCheckUtils]: 19: Hoare triple {2590#(and (<= main_~z~0 11) (<= 11 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2591#(and (<= main_~z~0 12) (<= 12 main_~z~0))} is VALID [2022-04-27 22:21:05,606 INFO L290 TraceCheckUtils]: 20: Hoare triple {2591#(and (<= main_~z~0 12) (<= 12 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2592#(and (<= 13 main_~z~0) (<= main_~z~0 13))} is VALID [2022-04-27 22:21:05,606 INFO L290 TraceCheckUtils]: 21: Hoare triple {2592#(and (<= 13 main_~z~0) (<= main_~z~0 13))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2593#(and (<= 14 main_~z~0) (<= main_~z~0 14))} is VALID [2022-04-27 22:21:05,607 INFO L290 TraceCheckUtils]: 22: Hoare triple {2593#(and (<= 14 main_~z~0) (<= main_~z~0 14))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2594#(and (<= main_~z~0 15) (<= 15 main_~z~0))} is VALID [2022-04-27 22:21:05,607 INFO L290 TraceCheckUtils]: 23: Hoare triple {2594#(and (<= main_~z~0 15) (<= 15 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2595#(and (<= 16 main_~z~0) (<= main_~z~0 16))} is VALID [2022-04-27 22:21:05,608 INFO L290 TraceCheckUtils]: 24: Hoare triple {2595#(and (<= 16 main_~z~0) (<= main_~z~0 16))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2596#(and (<= 17 main_~z~0) (<= main_~z~0 17))} is VALID [2022-04-27 22:21:05,608 INFO L290 TraceCheckUtils]: 25: Hoare triple {2596#(and (<= 17 main_~z~0) (<= main_~z~0 17))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2597#(and (<= 18 main_~z~0) (<= main_~z~0 18))} is VALID [2022-04-27 22:21:05,609 INFO L290 TraceCheckUtils]: 26: Hoare triple {2597#(and (<= 18 main_~z~0) (<= main_~z~0 18))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2598#(and (<= 19 main_~z~0) (<= main_~z~0 19))} is VALID [2022-04-27 22:21:05,609 INFO L290 TraceCheckUtils]: 27: Hoare triple {2598#(and (<= 19 main_~z~0) (<= main_~z~0 19))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2599#(and (<= main_~z~0 20) (<= 20 main_~z~0))} is VALID [2022-04-27 22:21:05,610 INFO L290 TraceCheckUtils]: 28: Hoare triple {2599#(and (<= main_~z~0 20) (<= 20 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2600#(and (<= main_~z~0 21) (<= 21 main_~z~0))} is VALID [2022-04-27 22:21:05,610 INFO L290 TraceCheckUtils]: 29: Hoare triple {2600#(and (<= main_~z~0 21) (<= 21 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2601#(and (<= 22 main_~z~0) (<= main_~z~0 22))} is VALID [2022-04-27 22:21:05,611 INFO L290 TraceCheckUtils]: 30: Hoare triple {2601#(and (<= 22 main_~z~0) (<= main_~z~0 22))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2602#(and (<= 23 main_~z~0) (<= main_~z~0 23))} is VALID [2022-04-27 22:21:05,616 INFO L290 TraceCheckUtils]: 31: Hoare triple {2602#(and (<= 23 main_~z~0) (<= main_~z~0 23))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2603#(and (<= main_~z~0 24) (<= 24 main_~z~0))} is VALID [2022-04-27 22:21:05,616 INFO L290 TraceCheckUtils]: 32: Hoare triple {2603#(and (<= main_~z~0 24) (<= 24 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2604#(and (<= 25 main_~z~0) (<= main_~z~0 25))} is VALID [2022-04-27 22:21:05,619 INFO L290 TraceCheckUtils]: 33: Hoare triple {2604#(and (<= 25 main_~z~0) (<= main_~z~0 25))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2605#(and (<= main_~z~0 26) (<= 26 main_~z~0))} is VALID [2022-04-27 22:21:05,621 INFO L290 TraceCheckUtils]: 34: Hoare triple {2605#(and (<= main_~z~0 26) (<= 26 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2606#(and (<= main_~z~0 27) (<= 27 main_~z~0))} is VALID [2022-04-27 22:21:05,621 INFO L290 TraceCheckUtils]: 35: Hoare triple {2606#(and (<= main_~z~0 27) (<= 27 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2607#(and (<= 28 main_~z~0) (<= main_~z~0 28))} is VALID [2022-04-27 22:21:05,623 INFO L290 TraceCheckUtils]: 36: Hoare triple {2607#(and (<= 28 main_~z~0) (<= main_~z~0 28))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2608#(and (<= main_~z~0 29) (<= 29 main_~z~0))} is VALID [2022-04-27 22:21:05,624 INFO L290 TraceCheckUtils]: 37: Hoare triple {2608#(and (<= main_~z~0 29) (<= 29 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2609#(and (<= 30 main_~z~0) (<= main_~z~0 30))} is VALID [2022-04-27 22:21:05,624 INFO L290 TraceCheckUtils]: 38: Hoare triple {2609#(and (<= 30 main_~z~0) (<= main_~z~0 30))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2610#(and (<= 31 main_~z~0) (<= main_~z~0 31))} is VALID [2022-04-27 22:21:05,625 INFO L290 TraceCheckUtils]: 39: Hoare triple {2610#(and (<= 31 main_~z~0) (<= main_~z~0 31))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2611#(and (<= 32 main_~z~0) (<= main_~z~0 32))} is VALID [2022-04-27 22:21:05,626 INFO L290 TraceCheckUtils]: 40: Hoare triple {2611#(and (<= 32 main_~z~0) (<= main_~z~0 32))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2612#(and (<= 33 main_~z~0) (<= main_~z~0 33))} is VALID [2022-04-27 22:21:05,626 INFO L290 TraceCheckUtils]: 41: Hoare triple {2612#(and (<= 33 main_~z~0) (<= main_~z~0 33))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2613#(and (<= main_~z~0 34) (<= 34 main_~z~0))} is VALID [2022-04-27 22:21:05,627 INFO L290 TraceCheckUtils]: 42: Hoare triple {2613#(and (<= main_~z~0 34) (<= 34 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2614#(and (<= main_~z~0 35) (<= 35 main_~z~0))} is VALID [2022-04-27 22:21:05,627 INFO L290 TraceCheckUtils]: 43: Hoare triple {2614#(and (<= main_~z~0 35) (<= 35 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2615#(and (<= 36 main_~z~0) (<= main_~z~0 36))} is VALID [2022-04-27 22:21:05,628 INFO L290 TraceCheckUtils]: 44: Hoare triple {2615#(and (<= 36 main_~z~0) (<= main_~z~0 36))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2616#(and (<= 37 main_~z~0) (<= main_~z~0 37))} is VALID [2022-04-27 22:21:05,628 INFO L290 TraceCheckUtils]: 45: Hoare triple {2616#(and (<= 37 main_~z~0) (<= main_~z~0 37))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2617#(and (<= main_~z~0 38) (<= 38 main_~z~0))} is VALID [2022-04-27 22:21:05,628 INFO L290 TraceCheckUtils]: 46: Hoare triple {2617#(and (<= main_~z~0 38) (<= 38 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2618#(and (<= main_~z~0 39) (<= 39 main_~z~0))} is VALID [2022-04-27 22:21:05,629 INFO L290 TraceCheckUtils]: 47: Hoare triple {2618#(and (<= main_~z~0 39) (<= 39 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2619#(and (<= main_~z~0 40) (<= 40 main_~z~0))} is VALID [2022-04-27 22:21:05,629 INFO L290 TraceCheckUtils]: 48: Hoare triple {2619#(and (<= main_~z~0 40) (<= 40 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2620#(and (<= main_~z~0 41) (<= 41 main_~z~0))} is VALID [2022-04-27 22:21:05,630 INFO L290 TraceCheckUtils]: 49: Hoare triple {2620#(and (<= main_~z~0 41) (<= 41 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2621#(and (<= 42 main_~z~0) (<= main_~z~0 42))} is VALID [2022-04-27 22:21:05,630 INFO L290 TraceCheckUtils]: 50: Hoare triple {2621#(and (<= 42 main_~z~0) (<= main_~z~0 42))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2622#(and (<= main_~z~0 43) (<= 43 main_~z~0))} is VALID [2022-04-27 22:21:05,631 INFO L290 TraceCheckUtils]: 51: Hoare triple {2622#(and (<= main_~z~0 43) (<= 43 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2623#(and (<= main_~z~0 44) (<= 44 main_~z~0))} is VALID [2022-04-27 22:21:05,631 INFO L290 TraceCheckUtils]: 52: Hoare triple {2623#(and (<= main_~z~0 44) (<= 44 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2624#(and (<= main_~z~0 45) (<= 45 main_~z~0))} is VALID [2022-04-27 22:21:05,632 INFO L290 TraceCheckUtils]: 53: Hoare triple {2624#(and (<= main_~z~0 45) (<= 45 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2625#(and (<= main_~z~0 46) (not (<= (+ (div main_~z~0 4294967296) 1) 0)))} is VALID [2022-04-27 22:21:05,632 INFO L290 TraceCheckUtils]: 54: Hoare triple {2625#(and (<= main_~z~0 46) (not (<= (+ (div main_~z~0 4294967296) 1) 0)))} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {2575#false} is VALID [2022-04-27 22:21:05,632 INFO L272 TraceCheckUtils]: 55: Hoare triple {2575#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {2575#false} is VALID [2022-04-27 22:21:05,632 INFO L290 TraceCheckUtils]: 56: Hoare triple {2575#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2575#false} is VALID [2022-04-27 22:21:05,632 INFO L290 TraceCheckUtils]: 57: Hoare triple {2575#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2575#false} is VALID [2022-04-27 22:21:05,633 INFO L290 TraceCheckUtils]: 58: Hoare triple {2575#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2575#false} is VALID [2022-04-27 22:21:05,633 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:21:05,633 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 22:21:05,633 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [550547322] [2022-04-27 22:21:05,633 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [550547322] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 22:21:05,634 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1142436185] [2022-04-27 22:21:05,634 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-04-27 22:21:05,634 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 22:21:05,634 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 22:21:05,635 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 22:21:05,635 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 22:21:34,510 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2022-04-27 22:21:34,511 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 22:21:34,524 INFO L263 TraceCheckSpWp]: Trace formula consists of 201 conjuncts, 95 conjunts are in the unsatisfiable core [2022-04-27 22:21:34,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 22:21:34,538 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 22:21:35,198 INFO L272 TraceCheckUtils]: 0: Hoare triple {2574#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:35,198 INFO L290 TraceCheckUtils]: 1: Hoare triple {2574#true} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2574#true} is VALID [2022-04-27 22:21:35,198 INFO L290 TraceCheckUtils]: 2: Hoare triple {2574#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:35,199 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2574#true} {2574#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:35,199 INFO L272 TraceCheckUtils]: 4: Hoare triple {2574#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:35,199 INFO L290 TraceCheckUtils]: 5: Hoare triple {2574#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {2574#true} is VALID [2022-04-27 22:21:35,199 INFO L290 TraceCheckUtils]: 6: Hoare triple {2574#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {2574#true} is VALID [2022-04-27 22:21:35,204 INFO L290 TraceCheckUtils]: 7: Hoare triple {2574#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {2579#(= main_~z~0 0)} is VALID [2022-04-27 22:21:35,205 INFO L290 TraceCheckUtils]: 8: Hoare triple {2579#(= main_~z~0 0)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2580#(and (<= main_~z~0 1) (<= 1 main_~z~0))} is VALID [2022-04-27 22:21:35,205 INFO L290 TraceCheckUtils]: 9: Hoare triple {2580#(and (<= main_~z~0 1) (<= 1 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2581#(and (<= main_~z~0 2) (<= 2 main_~z~0))} is VALID [2022-04-27 22:21:35,206 INFO L290 TraceCheckUtils]: 10: Hoare triple {2581#(and (<= main_~z~0 2) (<= 2 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2582#(and (<= main_~z~0 3) (<= 3 main_~z~0))} is VALID [2022-04-27 22:21:35,206 INFO L290 TraceCheckUtils]: 11: Hoare triple {2582#(and (<= main_~z~0 3) (<= 3 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2583#(and (<= 4 main_~z~0) (<= main_~z~0 4))} is VALID [2022-04-27 22:21:35,207 INFO L290 TraceCheckUtils]: 12: Hoare triple {2583#(and (<= 4 main_~z~0) (<= main_~z~0 4))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2584#(and (<= main_~z~0 5) (<= 5 main_~z~0))} is VALID [2022-04-27 22:21:35,207 INFO L290 TraceCheckUtils]: 13: Hoare triple {2584#(and (<= main_~z~0 5) (<= 5 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2585#(and (<= main_~z~0 6) (<= 6 main_~z~0))} is VALID [2022-04-27 22:21:35,208 INFO L290 TraceCheckUtils]: 14: Hoare triple {2585#(and (<= main_~z~0 6) (<= 6 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2586#(and (<= main_~z~0 7) (<= 7 main_~z~0))} is VALID [2022-04-27 22:21:35,208 INFO L290 TraceCheckUtils]: 15: Hoare triple {2586#(and (<= main_~z~0 7) (<= 7 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2587#(and (<= 8 main_~z~0) (<= main_~z~0 8))} is VALID [2022-04-27 22:21:35,210 INFO L290 TraceCheckUtils]: 16: Hoare triple {2587#(and (<= 8 main_~z~0) (<= main_~z~0 8))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2588#(and (<= 9 main_~z~0) (<= main_~z~0 9))} is VALID [2022-04-27 22:21:35,210 INFO L290 TraceCheckUtils]: 17: Hoare triple {2588#(and (<= 9 main_~z~0) (<= main_~z~0 9))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2589#(and (<= main_~z~0 10) (<= 10 main_~z~0))} is VALID [2022-04-27 22:21:35,211 INFO L290 TraceCheckUtils]: 18: Hoare triple {2589#(and (<= main_~z~0 10) (<= 10 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2590#(and (<= main_~z~0 11) (<= 11 main_~z~0))} is VALID [2022-04-27 22:21:35,211 INFO L290 TraceCheckUtils]: 19: Hoare triple {2590#(and (<= main_~z~0 11) (<= 11 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2591#(and (<= main_~z~0 12) (<= 12 main_~z~0))} is VALID [2022-04-27 22:21:35,212 INFO L290 TraceCheckUtils]: 20: Hoare triple {2591#(and (<= main_~z~0 12) (<= 12 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2592#(and (<= 13 main_~z~0) (<= main_~z~0 13))} is VALID [2022-04-27 22:21:35,212 INFO L290 TraceCheckUtils]: 21: Hoare triple {2592#(and (<= 13 main_~z~0) (<= main_~z~0 13))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2593#(and (<= 14 main_~z~0) (<= main_~z~0 14))} is VALID [2022-04-27 22:21:35,213 INFO L290 TraceCheckUtils]: 22: Hoare triple {2593#(and (<= 14 main_~z~0) (<= main_~z~0 14))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2594#(and (<= main_~z~0 15) (<= 15 main_~z~0))} is VALID [2022-04-27 22:21:35,213 INFO L290 TraceCheckUtils]: 23: Hoare triple {2594#(and (<= main_~z~0 15) (<= 15 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2595#(and (<= 16 main_~z~0) (<= main_~z~0 16))} is VALID [2022-04-27 22:21:35,214 INFO L290 TraceCheckUtils]: 24: Hoare triple {2595#(and (<= 16 main_~z~0) (<= main_~z~0 16))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2596#(and (<= 17 main_~z~0) (<= main_~z~0 17))} is VALID [2022-04-27 22:21:35,218 INFO L290 TraceCheckUtils]: 25: Hoare triple {2596#(and (<= 17 main_~z~0) (<= main_~z~0 17))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2597#(and (<= 18 main_~z~0) (<= main_~z~0 18))} is VALID [2022-04-27 22:21:35,219 INFO L290 TraceCheckUtils]: 26: Hoare triple {2597#(and (<= 18 main_~z~0) (<= main_~z~0 18))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2598#(and (<= 19 main_~z~0) (<= main_~z~0 19))} is VALID [2022-04-27 22:21:35,219 INFO L290 TraceCheckUtils]: 27: Hoare triple {2598#(and (<= 19 main_~z~0) (<= main_~z~0 19))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2599#(and (<= main_~z~0 20) (<= 20 main_~z~0))} is VALID [2022-04-27 22:21:35,220 INFO L290 TraceCheckUtils]: 28: Hoare triple {2599#(and (<= main_~z~0 20) (<= 20 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2600#(and (<= main_~z~0 21) (<= 21 main_~z~0))} is VALID [2022-04-27 22:21:35,220 INFO L290 TraceCheckUtils]: 29: Hoare triple {2600#(and (<= main_~z~0 21) (<= 21 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2601#(and (<= 22 main_~z~0) (<= main_~z~0 22))} is VALID [2022-04-27 22:21:35,221 INFO L290 TraceCheckUtils]: 30: Hoare triple {2601#(and (<= 22 main_~z~0) (<= main_~z~0 22))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2602#(and (<= 23 main_~z~0) (<= main_~z~0 23))} is VALID [2022-04-27 22:21:35,221 INFO L290 TraceCheckUtils]: 31: Hoare triple {2602#(and (<= 23 main_~z~0) (<= main_~z~0 23))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2603#(and (<= main_~z~0 24) (<= 24 main_~z~0))} is VALID [2022-04-27 22:21:35,222 INFO L290 TraceCheckUtils]: 32: Hoare triple {2603#(and (<= main_~z~0 24) (<= 24 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2604#(and (<= 25 main_~z~0) (<= main_~z~0 25))} is VALID [2022-04-27 22:21:35,222 INFO L290 TraceCheckUtils]: 33: Hoare triple {2604#(and (<= 25 main_~z~0) (<= main_~z~0 25))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2605#(and (<= main_~z~0 26) (<= 26 main_~z~0))} is VALID [2022-04-27 22:21:35,223 INFO L290 TraceCheckUtils]: 34: Hoare triple {2605#(and (<= main_~z~0 26) (<= 26 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2606#(and (<= main_~z~0 27) (<= 27 main_~z~0))} is VALID [2022-04-27 22:21:35,223 INFO L290 TraceCheckUtils]: 35: Hoare triple {2606#(and (<= main_~z~0 27) (<= 27 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2607#(and (<= 28 main_~z~0) (<= main_~z~0 28))} is VALID [2022-04-27 22:21:35,224 INFO L290 TraceCheckUtils]: 36: Hoare triple {2607#(and (<= 28 main_~z~0) (<= main_~z~0 28))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2608#(and (<= main_~z~0 29) (<= 29 main_~z~0))} is VALID [2022-04-27 22:21:35,224 INFO L290 TraceCheckUtils]: 37: Hoare triple {2608#(and (<= main_~z~0 29) (<= 29 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2609#(and (<= 30 main_~z~0) (<= main_~z~0 30))} is VALID [2022-04-27 22:21:35,225 INFO L290 TraceCheckUtils]: 38: Hoare triple {2609#(and (<= 30 main_~z~0) (<= main_~z~0 30))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2610#(and (<= 31 main_~z~0) (<= main_~z~0 31))} is VALID [2022-04-27 22:21:35,225 INFO L290 TraceCheckUtils]: 39: Hoare triple {2610#(and (<= 31 main_~z~0) (<= main_~z~0 31))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2611#(and (<= 32 main_~z~0) (<= main_~z~0 32))} is VALID [2022-04-27 22:21:35,225 INFO L290 TraceCheckUtils]: 40: Hoare triple {2611#(and (<= 32 main_~z~0) (<= main_~z~0 32))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2612#(and (<= 33 main_~z~0) (<= main_~z~0 33))} is VALID [2022-04-27 22:21:35,226 INFO L290 TraceCheckUtils]: 41: Hoare triple {2612#(and (<= 33 main_~z~0) (<= main_~z~0 33))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2613#(and (<= main_~z~0 34) (<= 34 main_~z~0))} is VALID [2022-04-27 22:21:35,226 INFO L290 TraceCheckUtils]: 42: Hoare triple {2613#(and (<= main_~z~0 34) (<= 34 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2614#(and (<= main_~z~0 35) (<= 35 main_~z~0))} is VALID [2022-04-27 22:21:35,227 INFO L290 TraceCheckUtils]: 43: Hoare triple {2614#(and (<= main_~z~0 35) (<= 35 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2615#(and (<= 36 main_~z~0) (<= main_~z~0 36))} is VALID [2022-04-27 22:21:35,227 INFO L290 TraceCheckUtils]: 44: Hoare triple {2615#(and (<= 36 main_~z~0) (<= main_~z~0 36))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2616#(and (<= 37 main_~z~0) (<= main_~z~0 37))} is VALID [2022-04-27 22:21:35,228 INFO L290 TraceCheckUtils]: 45: Hoare triple {2616#(and (<= 37 main_~z~0) (<= main_~z~0 37))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2617#(and (<= main_~z~0 38) (<= 38 main_~z~0))} is VALID [2022-04-27 22:21:35,228 INFO L290 TraceCheckUtils]: 46: Hoare triple {2617#(and (<= main_~z~0 38) (<= 38 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2618#(and (<= main_~z~0 39) (<= 39 main_~z~0))} is VALID [2022-04-27 22:21:35,231 INFO L290 TraceCheckUtils]: 47: Hoare triple {2618#(and (<= main_~z~0 39) (<= 39 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2619#(and (<= main_~z~0 40) (<= 40 main_~z~0))} is VALID [2022-04-27 22:21:35,231 INFO L290 TraceCheckUtils]: 48: Hoare triple {2619#(and (<= main_~z~0 40) (<= 40 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2620#(and (<= main_~z~0 41) (<= 41 main_~z~0))} is VALID [2022-04-27 22:21:35,232 INFO L290 TraceCheckUtils]: 49: Hoare triple {2620#(and (<= main_~z~0 41) (<= 41 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2621#(and (<= 42 main_~z~0) (<= main_~z~0 42))} is VALID [2022-04-27 22:21:35,232 INFO L290 TraceCheckUtils]: 50: Hoare triple {2621#(and (<= 42 main_~z~0) (<= main_~z~0 42))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2622#(and (<= main_~z~0 43) (<= 43 main_~z~0))} is VALID [2022-04-27 22:21:35,233 INFO L290 TraceCheckUtils]: 51: Hoare triple {2622#(and (<= main_~z~0 43) (<= 43 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2623#(and (<= main_~z~0 44) (<= 44 main_~z~0))} is VALID [2022-04-27 22:21:35,233 INFO L290 TraceCheckUtils]: 52: Hoare triple {2623#(and (<= main_~z~0 44) (<= 44 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2624#(and (<= main_~z~0 45) (<= 45 main_~z~0))} is VALID [2022-04-27 22:21:35,234 INFO L290 TraceCheckUtils]: 53: Hoare triple {2624#(and (<= main_~z~0 45) (<= 45 main_~z~0))} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2789#(and (<= 46 main_~z~0) (<= main_~z~0 46))} is VALID [2022-04-27 22:21:35,234 INFO L290 TraceCheckUtils]: 54: Hoare triple {2789#(and (<= 46 main_~z~0) (<= main_~z~0 46))} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {2575#false} is VALID [2022-04-27 22:21:35,234 INFO L272 TraceCheckUtils]: 55: Hoare triple {2575#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {2575#false} is VALID [2022-04-27 22:21:35,234 INFO L290 TraceCheckUtils]: 56: Hoare triple {2575#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2575#false} is VALID [2022-04-27 22:21:35,234 INFO L290 TraceCheckUtils]: 57: Hoare triple {2575#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2575#false} is VALID [2022-04-27 22:21:35,234 INFO L290 TraceCheckUtils]: 58: Hoare triple {2575#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2575#false} is VALID [2022-04-27 22:21:35,235 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:21:35,235 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 22:21:38,432 INFO L290 TraceCheckUtils]: 58: Hoare triple {2575#false} [96] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2575#false} is VALID [2022-04-27 22:21:38,433 INFO L290 TraceCheckUtils]: 57: Hoare triple {2575#false} [92] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2575#false} is VALID [2022-04-27 22:21:38,433 INFO L290 TraceCheckUtils]: 56: Hoare triple {2575#false} [86] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2575#false} is VALID [2022-04-27 22:21:38,433 INFO L272 TraceCheckUtils]: 55: Hoare triple {2575#false} [95] L24-3-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~z~0_7 4) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~z~0=v_main_~z~0_7} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~z~0] {2575#false} is VALID [2022-04-27 22:21:38,433 INFO L290 TraceCheckUtils]: 54: Hoare triple {2817#(< (mod main_~z~0 4294967296) 268435455)} [89] L24-2-->L24-3: Formula: (not (< (mod v_main_~z~0_1 4294967296) 268435455)) InVars {main_~z~0=v_main_~z~0_1} OutVars{main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[] {2575#false} is VALID [2022-04-27 22:21:38,434 INFO L290 TraceCheckUtils]: 53: Hoare triple {2821#(< (mod (+ main_~z~0 1) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2817#(< (mod main_~z~0 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,434 INFO L290 TraceCheckUtils]: 52: Hoare triple {2825#(< (mod (+ main_~z~0 2) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2821#(< (mod (+ main_~z~0 1) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,435 INFO L290 TraceCheckUtils]: 51: Hoare triple {2829#(< (mod (+ main_~z~0 3) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2825#(< (mod (+ main_~z~0 2) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,435 INFO L290 TraceCheckUtils]: 50: Hoare triple {2833#(< (mod (+ main_~z~0 4) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2829#(< (mod (+ main_~z~0 3) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,437 INFO L290 TraceCheckUtils]: 49: Hoare triple {2837#(< (mod (+ 5 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2833#(< (mod (+ main_~z~0 4) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,438 INFO L290 TraceCheckUtils]: 48: Hoare triple {2841#(< (mod (+ main_~z~0 6) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2837#(< (mod (+ 5 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,439 INFO L290 TraceCheckUtils]: 47: Hoare triple {2845#(< (mod (+ 7 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2841#(< (mod (+ main_~z~0 6) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,439 INFO L290 TraceCheckUtils]: 46: Hoare triple {2849#(< (mod (+ main_~z~0 8) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2845#(< (mod (+ 7 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,440 INFO L290 TraceCheckUtils]: 45: Hoare triple {2853#(< (mod (+ main_~z~0 9) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2849#(< (mod (+ main_~z~0 8) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,440 INFO L290 TraceCheckUtils]: 44: Hoare triple {2857#(< (mod (+ main_~z~0 10) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2853#(< (mod (+ main_~z~0 9) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,441 INFO L290 TraceCheckUtils]: 43: Hoare triple {2861#(< (mod (+ main_~z~0 11) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2857#(< (mod (+ main_~z~0 10) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,441 INFO L290 TraceCheckUtils]: 42: Hoare triple {2865#(< (mod (+ main_~z~0 12) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2861#(< (mod (+ main_~z~0 11) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,442 INFO L290 TraceCheckUtils]: 41: Hoare triple {2869#(< (mod (+ main_~z~0 13) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2865#(< (mod (+ main_~z~0 12) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,443 INFO L290 TraceCheckUtils]: 40: Hoare triple {2873#(< (mod (+ main_~z~0 14) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2869#(< (mod (+ main_~z~0 13) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,443 INFO L290 TraceCheckUtils]: 39: Hoare triple {2877#(< (mod (+ main_~z~0 15) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2873#(< (mod (+ main_~z~0 14) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,444 INFO L290 TraceCheckUtils]: 38: Hoare triple {2881#(< (mod (+ main_~z~0 16) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2877#(< (mod (+ main_~z~0 15) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,444 INFO L290 TraceCheckUtils]: 37: Hoare triple {2885#(< (mod (+ main_~z~0 17) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2881#(< (mod (+ main_~z~0 16) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,445 INFO L290 TraceCheckUtils]: 36: Hoare triple {2889#(< (mod (+ main_~z~0 18) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2885#(< (mod (+ main_~z~0 17) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,445 INFO L290 TraceCheckUtils]: 35: Hoare triple {2893#(< (mod (+ 19 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2889#(< (mod (+ main_~z~0 18) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,446 INFO L290 TraceCheckUtils]: 34: Hoare triple {2897#(< (mod (+ main_~z~0 20) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2893#(< (mod (+ 19 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,446 INFO L290 TraceCheckUtils]: 33: Hoare triple {2901#(< (mod (+ main_~z~0 21) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2897#(< (mod (+ main_~z~0 20) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,447 INFO L290 TraceCheckUtils]: 32: Hoare triple {2905#(< (mod (+ main_~z~0 22) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2901#(< (mod (+ main_~z~0 21) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,448 INFO L290 TraceCheckUtils]: 31: Hoare triple {2909#(< (mod (+ 23 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2905#(< (mod (+ main_~z~0 22) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,448 INFO L290 TraceCheckUtils]: 30: Hoare triple {2913#(< (mod (+ main_~z~0 24) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2909#(< (mod (+ 23 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,449 INFO L290 TraceCheckUtils]: 29: Hoare triple {2917#(< (mod (+ main_~z~0 25) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2913#(< (mod (+ main_~z~0 24) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,449 INFO L290 TraceCheckUtils]: 28: Hoare triple {2921#(< (mod (+ main_~z~0 26) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2917#(< (mod (+ main_~z~0 25) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,450 INFO L290 TraceCheckUtils]: 27: Hoare triple {2925#(< (mod (+ main_~z~0 27) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2921#(< (mod (+ main_~z~0 26) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,450 INFO L290 TraceCheckUtils]: 26: Hoare triple {2929#(< (mod (+ main_~z~0 28) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2925#(< (mod (+ main_~z~0 27) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,451 INFO L290 TraceCheckUtils]: 25: Hoare triple {2933#(< (mod (+ 29 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2929#(< (mod (+ main_~z~0 28) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,452 INFO L290 TraceCheckUtils]: 24: Hoare triple {2937#(< (mod (+ 30 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2933#(< (mod (+ 29 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,452 INFO L290 TraceCheckUtils]: 23: Hoare triple {2941#(< (mod (+ main_~z~0 31) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2937#(< (mod (+ 30 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,453 INFO L290 TraceCheckUtils]: 22: Hoare triple {2945#(< (mod (+ 32 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2941#(< (mod (+ main_~z~0 31) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,453 INFO L290 TraceCheckUtils]: 21: Hoare triple {2949#(< (mod (+ main_~z~0 33) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2945#(< (mod (+ 32 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,454 INFO L290 TraceCheckUtils]: 20: Hoare triple {2953#(< (mod (+ main_~z~0 34) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2949#(< (mod (+ main_~z~0 33) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,454 INFO L290 TraceCheckUtils]: 19: Hoare triple {2957#(< (mod (+ 35 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2953#(< (mod (+ main_~z~0 34) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,455 INFO L290 TraceCheckUtils]: 18: Hoare triple {2961#(< (mod (+ main_~z~0 36) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2957#(< (mod (+ 35 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,456 INFO L290 TraceCheckUtils]: 17: Hoare triple {2965#(< (mod (+ main_~z~0 37) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2961#(< (mod (+ main_~z~0 36) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,456 INFO L290 TraceCheckUtils]: 16: Hoare triple {2969#(< (mod (+ main_~z~0 38) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2965#(< (mod (+ main_~z~0 37) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,457 INFO L290 TraceCheckUtils]: 15: Hoare triple {2973#(< (mod (+ main_~z~0 39) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2969#(< (mod (+ main_~z~0 38) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,457 INFO L290 TraceCheckUtils]: 14: Hoare triple {2977#(< (mod (+ 40 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2973#(< (mod (+ main_~z~0 39) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,459 INFO L290 TraceCheckUtils]: 13: Hoare triple {2981#(< (mod (+ 41 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2977#(< (mod (+ 40 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,460 INFO L290 TraceCheckUtils]: 12: Hoare triple {2985#(< (mod (+ 42 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2981#(< (mod (+ 41 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,461 INFO L290 TraceCheckUtils]: 11: Hoare triple {2989#(< (mod (+ main_~z~0 43) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2985#(< (mod (+ 42 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,461 INFO L290 TraceCheckUtils]: 10: Hoare triple {2993#(< (mod (+ 44 main_~z~0) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2989#(< (mod (+ main_~z~0 43) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,463 INFO L290 TraceCheckUtils]: 9: Hoare triple {2997#(< (mod (+ main_~z~0 45) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2993#(< (mod (+ 44 main_~z~0) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,463 INFO L290 TraceCheckUtils]: 8: Hoare triple {3001#(< (mod (+ main_~z~0 46) 4294967296) 268435455)} [90] L24-2-->L24-2: Formula: (and (< (mod v_main_~z~0_3 4294967296) 268435455) (= (+ v_main_~z~0_3 1) v_main_~z~0_2)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~z~0, main_#t~post4] {2997#(< (mod (+ main_~z~0 45) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,464 INFO L290 TraceCheckUtils]: 7: Hoare triple {2574#true} [84] L22-2-->L24-2: Formula: (and (< (mod v_main_~y~0_7 4294967296) 268435455) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_7} OutVars{main_~y~0=v_main_~y~0_7, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {3001#(< (mod (+ main_~z~0 46) 4294967296) 268435455)} is VALID [2022-04-27 22:21:38,464 INFO L290 TraceCheckUtils]: 6: Hoare triple {2574#true} [80] L19-2-->L22-2: Formula: (and (< (mod v_main_~x~0_5 4294967296) 268435455) (= v_main_~y~0_5 0)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5, main_~y~0=v_main_~y~0_5} AuxVars[] AssignedVars[main_~y~0] {2574#true} is VALID [2022-04-27 22:21:38,464 INFO L290 TraceCheckUtils]: 5: Hoare triple {2574#true} [76] mainENTRY-->L19-2: Formula: (and (= v_main_~w~0_1 0) (= v_main_~x~0_1 0) (= v_main_~z~0_5 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~w~0=v_main_~w~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[main_~w~0, main_~x~0, main_~z~0, main_~y~0] {2574#true} is VALID [2022-04-27 22:21:38,464 INFO L272 TraceCheckUtils]: 4: Hoare triple {2574#true} [73] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:38,464 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2574#true} {2574#true} [100] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:38,464 INFO L290 TraceCheckUtils]: 2: Hoare triple {2574#true} [77] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:38,464 INFO L290 TraceCheckUtils]: 1: Hoare triple {2574#true} [74] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2574#true} is VALID [2022-04-27 22:21:38,464 INFO L272 TraceCheckUtils]: 0: Hoare triple {2574#true} [72] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2574#true} is VALID [2022-04-27 22:21:38,465 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 22:21:38,465 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1142436185] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 22:21:38,465 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 22:21:38,465 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 49, 49] total 98 [2022-04-27 22:21:38,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1459792102] [2022-04-27 22:21:38,465 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 22:21:38,466 INFO L78 Accepts]: Start accepts. Automaton has has 98 states, 98 states have (on average 1.0816326530612246) internal successors, (106), 97 states have internal predecessors, (106), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 59 [2022-04-27 22:21:38,466 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 22:21:38,467 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 98 states, 98 states have (on average 1.0816326530612246) internal successors, (106), 97 states have internal predecessors, (106), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:21:38,532 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 111 edges. 111 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 22:21:38,532 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 98 states [2022-04-27 22:21:38,532 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 22:21:38,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2022-04-27 22:21:38,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2496, Invalid=7010, Unknown=0, NotChecked=0, Total=9506 [2022-04-27 22:21:38,536 INFO L87 Difference]: Start difference. First operand 68 states and 72 transitions. Second operand has 98 states, 98 states have (on average 1.0816326530612246) internal successors, (106), 97 states have internal predecessors, (106), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 22:22:29,656 WARN L232 SmtUtils]: Spent 12.23s on a formula simplification. DAG size of input: 196 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 22:22:31,698 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (< (mod (+ 11 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 39 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 9 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 8 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 23 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 37 c_main_~z~0) 4294967296) 268435455) (< (mod (+ c_main_~z~0 27) 4294967296) 268435455) (< (mod (+ 13 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 21 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 34 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 30 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 44 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 33 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 41 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 43 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 35 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 36 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 25 c_main_~z~0) 4294967296) 268435455) (< (mod c_main_~z~0 4294967296) 268435455) (< (mod (+ 2 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 31 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 38 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 42 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 45 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 15 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 32 c_main_~z~0) 4294967296) 268435455) (< (mod (+ c_main_~z~0 24) 4294967296) 268435455) (< (mod (+ 6 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 4 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 16 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 5 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 10 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 28 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 19 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 40 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 22 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 14 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 26 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 18 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 12 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 3 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 20 c_main_~z~0) 4294967296) 268435455) (= |c_#NULL.offset| |c_old(#NULL.offset)|) (< (mod (+ 17 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 29 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 7 c_main_~z~0) 4294967296) 268435455) (< (mod (+ c_main_~z~0 1) 4294967296) 268435455)) is different from false [2022-04-27 22:23:24,630 WARN L232 SmtUtils]: Spent 10.45s on a formula simplification. DAG size of input: 182 DAG size of output: 10 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 22:23:26,688 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (< (mod (+ 11 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 39 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 9 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 8 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 23 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 37 c_main_~z~0) 4294967296) 268435455) (< (mod (+ c_main_~z~0 27) 4294967296) 268435455) (< (mod (+ 13 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 21 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 34 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 30 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 33 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 41 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 43 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 35 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 36 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 25 c_main_~z~0) 4294967296) 268435455) (< (mod c_main_~z~0 4294967296) 268435455) (< (mod (+ 2 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 31 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 38 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 42 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 15 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 32 c_main_~z~0) 4294967296) 268435455) (< (mod (+ c_main_~z~0 24) 4294967296) 268435455) (< (mod (+ 6 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 4 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 16 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 5 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 10 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 28 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 19 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 40 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 22 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 14 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 26 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 18 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 12 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 3 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 20 c_main_~z~0) 4294967296) 268435455) (= |c_#NULL.offset| |c_old(#NULL.offset)|) (< (mod (+ 17 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 29 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 7 c_main_~z~0) 4294967296) 268435455) (< (mod (+ c_main_~z~0 1) 4294967296) 268435455)) is different from false [2022-04-27 22:24:16,741 WARN L232 SmtUtils]: Spent 5.71s on a formula simplification. DAG size of input: 174 DAG size of output: 10 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 22:24:18,788 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (< (mod (+ 11 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 39 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 9 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 8 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 23 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 37 c_main_~z~0) 4294967296) 268435455) (< (mod (+ c_main_~z~0 27) 4294967296) 268435455) (< (mod (+ 13 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 21 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 34 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 30 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 33 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 41 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 35 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 36 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 25 c_main_~z~0) 4294967296) 268435455) (< (mod c_main_~z~0 4294967296) 268435455) (< (mod (+ 2 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 31 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 38 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 15 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 32 c_main_~z~0) 4294967296) 268435455) (< (mod (+ c_main_~z~0 24) 4294967296) 268435455) (< (mod (+ 6 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 4 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 16 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 5 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 10 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 28 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 19 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 40 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 22 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 14 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 26 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 18 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 12 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 3 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 20 c_main_~z~0) 4294967296) 268435455) (= |c_#NULL.offset| |c_old(#NULL.offset)|) (< (mod (+ 17 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 29 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 7 c_main_~z~0) 4294967296) 268435455) (< (mod (+ c_main_~z~0 1) 4294967296) 268435455)) is different from false [2022-04-27 22:25:11,409 WARN L232 SmtUtils]: Spent 8.21s on a formula simplification. DAG size of input: 166 DAG size of output: 10 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 22:26:09,047 WARN L232 SmtUtils]: Spent 14.92s on a formula simplification. DAG size of input: 168 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 22:26:11,109 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (< (mod (+ 11 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 9 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 8 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 23 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 37 c_main_~z~0) 4294967296) 268435455) (< (mod (+ c_main_~z~0 27) 4294967296) 268435455) (< (mod (+ 13 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 21 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 34 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 30 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 33 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 35 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 36 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 25 c_main_~z~0) 4294967296) 268435455) (< (mod c_main_~z~0 4294967296) 268435455) (< (mod (+ 2 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 31 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 38 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 15 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 32 c_main_~z~0) 4294967296) 268435455) (< (mod (+ c_main_~z~0 24) 4294967296) 268435455) (< (mod (+ 6 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 4 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 16 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 5 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 10 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 28 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 19 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 22 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 14 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 26 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 18 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 12 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 3 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 20 c_main_~z~0) 4294967296) 268435455) (= |c_#NULL.offset| |c_old(#NULL.offset)|) (< (mod (+ 17 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 29 c_main_~z~0) 4294967296) 268435455) (< (mod (+ 7 c_main_~z~0) 4294967296) 268435455) (< (mod (+ c_main_~z~0 1) 4294967296) 268435455)) is different from false [2022-04-27 22:27:17,097 WARN L232 SmtUtils]: Spent 12.54s on a formula simplification. DAG size of input: 154 DAG size of output: 10 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 22:28:01,087 WARN L232 SmtUtils]: Spent 7.29s on a formula simplification. DAG size of input: 156 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 22:28:53,401 WARN L232 SmtUtils]: Spent 5.73s on a formula simplification. DAG size of input: 152 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 22:33:25,708 WARN L232 SmtUtils]: Spent 6.42s on a formula simplification. DAG size of input: 132 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate)