java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf -i ../../../trunk/examples/svcomp/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point.cil.out.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-112bae1 [2019-09-08 17:18:19,205 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-09-08 17:18:19,207 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-09-08 17:18:19,219 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-09-08 17:18:19,219 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-09-08 17:18:19,220 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-09-08 17:18:19,221 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-09-08 17:18:19,223 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-09-08 17:18:19,225 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-09-08 17:18:19,226 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-09-08 17:18:19,227 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-09-08 17:18:19,228 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-09-08 17:18:19,228 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-09-08 17:18:19,229 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-09-08 17:18:19,230 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-09-08 17:18:19,231 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-09-08 17:18:19,232 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-09-08 17:18:19,233 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-09-08 17:18:19,234 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-09-08 17:18:19,236 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-09-08 17:18:19,238 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-09-08 17:18:19,239 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-09-08 17:18:19,240 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-09-08 17:18:19,241 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-09-08 17:18:19,243 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-09-08 17:18:19,243 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-09-08 17:18:19,243 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-09-08 17:18:19,244 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-09-08 17:18:19,245 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-09-08 17:18:19,246 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-09-08 17:18:19,246 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-09-08 17:18:19,247 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-09-08 17:18:19,247 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-09-08 17:18:19,248 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-09-08 17:18:19,249 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-09-08 17:18:19,249 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-09-08 17:18:19,250 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-09-08 17:18:19,250 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-09-08 17:18:19,251 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-09-08 17:18:19,251 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-09-08 17:18:19,252 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-09-08 17:18:19,253 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-09-08 17:18:19,267 INFO L113 SettingsManager]: Loading preferences was successful [2019-09-08 17:18:19,268 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-09-08 17:18:19,269 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-09-08 17:18:19,269 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-09-08 17:18:19,269 INFO L138 SettingsManager]: * Use SBE=true [2019-09-08 17:18:19,270 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-09-08 17:18:19,270 INFO L138 SettingsManager]: * sizeof long=4 [2019-09-08 17:18:19,270 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-09-08 17:18:19,270 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-09-08 17:18:19,270 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-09-08 17:18:19,271 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-09-08 17:18:19,271 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-09-08 17:18:19,271 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-09-08 17:18:19,271 INFO L138 SettingsManager]: * sizeof long double=12 [2019-09-08 17:18:19,271 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-09-08 17:18:19,272 INFO L138 SettingsManager]: * Use constant arrays=true [2019-09-08 17:18:19,272 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-09-08 17:18:19,272 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-09-08 17:18:19,272 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-09-08 17:18:19,273 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-09-08 17:18:19,273 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-09-08 17:18:19,273 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-09-08 17:18:19,273 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-09-08 17:18:19,273 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-09-08 17:18:19,274 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-09-08 17:18:19,274 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-09-08 17:18:19,274 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-09-08 17:18:19,274 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-09-08 17:18:19,274 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-09-08 17:18:19,302 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-09-08 17:18:19,315 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-09-08 17:18:19,318 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-09-08 17:18:19,320 INFO L271 PluginConnector]: Initializing CDTParser... [2019-09-08 17:18:19,320 INFO L275 PluginConnector]: CDTParser initialized [2019-09-08 17:18:19,321 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point.cil.out.i [2019-09-08 17:18:19,403 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b84094da2/ccd4325f5f284439adcbfe7a2571b3ad/FLAG710d210c2 [2019-09-08 17:18:20,156 INFO L306 CDTParser]: Found 1 translation units. [2019-09-08 17:18:20,159 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point.cil.out.i [2019-09-08 17:18:20,192 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b84094da2/ccd4325f5f284439adcbfe7a2571b3ad/FLAG710d210c2 [2019-09-08 17:18:20,240 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b84094da2/ccd4325f5f284439adcbfe7a2571b3ad [2019-09-08 17:18:20,251 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-09-08 17:18:20,253 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-09-08 17:18:20,254 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-09-08 17:18:20,254 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-09-08 17:18:20,258 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-09-08 17:18:20,259 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.09 05:18:20" (1/1) ... [2019-09-08 17:18:20,262 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@326aca08 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.09 05:18:20, skipping insertion in model container [2019-09-08 17:18:20,262 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.09 05:18:20" (1/1) ... [2019-09-08 17:18:20,269 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-09-08 17:18:20,345 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-09-08 17:18:21,357 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-09-08 17:18:21,396 INFO L188 MainTranslator]: Completed pre-run [2019-09-08 17:18:21,585 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-09-08 17:18:21,675 INFO L192 MainTranslator]: Completed translation [2019-09-08 17:18:21,675 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.09 05:18:21 WrapperNode [2019-09-08 17:18:21,675 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-09-08 17:18:21,677 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-09-08 17:18:21,677 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-09-08 17:18:21,677 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-09-08 17:18:21,693 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.09 05:18:21" (1/1) ... [2019-09-08 17:18:21,694 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.09 05:18:21" (1/1) ... [2019-09-08 17:18:21,758 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.09 05:18:21" (1/1) ... [2019-09-08 17:18:21,758 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.09 05:18:21" (1/1) ... [2019-09-08 17:18:21,850 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.09 05:18:21" (1/1) ... [2019-09-08 17:18:21,861 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.09 05:18:21" (1/1) ... [2019-09-08 17:18:21,872 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.09 05:18:21" (1/1) ... [2019-09-08 17:18:21,888 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-09-08 17:18:21,889 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-09-08 17:18:21,889 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-09-08 17:18:21,889 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-09-08 17:18:21,890 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.09 05:18:21" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-09-08 17:18:21,969 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-09-08 17:18:21,970 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-09-08 17:18:21,970 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2019-09-08 17:18:21,970 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2019-09-08 17:18:21,971 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2019-09-08 17:18:21,971 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2019-09-08 17:18:21,971 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2019-09-08 17:18:21,972 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2019-09-08 17:18:21,972 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_undef_int [2019-09-08 17:18:21,972 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_undef_ptr [2019-09-08 17:18:21,973 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_undef_ulong [2019-09-08 17:18:21,973 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2019-09-08 17:18:21,973 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2019-09-08 17:18:21,974 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_expect [2019-09-08 17:18:21,974 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_trap [2019-09-08 17:18:21,975 INFO L138 BoogieDeclarations]: Found implementation of procedure request_irq [2019-09-08 17:18:21,977 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2019-09-08 17:18:21,977 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2019-09-08 17:18:21,977 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2019-09-08 17:18:21,977 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2019-09-08 17:18:21,977 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2019-09-08 17:18:21,978 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2019-09-08 17:18:21,978 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2019-09-08 17:18:21,978 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2019-09-08 17:18:21,978 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2019-09-08 17:18:21,978 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2019-09-08 17:18:21,978 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2019-09-08 17:18:21,978 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2019-09-08 17:18:21,979 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2019-09-08 17:18:21,979 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2019-09-08 17:18:21,979 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2019-09-08 17:18:21,979 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2019-09-08 17:18:21,979 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_probe [2019-09-08 17:18:21,979 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2019-09-08 17:18:21,979 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2019-09-08 17:18:21,980 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2019-09-08 17:18:21,980 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2019-09-08 17:18:21,980 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2019-09-08 17:18:21,980 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2019-09-08 17:18:21,980 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2019-09-08 17:18:21,980 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_suitable_irq_1 [2019-09-08 17:18:21,981 INFO L138 BoogieDeclarations]: Found implementation of procedure reg_check_1 [2019-09-08 17:18:21,981 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2019-09-08 17:18:21,981 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_rtc_class_ops_3 [2019-09-08 17:18:21,981 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2019-09-08 17:18:21,981 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2019-09-08 17:18:21,981 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-09-08 17:18:21,981 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2019-09-08 17:18:21,982 INFO L138 BoogieDeclarations]: Found implementation of procedure PTR_ERR [2019-09-08 17:18:21,982 INFO L138 BoogieDeclarations]: Found implementation of procedure IS_ERR [2019-09-08 17:18:21,982 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_kzalloc_22 [2019-09-08 17:18:21,982 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_register_23 [2019-09-08 17:18:21,982 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_request_irq_24 [2019-09-08 17:18:21,982 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_25 [2019-09-08 17:18:21,983 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2019-09-08 17:18:21,983 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2019-09-08 17:18:21,983 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_is_err [2019-09-08 17:18:21,983 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_err_ptr [2019-09-08 17:18:21,983 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_ptr_err [2019-09-08 17:18:21,984 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_is_err_or_null [2019-09-08 17:18:21,984 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_init [2019-09-08 17:18:21,984 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2019-09-08 17:18:21,984 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2019-09-08 17:18:21,984 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2019-09-08 17:18:21,984 INFO L138 BoogieDeclarations]: Found implementation of procedure __request_region [2019-09-08 17:18:21,984 INFO L138 BoogieDeclarations]: Found implementation of procedure _raw_spin_unlock_irqrestore [2019-09-08 17:18:21,985 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_err [2019-09-08 17:18:21,985 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_get_drvdata [2019-09-08 17:18:21,985 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_notice [2019-09-08 17:18:21,985 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_set_drvdata [2019-09-08 17:18:21,985 INFO L138 BoogieDeclarations]: Found implementation of procedure device_init_wakeup [2019-09-08 17:18:21,986 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2019-09-08 17:18:21,986 INFO L138 BoogieDeclarations]: Found implementation of procedure irq_set_irq_wake [2019-09-08 17:18:21,986 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2019-09-08 17:18:21,987 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize [2019-09-08 17:18:21,987 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_2 [2019-09-08 17:18:21,987 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_probe_3 [2019-09-08 17:18:21,987 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_release_3 [2019-09-08 17:18:21,987 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_probe [2019-09-08 17:18:21,988 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_driver_unregister [2019-09-08 17:18:21,988 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_irq [2019-09-08 17:18:21,988 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_resource [2019-09-08 17:18:21,989 INFO L138 BoogieDeclarations]: Found implementation of procedure request_threaded_irq [2019-09-08 17:18:21,989 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_device_register [2019-09-08 17:18:21,989 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_device_unregister [2019-09-08 17:18:21,989 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_time_to_tm [2019-09-08 17:18:21,989 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_tm_to_time [2019-09-08 17:18:21,990 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_update_irq [2019-09-08 17:18:21,990 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_valid_tm [2019-09-08 17:18:21,990 INFO L138 BoogieDeclarations]: Found implementation of procedure seq_printf [2019-09-08 17:18:21,991 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_ioremap [2019-09-08 17:18:21,991 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_iounmap [2019-09-08 17:18:21,991 INFO L138 BoogieDeclarations]: Found implementation of procedure external_alloc [2019-09-08 17:18:21,992 INFO L138 BoogieDeclarations]: Found implementation of procedure kfree [2019-09-08 17:18:21,992 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2019-09-08 17:18:21,992 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2019-09-08 17:18:21,992 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-09-08 17:18:21,992 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_expect [2019-09-08 17:18:21,993 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_is_err [2019-09-08 17:18:21,993 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_ptr_err [2019-09-08 17:18:21,993 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2019-09-08 17:18:21,993 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2019-09-08 17:18:21,993 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2019-09-08 17:18:21,993 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2019-09-08 17:18:21,994 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2019-09-08 17:18:21,994 INFO L130 BoogieDeclarations]: Found specification of procedure memset [2019-09-08 17:18:21,994 INFO L130 BoogieDeclarations]: Found specification of procedure _raw_spin_unlock_irqrestore [2019-09-08 17:18:21,994 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2019-09-08 17:18:21,994 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2019-09-08 17:18:21,994 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2019-09-08 17:18:21,995 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2019-09-08 17:18:21,995 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2019-09-08 17:18:21,995 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_kzalloc_22 [2019-09-08 17:18:21,995 INFO L130 BoogieDeclarations]: Found specification of procedure malloc [2019-09-08 17:18:21,995 INFO L130 BoogieDeclarations]: Found specification of procedure calloc [2019-09-08 17:18:21,996 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-09-08 17:18:21,996 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2019-09-08 17:18:21,996 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_ulong [2019-09-08 17:18:21,996 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_pointer [2019-09-08 17:18:21,997 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assume [2019-09-08 17:18:21,997 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2019-09-08 17:18:21,997 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2019-09-08 17:18:21,997 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_undef_int [2019-09-08 17:18:21,998 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_undef_ptr [2019-09-08 17:18:21,999 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_undef_ulong [2019-09-08 17:18:21,999 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2019-09-08 17:18:21,999 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2019-09-08 17:18:21,999 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_trap [2019-09-08 17:18:22,000 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2019-09-08 17:18:22,000 INFO L130 BoogieDeclarations]: Found specification of procedure activate_suitable_irq_1 [2019-09-08 17:18:22,000 INFO L130 BoogieDeclarations]: Found specification of procedure reg_check_1 [2019-09-08 17:18:22,000 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2019-09-08 17:18:22,001 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_rtc_class_ops_3 [2019-09-08 17:18:22,001 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2019-09-08 17:18:22,001 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2019-09-08 17:18:22,001 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_ioremap [2019-09-08 17:18:22,001 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2019-09-08 17:18:22,002 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2019-09-08 17:18:22,002 INFO L130 BoogieDeclarations]: Found specification of procedure request_threaded_irq [2019-09-08 17:18:22,002 INFO L130 BoogieDeclarations]: Found specification of procedure request_irq [2019-09-08 17:18:22,005 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_request_irq_24 [2019-09-08 17:18:22,006 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2019-09-08 17:18:22,006 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2019-09-08 17:18:22,007 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2019-09-08 17:18:22,013 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2019-09-08 17:18:22,013 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2019-09-08 17:18:22,013 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_valid_tm [2019-09-08 17:18:22,013 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2019-09-08 17:18:22,013 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2019-09-08 17:18:22,014 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2019-09-08 17:18:22,014 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-09-08 17:18:22,014 INFO L130 BoogieDeclarations]: Found specification of procedure __request_region [2019-09-08 17:18:22,015 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2019-09-08 17:18:22,015 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2019-09-08 17:18:22,015 INFO L130 BoogieDeclarations]: Found specification of procedure device_init_wakeup [2019-09-08 17:18:22,016 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2019-09-08 17:18:22,016 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2019-09-08 17:18:22,016 INFO L130 BoogieDeclarations]: Found specification of procedure dev_set_drvdata [2019-09-08 17:18:22,016 INFO L130 BoogieDeclarations]: Found specification of procedure dev_err [2019-09-08 17:18:22,016 INFO L130 BoogieDeclarations]: Found specification of procedure dev_notice [2019-09-08 17:18:22,017 INFO L130 BoogieDeclarations]: Found specification of procedure seq_printf [2019-09-08 17:18:22,017 INFO L130 BoogieDeclarations]: Found specification of procedure PTR_ERR [2019-09-08 17:18:22,017 INFO L130 BoogieDeclarations]: Found specification of procedure IS_ERR [2019-09-08 17:18:22,017 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_register [2019-09-08 17:18:22,017 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_register_23 [2019-09-08 17:18:22,017 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2019-09-08 17:18:22,018 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_25 [2019-09-08 17:18:22,018 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2019-09-08 17:18:22,018 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_update_irq [2019-09-08 17:18:22,018 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2019-09-08 17:18:22,018 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_irq [2019-09-08 17:18:22,018 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_unregister [2019-09-08 17:18:22,018 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_probe [2019-09-08 17:18:22,019 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2019-09-08 17:18:22,019 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2019-09-08 17:18:22,019 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2019-09-08 17:18:22,019 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2019-09-08 17:18:22,019 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-09-08 17:18:22,019 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2019-09-08 17:18:22,020 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2019-09-08 17:18:22,020 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-09-08 17:18:22,020 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-09-08 17:18:22,020 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2019-09-08 17:18:22,020 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2019-09-08 17:18:22,020 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2019-09-08 17:18:22,020 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2019-09-08 17:18:22,021 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2019-09-08 17:18:22,021 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_probe [2019-09-08 17:18:22,021 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2019-09-08 17:18:22,021 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2019-09-08 17:18:22,021 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2019-09-08 17:18:22,021 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2019-09-08 17:18:22,022 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2019-09-08 17:18:22,022 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2019-09-08 17:18:22,022 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2019-09-08 17:18:22,022 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize [2019-09-08 17:18:22,022 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2019-09-08 17:18:22,022 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_2 [2019-09-08 17:18:22,023 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_3 [2019-09-08 17:18:22,023 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_release_3 [2019-09-08 17:18:22,023 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-09-08 17:18:22,023 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2019-09-08 17:18:22,023 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_err_ptr [2019-09-08 17:18:22,023 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_is_err_or_null [2019-09-08 17:18:22,023 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_init [2019-09-08 17:18:22,024 INFO L130 BoogieDeclarations]: Found specification of procedure external_alloc [2019-09-08 17:18:22,024 INFO L130 BoogieDeclarations]: Found specification of procedure free [2019-09-08 17:18:22,024 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-09-08 17:18:22,024 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2019-09-08 17:18:22,024 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2019-09-08 17:18:22,024 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-09-08 17:18:22,677 INFO L684 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2019-09-08 17:18:27,334 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-09-08 17:18:27,334 INFO L283 CfgBuilder]: Removed 0 assume(true) statements. [2019-09-08 17:18:27,336 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.09 05:18:27 BoogieIcfgContainer [2019-09-08 17:18:27,336 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-09-08 17:18:27,338 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-09-08 17:18:27,338 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-09-08 17:18:27,341 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-09-08 17:18:27,341 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 08.09 05:18:20" (1/3) ... [2019-09-08 17:18:27,342 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@bca6b14 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.09 05:18:27, skipping insertion in model container [2019-09-08 17:18:27,342 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.09 05:18:21" (2/3) ... [2019-09-08 17:18:27,343 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@bca6b14 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.09 05:18:27, skipping insertion in model container [2019-09-08 17:18:27,343 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.09 05:18:27" (3/3) ... [2019-09-08 17:18:27,344 INFO L109 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point.cil.out.i [2019-09-08 17:18:27,354 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-09-08 17:18:27,366 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-09-08 17:18:27,383 INFO L252 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-09-08 17:18:27,425 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2019-09-08 17:18:27,426 INFO L377 AbstractCegarLoop]: Interprodecural is true [2019-09-08 17:18:27,426 INFO L378 AbstractCegarLoop]: Hoare is true [2019-09-08 17:18:27,426 INFO L379 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-09-08 17:18:27,426 INFO L380 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-09-08 17:18:27,426 INFO L381 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-09-08 17:18:27,426 INFO L382 AbstractCegarLoop]: Difference is false [2019-09-08 17:18:27,426 INFO L383 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-09-08 17:18:27,426 INFO L388 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-09-08 17:18:27,457 INFO L276 IsEmpty]: Start isEmpty. Operand 631 states. [2019-09-08 17:18:27,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-09-08 17:18:27,472 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:27,473 INFO L399 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:27,475 INFO L418 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:27,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:27,481 INFO L82 PathProgramCache]: Analyzing trace with hash -831317850, now seen corresponding path program 1 times [2019-09-08 17:18:27,483 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:27,483 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:27,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:27,553 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:27,553 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:27,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:27,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-09-08 17:18:27,941 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-09-08 17:18:27,941 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-09-08 17:18:27,946 INFO L454 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-09-08 17:18:27,964 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-09-08 17:18:27,965 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-09-08 17:18:27,968 INFO L87 Difference]: Start difference. First operand 631 states. Second operand 3 states. [2019-09-08 17:18:28,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-09-08 17:18:28,130 INFO L93 Difference]: Finished difference Result 822 states and 1040 transitions. [2019-09-08 17:18:28,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-09-08 17:18:28,132 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-09-08 17:18:28,133 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-09-08 17:18:28,168 INFO L225 Difference]: With dead ends: 822 [2019-09-08 17:18:28,169 INFO L226 Difference]: Without dead ends: 331 [2019-09-08 17:18:28,184 INFO L628 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-09-08 17:18:28,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 331 states. [2019-09-08 17:18:28,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 331 to 331. [2019-09-08 17:18:28,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 331 states. [2019-09-08 17:18:28,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 331 states to 331 states and 401 transitions. [2019-09-08 17:18:28,328 INFO L78 Accepts]: Start accepts. Automaton has 331 states and 401 transitions. Word has length 47 [2019-09-08 17:18:28,333 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-09-08 17:18:28,334 INFO L475 AbstractCegarLoop]: Abstraction has 331 states and 401 transitions. [2019-09-08 17:18:28,336 INFO L476 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-09-08 17:18:28,336 INFO L276 IsEmpty]: Start isEmpty. Operand 331 states and 401 transitions. [2019-09-08 17:18:28,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-09-08 17:18:28,353 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:28,354 INFO L399 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:28,354 INFO L418 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:28,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:28,355 INFO L82 PathProgramCache]: Analyzing trace with hash 1836309482, now seen corresponding path program 1 times [2019-09-08 17:18:28,355 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:28,355 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:28,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:28,359 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:28,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:28,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:28,489 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-09-08 17:18:28,490 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-09-08 17:18:28,490 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-09-08 17:18:28,501 INFO L454 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-09-08 17:18:28,502 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-09-08 17:18:28,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-09-08 17:18:28,505 INFO L87 Difference]: Start difference. First operand 331 states and 401 transitions. Second operand 3 states. [2019-09-08 17:18:28,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-09-08 17:18:28,650 INFO L93 Difference]: Finished difference Result 774 states and 940 transitions. [2019-09-08 17:18:28,651 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-09-08 17:18:28,651 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2019-09-08 17:18:28,651 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-09-08 17:18:28,655 INFO L225 Difference]: With dead ends: 774 [2019-09-08 17:18:28,656 INFO L226 Difference]: Without dead ends: 460 [2019-09-08 17:18:28,658 INFO L628 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-09-08 17:18:28,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 460 states. [2019-09-08 17:18:28,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 460 to 457. [2019-09-08 17:18:28,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 457 states. [2019-09-08 17:18:28,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 457 states to 457 states and 555 transitions. [2019-09-08 17:18:28,708 INFO L78 Accepts]: Start accepts. Automaton has 457 states and 555 transitions. Word has length 68 [2019-09-08 17:18:28,709 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-09-08 17:18:28,709 INFO L475 AbstractCegarLoop]: Abstraction has 457 states and 555 transitions. [2019-09-08 17:18:28,709 INFO L476 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-09-08 17:18:28,709 INFO L276 IsEmpty]: Start isEmpty. Operand 457 states and 555 transitions. [2019-09-08 17:18:28,712 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-09-08 17:18:28,712 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:28,713 INFO L399 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:28,713 INFO L418 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:28,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:28,713 INFO L82 PathProgramCache]: Analyzing trace with hash -1475112585, now seen corresponding path program 1 times [2019-09-08 17:18:28,714 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:28,714 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:28,722 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:28,722 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:28,722 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:28,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:28,896 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-09-08 17:18:28,896 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-09-08 17:18:28,897 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-09-08 17:18:28,897 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-09-08 17:18:28,897 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-09-08 17:18:28,897 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-09-08 17:18:28,898 INFO L87 Difference]: Start difference. First operand 457 states and 555 transitions. Second operand 5 states. [2019-09-08 17:18:29,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-09-08 17:18:29,032 INFO L93 Difference]: Finished difference Result 1341 states and 1657 transitions. [2019-09-08 17:18:29,032 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-09-08 17:18:29,032 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 70 [2019-09-08 17:18:29,033 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-09-08 17:18:29,041 INFO L225 Difference]: With dead ends: 1341 [2019-09-08 17:18:29,041 INFO L226 Difference]: Without dead ends: 910 [2019-09-08 17:18:29,044 INFO L628 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-09-08 17:18:29,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 910 states. [2019-09-08 17:18:29,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 910 to 887. [2019-09-08 17:18:29,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 887 states. [2019-09-08 17:18:29,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 887 states to 887 states and 1086 transitions. [2019-09-08 17:18:29,156 INFO L78 Accepts]: Start accepts. Automaton has 887 states and 1086 transitions. Word has length 70 [2019-09-08 17:18:29,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-09-08 17:18:29,158 INFO L475 AbstractCegarLoop]: Abstraction has 887 states and 1086 transitions. [2019-09-08 17:18:29,159 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-09-08 17:18:29,159 INFO L276 IsEmpty]: Start isEmpty. Operand 887 states and 1086 transitions. [2019-09-08 17:18:29,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2019-09-08 17:18:29,165 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:29,165 INFO L399 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:29,165 INFO L418 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:29,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:29,166 INFO L82 PathProgramCache]: Analyzing trace with hash -1184897628, now seen corresponding path program 1 times [2019-09-08 17:18:29,166 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:29,167 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:29,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:29,170 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:29,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:29,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:29,287 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-09-08 17:18:29,287 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-09-08 17:18:29,287 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-09-08 17:18:29,288 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-09-08 17:18:29,288 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-09-08 17:18:29,289 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-09-08 17:18:29,289 INFO L87 Difference]: Start difference. First operand 887 states and 1086 transitions. Second operand 5 states. [2019-09-08 17:18:29,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-09-08 17:18:29,412 INFO L93 Difference]: Finished difference Result 1780 states and 2200 transitions. [2019-09-08 17:18:29,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-09-08 17:18:29,413 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 71 [2019-09-08 17:18:29,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-09-08 17:18:29,421 INFO L225 Difference]: With dead ends: 1780 [2019-09-08 17:18:29,421 INFO L226 Difference]: Without dead ends: 919 [2019-09-08 17:18:29,425 INFO L628 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-09-08 17:18:29,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states. [2019-09-08 17:18:29,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 895. [2019-09-08 17:18:29,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 895 states. [2019-09-08 17:18:29,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 895 states to 895 states and 1088 transitions. [2019-09-08 17:18:29,480 INFO L78 Accepts]: Start accepts. Automaton has 895 states and 1088 transitions. Word has length 71 [2019-09-08 17:18:29,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-09-08 17:18:29,481 INFO L475 AbstractCegarLoop]: Abstraction has 895 states and 1088 transitions. [2019-09-08 17:18:29,481 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-09-08 17:18:29,481 INFO L276 IsEmpty]: Start isEmpty. Operand 895 states and 1088 transitions. [2019-09-08 17:18:29,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-09-08 17:18:29,483 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:29,484 INFO L399 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:29,484 INFO L418 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:29,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:29,484 INFO L82 PathProgramCache]: Analyzing trace with hash 1790903156, now seen corresponding path program 1 times [2019-09-08 17:18:29,486 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:29,486 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:29,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:29,489 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:29,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:29,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:29,611 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-09-08 17:18:29,612 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-09-08 17:18:29,612 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-09-08 17:18:29,612 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-09-08 17:18:29,612 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-09-08 17:18:29,613 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-09-08 17:18:29,613 INFO L87 Difference]: Start difference. First operand 895 states and 1088 transitions. Second operand 5 states. [2019-09-08 17:18:29,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-09-08 17:18:29,735 INFO L93 Difference]: Finished difference Result 1796 states and 2200 transitions. [2019-09-08 17:18:29,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-09-08 17:18:29,736 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 72 [2019-09-08 17:18:29,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-09-08 17:18:29,742 INFO L225 Difference]: With dead ends: 1796 [2019-09-08 17:18:29,743 INFO L226 Difference]: Without dead ends: 927 [2019-09-08 17:18:29,746 INFO L628 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-09-08 17:18:29,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 927 states. [2019-09-08 17:18:29,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 927 to 903. [2019-09-08 17:18:29,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 903 states. [2019-09-08 17:18:29,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 903 states to 903 states and 1090 transitions. [2019-09-08 17:18:29,803 INFO L78 Accepts]: Start accepts. Automaton has 903 states and 1090 transitions. Word has length 72 [2019-09-08 17:18:29,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-09-08 17:18:29,804 INFO L475 AbstractCegarLoop]: Abstraction has 903 states and 1090 transitions. [2019-09-08 17:18:29,804 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-09-08 17:18:29,804 INFO L276 IsEmpty]: Start isEmpty. Operand 903 states and 1090 transitions. [2019-09-08 17:18:29,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-09-08 17:18:29,806 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:29,806 INFO L399 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:29,806 INFO L418 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:29,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:29,807 INFO L82 PathProgramCache]: Analyzing trace with hash 2120518657, now seen corresponding path program 1 times [2019-09-08 17:18:29,807 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:29,807 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:29,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:29,812 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:29,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:29,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:29,914 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-09-08 17:18:29,914 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-09-08 17:18:29,914 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-09-08 17:18:29,915 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-09-08 17:18:29,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-09-08 17:18:29,916 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-09-08 17:18:29,917 INFO L87 Difference]: Start difference. First operand 903 states and 1090 transitions. Second operand 5 states. [2019-09-08 17:18:30,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-09-08 17:18:30,022 INFO L93 Difference]: Finished difference Result 1707 states and 2078 transitions. [2019-09-08 17:18:30,022 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-09-08 17:18:30,022 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2019-09-08 17:18:30,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-09-08 17:18:30,027 INFO L225 Difference]: With dead ends: 1707 [2019-09-08 17:18:30,027 INFO L226 Difference]: Without dead ends: 830 [2019-09-08 17:18:30,031 INFO L628 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-09-08 17:18:30,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states. [2019-09-08 17:18:30,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 812. [2019-09-08 17:18:30,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 812 states. [2019-09-08 17:18:30,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 812 states to 812 states and 974 transitions. [2019-09-08 17:18:30,072 INFO L78 Accepts]: Start accepts. Automaton has 812 states and 974 transitions. Word has length 73 [2019-09-08 17:18:30,073 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-09-08 17:18:30,073 INFO L475 AbstractCegarLoop]: Abstraction has 812 states and 974 transitions. [2019-09-08 17:18:30,073 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-09-08 17:18:30,073 INFO L276 IsEmpty]: Start isEmpty. Operand 812 states and 974 transitions. [2019-09-08 17:18:30,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-09-08 17:18:30,075 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:30,075 INFO L399 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:30,076 INFO L418 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:30,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:30,076 INFO L82 PathProgramCache]: Analyzing trace with hash -738457202, now seen corresponding path program 1 times [2019-09-08 17:18:30,076 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:30,076 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:30,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:30,078 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:30,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:30,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:30,199 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-09-08 17:18:30,200 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-09-08 17:18:30,200 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-09-08 17:18:30,225 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:30,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:30,428 INFO L256 TraceCheckSpWp]: Trace formula consists of 947 conjuncts, 3 conjunts are in the unsatisfiable core [2019-09-08 17:18:30,440 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-09-08 17:18:30,527 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [MP z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (2)] Exception during sending of exit command (exit): Broken pipe [2019-09-08 17:18:30,537 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-09-08 17:18:30,537 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [9] total 11 [2019-09-08 17:18:30,538 INFO L454 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-09-08 17:18:30,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-09-08 17:18:30,539 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2019-09-08 17:18:30,539 INFO L87 Difference]: Start difference. First operand 812 states and 974 transitions. Second operand 11 states. [2019-09-08 17:18:33,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-09-08 17:18:33,545 INFO L93 Difference]: Finished difference Result 2158 states and 2676 transitions. [2019-09-08 17:18:33,552 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-09-08 17:18:33,552 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 85 [2019-09-08 17:18:33,553 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-09-08 17:18:33,561 INFO L225 Difference]: With dead ends: 2158 [2019-09-08 17:18:33,561 INFO L226 Difference]: Without dead ends: 1369 [2019-09-08 17:18:33,564 INFO L628 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=116, Invalid=436, Unknown=0, NotChecked=0, Total=552 [2019-09-08 17:18:33,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1369 states. [2019-09-08 17:18:33,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1369 to 1156. [2019-09-08 17:18:33,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1156 states. [2019-09-08 17:18:33,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1156 states to 1156 states and 1393 transitions. [2019-09-08 17:18:33,642 INFO L78 Accepts]: Start accepts. Automaton has 1156 states and 1393 transitions. Word has length 85 [2019-09-08 17:18:33,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-09-08 17:18:33,642 INFO L475 AbstractCegarLoop]: Abstraction has 1156 states and 1393 transitions. [2019-09-08 17:18:33,642 INFO L476 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-09-08 17:18:33,643 INFO L276 IsEmpty]: Start isEmpty. Operand 1156 states and 1393 transitions. [2019-09-08 17:18:33,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-09-08 17:18:33,645 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:33,645 INFO L399 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:33,646 INFO L418 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:33,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:33,646 INFO L82 PathProgramCache]: Analyzing trace with hash -1815039665, now seen corresponding path program 1 times [2019-09-08 17:18:33,646 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:33,647 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:33,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:33,650 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:33,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:33,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:33,824 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-09-08 17:18:33,825 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-09-08 17:18:33,825 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2019-09-08 17:18:33,847 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-09-08 17:18:33,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:33,993 INFO L256 TraceCheckSpWp]: Trace formula consists of 955 conjuncts, 4 conjunts are in the unsatisfiable core [2019-09-08 17:18:34,000 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-09-08 17:18:34,070 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2019-09-08 17:18:34,077 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-09-08 17:18:34,077 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 5] total 13 [2019-09-08 17:18:34,080 INFO L454 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-09-08 17:18:34,080 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-09-08 17:18:34,080 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=132, Unknown=0, NotChecked=0, Total=156 [2019-09-08 17:18:34,081 INFO L87 Difference]: Start difference. First operand 1156 states and 1393 transitions. Second operand 13 states. [2019-09-08 17:18:35,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-09-08 17:18:35,458 INFO L93 Difference]: Finished difference Result 2675 states and 3235 transitions. [2019-09-08 17:18:35,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-09-08 17:18:35,459 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 87 [2019-09-08 17:18:35,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-09-08 17:18:35,470 INFO L225 Difference]: With dead ends: 2675 [2019-09-08 17:18:35,470 INFO L226 Difference]: Without dead ends: 1543 [2019-09-08 17:18:35,476 INFO L628 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 93 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=147, Invalid=609, Unknown=0, NotChecked=0, Total=756 [2019-09-08 17:18:35,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1543 states. [2019-09-08 17:18:35,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1543 to 1474. [2019-09-08 17:18:35,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1474 states. [2019-09-08 17:18:35,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1474 states to 1474 states and 1787 transitions. [2019-09-08 17:18:35,571 INFO L78 Accepts]: Start accepts. Automaton has 1474 states and 1787 transitions. Word has length 87 [2019-09-08 17:18:35,572 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-09-08 17:18:35,572 INFO L475 AbstractCegarLoop]: Abstraction has 1474 states and 1787 transitions. [2019-09-08 17:18:35,572 INFO L476 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-09-08 17:18:35,572 INFO L276 IsEmpty]: Start isEmpty. Operand 1474 states and 1787 transitions. [2019-09-08 17:18:35,576 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2019-09-08 17:18:35,577 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:35,577 INFO L399 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:35,577 INFO L418 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:35,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:35,578 INFO L82 PathProgramCache]: Analyzing trace with hash -896548153, now seen corresponding path program 1 times [2019-09-08 17:18:35,578 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:35,578 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:35,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:35,582 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:35,582 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:35,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:35,797 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-09-08 17:18:35,798 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-09-08 17:18:35,798 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-09-08 17:18:35,834 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:35,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:35,975 INFO L256 TraceCheckSpWp]: Trace formula consists of 963 conjuncts, 5 conjunts are in the unsatisfiable core [2019-09-08 17:18:35,984 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-09-08 17:18:36,079 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2019-09-08 17:18:36,084 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-09-08 17:18:36,085 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 6] total 14 [2019-09-08 17:18:36,085 INFO L454 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-09-08 17:18:36,086 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-09-08 17:18:36,086 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2019-09-08 17:18:36,086 INFO L87 Difference]: Start difference. First operand 1474 states and 1787 transitions. Second operand 14 states. [2019-09-08 17:18:37,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-09-08 17:18:37,339 INFO L93 Difference]: Finished difference Result 3310 states and 4026 transitions. [2019-09-08 17:18:37,340 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-09-08 17:18:37,340 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 89 [2019-09-08 17:18:37,340 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-09-08 17:18:37,352 INFO L225 Difference]: With dead ends: 3310 [2019-09-08 17:18:37,352 INFO L226 Difference]: Without dead ends: 1861 [2019-09-08 17:18:37,358 INFO L628 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 109 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=162, Invalid=708, Unknown=0, NotChecked=0, Total=870 [2019-09-08 17:18:37,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1861 states. [2019-09-08 17:18:37,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1861 to 1475. [2019-09-08 17:18:37,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1475 states. [2019-09-08 17:18:37,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1475 states to 1475 states and 1788 transitions. [2019-09-08 17:18:37,510 INFO L78 Accepts]: Start accepts. Automaton has 1475 states and 1788 transitions. Word has length 89 [2019-09-08 17:18:37,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-09-08 17:18:37,510 INFO L475 AbstractCegarLoop]: Abstraction has 1475 states and 1788 transitions. [2019-09-08 17:18:37,510 INFO L476 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-09-08 17:18:37,510 INFO L276 IsEmpty]: Start isEmpty. Operand 1475 states and 1788 transitions. [2019-09-08 17:18:37,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2019-09-08 17:18:37,514 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:37,515 INFO L399 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:37,515 INFO L418 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:37,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:37,516 INFO L82 PathProgramCache]: Analyzing trace with hash -2063937176, now seen corresponding path program 1 times [2019-09-08 17:18:37,516 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:37,516 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:37,519 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:37,519 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:37,519 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:37,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:37,688 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-09-08 17:18:37,688 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-09-08 17:18:37,688 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2019-09-08 17:18:37,711 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-09-08 17:18:37,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:37,909 INFO L256 TraceCheckSpWp]: Trace formula consists of 971 conjuncts, 6 conjunts are in the unsatisfiable core [2019-09-08 17:18:37,919 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-09-08 17:18:38,065 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2019-09-08 17:18:38,070 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-09-08 17:18:38,070 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7] total 15 [2019-09-08 17:18:38,071 INFO L454 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-09-08 17:18:38,071 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-09-08 17:18:38,072 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=177, Unknown=0, NotChecked=0, Total=210 [2019-09-08 17:18:38,072 INFO L87 Difference]: Start difference. First operand 1475 states and 1788 transitions. Second operand 15 states. [2019-09-08 17:18:39,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-09-08 17:18:39,377 INFO L93 Difference]: Finished difference Result 2867 states and 3473 transitions. [2019-09-08 17:18:39,377 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-09-08 17:18:39,378 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 91 [2019-09-08 17:18:39,378 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-09-08 17:18:39,385 INFO L225 Difference]: With dead ends: 2867 [2019-09-08 17:18:39,385 INFO L226 Difference]: Without dead ends: 1418 [2019-09-08 17:18:39,390 INFO L628 BasicCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 111 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=172, Invalid=758, Unknown=0, NotChecked=0, Total=930 [2019-09-08 17:18:39,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1418 states. [2019-09-08 17:18:39,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1418 to 402. [2019-09-08 17:18:39,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 402 states. [2019-09-08 17:18:39,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 402 states to 402 states and 469 transitions. [2019-09-08 17:18:39,424 INFO L78 Accepts]: Start accepts. Automaton has 402 states and 469 transitions. Word has length 91 [2019-09-08 17:18:39,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-09-08 17:18:39,424 INFO L475 AbstractCegarLoop]: Abstraction has 402 states and 469 transitions. [2019-09-08 17:18:39,424 INFO L476 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-09-08 17:18:39,424 INFO L276 IsEmpty]: Start isEmpty. Operand 402 states and 469 transitions. [2019-09-08 17:18:39,426 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2019-09-08 17:18:39,426 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:39,426 INFO L399 BasicCegarLoop]: trace histogram [4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:39,427 INFO L418 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:39,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:39,427 INFO L82 PathProgramCache]: Analyzing trace with hash 1884749160, now seen corresponding path program 1 times [2019-09-08 17:18:39,427 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:39,427 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:39,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:39,430 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:39,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:39,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:39,519 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-09-08 17:18:39,520 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-09-08 17:18:39,520 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-09-08 17:18:39,520 INFO L454 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-09-08 17:18:39,521 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-09-08 17:18:39,522 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-09-08 17:18:39,522 INFO L87 Difference]: Start difference. First operand 402 states and 469 transitions. Second operand 3 states. [2019-09-08 17:18:39,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-09-08 17:18:39,622 INFO L93 Difference]: Finished difference Result 856 states and 1016 transitions. [2019-09-08 17:18:39,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-09-08 17:18:39,622 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 101 [2019-09-08 17:18:39,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-09-08 17:18:39,626 INFO L225 Difference]: With dead ends: 856 [2019-09-08 17:18:39,626 INFO L226 Difference]: Without dead ends: 484 [2019-09-08 17:18:39,628 INFO L628 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-09-08 17:18:39,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 484 states. [2019-09-08 17:18:39,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 484 to 484. [2019-09-08 17:18:39,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 484 states. [2019-09-08 17:18:39,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 570 transitions. [2019-09-08 17:18:39,657 INFO L78 Accepts]: Start accepts. Automaton has 484 states and 570 transitions. Word has length 101 [2019-09-08 17:18:39,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-09-08 17:18:39,658 INFO L475 AbstractCegarLoop]: Abstraction has 484 states and 570 transitions. [2019-09-08 17:18:39,658 INFO L476 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-09-08 17:18:39,658 INFO L276 IsEmpty]: Start isEmpty. Operand 484 states and 570 transitions. [2019-09-08 17:18:39,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2019-09-08 17:18:39,661 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:39,661 INFO L399 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:39,662 INFO L418 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:39,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:39,662 INFO L82 PathProgramCache]: Analyzing trace with hash -1752423767, now seen corresponding path program 1 times [2019-09-08 17:18:39,662 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:39,662 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:39,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:39,664 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:39,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:39,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-09-08 17:18:39,765 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2019-09-08 17:18:39,766 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-09-08 17:18:39,766 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-09-08 17:18:39,766 INFO L454 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-09-08 17:18:39,767 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-09-08 17:18:39,767 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-09-08 17:18:39,767 INFO L87 Difference]: Start difference. First operand 484 states and 570 transitions. Second operand 3 states. [2019-09-08 17:18:39,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-09-08 17:18:39,871 INFO L93 Difference]: Finished difference Result 1173 states and 1377 transitions. [2019-09-08 17:18:39,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-09-08 17:18:39,872 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 118 [2019-09-08 17:18:39,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-09-08 17:18:39,877 INFO L225 Difference]: With dead ends: 1173 [2019-09-08 17:18:39,877 INFO L226 Difference]: Without dead ends: 719 [2019-09-08 17:18:39,880 INFO L628 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-09-08 17:18:39,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 719 states. [2019-09-08 17:18:39,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 719 to 716. [2019-09-08 17:18:39,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 716 states. [2019-09-08 17:18:39,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 716 states and 828 transitions. [2019-09-08 17:18:39,922 INFO L78 Accepts]: Start accepts. Automaton has 716 states and 828 transitions. Word has length 118 [2019-09-08 17:18:39,923 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-09-08 17:18:39,923 INFO L475 AbstractCegarLoop]: Abstraction has 716 states and 828 transitions. [2019-09-08 17:18:39,923 INFO L476 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-09-08 17:18:39,923 INFO L276 IsEmpty]: Start isEmpty. Operand 716 states and 828 transitions. [2019-09-08 17:18:39,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2019-09-08 17:18:39,925 INFO L391 BasicCegarLoop]: Found error trace [2019-09-08 17:18:39,926 INFO L399 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-09-08 17:18:39,926 INFO L418 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-09-08 17:18:39,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-09-08 17:18:39,926 INFO L82 PathProgramCache]: Analyzing trace with hash -151311920, now seen corresponding path program 1 times [2019-09-08 17:18:39,926 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2019-09-08 17:18:39,927 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2019-09-08 17:18:39,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:39,929 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-09-08 17:18:39,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-09-08 17:18:40,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-09-08 17:18:40,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-09-08 17:18:40,503 INFO L466 BasicCegarLoop]: Counterexample might be feasible [2019-09-08 17:18:40,551 WARN L417 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) [2019-09-08 17:18:40,589 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 4294967329 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2019-09-08 17:18:40,590 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 4294967364 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2019-09-08 17:18:40,591 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 4294967358 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2019-09-08 17:18:40,592 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: IntegerLiteral 4294967331 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2019-09-08 17:18:40,607 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,609 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,609 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,611 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,611 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,617 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,617 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,619 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,619 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,625 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,625 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,627 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,627 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,628 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,628 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,630 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,630 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,630 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,631 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,631 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,632 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,634 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,634 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,634 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,635 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,636 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,636 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,637 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,637 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,638 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,639 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,639 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,640 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,640 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,641 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,641 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,642 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,642 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,643 WARN L1298 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2019-09-08 17:18:40,704 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 08.09 05:18:40 BoogieIcfgContainer [2019-09-08 17:18:40,705 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-09-08 17:18:40,711 INFO L168 Benchmark]: Toolchain (without parser) took 20453.63 ms. Allocated memory was 133.2 MB in the beginning and 583.5 MB in the end (delta: 450.4 MB). Free memory was 85.0 MB in the beginning and 409.3 MB in the end (delta: -324.4 MB). Peak memory consumption was 126.0 MB. Max. memory is 7.1 GB. [2019-09-08 17:18:40,712 INFO L168 Benchmark]: CDTParser took 0.22 ms. Allocated memory is still 133.2 MB. Free memory is still 107.2 MB. There was no memory consumed. Max. memory is 7.1 GB. [2019-09-08 17:18:40,713 INFO L168 Benchmark]: CACSL2BoogieTranslator took 1421.70 ms. Allocated memory was 133.2 MB in the beginning and 201.9 MB in the end (delta: 68.7 MB). Free memory was 85.0 MB in the beginning and 125.6 MB in the end (delta: -40.7 MB). Peak memory consumption was 33.6 MB. Max. memory is 7.1 GB. [2019-09-08 17:18:40,713 INFO L168 Benchmark]: Boogie Preprocessor took 211.81 ms. Allocated memory is still 201.9 MB. Free memory was 125.6 MB in the beginning and 115.9 MB in the end (delta: 9.8 MB). Peak memory consumption was 9.8 MB. Max. memory is 7.1 GB. [2019-09-08 17:18:40,715 INFO L168 Benchmark]: RCFGBuilder took 5447.80 ms. Allocated memory was 201.9 MB in the beginning and 344.5 MB in the end (delta: 142.6 MB). Free memory was 115.9 MB in the beginning and 201.6 MB in the end (delta: -85.7 MB). Peak memory consumption was 185.2 MB. Max. memory is 7.1 GB. [2019-09-08 17:18:40,718 INFO L168 Benchmark]: TraceAbstraction took 13367.24 ms. Allocated memory was 344.5 MB in the beginning and 583.5 MB in the end (delta: 239.1 MB). Free memory was 201.6 MB in the beginning and 409.3 MB in the end (delta: -207.7 MB). Peak memory consumption was 31.3 MB. Max. memory is 7.1 GB. [2019-09-08 17:18:40,727 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.22 ms. Allocated memory is still 133.2 MB. Free memory is still 107.2 MB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 1421.70 ms. Allocated memory was 133.2 MB in the beginning and 201.9 MB in the end (delta: 68.7 MB). Free memory was 85.0 MB in the beginning and 125.6 MB in the end (delta: -40.7 MB). Peak memory consumption was 33.6 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 211.81 ms. Allocated memory is still 201.9 MB. Free memory was 125.6 MB in the beginning and 115.9 MB in the end (delta: 9.8 MB). Peak memory consumption was 9.8 MB. Max. memory is 7.1 GB. * RCFGBuilder took 5447.80 ms. Allocated memory was 201.9 MB in the beginning and 344.5 MB in the end (delta: 142.6 MB). Free memory was 115.9 MB in the beginning and 201.6 MB in the end (delta: -85.7 MB). Peak memory consumption was 185.2 MB. Max. memory is 7.1 GB. * TraceAbstraction took 13367.24 ms. Allocated memory was 344.5 MB in the beginning and 583.5 MB in the end (delta: 239.1 MB). Free memory was 201.6 MB in the beginning and 409.3 MB in the end (delta: -207.7 MB). Peak memory consumption was 31.3 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 4294967329 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 4294967364 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 4294967358 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: IntegerLiteral 4294967331 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1664]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of large string literal at line 2219, overapproximation of bitwiseAnd at line 1830. Possible FailurePath: [L1687] int ldv_irq_1_2 = 0; [L1688] int LDV_IN_INTERRUPT = 1; [L1689] int ldv_irq_1_3 = 0; [L1690] struct platform_device *tegra_rtc_driver_group0 ; [L1691] void *ldv_irq_data_1_1 ; [L1692] int ldv_irq_1_1 = 0; [L1693] int ldv_irq_1_0 = 0; [L1694] int ldv_irq_line_1_3 ; [L1695] void *ldv_irq_data_1_0 ; [L1696] int ldv_state_variable_0 ; [L1697] struct device *tegra_rtc_ops_group1 ; [L1698] int ldv_state_variable_3 ; [L1699] int ldv_irq_line_1_0 ; [L1700] int ldv_state_variable_2 ; [L1701] void *ldv_irq_data_1_3 ; [L1702] int ref_cnt ; [L1703] int ldv_irq_line_1_1 ; [L1704] struct rtc_time *tegra_rtc_ops_group0 ; [L1705] void *ldv_irq_data_1_2 ; [L1706] int ldv_state_variable_1 ; [L1707] int ldv_irq_line_1_2 ; [L1708] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2050-L2052] static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2218-L2219] static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2235] int ldv_retval_2 ; [L2236] int ldv_retval_0 ; [L2238] int ldv_retval_1 ; [L2761] int ldv_init = 0; VAL [\old(LDV_IN_INTERRUPT)=4294967311, \old(ldv_init)=4294967336, \old(ldv_irq_1_0)=4294967342, \old(ldv_irq_1_1)=4294967334, \old(ldv_irq_1_2)=4294967345, \old(ldv_irq_1_3)=4294967333, \old(ldv_irq_data_1_0)=4294967337, \old(ldv_irq_data_1_0)=4294967302, \old(ldv_irq_data_1_1)=4294967350, \old(ldv_irq_data_1_1)=4294967324, \old(ldv_irq_data_1_2)=4294967315, \old(ldv_irq_data_1_2)=4294967328, \old(ldv_irq_data_1_3)=4294967340, \old(ldv_irq_data_1_3)=4294967297, \old(ldv_irq_line_1_0)=4294967343, \old(ldv_irq_line_1_1)=4294967363, \old(ldv_irq_line_1_2)=4294967359, \old(ldv_irq_line_1_3)=4294967306, \old(ldv_retval_0)=4294967310, \old(ldv_retval_1)=4294967304, \old(ldv_retval_2)=4294967327, \old(ldv_state_variable_0)=4294967323, \old(ldv_state_variable_1)=4294967351, \old(ldv_state_variable_2)=4294967346, \old(ldv_state_variable_3)=4294967366, \old(ref_cnt)=4294967341, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver_group0)=4294967338, \old(tegra_rtc_driver_group0)=4294967357, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops_group0)=4294967318, \old(tegra_rtc_ops_group0)=4294967339, \old(tegra_rtc_ops_group1)=4294967332, \old(tegra_rtc_ops_group1)=4294967354, \old(tegra_rtc_ops_group2)=4294967313, \old(tegra_rtc_ops_group2)=4294967299, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2390] struct seq_file *ldvarg1 ; [L2391] void *tmp ; [L2392] unsigned int ldvarg0 ; [L2393] unsigned int tmp___0 ; [L2394] pm_message_t ldvarg2 ; [L2395] int tmp___1 ; [L2396] int tmp___2 ; [L2397] int tmp___3 ; [L2398] int tmp___4 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] CALL, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result={0:0}, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, size=136, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2400] RET, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_zalloc(136U)={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2400] tmp = ldv_zalloc(136U) [L2401] ldvarg1 = (struct seq_file *)tmp [L2402] tmp___0 = __VERIFIER_nondet_uint() [L2403] ldvarg0 = tmp___0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21] [L2404] FCALL ldv_initialize() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21] [L2405] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, memset((void *)(& ldvarg2), 0, 4U)={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21] [L2406] ldv_state_variable_1 = 1 [L2407] ref_cnt = 0 [L2408] ldv_state_variable_0 = 1 [L2409] ldv_state_variable_3 = 0 [L2410] ldv_state_variable_2 = 0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=1] [L2421] COND TRUE ldv_state_variable_0 != 0 [L2422] tmp___2 = __VERIFIER_nondet_int() [L2424] case 0: [L2432] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=1, tmp___2=1] [L2433] COND TRUE ldv_state_variable_0 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=1, tmp___2=1] [L2434] CALL, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2222] int tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] CALL, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, arg0={-5:0}, arg1={-1:11}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2842] return __VERIFIER_nondet_int(); [L2224] RET, EXPR platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe)=0, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2224] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2225] return (tmp); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp=0] [L2434] RET, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_init()=0, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=1, tmp___2=1] [L2434] ldv_retval_0 = tegra_rtc_init() [L2435] COND TRUE ldv_retval_0 == 0 [L2436] ldv_state_variable_0 = 3 [L2437] ldv_state_variable_2 = 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=1, tmp___2=1] [L2438] CALL ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2355] void *tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] CALL, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1621] void *p ; [L1622] void *tmp ; [L1623] int tmp___0 ; [L1625] tmp___0 = __VERIFIER_nondet_int() [L1626] COND TRUE tmp___0 != 0 [L1627] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result={0:0}, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, size=624, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2357] RET, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2357] tmp = ldv_zalloc(624U) [L2358] tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2438] RET ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=1, tmp___2=1] [L2441] COND FALSE !(ldv_retval_0 != 0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=1, tmp___2=1] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=3, tmp___2=1] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: [L2566] case 1: [L2576] case 2: [L2596] case 3: [L2606] case 4: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=3, tmp___2=1, tmp___4=4] [L2607] COND TRUE ldv_state_variable_2 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=3, tmp___2=1, tmp___4=4] [L2608] CALL ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2830] return __VERIFIER_nondet_int(); [L2608] RET ldv_probe_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_probe_2()=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=0, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=3, tmp___2=1, tmp___4=4] [L2609] ldv_state_variable_2 = 2 [L2610] ref_cnt = ref_cnt + 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=3, tmp___2=1, tmp___4=4] [L2412] tmp___1 = __VERIFIER_nondet_int() [L2414] case 0: [L2420] case 1: [L2456] case 2: [L2550] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=3, tmp___2=1, tmp___4=4] [L2551] COND TRUE ldv_state_variable_2 != 0 [L2552] tmp___4 = __VERIFIER_nondet_int() [L2554] case 0: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=3, tmp___2=1, tmp___4=0] [L2555] COND FALSE !(ldv_state_variable_2 == 4) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=3, tmp___2=1, tmp___4=0] [L2560] COND TRUE ldv_state_variable_2 == 2 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=21, ldvarg1={0:0}, ldvarg2={3:0}, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=21, tmp___1=3, tmp___2=1, tmp___4=0] [L2561] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2214] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, dev={0:8}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1952] struct tegra_rtc_info *info ; [L1953] void *tmp ; [L1954] unsigned int status ; [L1955] unsigned long sl_irq_flags ; [L1956] u32 __v ; [L1957] u32 __v___0 ; VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, dev={0:8}, dev={0:8}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, arg0={0:8}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_nondet_pointer(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, arg0={0:8}, arg0={0:8}, external_alloc()={4294967335:4294967362}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1959] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, dev={0:8}, dev={0:8}, dev_get_drvdata((struct device const *)dev)={4294967335:4294967362}, enabled=0, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1959] tmp = dev_get_drvdata((struct device const *)dev) [L1960] info = (struct tegra_rtc_info *)tmp VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, dev={0:8}, dev={0:8}, enabled=0, info={4294967335:4294967362}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={4294967335:4294967362}] [L1961] CALL tegra_rtc_wait_while_busy(dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, dev={0:8}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1835] struct tegra_rtc_info *info ; [L1836] void *tmp ; [L1837] int retries ; [L1838] int tmp___0 ; [L1839] u32 tmp___1 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, dev={0:8}, dev={0:8}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] CALL, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, arg0={0:8}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] CALL, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2893] return __VERIFIER_nondet_pointer(); [L2801] RET, EXPR external_alloc() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, arg0={0:8}, arg0={0:8}, external_alloc()={4294967355:8}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2801] return (void *)external_alloc(); [L1841] RET, EXPR dev_get_drvdata((struct device const *)dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, dev={0:8}, dev={0:8}, dev_get_drvdata((struct device const *)dev)={4294967355:8}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1841] tmp = dev_get_drvdata((struct device const *)dev) [L1842] info = (struct tegra_rtc_info *)tmp [L1843] retries = 500 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, dev={0:8}, dev={0:8}, info={4294967355:8}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={4294967355:8}] [L1854] CALL, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, info={4294967355:8}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1825] u32 __v ; [L1826] u32 __v___0 ; [L1828] EXPR info->rtc_base [L1828] EXPR (unsigned int volatile *)info->rtc_base + 4U [L1828] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1829] __v = __v___0 [L1830] return (__v & 1U); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, __v=2, __v___0=2, info={4294967355:8}, info={4294967355:8}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1854] RET, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, dev={0:8}, dev={0:8}, info={4294967355:8}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_check_busy(info)=4294967296, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={4294967355:8}] [L1854] tmp___1 = tegra_rtc_check_busy(info) [L1855] COND FALSE !(tmp___1 != 0U) [L1859] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, \result=0, __this_module={4294967325:4294967308}, dev={0:8}, dev={0:8}, info={4294967355:8}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={4294967355:8}, tmp___1=0] [L1961] RET tegra_rtc_wait_while_busy(dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, dev={0:8}, dev={0:8}, enabled=0, info={4294967335:4294967362}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tegra_rtc_wait_while_busy(dev)=0, tmp={4294967335:4294967362}] [L1962] CALL ldv_spin_lock_check() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2775] COND FALSE !(ldv_init == 1) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2777] CALL ldv_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1664] __VERIFIER_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=0, \old(tegra_rtc_driver_group0)=0, __this_module={4294967325:4294967308}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-5:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-6:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 96 procedures, 671 locations, 1 error locations. UNSAFE Result, 13.2s OverallTime, 13 OverallIterations, 4 TraceHistogramMax, 8.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5046 SDtfs, 6551 SDslu, 18577 SDs, 0 SdLazy, 4261 SolverSat, 1530 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 513 GetRequests, 380 SyntacticMatches, 0 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 383 ImplicationChecksByTransitivity, 2.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1475occurred in iteration=9, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.8s AutomataMinimizationTime, 12 MinimizatonAttempts, 1779 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 1.1s SatisfiabilityAnalysisTime, 1.7s InterpolantComputationTime, 1443 NumberOfCodeBlocks, 1443 NumberOfCodeBlocksAsserted, 17 NumberOfCheckSat, 1308 ConstructedInterpolants, 0 QuantifiedInterpolants, 150756 SizeOfPredicates, 4 NumberOfNonLiveVariables, 3836 ConjunctsInSsa, 18 ConjunctsInUnsatCore, 16 InterpolantComputations, 9 PerfectInterpolantSequences, 221/250 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request...