java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/svcomp-Reach-32bit-Automizer_Default+AIv2_INT.epf -i ../../../trunk/examples/svcomp/systemc/transmitter.05.cil.c -------------------------------------------------------------------------------- This is Ultimate 0.1.24-673a906-m [2019-10-03 04:12:03,602 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-03 04:12:03,604 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-03 04:12:03,615 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-03 04:12:03,616 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-03 04:12:03,617 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-03 04:12:03,618 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-03 04:12:03,620 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-03 04:12:03,622 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-03 04:12:03,623 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-03 04:12:03,624 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-03 04:12:03,625 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-03 04:12:03,625 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-03 04:12:03,626 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-03 04:12:03,627 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-03 04:12:03,628 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-03 04:12:03,629 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-03 04:12:03,630 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-03 04:12:03,632 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-03 04:12:03,634 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-03 04:12:03,635 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-03 04:12:03,637 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-03 04:12:03,638 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-03 04:12:03,638 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-03 04:12:03,641 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-10-03 04:12:03,641 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-10-03 04:12:03,641 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-10-03 04:12:03,642 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-10-03 04:12:03,643 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-10-03 04:12:03,644 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-10-03 04:12:03,644 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-03 04:12:03,645 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-03 04:12:03,646 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-03 04:12:03,646 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-03 04:12:03,648 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-03 04:12:03,648 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-03 04:12:03,649 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-03 04:12:03,649 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-03 04:12:03,649 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-03 04:12:03,650 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-03 04:12:03,651 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-03 04:12:03,651 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/svcomp-Reach-32bit-Automizer_Default+AIv2_INT.epf [2019-10-03 04:12:03,666 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-03 04:12:03,667 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-03 04:12:03,667 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2019-10-03 04:12:03,667 INFO L138 SettingsManager]: * Log level for plugins=info [2019-10-03 04:12:03,668 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-10-03 04:12:03,668 INFO L138 SettingsManager]: * User list type=DISABLED [2019-10-03 04:12:03,668 INFO L138 SettingsManager]: * Ignore calls to and inside polymorphic procedures=false [2019-10-03 04:12:03,668 INFO L138 SettingsManager]: * Ignore calls to recursive procedures=false [2019-10-03 04:12:03,669 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-10-03 04:12:03,669 INFO L138 SettingsManager]: * Abstract domain=IntervalDomain [2019-10-03 04:12:03,670 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-03 04:12:03,670 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-03 04:12:03,670 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-03 04:12:03,670 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-03 04:12:03,670 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-03 04:12:03,671 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-03 04:12:03,671 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-03 04:12:03,671 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-03 04:12:03,671 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-03 04:12:03,671 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-03 04:12:03,672 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-03 04:12:03,672 INFO L138 SettingsManager]: * Remove goto edges from RCFG=true [2019-10-03 04:12:03,672 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-03 04:12:03,672 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-03 04:12:03,672 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-03 04:12:03,673 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-03 04:12:03,673 INFO L138 SettingsManager]: * Trace refinement strategy=TAIPAN [2019-10-03 04:12:03,673 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-03 04:12:03,673 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-10-03 04:12:03,673 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-10-03 04:12:03,722 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-03 04:12:03,739 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-03 04:12:03,745 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-03 04:12:03,746 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-03 04:12:03,747 INFO L275 PluginConnector]: CDTParser initialized [2019-10-03 04:12:03,747 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/systemc/transmitter.05.cil.c [2019-10-03 04:12:03,818 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e0cb4497f/7b17685691194d578a55da3db209cbea/FLAG6d9bcb83b [2019-10-03 04:12:04,280 INFO L306 CDTParser]: Found 1 translation units. [2019-10-03 04:12:04,281 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/systemc/transmitter.05.cil.c [2019-10-03 04:12:04,293 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e0cb4497f/7b17685691194d578a55da3db209cbea/FLAG6d9bcb83b [2019-10-03 04:12:04,674 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e0cb4497f/7b17685691194d578a55da3db209cbea [2019-10-03 04:12:04,683 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-03 04:12:04,685 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-03 04:12:04,686 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-03 04:12:04,686 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-03 04:12:04,690 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-03 04:12:04,691 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.10 04:12:04" (1/1) ... [2019-10-03 04:12:04,694 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4db268e0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.10 04:12:04, skipping insertion in model container [2019-10-03 04:12:04,695 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.10 04:12:04" (1/1) ... [2019-10-03 04:12:04,703 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-03 04:12:04,760 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-03 04:12:05,043 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-03 04:12:05,055 INFO L188 MainTranslator]: Completed pre-run [2019-10-03 04:12:05,263 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-03 04:12:05,288 INFO L192 MainTranslator]: Completed translation [2019-10-03 04:12:05,289 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.10 04:12:05 WrapperNode [2019-10-03 04:12:05,289 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-03 04:12:05,290 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-03 04:12:05,290 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-03 04:12:05,290 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-03 04:12:05,303 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.10 04:12:05" (1/1) ... [2019-10-03 04:12:05,303 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.10 04:12:05" (1/1) ... [2019-10-03 04:12:05,314 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.10 04:12:05" (1/1) ... [2019-10-03 04:12:05,314 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.10 04:12:05" (1/1) ... [2019-10-03 04:12:05,331 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.10 04:12:05" (1/1) ... [2019-10-03 04:12:05,353 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.10 04:12:05" (1/1) ... [2019-10-03 04:12:05,357 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.10 04:12:05" (1/1) ... [2019-10-03 04:12:05,365 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-03 04:12:05,366 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-03 04:12:05,366 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-03 04:12:05,366 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-03 04:12:05,367 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.10 04:12:05" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-03 04:12:05,426 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-03 04:12:05,426 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-03 04:12:05,426 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2019-10-03 04:12:05,427 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2019-10-03 04:12:05,427 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2019-10-03 04:12:05,427 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2019-10-03 04:12:05,427 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit3 [2019-10-03 04:12:05,427 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit4 [2019-10-03 04:12:05,427 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit5 [2019-10-03 04:12:05,427 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2019-10-03 04:12:05,427 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2019-10-03 04:12:05,428 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2019-10-03 04:12:05,428 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit3_triggered [2019-10-03 04:12:05,429 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit4_triggered [2019-10-03 04:12:05,429 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit5_triggered [2019-10-03 04:12:05,430 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2019-10-03 04:12:05,430 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2019-10-03 04:12:05,430 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2019-10-03 04:12:05,430 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2019-10-03 04:12:05,430 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2019-10-03 04:12:05,431 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2019-10-03 04:12:05,431 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2019-10-03 04:12:05,431 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2019-10-03 04:12:05,431 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2019-10-03 04:12:05,431 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2019-10-03 04:12:05,432 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2019-10-03 04:12:05,432 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2019-10-03 04:12:05,432 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2019-10-03 04:12:05,432 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-03 04:12:05,433 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-03 04:12:05,433 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-03 04:12:05,433 INFO L130 BoogieDeclarations]: Found specification of procedure error [2019-10-03 04:12:05,433 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2019-10-03 04:12:05,433 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2019-10-03 04:12:05,433 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2019-10-03 04:12:05,434 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit3_triggered [2019-10-03 04:12:05,434 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit4_triggered [2019-10-03 04:12:05,434 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit5_triggered [2019-10-03 04:12:05,435 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2019-10-03 04:12:05,435 INFO L130 BoogieDeclarations]: Found specification of procedure master [2019-10-03 04:12:05,435 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2019-10-03 04:12:05,435 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2019-10-03 04:12:05,435 INFO L130 BoogieDeclarations]: Found specification of procedure transmit3 [2019-10-03 04:12:05,435 INFO L130 BoogieDeclarations]: Found specification of procedure transmit4 [2019-10-03 04:12:05,435 INFO L130 BoogieDeclarations]: Found specification of procedure transmit5 [2019-10-03 04:12:05,436 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2019-10-03 04:12:05,436 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2019-10-03 04:12:05,436 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2019-10-03 04:12:05,436 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2019-10-03 04:12:05,436 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2019-10-03 04:12:05,436 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2019-10-03 04:12:05,437 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2019-10-03 04:12:05,437 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2019-10-03 04:12:05,437 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2019-10-03 04:12:05,437 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2019-10-03 04:12:05,437 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2019-10-03 04:12:05,437 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2019-10-03 04:12:05,437 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-03 04:12:05,438 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-03 04:12:05,438 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-03 04:12:06,270 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-03 04:12:06,271 INFO L283 CfgBuilder]: Removed 9 assume(true) statements. [2019-10-03 04:12:06,272 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.10 04:12:06 BoogieIcfgContainer [2019-10-03 04:12:06,272 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-03 04:12:06,273 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-03 04:12:06,274 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-03 04:12:06,277 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-03 04:12:06,277 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.10 04:12:04" (1/3) ... [2019-10-03 04:12:06,278 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6e34e855 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.10 04:12:06, skipping insertion in model container [2019-10-03 04:12:06,278 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.10 04:12:05" (2/3) ... [2019-10-03 04:12:06,278 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6e34e855 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.10 04:12:06, skipping insertion in model container [2019-10-03 04:12:06,279 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.10 04:12:06" (3/3) ... [2019-10-03 04:12:06,280 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.05.cil.c [2019-10-03 04:12:06,289 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-03 04:12:06,295 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-03 04:12:06,312 INFO L252 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-03 04:12:06,340 INFO L377 AbstractCegarLoop]: Interprodecural is true [2019-10-03 04:12:06,340 INFO L378 AbstractCegarLoop]: Hoare is false [2019-10-03 04:12:06,340 INFO L379 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-03 04:12:06,340 INFO L380 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-03 04:12:06,341 INFO L381 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-03 04:12:06,341 INFO L382 AbstractCegarLoop]: Difference is false [2019-10-03 04:12:06,341 INFO L383 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-03 04:12:06,341 INFO L388 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-03 04:12:06,364 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states. [2019-10-03 04:12:06,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:06,384 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:06,385 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:06,388 INFO L418 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:06,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:06,394 INFO L82 PathProgramCache]: Analyzing trace with hash 1433392200, now seen corresponding path program 1 times [2019-10-03 04:12:06,396 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:06,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:06,453 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:06,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:06,454 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:06,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:06,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:06,848 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:06,848 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-03 04:12:06,849 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:06,854 INFO L454 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-03 04:12:06,870 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-03 04:12:06,871 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-03 04:12:06,874 INFO L87 Difference]: Start difference. First operand 259 states. Second operand 4 states. [2019-10-03 04:12:07,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:07,144 INFO L93 Difference]: Finished difference Result 257 states and 357 transitions. [2019-10-03 04:12:07,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-03 04:12:07,146 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2019-10-03 04:12:07,146 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:07,163 INFO L225 Difference]: With dead ends: 257 [2019-10-03 04:12:07,163 INFO L226 Difference]: Without dead ends: 250 [2019-10-03 04:12:07,165 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-03 04:12:07,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 250 states. [2019-10-03 04:12:07,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 250 to 250. [2019-10-03 04:12:07,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2019-10-03 04:12:07,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 350 transitions. [2019-10-03 04:12:07,241 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 350 transitions. Word has length 135 [2019-10-03 04:12:07,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:07,244 INFO L475 AbstractCegarLoop]: Abstraction has 250 states and 350 transitions. [2019-10-03 04:12:07,244 INFO L476 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-03 04:12:07,244 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 350 transitions. [2019-10-03 04:12:07,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:07,249 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:07,249 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:07,250 INFO L418 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:07,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:07,251 INFO L82 PathProgramCache]: Analyzing trace with hash -1139572410, now seen corresponding path program 1 times [2019-10-03 04:12:07,252 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:07,254 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:07,254 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:07,254 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:07,254 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:07,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:07,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:07,529 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:07,529 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:07,529 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:07,536 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:07,542 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:07,543 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:07,543 INFO L87 Difference]: Start difference. First operand 250 states and 350 transitions. Second operand 5 states. [2019-10-03 04:12:08,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:08,208 INFO L93 Difference]: Finished difference Result 290 states and 420 transitions. [2019-10-03 04:12:08,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:08,209 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:08,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:08,218 INFO L225 Difference]: With dead ends: 290 [2019-10-03 04:12:08,218 INFO L226 Difference]: Without dead ends: 290 [2019-10-03 04:12:08,219 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:08,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 290 states. [2019-10-03 04:12:08,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 290 to 250. [2019-10-03 04:12:08,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2019-10-03 04:12:08,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 349 transitions. [2019-10-03 04:12:08,249 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 349 transitions. Word has length 135 [2019-10-03 04:12:08,249 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:08,249 INFO L475 AbstractCegarLoop]: Abstraction has 250 states and 349 transitions. [2019-10-03 04:12:08,250 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:08,250 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 349 transitions. [2019-10-03 04:12:08,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:08,253 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:08,253 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:08,253 INFO L418 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:08,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:08,254 INFO L82 PathProgramCache]: Analyzing trace with hash 1024044164, now seen corresponding path program 1 times [2019-10-03 04:12:08,254 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:08,256 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:08,256 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:08,256 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:08,256 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:08,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:08,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:08,397 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:08,397 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:08,397 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:08,398 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:08,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:08,399 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:08,399 INFO L87 Difference]: Start difference. First operand 250 states and 349 transitions. Second operand 5 states. [2019-10-03 04:12:08,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:08,976 INFO L93 Difference]: Finished difference Result 290 states and 420 transitions. [2019-10-03 04:12:08,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:08,976 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:08,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:08,979 INFO L225 Difference]: With dead ends: 290 [2019-10-03 04:12:08,979 INFO L226 Difference]: Without dead ends: 290 [2019-10-03 04:12:08,980 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:08,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 290 states. [2019-10-03 04:12:08,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 290 to 250. [2019-10-03 04:12:08,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2019-10-03 04:12:08,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 348 transitions. [2019-10-03 04:12:08,999 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 348 transitions. Word has length 135 [2019-10-03 04:12:08,999 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:08,999 INFO L475 AbstractCegarLoop]: Abstraction has 250 states and 348 transitions. [2019-10-03 04:12:08,999 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:08,999 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 348 transitions. [2019-10-03 04:12:09,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:09,002 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:09,003 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:09,003 INFO L418 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:09,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:09,003 INFO L82 PathProgramCache]: Analyzing trace with hash -14540410, now seen corresponding path program 1 times [2019-10-03 04:12:09,004 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:09,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:09,005 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:09,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:09,005 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:09,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:09,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:09,097 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:09,098 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:09,098 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:09,098 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:09,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:09,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:09,099 INFO L87 Difference]: Start difference. First operand 250 states and 348 transitions. Second operand 5 states. [2019-10-03 04:12:09,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:09,805 INFO L93 Difference]: Finished difference Result 288 states and 415 transitions. [2019-10-03 04:12:09,806 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:09,806 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:09,806 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:09,808 INFO L225 Difference]: With dead ends: 288 [2019-10-03 04:12:09,809 INFO L226 Difference]: Without dead ends: 288 [2019-10-03 04:12:09,809 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:09,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2019-10-03 04:12:09,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 250. [2019-10-03 04:12:09,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2019-10-03 04:12:09,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 347 transitions. [2019-10-03 04:12:09,823 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 347 transitions. Word has length 135 [2019-10-03 04:12:09,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:09,824 INFO L475 AbstractCegarLoop]: Abstraction has 250 states and 347 transitions. [2019-10-03 04:12:09,824 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:09,824 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 347 transitions. [2019-10-03 04:12:09,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:09,826 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:09,827 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:09,827 INFO L418 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:09,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:09,827 INFO L82 PathProgramCache]: Analyzing trace with hash -1987705788, now seen corresponding path program 1 times [2019-10-03 04:12:09,828 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:09,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:09,829 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:09,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:09,829 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:09,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:09,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:09,898 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:09,899 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:09,899 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:09,899 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:09,900 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:09,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:09,900 INFO L87 Difference]: Start difference. First operand 250 states and 347 transitions. Second operand 5 states. [2019-10-03 04:12:10,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:10,463 INFO L93 Difference]: Finished difference Result 286 states and 410 transitions. [2019-10-03 04:12:10,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:10,463 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:10,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:10,465 INFO L225 Difference]: With dead ends: 286 [2019-10-03 04:12:10,466 INFO L226 Difference]: Without dead ends: 286 [2019-10-03 04:12:10,466 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:10,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286 states. [2019-10-03 04:12:10,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286 to 250. [2019-10-03 04:12:10,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2019-10-03 04:12:10,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 346 transitions. [2019-10-03 04:12:10,480 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 346 transitions. Word has length 135 [2019-10-03 04:12:10,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:10,480 INFO L475 AbstractCegarLoop]: Abstraction has 250 states and 346 transitions. [2019-10-03 04:12:10,480 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:10,481 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 346 transitions. [2019-10-03 04:12:10,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:10,483 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:10,483 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:10,483 INFO L418 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:10,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:10,484 INFO L82 PathProgramCache]: Analyzing trace with hash 165401030, now seen corresponding path program 1 times [2019-10-03 04:12:10,484 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:10,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:10,485 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:10,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:10,485 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:10,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:10,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:10,553 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:10,554 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:10,554 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:10,554 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:10,555 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:10,555 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:10,555 INFO L87 Difference]: Start difference. First operand 250 states and 346 transitions. Second operand 5 states. [2019-10-03 04:12:11,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:11,142 INFO L93 Difference]: Finished difference Result 284 states and 405 transitions. [2019-10-03 04:12:11,143 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:11,143 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:11,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:11,146 INFO L225 Difference]: With dead ends: 284 [2019-10-03 04:12:11,146 INFO L226 Difference]: Without dead ends: 284 [2019-10-03 04:12:11,147 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:11,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states. [2019-10-03 04:12:11,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 250. [2019-10-03 04:12:11,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2019-10-03 04:12:11,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 345 transitions. [2019-10-03 04:12:11,158 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 345 transitions. Word has length 135 [2019-10-03 04:12:11,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:11,158 INFO L475 AbstractCegarLoop]: Abstraction has 250 states and 345 transitions. [2019-10-03 04:12:11,158 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:11,159 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 345 transitions. [2019-10-03 04:12:11,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:11,160 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:11,161 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:11,161 INFO L418 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:11,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:11,161 INFO L82 PathProgramCache]: Analyzing trace with hash -457880572, now seen corresponding path program 1 times [2019-10-03 04:12:11,162 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:11,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:11,163 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:11,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:11,163 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:11,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:11,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:11,229 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:11,229 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:11,229 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:11,229 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:11,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:11,230 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:11,230 INFO L87 Difference]: Start difference. First operand 250 states and 345 transitions. Second operand 5 states. [2019-10-03 04:12:11,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:11,783 INFO L93 Difference]: Finished difference Result 282 states and 400 transitions. [2019-10-03 04:12:11,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:11,783 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:11,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:11,787 INFO L225 Difference]: With dead ends: 282 [2019-10-03 04:12:11,787 INFO L226 Difference]: Without dead ends: 282 [2019-10-03 04:12:11,788 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:11,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2019-10-03 04:12:11,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 250. [2019-10-03 04:12:11,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2019-10-03 04:12:11,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 344 transitions. [2019-10-03 04:12:11,798 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 344 transitions. Word has length 135 [2019-10-03 04:12:11,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:11,799 INFO L475 AbstractCegarLoop]: Abstraction has 250 states and 344 transitions. [2019-10-03 04:12:11,799 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:11,799 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 344 transitions. [2019-10-03 04:12:11,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:11,801 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:11,801 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:11,801 INFO L418 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:11,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:11,802 INFO L82 PathProgramCache]: Analyzing trace with hash -339439098, now seen corresponding path program 1 times [2019-10-03 04:12:11,802 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:11,803 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:11,803 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:11,803 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:11,803 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:11,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:11,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:11,890 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:11,890 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:11,890 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:11,891 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:11,891 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:11,891 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:11,892 INFO L87 Difference]: Start difference. First operand 250 states and 344 transitions. Second operand 5 states. [2019-10-03 04:12:12,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:12,413 INFO L93 Difference]: Finished difference Result 308 states and 445 transitions. [2019-10-03 04:12:12,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:12,413 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:12,414 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:12,416 INFO L225 Difference]: With dead ends: 308 [2019-10-03 04:12:12,416 INFO L226 Difference]: Without dead ends: 308 [2019-10-03 04:12:12,417 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:12,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states. [2019-10-03 04:12:12,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 250. [2019-10-03 04:12:12,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2019-10-03 04:12:12,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 343 transitions. [2019-10-03 04:12:12,427 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 343 transitions. Word has length 135 [2019-10-03 04:12:12,428 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:12,428 INFO L475 AbstractCegarLoop]: Abstraction has 250 states and 343 transitions. [2019-10-03 04:12:12,428 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:12,428 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 343 transitions. [2019-10-03 04:12:12,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:12,430 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:12,430 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:12,431 INFO L418 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:12,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:12,431 INFO L82 PathProgramCache]: Analyzing trace with hash 1049854916, now seen corresponding path program 1 times [2019-10-03 04:12:12,431 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:12,432 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:12,433 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:12,433 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:12,433 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:12,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:12,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:12,511 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:12,511 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:12,512 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:12,513 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:12,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:12,516 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:12,516 INFO L87 Difference]: Start difference. First operand 250 states and 343 transitions. Second operand 5 states. [2019-10-03 04:12:13,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:13,010 INFO L93 Difference]: Finished difference Result 304 states and 436 transitions. [2019-10-03 04:12:13,010 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:13,010 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:13,010 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:13,013 INFO L225 Difference]: With dead ends: 304 [2019-10-03 04:12:13,013 INFO L226 Difference]: Without dead ends: 304 [2019-10-03 04:12:13,014 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:13,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304 states. [2019-10-03 04:12:13,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304 to 250. [2019-10-03 04:12:13,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2019-10-03 04:12:13,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 342 transitions. [2019-10-03 04:12:13,037 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 342 transitions. Word has length 135 [2019-10-03 04:12:13,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:13,037 INFO L475 AbstractCegarLoop]: Abstraction has 250 states and 342 transitions. [2019-10-03 04:12:13,037 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:13,037 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 342 transitions. [2019-10-03 04:12:13,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:13,039 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:13,040 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:13,040 INFO L418 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:13,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:13,041 INFO L82 PathProgramCache]: Analyzing trace with hash -816853758, now seen corresponding path program 1 times [2019-10-03 04:12:13,041 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:13,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:13,044 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:13,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:13,044 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:13,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:13,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:13,192 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:13,192 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:13,192 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:13,193 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:13,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:13,194 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:13,194 INFO L87 Difference]: Start difference. First operand 250 states and 342 transitions. Second operand 5 states. [2019-10-03 04:12:13,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:13,665 INFO L93 Difference]: Finished difference Result 302 states and 431 transitions. [2019-10-03 04:12:13,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:13,666 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:13,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:13,669 INFO L225 Difference]: With dead ends: 302 [2019-10-03 04:12:13,669 INFO L226 Difference]: Without dead ends: 302 [2019-10-03 04:12:13,669 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:13,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 302 states. [2019-10-03 04:12:13,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 302 to 250. [2019-10-03 04:12:13,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2019-10-03 04:12:13,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 341 transitions. [2019-10-03 04:12:13,678 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 341 transitions. Word has length 135 [2019-10-03 04:12:13,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:13,679 INFO L475 AbstractCegarLoop]: Abstraction has 250 states and 341 transitions. [2019-10-03 04:12:13,679 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:13,679 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 341 transitions. [2019-10-03 04:12:13,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:13,681 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:13,681 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:13,681 INFO L418 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:13,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:13,682 INFO L82 PathProgramCache]: Analyzing trace with hash -2123996156, now seen corresponding path program 1 times [2019-10-03 04:12:13,682 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:13,683 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:13,683 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:13,683 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:13,683 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:13,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:13,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:13,756 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:13,756 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:13,756 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:13,756 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:13,757 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:13,757 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:13,757 INFO L87 Difference]: Start difference. First operand 250 states and 341 transitions. Second operand 5 states. [2019-10-03 04:12:14,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:14,236 INFO L93 Difference]: Finished difference Result 300 states and 426 transitions. [2019-10-03 04:12:14,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:14,236 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:14,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:14,238 INFO L225 Difference]: With dead ends: 300 [2019-10-03 04:12:14,239 INFO L226 Difference]: Without dead ends: 300 [2019-10-03 04:12:14,239 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:14,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 300 states. [2019-10-03 04:12:14,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 300 to 250. [2019-10-03 04:12:14,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2019-10-03 04:12:14,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 340 transitions. [2019-10-03 04:12:14,289 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 340 transitions. Word has length 135 [2019-10-03 04:12:14,289 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:14,289 INFO L475 AbstractCegarLoop]: Abstraction has 250 states and 340 transitions. [2019-10-03 04:12:14,289 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:14,289 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 340 transitions. [2019-10-03 04:12:14,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:14,291 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:14,292 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:14,292 INFO L418 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:14,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:14,293 INFO L82 PathProgramCache]: Analyzing trace with hash -226499390, now seen corresponding path program 1 times [2019-10-03 04:12:14,294 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:14,295 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:14,295 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:14,295 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:14,295 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:14,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:14,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:14,368 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:14,369 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-03 04:12:14,369 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:14,369 INFO L454 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-03 04:12:14,369 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-03 04:12:14,370 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-03 04:12:14,371 INFO L87 Difference]: Start difference. First operand 250 states and 340 transitions. Second operand 4 states. [2019-10-03 04:12:14,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:14,632 INFO L93 Difference]: Finished difference Result 468 states and 634 transitions. [2019-10-03 04:12:14,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-03 04:12:14,633 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2019-10-03 04:12:14,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:14,637 INFO L225 Difference]: With dead ends: 468 [2019-10-03 04:12:14,637 INFO L226 Difference]: Without dead ends: 468 [2019-10-03 04:12:14,638 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-03 04:12:14,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 468 states. [2019-10-03 04:12:14,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 468 to 463. [2019-10-03 04:12:14,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2019-10-03 04:12:14,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 630 transitions. [2019-10-03 04:12:14,663 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 630 transitions. Word has length 135 [2019-10-03 04:12:14,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:14,664 INFO L475 AbstractCegarLoop]: Abstraction has 463 states and 630 transitions. [2019-10-03 04:12:14,664 INFO L476 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-03 04:12:14,665 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 630 transitions. [2019-10-03 04:12:14,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:14,667 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:14,668 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:14,668 INFO L418 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:14,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:14,669 INFO L82 PathProgramCache]: Analyzing trace with hash 890685571, now seen corresponding path program 1 times [2019-10-03 04:12:14,669 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:14,671 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:14,671 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:14,671 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:14,672 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:14,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:14,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:14,765 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:14,765 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-03 04:12:14,765 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:14,766 INFO L454 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-03 04:12:14,766 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-03 04:12:14,767 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-03 04:12:14,767 INFO L87 Difference]: Start difference. First operand 463 states and 630 transitions. Second operand 4 states. [2019-10-03 04:12:15,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:15,063 INFO L93 Difference]: Finished difference Result 889 states and 1205 transitions. [2019-10-03 04:12:15,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-03 04:12:15,064 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2019-10-03 04:12:15,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:15,070 INFO L225 Difference]: With dead ends: 889 [2019-10-03 04:12:15,071 INFO L226 Difference]: Without dead ends: 889 [2019-10-03 04:12:15,071 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-03 04:12:15,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 889 states. [2019-10-03 04:12:15,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 889 to 882. [2019-10-03 04:12:15,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 882 states. [2019-10-03 04:12:15,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 882 states to 882 states and 1199 transitions. [2019-10-03 04:12:15,102 INFO L78 Accepts]: Start accepts. Automaton has 882 states and 1199 transitions. Word has length 135 [2019-10-03 04:12:15,103 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:15,103 INFO L475 AbstractCegarLoop]: Abstraction has 882 states and 1199 transitions. [2019-10-03 04:12:15,103 INFO L476 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-03 04:12:15,103 INFO L276 IsEmpty]: Start isEmpty. Operand 882 states and 1199 transitions. [2019-10-03 04:12:15,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:15,105 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:15,105 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:15,105 INFO L418 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:15,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:15,106 INFO L82 PathProgramCache]: Analyzing trace with hash 435779490, now seen corresponding path program 1 times [2019-10-03 04:12:15,106 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:15,107 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:15,108 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:15,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:15,108 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:15,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:15,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:15,184 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:15,185 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-03 04:12:15,185 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:15,185 INFO L454 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-03 04:12:15,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-03 04:12:15,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:15,186 INFO L87 Difference]: Start difference. First operand 882 states and 1199 transitions. Second operand 6 states. [2019-10-03 04:12:15,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:15,222 INFO L93 Difference]: Finished difference Result 920 states and 1255 transitions. [2019-10-03 04:12:15,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-03 04:12:15,222 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 135 [2019-10-03 04:12:15,223 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:15,228 INFO L225 Difference]: With dead ends: 920 [2019-10-03 04:12:15,228 INFO L226 Difference]: Without dead ends: 920 [2019-10-03 04:12:15,229 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2019-10-03 04:12:15,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 920 states. [2019-10-03 04:12:15,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 920 to 892. [2019-10-03 04:12:15,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 892 states. [2019-10-03 04:12:15,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 892 states to 892 states and 1207 transitions. [2019-10-03 04:12:15,259 INFO L78 Accepts]: Start accepts. Automaton has 892 states and 1207 transitions. Word has length 135 [2019-10-03 04:12:15,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:15,260 INFO L475 AbstractCegarLoop]: Abstraction has 892 states and 1207 transitions. [2019-10-03 04:12:15,260 INFO L476 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-03 04:12:15,260 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 1207 transitions. [2019-10-03 04:12:15,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:15,262 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:15,262 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:15,262 INFO L418 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:15,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:15,263 INFO L82 PathProgramCache]: Analyzing trace with hash 1274813152, now seen corresponding path program 1 times [2019-10-03 04:12:15,263 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:15,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:15,264 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:15,265 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:15,265 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:15,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:15,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:15,351 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:15,351 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-03 04:12:15,352 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:15,352 INFO L454 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-03 04:12:15,352 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-03 04:12:15,353 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-03 04:12:15,353 INFO L87 Difference]: Start difference. First operand 892 states and 1207 transitions. Second operand 4 states. [2019-10-03 04:12:15,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:15,659 INFO L93 Difference]: Finished difference Result 1735 states and 2341 transitions. [2019-10-03 04:12:15,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-03 04:12:15,660 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2019-10-03 04:12:15,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:15,670 INFO L225 Difference]: With dead ends: 1735 [2019-10-03 04:12:15,670 INFO L226 Difference]: Without dead ends: 1735 [2019-10-03 04:12:15,670 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-03 04:12:15,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1735 states. [2019-10-03 04:12:15,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1735 to 1724. [2019-10-03 04:12:15,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1724 states. [2019-10-03 04:12:15,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1724 states to 1724 states and 2331 transitions. [2019-10-03 04:12:15,724 INFO L78 Accepts]: Start accepts. Automaton has 1724 states and 2331 transitions. Word has length 135 [2019-10-03 04:12:15,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:15,725 INFO L475 AbstractCegarLoop]: Abstraction has 1724 states and 2331 transitions. [2019-10-03 04:12:15,725 INFO L476 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-03 04:12:15,725 INFO L276 IsEmpty]: Start isEmpty. Operand 1724 states and 2331 transitions. [2019-10-03 04:12:15,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:15,727 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:15,727 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:15,727 INFO L418 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:15,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:15,728 INFO L82 PathProgramCache]: Analyzing trace with hash 1415912673, now seen corresponding path program 1 times [2019-10-03 04:12:15,728 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:15,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:15,729 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:15,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:15,730 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:15,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:15,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:15,796 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:15,796 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-03 04:12:15,796 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:15,796 INFO L454 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-03 04:12:15,797 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-03 04:12:15,797 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-03 04:12:15,797 INFO L87 Difference]: Start difference. First operand 1724 states and 2331 transitions. Second operand 4 states. [2019-10-03 04:12:16,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:16,094 INFO L93 Difference]: Finished difference Result 3375 states and 4559 transitions. [2019-10-03 04:12:16,094 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-03 04:12:16,094 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2019-10-03 04:12:16,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:16,119 INFO L225 Difference]: With dead ends: 3375 [2019-10-03 04:12:16,119 INFO L226 Difference]: Without dead ends: 3375 [2019-10-03 04:12:16,120 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-03 04:12:16,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3375 states. [2019-10-03 04:12:16,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3375 to 3356. [2019-10-03 04:12:16,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3356 states. [2019-10-03 04:12:16,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3356 states to 3356 states and 4541 transitions. [2019-10-03 04:12:16,265 INFO L78 Accepts]: Start accepts. Automaton has 3356 states and 4541 transitions. Word has length 135 [2019-10-03 04:12:16,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:16,266 INFO L475 AbstractCegarLoop]: Abstraction has 3356 states and 4541 transitions. [2019-10-03 04:12:16,266 INFO L476 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-03 04:12:16,266 INFO L276 IsEmpty]: Start isEmpty. Operand 3356 states and 4541 transitions. [2019-10-03 04:12:16,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:16,269 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:16,270 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:16,270 INFO L418 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:16,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:16,271 INFO L82 PathProgramCache]: Analyzing trace with hash 237938112, now seen corresponding path program 1 times [2019-10-03 04:12:16,271 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:16,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:16,272 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:16,273 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:16,273 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:16,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:16,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:16,349 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:16,349 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-03 04:12:16,350 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:16,350 INFO L454 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-03 04:12:16,350 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-03 04:12:16,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:16,351 INFO L87 Difference]: Start difference. First operand 3356 states and 4541 transitions. Second operand 6 states. [2019-10-03 04:12:16,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:16,429 INFO L93 Difference]: Finished difference Result 3460 states and 4685 transitions. [2019-10-03 04:12:16,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-03 04:12:16,429 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 135 [2019-10-03 04:12:16,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:16,449 INFO L225 Difference]: With dead ends: 3460 [2019-10-03 04:12:16,449 INFO L226 Difference]: Without dead ends: 3460 [2019-10-03 04:12:16,450 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2019-10-03 04:12:16,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3460 states. [2019-10-03 04:12:16,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3460 to 3396. [2019-10-03 04:12:16,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3396 states. [2019-10-03 04:12:16,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3396 states to 3396 states and 4573 transitions. [2019-10-03 04:12:16,556 INFO L78 Accepts]: Start accepts. Automaton has 3396 states and 4573 transitions. Word has length 135 [2019-10-03 04:12:16,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:16,557 INFO L475 AbstractCegarLoop]: Abstraction has 3396 states and 4573 transitions. [2019-10-03 04:12:16,557 INFO L476 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-03 04:12:16,557 INFO L276 IsEmpty]: Start isEmpty. Operand 3396 states and 4573 transitions. [2019-10-03 04:12:16,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:16,559 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:16,559 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:16,559 INFO L418 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:16,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:16,560 INFO L82 PathProgramCache]: Analyzing trace with hash 439762046, now seen corresponding path program 1 times [2019-10-03 04:12:16,560 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:16,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:16,561 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:16,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:16,561 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:16,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:16,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:16,628 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:16,628 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-03 04:12:16,629 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:16,631 INFO L454 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-03 04:12:16,631 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-03 04:12:16,632 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:16,632 INFO L87 Difference]: Start difference. First operand 3396 states and 4573 transitions. Second operand 6 states. [2019-10-03 04:12:16,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:16,677 INFO L93 Difference]: Finished difference Result 3508 states and 4718 transitions. [2019-10-03 04:12:16,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-03 04:12:16,677 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 135 [2019-10-03 04:12:16,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:16,728 INFO L225 Difference]: With dead ends: 3508 [2019-10-03 04:12:16,728 INFO L226 Difference]: Without dead ends: 3508 [2019-10-03 04:12:16,728 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2019-10-03 04:12:16,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3508 states. [2019-10-03 04:12:16,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3508 to 3476. [2019-10-03 04:12:16,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3476 states. [2019-10-03 04:12:16,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3476 states to 3476 states and 4653 transitions. [2019-10-03 04:12:16,823 INFO L78 Accepts]: Start accepts. Automaton has 3476 states and 4653 transitions. Word has length 135 [2019-10-03 04:12:16,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:16,823 INFO L475 AbstractCegarLoop]: Abstraction has 3476 states and 4653 transitions. [2019-10-03 04:12:16,824 INFO L476 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-03 04:12:16,824 INFO L276 IsEmpty]: Start isEmpty. Operand 3476 states and 4653 transitions. [2019-10-03 04:12:16,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:16,826 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:16,826 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:16,826 INFO L418 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:16,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:16,827 INFO L82 PathProgramCache]: Analyzing trace with hash 687908540, now seen corresponding path program 1 times [2019-10-03 04:12:16,827 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:16,828 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:16,828 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:16,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:16,829 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:16,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:16,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:16,904 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:16,904 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:16,904 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:16,906 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:16,907 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:16,907 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:16,907 INFO L87 Difference]: Start difference. First operand 3476 states and 4653 transitions. Second operand 5 states. [2019-10-03 04:12:17,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:17,711 INFO L93 Difference]: Finished difference Result 5068 states and 6774 transitions. [2019-10-03 04:12:17,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-10-03 04:12:17,712 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:17,712 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:17,749 INFO L225 Difference]: With dead ends: 5068 [2019-10-03 04:12:17,750 INFO L226 Difference]: Without dead ends: 5068 [2019-10-03 04:12:17,750 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2019-10-03 04:12:17,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5068 states. [2019-10-03 04:12:17,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5068 to 4716. [2019-10-03 04:12:17,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4716 states. [2019-10-03 04:12:17,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4716 states to 4716 states and 6133 transitions. [2019-10-03 04:12:17,914 INFO L78 Accepts]: Start accepts. Automaton has 4716 states and 6133 transitions. Word has length 135 [2019-10-03 04:12:17,914 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:17,915 INFO L475 AbstractCegarLoop]: Abstraction has 4716 states and 6133 transitions. [2019-10-03 04:12:17,915 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:17,915 INFO L276 IsEmpty]: Start isEmpty. Operand 4716 states and 6133 transitions. [2019-10-03 04:12:17,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:17,917 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:17,918 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:17,918 INFO L418 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:17,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:17,918 INFO L82 PathProgramCache]: Analyzing trace with hash -341450758, now seen corresponding path program 1 times [2019-10-03 04:12:17,918 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:17,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:17,920 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:17,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:17,920 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:17,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:17,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:17,986 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:17,986 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:17,986 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:17,987 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:17,987 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:17,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:17,988 INFO L87 Difference]: Start difference. First operand 4716 states and 6133 transitions. Second operand 5 states. [2019-10-03 04:12:18,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:18,535 INFO L93 Difference]: Finished difference Result 4716 states and 6093 transitions. [2019-10-03 04:12:18,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:18,535 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:18,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:18,559 INFO L225 Difference]: With dead ends: 4716 [2019-10-03 04:12:18,559 INFO L226 Difference]: Without dead ends: 4716 [2019-10-03 04:12:18,559 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:18,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4716 states. [2019-10-03 04:12:18,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4716 to 4716. [2019-10-03 04:12:18,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4716 states. [2019-10-03 04:12:18,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4716 states to 4716 states and 6093 transitions. [2019-10-03 04:12:18,672 INFO L78 Accepts]: Start accepts. Automaton has 4716 states and 6093 transitions. Word has length 135 [2019-10-03 04:12:18,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:18,672 INFO L475 AbstractCegarLoop]: Abstraction has 4716 states and 6093 transitions. [2019-10-03 04:12:18,673 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:18,673 INFO L276 IsEmpty]: Start isEmpty. Operand 4716 states and 6093 transitions. [2019-10-03 04:12:18,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:18,675 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:18,675 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:18,675 INFO L418 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:18,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:18,676 INFO L82 PathProgramCache]: Analyzing trace with hash 318080764, now seen corresponding path program 1 times [2019-10-03 04:12:18,676 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:18,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:18,677 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:18,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:18,677 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:18,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:18,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:18,750 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:18,750 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:18,750 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:18,750 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:18,751 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:18,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:18,751 INFO L87 Difference]: Start difference. First operand 4716 states and 6093 transitions. Second operand 5 states. [2019-10-03 04:12:19,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:19,195 INFO L93 Difference]: Finished difference Result 4716 states and 6053 transitions. [2019-10-03 04:12:19,196 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:19,196 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:19,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:19,215 INFO L225 Difference]: With dead ends: 4716 [2019-10-03 04:12:19,215 INFO L226 Difference]: Without dead ends: 4716 [2019-10-03 04:12:19,215 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:19,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4716 states. [2019-10-03 04:12:19,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4716 to 4716. [2019-10-03 04:12:19,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4716 states. [2019-10-03 04:12:19,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4716 states to 4716 states and 6053 transitions. [2019-10-03 04:12:19,320 INFO L78 Accepts]: Start accepts. Automaton has 4716 states and 6053 transitions. Word has length 135 [2019-10-03 04:12:19,320 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:19,321 INFO L475 AbstractCegarLoop]: Abstraction has 4716 states and 6053 transitions. [2019-10-03 04:12:19,321 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:19,321 INFO L276 IsEmpty]: Start isEmpty. Operand 4716 states and 6053 transitions. [2019-10-03 04:12:19,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:19,322 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:19,323 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:19,323 INFO L418 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:19,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:19,323 INFO L82 PathProgramCache]: Analyzing trace with hash -76286022, now seen corresponding path program 1 times [2019-10-03 04:12:19,323 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:19,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:19,325 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:19,325 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:19,325 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:19,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:19,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:19,388 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:19,388 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:19,389 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:19,389 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:19,389 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:19,390 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:19,390 INFO L87 Difference]: Start difference. First operand 4716 states and 6053 transitions. Second operand 5 states. [2019-10-03 04:12:20,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:20,157 INFO L93 Difference]: Finished difference Result 4716 states and 6013 transitions. [2019-10-03 04:12:20,157 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:20,157 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:20,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:20,181 INFO L225 Difference]: With dead ends: 4716 [2019-10-03 04:12:20,181 INFO L226 Difference]: Without dead ends: 4716 [2019-10-03 04:12:20,182 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:20,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4716 states. [2019-10-03 04:12:20,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4716 to 4716. [2019-10-03 04:12:20,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4716 states. [2019-10-03 04:12:20,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4716 states to 4716 states and 6013 transitions. [2019-10-03 04:12:20,318 INFO L78 Accepts]: Start accepts. Automaton has 4716 states and 6013 transitions. Word has length 135 [2019-10-03 04:12:20,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:20,319 INFO L475 AbstractCegarLoop]: Abstraction has 4716 states and 6013 transitions. [2019-10-03 04:12:20,319 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:20,319 INFO L276 IsEmpty]: Start isEmpty. Operand 4716 states and 6013 transitions. [2019-10-03 04:12:20,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:20,321 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:20,321 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:20,321 INFO L418 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:20,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:20,322 INFO L82 PathProgramCache]: Analyzing trace with hash -920291524, now seen corresponding path program 1 times [2019-10-03 04:12:20,322 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:20,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:20,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:20,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:20,324 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:20,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:20,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:20,385 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:20,385 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:20,386 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:20,386 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:20,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:20,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:20,387 INFO L87 Difference]: Start difference. First operand 4716 states and 6013 transitions. Second operand 5 states. [2019-10-03 04:12:20,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:20,863 INFO L93 Difference]: Finished difference Result 4716 states and 5973 transitions. [2019-10-03 04:12:20,863 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:12:20,863 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:20,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:20,881 INFO L225 Difference]: With dead ends: 4716 [2019-10-03 04:12:20,881 INFO L226 Difference]: Without dead ends: 4716 [2019-10-03 04:12:20,882 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:12:20,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4716 states. [2019-10-03 04:12:20,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4716 to 4716. [2019-10-03 04:12:20,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4716 states. [2019-10-03 04:12:20,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4716 states to 4716 states and 5973 transitions. [2019-10-03 04:12:20,988 INFO L78 Accepts]: Start accepts. Automaton has 4716 states and 5973 transitions. Word has length 135 [2019-10-03 04:12:20,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:20,989 INFO L475 AbstractCegarLoop]: Abstraction has 4716 states and 5973 transitions. [2019-10-03 04:12:20,989 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:20,989 INFO L276 IsEmpty]: Start isEmpty. Operand 4716 states and 5973 transitions. [2019-10-03 04:12:20,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:20,991 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:20,991 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:20,991 INFO L418 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:20,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:20,992 INFO L82 PathProgramCache]: Analyzing trace with hash 1130692474, now seen corresponding path program 1 times [2019-10-03 04:12:20,992 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:20,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:20,993 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:20,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:20,993 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:21,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:21,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:21,062 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:21,063 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:21,063 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:21,063 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:21,063 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:21,064 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:21,064 INFO L87 Difference]: Start difference. First operand 4716 states and 5973 transitions. Second operand 5 states. [2019-10-03 04:12:21,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:21,834 INFO L93 Difference]: Finished difference Result 5428 states and 6845 transitions. [2019-10-03 04:12:21,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-03 04:12:21,835 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:21,835 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:21,857 INFO L225 Difference]: With dead ends: 5428 [2019-10-03 04:12:21,857 INFO L226 Difference]: Without dead ends: 5428 [2019-10-03 04:12:21,858 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-10-03 04:12:21,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5428 states. [2019-10-03 04:12:21,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5428 to 5424. [2019-10-03 04:12:21,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5424 states. [2019-10-03 04:12:22,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5424 states to 5424 states and 6841 transitions. [2019-10-03 04:12:22,017 INFO L78 Accepts]: Start accepts. Automaton has 5424 states and 6841 transitions. Word has length 135 [2019-10-03 04:12:22,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:22,018 INFO L475 AbstractCegarLoop]: Abstraction has 5424 states and 6841 transitions. [2019-10-03 04:12:22,018 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:22,018 INFO L276 IsEmpty]: Start isEmpty. Operand 5424 states and 6841 transitions. [2019-10-03 04:12:22,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:22,022 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:22,022 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:22,022 INFO L418 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:22,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:22,023 INFO L82 PathProgramCache]: Analyzing trace with hash 1405452088, now seen corresponding path program 1 times [2019-10-03 04:12:22,023 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:22,024 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:22,025 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:22,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:22,025 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:22,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:22,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:22,128 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:22,129 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:22,129 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:22,129 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:22,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:22,130 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:22,130 INFO L87 Difference]: Start difference. First operand 5424 states and 6841 transitions. Second operand 5 states. [2019-10-03 04:12:23,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:23,155 INFO L93 Difference]: Finished difference Result 7478 states and 9720 transitions. [2019-10-03 04:12:23,155 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-10-03 04:12:23,156 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:23,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:23,191 INFO L225 Difference]: With dead ends: 7478 [2019-10-03 04:12:23,191 INFO L226 Difference]: Without dead ends: 7478 [2019-10-03 04:12:23,192 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2019-10-03 04:12:23,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7478 states. [2019-10-03 04:12:23,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7478 to 6890. [2019-10-03 04:12:23,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6890 states. [2019-10-03 04:12:23,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6890 states to 6890 states and 8515 transitions. [2019-10-03 04:12:23,420 INFO L78 Accepts]: Start accepts. Automaton has 6890 states and 8515 transitions. Word has length 135 [2019-10-03 04:12:23,421 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:23,421 INFO L475 AbstractCegarLoop]: Abstraction has 6890 states and 8515 transitions. [2019-10-03 04:12:23,421 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:23,421 INFO L276 IsEmpty]: Start isEmpty. Operand 6890 states and 8515 transitions. [2019-10-03 04:12:23,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:23,424 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:23,424 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:23,424 INFO L418 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:23,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:23,425 INFO L82 PathProgramCache]: Analyzing trace with hash 2107051962, now seen corresponding path program 1 times [2019-10-03 04:12:23,425 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:23,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:23,427 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:23,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:23,427 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:23,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:23,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:23,528 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:23,529 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:23,529 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:23,530 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:23,530 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:23,530 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:23,530 INFO L87 Difference]: Start difference. First operand 6890 states and 8515 transitions. Second operand 5 states. [2019-10-03 04:12:24,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:24,405 INFO L93 Difference]: Finished difference Result 7790 states and 9839 transitions. [2019-10-03 04:12:24,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-03 04:12:24,406 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:24,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:24,431 INFO L225 Difference]: With dead ends: 7790 [2019-10-03 04:12:24,431 INFO L226 Difference]: Without dead ends: 7790 [2019-10-03 04:12:24,431 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-10-03 04:12:24,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7790 states. [2019-10-03 04:12:24,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7790 to 7334. [2019-10-03 04:12:24,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7334 states. [2019-10-03 04:12:24,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7334 states to 7334 states and 8915 transitions. [2019-10-03 04:12:24,590 INFO L78 Accepts]: Start accepts. Automaton has 7334 states and 8915 transitions. Word has length 135 [2019-10-03 04:12:24,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:24,591 INFO L475 AbstractCegarLoop]: Abstraction has 7334 states and 8915 transitions. [2019-10-03 04:12:24,591 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:24,591 INFO L276 IsEmpty]: Start isEmpty. Operand 7334 states and 8915 transitions. [2019-10-03 04:12:24,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:24,593 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:24,593 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:24,593 INFO L418 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:24,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:24,594 INFO L82 PathProgramCache]: Analyzing trace with hash 2129684216, now seen corresponding path program 1 times [2019-10-03 04:12:24,594 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:24,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:24,596 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:24,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:24,596 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:24,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:24,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:24,673 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:24,673 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:24,673 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:24,674 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:24,674 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:24,674 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:24,674 INFO L87 Difference]: Start difference. First operand 7334 states and 8915 transitions. Second operand 5 states. [2019-10-03 04:12:25,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:25,386 INFO L93 Difference]: Finished difference Result 8574 states and 10603 transitions. [2019-10-03 04:12:25,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-03 04:12:25,387 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:25,387 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:25,417 INFO L225 Difference]: With dead ends: 8574 [2019-10-03 04:12:25,417 INFO L226 Difference]: Without dead ends: 8574 [2019-10-03 04:12:25,417 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-10-03 04:12:25,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8574 states. [2019-10-03 04:12:25,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8574 to 7922. [2019-10-03 04:12:25,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7922 states. [2019-10-03 04:12:25,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7922 states to 7922 states and 9455 transitions. [2019-10-03 04:12:25,581 INFO L78 Accepts]: Start accepts. Automaton has 7922 states and 9455 transitions. Word has length 135 [2019-10-03 04:12:25,581 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:25,581 INFO L475 AbstractCegarLoop]: Abstraction has 7922 states and 9455 transitions. [2019-10-03 04:12:25,581 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:25,581 INFO L276 IsEmpty]: Start isEmpty. Operand 7922 states and 9455 transitions. [2019-10-03 04:12:25,583 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:25,583 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:25,583 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:25,584 INFO L418 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:25,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:25,584 INFO L82 PathProgramCache]: Analyzing trace with hash -779079686, now seen corresponding path program 1 times [2019-10-03 04:12:25,584 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:25,585 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:25,586 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:25,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:25,586 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:25,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:25,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:25,675 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:25,675 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-03 04:12:25,675 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:25,676 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:12:25,676 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:12:25,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-03 04:12:25,677 INFO L87 Difference]: Start difference. First operand 7922 states and 9455 transitions. Second operand 5 states. [2019-10-03 04:12:26,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:26,403 INFO L93 Difference]: Finished difference Result 9698 states and 12146 transitions. [2019-10-03 04:12:26,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-03 04:12:26,403 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 135 [2019-10-03 04:12:26,404 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:26,434 INFO L225 Difference]: With dead ends: 9698 [2019-10-03 04:12:26,435 INFO L226 Difference]: Without dead ends: 9698 [2019-10-03 04:12:26,435 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-10-03 04:12:26,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9698 states. [2019-10-03 04:12:26,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9698 to 8640. [2019-10-03 04:12:26,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8640 states. [2019-10-03 04:12:26,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8640 states to 8640 states and 10101 transitions. [2019-10-03 04:12:26,609 INFO L78 Accepts]: Start accepts. Automaton has 8640 states and 10101 transitions. Word has length 135 [2019-10-03 04:12:26,609 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:26,610 INFO L475 AbstractCegarLoop]: Abstraction has 8640 states and 10101 transitions. [2019-10-03 04:12:26,610 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:12:26,610 INFO L276 IsEmpty]: Start isEmpty. Operand 8640 states and 10101 transitions. [2019-10-03 04:12:26,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-10-03 04:12:26,612 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:26,612 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:26,612 INFO L418 AbstractCegarLoop]: === Iteration 29 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:26,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:26,613 INFO L82 PathProgramCache]: Analyzing trace with hash -1288552776, now seen corresponding path program 1 times [2019-10-03 04:12:26,613 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:26,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:26,614 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:26,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:26,614 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:26,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:26,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:26,666 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:26,666 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-03 04:12:26,666 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:26,667 INFO L454 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-03 04:12:26,667 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-03 04:12:26,667 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:12:26,667 INFO L87 Difference]: Start difference. First operand 8640 states and 10101 transitions. Second operand 3 states. [2019-10-03 04:12:26,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:26,739 INFO L93 Difference]: Finished difference Result 16945 states and 20169 transitions. [2019-10-03 04:12:26,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-03 04:12:26,739 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 135 [2019-10-03 04:12:26,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:26,790 INFO L225 Difference]: With dead ends: 16945 [2019-10-03 04:12:26,791 INFO L226 Difference]: Without dead ends: 16945 [2019-10-03 04:12:26,792 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:12:26,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16945 states. [2019-10-03 04:12:27,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16945 to 16530. [2019-10-03 04:12:27,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16530 states. [2019-10-03 04:12:27,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16530 states to 16530 states and 19719 transitions. [2019-10-03 04:12:27,105 INFO L78 Accepts]: Start accepts. Automaton has 16530 states and 19719 transitions. Word has length 135 [2019-10-03 04:12:27,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:27,106 INFO L475 AbstractCegarLoop]: Abstraction has 16530 states and 19719 transitions. [2019-10-03 04:12:27,106 INFO L476 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-03 04:12:27,106 INFO L276 IsEmpty]: Start isEmpty. Operand 16530 states and 19719 transitions. [2019-10-03 04:12:27,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-10-03 04:12:27,110 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:27,110 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:27,110 INFO L418 AbstractCegarLoop]: === Iteration 30 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:27,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:27,111 INFO L82 PathProgramCache]: Analyzing trace with hash 1830447968, now seen corresponding path program 1 times [2019-10-03 04:12:27,111 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:27,113 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:27,113 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:27,113 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:27,113 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:27,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:27,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-03 04:12:27,172 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:27,172 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-03 04:12:27,172 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:27,173 INFO L454 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-03 04:12:27,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-03 04:12:27,174 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:12:27,174 INFO L87 Difference]: Start difference. First operand 16530 states and 19719 transitions. Second operand 3 states. [2019-10-03 04:12:27,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:27,427 INFO L93 Difference]: Finished difference Result 32370 states and 39888 transitions. [2019-10-03 04:12:27,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-03 04:12:27,427 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 136 [2019-10-03 04:12:27,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:27,508 INFO L225 Difference]: With dead ends: 32370 [2019-10-03 04:12:27,508 INFO L226 Difference]: Without dead ends: 32370 [2019-10-03 04:12:27,509 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:12:27,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32370 states. [2019-10-03 04:12:28,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32370 to 32350. [2019-10-03 04:12:28,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32350 states. [2019-10-03 04:12:28,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32350 states to 32350 states and 39850 transitions. [2019-10-03 04:12:28,147 INFO L78 Accepts]: Start accepts. Automaton has 32350 states and 39850 transitions. Word has length 136 [2019-10-03 04:12:28,148 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:28,148 INFO L475 AbstractCegarLoop]: Abstraction has 32350 states and 39850 transitions. [2019-10-03 04:12:28,148 INFO L476 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-03 04:12:28,148 INFO L276 IsEmpty]: Start isEmpty. Operand 32350 states and 39850 transitions. [2019-10-03 04:12:28,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2019-10-03 04:12:28,156 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:28,156 INFO L411 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:28,157 INFO L418 AbstractCegarLoop]: === Iteration 31 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:28,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:28,157 INFO L82 PathProgramCache]: Analyzing trace with hash -69975947, now seen corresponding path program 1 times [2019-10-03 04:12:28,157 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:28,158 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:28,159 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:28,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:28,159 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:28,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:28,215 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-10-03 04:12:28,215 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:28,215 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-03 04:12:28,215 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:28,216 INFO L454 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-03 04:12:28,216 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-03 04:12:28,217 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:12:28,217 INFO L87 Difference]: Start difference. First operand 32350 states and 39850 transitions. Second operand 3 states. [2019-10-03 04:12:28,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:28,619 INFO L93 Difference]: Finished difference Result 64224 states and 80484 transitions. [2019-10-03 04:12:28,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-03 04:12:28,620 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 159 [2019-10-03 04:12:28,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:29,849 INFO L225 Difference]: With dead ends: 64224 [2019-10-03 04:12:29,850 INFO L226 Difference]: Without dead ends: 48358 [2019-10-03 04:12:29,850 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:12:29,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48358 states. [2019-10-03 04:12:30,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48358 to 48358. [2019-10-03 04:12:30,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48358 states. [2019-10-03 04:12:30,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48358 states to 48358 states and 60016 transitions. [2019-10-03 04:12:30,838 INFO L78 Accepts]: Start accepts. Automaton has 48358 states and 60016 transitions. Word has length 159 [2019-10-03 04:12:30,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:30,838 INFO L475 AbstractCegarLoop]: Abstraction has 48358 states and 60016 transitions. [2019-10-03 04:12:30,838 INFO L476 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-03 04:12:30,839 INFO L276 IsEmpty]: Start isEmpty. Operand 48358 states and 60016 transitions. [2019-10-03 04:12:30,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 231 [2019-10-03 04:12:30,889 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:30,890 INFO L411 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:30,890 INFO L418 AbstractCegarLoop]: === Iteration 32 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:30,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:30,891 INFO L82 PathProgramCache]: Analyzing trace with hash -1782115071, now seen corresponding path program 1 times [2019-10-03 04:12:30,891 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:30,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:30,893 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:30,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:30,893 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:31,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:31,164 INFO L134 CoverageAnalysis]: Checked inductivity of 75 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2019-10-03 04:12:31,164 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:31,164 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-03 04:12:31,164 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:31,165 INFO L454 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-03 04:12:31,165 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-03 04:12:31,165 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-03 04:12:31,165 INFO L87 Difference]: Start difference. First operand 48358 states and 60016 transitions. Second operand 4 states. [2019-10-03 04:12:31,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:31,509 INFO L93 Difference]: Finished difference Result 37786 states and 46258 transitions. [2019-10-03 04:12:31,510 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-03 04:12:31,510 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 230 [2019-10-03 04:12:31,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:31,632 INFO L225 Difference]: With dead ends: 37786 [2019-10-03 04:12:31,633 INFO L226 Difference]: Without dead ends: 37786 [2019-10-03 04:12:31,634 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-03 04:12:31,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37786 states. [2019-10-03 04:12:32,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37786 to 37276. [2019-10-03 04:12:32,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37276 states. [2019-10-03 04:12:32,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37276 states to 37276 states and 45697 transitions. [2019-10-03 04:12:32,346 INFO L78 Accepts]: Start accepts. Automaton has 37276 states and 45697 transitions. Word has length 230 [2019-10-03 04:12:32,347 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:32,347 INFO L475 AbstractCegarLoop]: Abstraction has 37276 states and 45697 transitions. [2019-10-03 04:12:32,347 INFO L476 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-03 04:12:32,347 INFO L276 IsEmpty]: Start isEmpty. Operand 37276 states and 45697 transitions. [2019-10-03 04:12:32,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 231 [2019-10-03 04:12:32,375 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:32,375 INFO L411 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:32,375 INFO L418 AbstractCegarLoop]: === Iteration 33 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:32,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:32,376 INFO L82 PathProgramCache]: Analyzing trace with hash 1668882113, now seen corresponding path program 1 times [2019-10-03 04:12:32,376 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:32,377 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:32,378 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:32,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:32,378 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:32,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:33,548 INFO L134 CoverageAnalysis]: Checked inductivity of 75 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2019-10-03 04:12:33,548 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:33,549 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-03 04:12:33,549 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:33,551 INFO L454 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-03 04:12:33,551 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-03 04:12:33,551 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:12:33,551 INFO L87 Difference]: Start difference. First operand 37276 states and 45697 transitions. Second operand 3 states. [2019-10-03 04:12:34,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:34,028 INFO L93 Difference]: Finished difference Result 70225 states and 91195 transitions. [2019-10-03 04:12:34,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-03 04:12:34,028 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 230 [2019-10-03 04:12:34,029 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:34,255 INFO L225 Difference]: With dead ends: 70225 [2019-10-03 04:12:34,255 INFO L226 Difference]: Without dead ends: 70225 [2019-10-03 04:12:34,256 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:12:34,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70225 states. [2019-10-03 04:12:35,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70225 to 69574. [2019-10-03 04:12:35,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69574 states. [2019-10-03 04:12:36,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69574 states to 69574 states and 90321 transitions. [2019-10-03 04:12:36,013 INFO L78 Accepts]: Start accepts. Automaton has 69574 states and 90321 transitions. Word has length 230 [2019-10-03 04:12:36,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:36,014 INFO L475 AbstractCegarLoop]: Abstraction has 69574 states and 90321 transitions. [2019-10-03 04:12:36,014 INFO L476 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-03 04:12:36,014 INFO L276 IsEmpty]: Start isEmpty. Operand 69574 states and 90321 transitions. [2019-10-03 04:12:36,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 232 [2019-10-03 04:12:36,063 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:36,063 INFO L411 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:36,063 INFO L418 AbstractCegarLoop]: === Iteration 34 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:36,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:36,064 INFO L82 PathProgramCache]: Analyzing trace with hash 1695040857, now seen corresponding path program 1 times [2019-10-03 04:12:36,064 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:36,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:36,065 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:36,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:36,065 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:36,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:36,171 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2019-10-03 04:12:36,172 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:12:36,172 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:12:36,173 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 232 with the following transitions: [2019-10-03 04:12:36,176 INFO L207 CegarAbsIntRunner]: [89], [91], [94], [105], [107], [113], [118], [121], [132], [134], [136], [138], [142], [143], [148], [162], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [255], [257], [259], [260], [328], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [369], [372], [377], [380], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [594], [595], [596], [606], [608], [610], [611], [612], [621], [624], [627], [633], [639], [655], [668], [681], [685], [688], [691], [698], [701], [713], [716], [719], [723], [725], [727], [728], [729], [730], [744], [746], [779], [780], [787], [789], [790], [791], [792], [793], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [813], [814], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [857], [858], [859] [2019-10-03 04:12:36,249 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:12:36,249 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:12:36,490 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-10-03 04:12:36,492 INFO L272 AbstractInterpreter]: Visited 128 different actions 128 times. Never merged. Never widened. Performed 615 root evaluator evaluations with a maximum evaluation depth of 4. Performed 615 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Never found a fixpoint. Largest state had 70 variables. [2019-10-03 04:12:36,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:36,497 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-10-03 04:12:36,882 INFO L227 lantSequenceWeakener]: Weakened 136 states. On average, predicates are now at 65.26% of their original sizes. [2019-10-03 04:12:36,882 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-10-03 04:12:38,775 INFO L420 sIntCurrentIteration]: We unified 230 AI predicates to 230 [2019-10-03 04:12:38,776 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-10-03 04:12:38,776 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-03 04:12:38,777 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [57] imperfect sequences [6] total 61 [2019-10-03 04:12:38,777 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:38,778 INFO L454 AbstractCegarLoop]: Interpolant automaton has 57 states [2019-10-03 04:12:38,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2019-10-03 04:12:38,779 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=600, Invalid=2592, Unknown=0, NotChecked=0, Total=3192 [2019-10-03 04:12:38,780 INFO L87 Difference]: Start difference. First operand 69574 states and 90321 transitions. Second operand 57 states. [2019-10-03 04:12:56,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:56,601 INFO L93 Difference]: Finished difference Result 69819 states and 90706 transitions. [2019-10-03 04:12:56,601 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-03 04:12:56,601 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 231 [2019-10-03 04:12:56,601 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:56,826 INFO L225 Difference]: With dead ends: 69819 [2019-10-03 04:12:56,826 INFO L226 Difference]: Without dead ends: 69819 [2019-10-03 04:12:56,829 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 269 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2291 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=1734, Invalid=7386, Unknown=0, NotChecked=0, Total=9120 [2019-10-03 04:12:56,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69819 states. [2019-10-03 04:12:58,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69819 to 69749. [2019-10-03 04:12:58,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69749 states. [2019-10-03 04:12:58,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69749 states to 69749 states and 90633 transitions. [2019-10-03 04:12:58,330 INFO L78 Accepts]: Start accepts. Automaton has 69749 states and 90633 transitions. Word has length 231 [2019-10-03 04:12:58,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:12:58,330 INFO L475 AbstractCegarLoop]: Abstraction has 69749 states and 90633 transitions. [2019-10-03 04:12:58,330 INFO L476 AbstractCegarLoop]: Interpolant automaton has 57 states. [2019-10-03 04:12:58,330 INFO L276 IsEmpty]: Start isEmpty. Operand 69749 states and 90633 transitions. [2019-10-03 04:12:58,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2019-10-03 04:12:58,364 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:12:58,364 INFO L411 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:12:58,364 INFO L418 AbstractCegarLoop]: === Iteration 35 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:12:58,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:12:58,365 INFO L82 PathProgramCache]: Analyzing trace with hash -1780002429, now seen corresponding path program 1 times [2019-10-03 04:12:58,365 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:12:58,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:58,367 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:12:58,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:12:58,367 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:12:58,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:12:58,440 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2019-10-03 04:12:58,440 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:12:58,440 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-03 04:12:58,440 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:12:58,441 INFO L454 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-03 04:12:58,441 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-03 04:12:58,441 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:12:58,441 INFO L87 Difference]: Start difference. First operand 69749 states and 90633 transitions. Second operand 3 states. [2019-10-03 04:12:59,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:12:59,479 INFO L93 Difference]: Finished difference Result 103802 states and 140101 transitions. [2019-10-03 04:12:59,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-03 04:12:59,480 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 234 [2019-10-03 04:12:59,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:12:59,839 INFO L225 Difference]: With dead ends: 103802 [2019-10-03 04:12:59,839 INFO L226 Difference]: Without dead ends: 103802 [2019-10-03 04:12:59,840 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:12:59,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103802 states. [2019-10-03 04:13:02,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103802 to 103787. [2019-10-03 04:13:02,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103787 states. [2019-10-03 04:13:02,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103787 states to 103787 states and 140084 transitions. [2019-10-03 04:13:02,433 INFO L78 Accepts]: Start accepts. Automaton has 103787 states and 140084 transitions. Word has length 234 [2019-10-03 04:13:02,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:13:02,433 INFO L475 AbstractCegarLoop]: Abstraction has 103787 states and 140084 transitions. [2019-10-03 04:13:02,433 INFO L476 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-03 04:13:02,433 INFO L276 IsEmpty]: Start isEmpty. Operand 103787 states and 140084 transitions. [2019-10-03 04:13:02,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 236 [2019-10-03 04:13:02,474 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:13:02,474 INFO L411 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:13:02,474 INFO L418 AbstractCegarLoop]: === Iteration 36 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:13:02,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:13:02,475 INFO L82 PathProgramCache]: Analyzing trace with hash 1168602866, now seen corresponding path program 1 times [2019-10-03 04:13:02,475 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:13:02,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:13:02,476 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:13:02,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:13:02,477 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:13:02,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:13:02,548 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2019-10-03 04:13:02,548 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:13:02,548 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-03 04:13:02,548 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:13:02,549 INFO L454 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-03 04:13:02,549 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-03 04:13:02,549 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:13:02,550 INFO L87 Difference]: Start difference. First operand 103787 states and 140084 transitions. Second operand 3 states. [2019-10-03 04:13:03,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:13:03,430 INFO L93 Difference]: Finished difference Result 154951 states and 226313 transitions. [2019-10-03 04:13:03,430 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-03 04:13:03,430 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 235 [2019-10-03 04:13:03,431 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:13:07,330 INFO L225 Difference]: With dead ends: 154951 [2019-10-03 04:13:07,330 INFO L226 Difference]: Without dead ends: 154951 [2019-10-03 04:13:07,330 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:13:07,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154951 states. [2019-10-03 04:13:11,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154951 to 151474. [2019-10-03 04:13:11,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151474 states. [2019-10-03 04:13:11,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151474 states to 151474 states and 222135 transitions. [2019-10-03 04:13:11,874 INFO L78 Accepts]: Start accepts. Automaton has 151474 states and 222135 transitions. Word has length 235 [2019-10-03 04:13:11,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:13:11,874 INFO L475 AbstractCegarLoop]: Abstraction has 151474 states and 222135 transitions. [2019-10-03 04:13:11,874 INFO L476 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-03 04:13:11,875 INFO L276 IsEmpty]: Start isEmpty. Operand 151474 states and 222135 transitions. [2019-10-03 04:13:11,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 237 [2019-10-03 04:13:11,936 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:13:11,936 INFO L411 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:13:11,937 INFO L418 AbstractCegarLoop]: === Iteration 37 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:13:11,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:13:11,937 INFO L82 PathProgramCache]: Analyzing trace with hash 380931074, now seen corresponding path program 1 times [2019-10-03 04:13:11,937 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:13:11,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:13:11,939 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:13:11,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:13:11,939 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:13:11,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:13:12,012 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2019-10-03 04:13:12,012 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-03 04:13:12,012 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-03 04:13:12,013 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:13:12,013 INFO L454 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-03 04:13:12,013 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-03 04:13:12,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:13:12,014 INFO L87 Difference]: Start difference. First operand 151474 states and 222135 transitions. Second operand 3 states. [2019-10-03 04:13:14,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:13:14,329 INFO L93 Difference]: Finished difference Result 220692 states and 355711 transitions. [2019-10-03 04:13:14,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-03 04:13:14,329 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 236 [2019-10-03 04:13:14,329 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:13:15,038 INFO L225 Difference]: With dead ends: 220692 [2019-10-03 04:13:15,038 INFO L226 Difference]: Without dead ends: 220692 [2019-10-03 04:13:15,039 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-03 04:13:15,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220692 states. [2019-10-03 04:13:30,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220692 to 220623. [2019-10-03 04:13:30,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220623 states. [2019-10-03 04:13:32,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220623 states to 220623 states and 355598 transitions. [2019-10-03 04:13:32,715 INFO L78 Accepts]: Start accepts. Automaton has 220623 states and 355598 transitions. Word has length 236 [2019-10-03 04:13:32,715 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:13:32,715 INFO L475 AbstractCegarLoop]: Abstraction has 220623 states and 355598 transitions. [2019-10-03 04:13:32,715 INFO L476 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-03 04:13:32,716 INFO L276 IsEmpty]: Start isEmpty. Operand 220623 states and 355598 transitions. [2019-10-03 04:13:32,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 238 [2019-10-03 04:13:32,776 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:13:32,776 INFO L411 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:13:32,777 INFO L418 AbstractCegarLoop]: === Iteration 38 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:13:32,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:13:32,777 INFO L82 PathProgramCache]: Analyzing trace with hash -1795294093, now seen corresponding path program 1 times [2019-10-03 04:13:32,777 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:13:32,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:13:32,779 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:13:32,779 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:13:32,779 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:13:32,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:13:32,866 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2019-10-03 04:13:32,866 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:13:32,866 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:13:32,866 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 238 with the following transitions: [2019-10-03 04:13:32,873 INFO L207 CegarAbsIntRunner]: [89], [91], [94], [105], [107], [113], [118], [121], [132], [134], [136], [138], [142], [143], [148], [162], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [255], [257], [259], [260], [328], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [369], [372], [377], [380], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [594], [595], [596], [606], [608], [610], [611], [612], [621], [624], [627], [633], [639], [646], [652], [659], [665], [672], [678], [685], [688], [691], [698], [701], [713], [716], [719], [723], [725], [727], [728], [729], [730], [744], [746], [779], [780], [787], [789], [790], [791], [792], [793], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [813], [814], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [857], [858], [859] [2019-10-03 04:13:32,885 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:13:32,886 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:13:33,001 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-10-03 04:13:33,002 INFO L272 AbstractInterpreter]: Visited 147 different actions 170 times. Merged at 16 different actions 16 times. Never widened. Performed 1059 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1059 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 1 fixpoints after 1 different actions. Largest state had 72 variables. [2019-10-03 04:13:33,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:13:33,002 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-10-03 04:13:33,247 INFO L227 lantSequenceWeakener]: Weakened 164 states. On average, predicates are now at 68.75% of their original sizes. [2019-10-03 04:13:33,248 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-10-03 04:13:36,699 INFO L420 sIntCurrentIteration]: We unified 236 AI predicates to 236 [2019-10-03 04:13:36,700 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-10-03 04:13:36,700 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-03 04:13:36,700 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [77] imperfect sequences [5] total 80 [2019-10-03 04:13:36,700 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:13:36,701 INFO L454 AbstractCegarLoop]: Interpolant automaton has 77 states [2019-10-03 04:13:36,702 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2019-10-03 04:13:36,704 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1136, Invalid=4716, Unknown=0, NotChecked=0, Total=5852 [2019-10-03 04:13:36,704 INFO L87 Difference]: Start difference. First operand 220623 states and 355598 transitions. Second operand 77 states. [2019-10-03 04:14:29,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:14:29,867 INFO L93 Difference]: Finished difference Result 297826 states and 487089 transitions. [2019-10-03 04:14:29,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 79 states. [2019-10-03 04:14:29,867 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 237 [2019-10-03 04:14:29,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:14:31,243 INFO L225 Difference]: With dead ends: 297826 [2019-10-03 04:14:31,243 INFO L226 Difference]: Without dead ends: 297826 [2019-10-03 04:14:31,248 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 307 GetRequests, 161 SyntacticMatches, 0 SemanticMatches, 146 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7045 ImplicationChecksByTransitivity, 7.2s TimeCoverageRelationStatistics Valid=3956, Invalid=17800, Unknown=0, NotChecked=0, Total=21756 [2019-10-03 04:14:31,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 297826 states. [2019-10-03 04:14:56,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 297826 to 294004. [2019-10-03 04:14:56,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 294004 states. [2019-10-03 04:15:06,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 294004 states to 294004 states and 480777 transitions. [2019-10-03 04:15:06,460 INFO L78 Accepts]: Start accepts. Automaton has 294004 states and 480777 transitions. Word has length 237 [2019-10-03 04:15:06,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:15:06,461 INFO L475 AbstractCegarLoop]: Abstraction has 294004 states and 480777 transitions. [2019-10-03 04:15:06,461 INFO L476 AbstractCegarLoop]: Interpolant automaton has 77 states. [2019-10-03 04:15:06,461 INFO L276 IsEmpty]: Start isEmpty. Operand 294004 states and 480777 transitions. [2019-10-03 04:15:06,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 244 [2019-10-03 04:15:06,622 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:15:06,623 INFO L411 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:15:06,623 INFO L418 AbstractCegarLoop]: === Iteration 39 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:15:06,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:15:06,624 INFO L82 PathProgramCache]: Analyzing trace with hash -395895037, now seen corresponding path program 1 times [2019-10-03 04:15:06,624 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:15:06,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:15:06,627 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:15:06,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:15:06,627 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:15:06,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:15:06,729 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [2019-10-03 04:15:06,730 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:15:06,730 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:15:06,730 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 244 with the following transitions: [2019-10-03 04:15:06,731 INFO L207 CegarAbsIntRunner]: [2], [18], [20], [28], [89], [91], [94], [105], [107], [113], [118], [121], [132], [134], [136], [138], [142], [143], [148], [162], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [255], [257], [259], [260], [328], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [369], [372], [377], [380], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [433], [438], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [594], [595], [596], [606], [608], [610], [611], [612], [621], [624], [627], [633], [639], [646], [649], [655], [659], [665], [672], [678], [685], [688], [691], [698], [701], [713], [716], [719], [723], [725], [727], [728], [729], [730], [744], [746], [779], [780], [787], [789], [790], [791], [792], [793], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [813], [814], [817], [818], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [857], [858], [859] [2019-10-03 04:15:06,741 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:15:06,741 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:15:06,825 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2019-10-03 04:15:06,827 INFO L272 AbstractInterpreter]: Visited 158 different actions 196 times. Merged at 19 different actions 19 times. Never widened. Performed 1175 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1175 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 2 fixpoints after 2 different actions. Largest state had 72 variables. [2019-10-03 04:15:06,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:15:06,828 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2019-10-03 04:15:06,828 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:15:06,829 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-10-03 04:15:06,883 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:15:06,883 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2019-10-03 04:15:07,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:15:07,042 INFO L256 TraceCheckSpWp]: Trace formula consists of 1235 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-03 04:15:07,071 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-03 04:15:07,149 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 60 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2019-10-03 04:15:07,149 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-03 04:15:07,365 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [MP z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (2)] Exception during sending of exit command (exit): Stream closed [2019-10-03 04:15:07,371 INFO L312 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2019-10-03 04:15:07,371 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [5] total 6 [2019-10-03 04:15:07,371 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:15:07,372 INFO L454 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-03 04:15:07,372 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-03 04:15:07,372 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:15:07,372 INFO L87 Difference]: Start difference. First operand 294004 states and 480777 transitions. Second operand 3 states. [2019-10-03 04:15:16,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:15:16,946 INFO L93 Difference]: Finished difference Result 426118 states and 737467 transitions. [2019-10-03 04:15:16,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-03 04:15:16,947 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 243 [2019-10-03 04:15:16,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:15:18,248 INFO L225 Difference]: With dead ends: 426118 [2019-10-03 04:15:18,249 INFO L226 Difference]: Without dead ends: 426118 [2019-10-03 04:15:18,249 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 491 GetRequests, 487 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:15:18,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 426118 states. [2019-10-03 04:15:57,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 426118 to 425662. [2019-10-03 04:15:57,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 425662 states. [2019-10-03 04:16:01,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425662 states to 425662 states and 736933 transitions. [2019-10-03 04:16:01,204 INFO L78 Accepts]: Start accepts. Automaton has 425662 states and 736933 transitions. Word has length 243 [2019-10-03 04:16:01,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:16:01,204 INFO L475 AbstractCegarLoop]: Abstraction has 425662 states and 736933 transitions. [2019-10-03 04:16:01,204 INFO L476 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-03 04:16:01,204 INFO L276 IsEmpty]: Start isEmpty. Operand 425662 states and 736933 transitions. [2019-10-03 04:16:01,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 245 [2019-10-03 04:16:01,317 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:16:01,318 INFO L411 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:16:01,318 INFO L418 AbstractCegarLoop]: === Iteration 40 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:16:01,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:16:01,319 INFO L82 PathProgramCache]: Analyzing trace with hash -1962258064, now seen corresponding path program 1 times [2019-10-03 04:16:01,319 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:16:01,320 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:16:01,320 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:16:01,320 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:16:01,321 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:16:01,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:16:02,345 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [2019-10-03 04:16:02,345 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:16:02,345 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:16:02,346 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 245 with the following transitions: [2019-10-03 04:16:02,346 INFO L207 CegarAbsIntRunner]: [2], [18], [20], [28], [89], [91], [94], [105], [107], [113], [118], [121], [132], [134], [136], [138], [142], [143], [148], [162], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [255], [257], [259], [260], [328], [331], [336], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [369], [372], [377], [380], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [433], [438], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [594], [595], [596], [606], [608], [610], [611], [612], [621], [624], [627], [633], [639], [646], [649], [655], [659], [665], [672], [678], [685], [688], [691], [698], [701], [713], [716], [719], [723], [725], [727], [728], [729], [730], [744], [746], [779], [780], [787], [789], [790], [791], [792], [793], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [813], [814], [817], [818], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [857], [858], [859] [2019-10-03 04:16:02,350 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:16:02,351 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:16:02,422 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2019-10-03 04:16:02,422 INFO L272 AbstractInterpreter]: Visited 159 different actions 197 times. Merged at 19 different actions 19 times. Never widened. Performed 1176 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1176 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 2 fixpoints after 2 different actions. Largest state had 72 variables. [2019-10-03 04:16:02,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:16:02,422 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2019-10-03 04:16:02,423 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:16:02,423 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-10-03 04:16:02,488 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:16:02,488 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2019-10-03 04:16:02,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:16:02,632 INFO L256 TraceCheckSpWp]: Trace formula consists of 1237 conjuncts, 10 conjunts are in the unsatisfiable core [2019-10-03 04:16:02,652 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-03 04:16:02,787 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 4 proven. 56 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2019-10-03 04:16:02,787 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-03 04:16:03,029 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2019-10-03 04:16:03,042 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-03 04:16:03,042 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [5, 5] total 9 [2019-10-03 04:16:03,042 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:16:03,043 INFO L454 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-03 04:16:03,043 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-03 04:16:03,043 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2019-10-03 04:16:03,043 INFO L87 Difference]: Start difference. First operand 425662 states and 736933 transitions. Second operand 5 states. [2019-10-03 04:16:18,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:16:18,840 INFO L93 Difference]: Finished difference Result 459628 states and 806686 transitions. [2019-10-03 04:16:18,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:16:18,841 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 244 [2019-10-03 04:16:18,842 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:16:20,774 INFO L225 Difference]: With dead ends: 459628 [2019-10-03 04:16:20,774 INFO L226 Difference]: Without dead ends: 459628 [2019-10-03 04:16:20,774 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 493 GetRequests, 481 SyntacticMatches, 5 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2019-10-03 04:16:21,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 459628 states. [2019-10-03 04:16:49,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 459628 to 458276. [2019-10-03 04:16:49,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 458276 states. [2019-10-03 04:17:07,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 458276 states to 458276 states and 798459 transitions. [2019-10-03 04:17:07,362 INFO L78 Accepts]: Start accepts. Automaton has 458276 states and 798459 transitions. Word has length 244 [2019-10-03 04:17:07,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:17:07,362 INFO L475 AbstractCegarLoop]: Abstraction has 458276 states and 798459 transitions. [2019-10-03 04:17:07,362 INFO L476 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-03 04:17:07,362 INFO L276 IsEmpty]: Start isEmpty. Operand 458276 states and 798459 transitions. [2019-10-03 04:17:10,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 318 [2019-10-03 04:17:10,144 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:17:10,145 INFO L411 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:17:10,145 INFO L418 AbstractCegarLoop]: === Iteration 41 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:17:10,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:17:10,145 INFO L82 PathProgramCache]: Analyzing trace with hash 1688032010, now seen corresponding path program 1 times [2019-10-03 04:17:10,146 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:17:10,147 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:17:10,147 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:17:10,147 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:17:10,148 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:17:10,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:17:10,278 INFO L134 CoverageAnalysis]: Checked inductivity of 203 backedges. 23 proven. 12 refuted. 0 times theorem prover too weak. 168 trivial. 0 not checked. [2019-10-03 04:17:10,278 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:17:10,279 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:17:10,279 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 318 with the following transitions: [2019-10-03 04:17:10,279 INFO L207 CegarAbsIntRunner]: [89], [91], [94], [105], [107], [113], [116], [118], [121], [132], [134], [136], [138], [142], [143], [148], [162], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [248], [253], [255], [257], [259], [260], [328], [331], [336], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [369], [372], [377], [380], [383], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [552], [568], [570], [572], [581], [583], [591], [594], [595], [596], [606], [608], [610], [611], [612], [621], [624], [627], [633], [636], [639], [646], [652], [659], [665], [672], [678], [685], [688], [698], [701], [713], [716], [719], [721], [723], [725], [727], [728], [729], [730], [744], [746], [779], [780], [787], [789], [790], [791], [792], [793], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [811], [812], [813], [814], [815], [816], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [857], [858], [859] [2019-10-03 04:17:10,281 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:17:10,282 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:17:10,632 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2019-10-03 04:17:10,633 INFO L272 AbstractInterpreter]: Visited 181 different actions 1190 times. Merged at 65 different actions 294 times. Never widened. Performed 6181 root evaluator evaluations with a maximum evaluation depth of 4. Performed 6181 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 29 fixpoints after 11 different actions. Largest state had 72 variables. [2019-10-03 04:17:10,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:17:10,633 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2019-10-03 04:17:10,633 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:17:10,633 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-10-03 04:17:10,689 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:17:10,690 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2019-10-03 04:17:10,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:17:10,854 INFO L256 TraceCheckSpWp]: Trace formula consists of 1460 conjuncts, 9 conjunts are in the unsatisfiable core [2019-10-03 04:17:10,860 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-03 04:17:10,912 INFO L134 CoverageAnalysis]: Checked inductivity of 203 backedges. 138 proven. 0 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-10-03 04:17:10,912 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-03 04:17:11,241 INFO L134 CoverageAnalysis]: Checked inductivity of 203 backedges. 23 proven. 12 refuted. 0 times theorem prover too weak. 168 trivial. 0 not checked. [2019-10-03 04:17:11,246 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-03 04:17:11,246 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [6, 6] total 6 [2019-10-03 04:17:11,247 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:17:11,247 INFO L454 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-03 04:17:11,247 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-03 04:17:11,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:17:11,248 INFO L87 Difference]: Start difference. First operand 458276 states and 798459 transitions. Second operand 6 states. [2019-10-03 04:17:21,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:17:21,834 INFO L93 Difference]: Finished difference Result 377963 states and 591265 transitions. [2019-10-03 04:17:21,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-03 04:17:21,834 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 317 [2019-10-03 04:17:21,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:17:22,685 INFO L225 Difference]: With dead ends: 377963 [2019-10-03 04:17:22,685 INFO L226 Difference]: Without dead ends: 312467 [2019-10-03 04:17:22,686 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 640 GetRequests, 635 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2019-10-03 04:17:22,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312467 states. [2019-10-03 04:17:36,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312467 to 312409. [2019-10-03 04:17:36,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 312409 states. [2019-10-03 04:17:38,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312409 states to 312409 states and 502966 transitions. [2019-10-03 04:17:38,925 INFO L78 Accepts]: Start accepts. Automaton has 312409 states and 502966 transitions. Word has length 317 [2019-10-03 04:17:38,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:17:38,925 INFO L475 AbstractCegarLoop]: Abstraction has 312409 states and 502966 transitions. [2019-10-03 04:17:38,925 INFO L476 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-03 04:17:38,925 INFO L276 IsEmpty]: Start isEmpty. Operand 312409 states and 502966 transitions. [2019-10-03 04:17:39,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 474 [2019-10-03 04:17:39,218 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:17:39,218 INFO L411 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:17:39,219 INFO L418 AbstractCegarLoop]: === Iteration 42 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:17:39,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:17:39,219 INFO L82 PathProgramCache]: Analyzing trace with hash -1334254435, now seen corresponding path program 1 times [2019-10-03 04:17:39,219 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:17:39,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:17:39,221 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:17:39,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:17:39,221 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:17:39,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:17:47,601 INFO L134 CoverageAnalysis]: Checked inductivity of 523 backedges. 45 proven. 26 refuted. 0 times theorem prover too weak. 452 trivial. 0 not checked. [2019-10-03 04:17:47,601 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:17:47,601 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:17:47,601 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 474 with the following transitions: [2019-10-03 04:17:47,601 INFO L207 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [116], [118], [121], [132], [134], [136], [138], [142], [143], [148], [151], [153], [156], [160], [161], [162], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [255], [257], [259], [260], [328], [331], [334], [336], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [369], [372], [377], [380], [383], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [594], [595], [596], [599], [604], [606], [608], [610], [611], [612], [621], [624], [627], [629], [633], [639], [646], [652], [659], [665], [672], [675], [681], [685], [688], [691], [698], [701], [704], [712], [713], [716], [719], [721], [723], [725], [727], [728], [729], [730], [744], [746], [748], [750], [755], [763], [766], [771], [779], [780], [783], [784], [787], [789], [790], [791], [792], [793], [795], [796], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [813], [814], [821], [822], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [838], [839], [840], [841], [842], [843], [844], [845], [846], [847], [848], [855], [856], [857], [858], [859] [2019-10-03 04:17:47,606 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:17:47,606 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:17:47,799 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2019-10-03 04:17:47,800 INFO L272 AbstractInterpreter]: Visited 186 different actions 694 times. Merged at 53 different actions 167 times. Never widened. Performed 3537 root evaluator evaluations with a maximum evaluation depth of 4. Performed 3537 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 29 fixpoints after 12 different actions. Largest state had 72 variables. [2019-10-03 04:17:47,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:17:47,800 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2019-10-03 04:17:47,800 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:17:47,800 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-10-03 04:17:47,878 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:17:47,878 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2019-10-03 04:17:48,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:17:48,107 INFO L256 TraceCheckSpWp]: Trace formula consists of 1977 conjuncts, 5 conjunts are in the unsatisfiable core [2019-10-03 04:17:48,120 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-03 04:17:48,279 INFO L134 CoverageAnalysis]: Checked inductivity of 523 backedges. 291 proven. 0 refuted. 0 times theorem prover too weak. 232 trivial. 0 not checked. [2019-10-03 04:17:48,280 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-03 04:17:48,651 INFO L134 CoverageAnalysis]: Checked inductivity of 523 backedges. 50 proven. 12 refuted. 0 times theorem prover too weak. 461 trivial. 0 not checked. [2019-10-03 04:17:48,655 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-03 04:17:48,655 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [8, 6] total 12 [2019-10-03 04:17:48,655 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:17:48,656 INFO L454 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-03 04:17:48,656 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-03 04:17:48,656 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2019-10-03 04:17:48,656 INFO L87 Difference]: Start difference. First operand 312409 states and 502966 transitions. Second operand 6 states. [2019-10-03 04:17:49,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:17:49,033 INFO L93 Difference]: Finished difference Result 134597 states and 158162 transitions. [2019-10-03 04:17:49,033 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-10-03 04:17:49,033 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 473 [2019-10-03 04:17:49,033 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:17:49,258 INFO L225 Difference]: With dead ends: 134597 [2019-10-03 04:17:49,258 INFO L226 Difference]: Without dead ends: 134597 [2019-10-03 04:17:49,259 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 958 GetRequests, 942 SyntacticMatches, 4 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2019-10-03 04:17:49,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134597 states. [2019-10-03 04:17:50,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134597 to 129153. [2019-10-03 04:17:50,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129153 states. [2019-10-03 04:17:50,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129153 states to 129153 states and 150441 transitions. [2019-10-03 04:17:50,823 INFO L78 Accepts]: Start accepts. Automaton has 129153 states and 150441 transitions. Word has length 473 [2019-10-03 04:17:50,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:17:50,823 INFO L475 AbstractCegarLoop]: Abstraction has 129153 states and 150441 transitions. [2019-10-03 04:17:50,823 INFO L476 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-03 04:17:50,823 INFO L276 IsEmpty]: Start isEmpty. Operand 129153 states and 150441 transitions. [2019-10-03 04:17:50,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 324 [2019-10-03 04:17:50,888 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:17:50,889 INFO L411 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:17:50,889 INFO L418 AbstractCegarLoop]: === Iteration 43 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:17:50,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:17:50,889 INFO L82 PathProgramCache]: Analyzing trace with hash 1955615783, now seen corresponding path program 1 times [2019-10-03 04:17:50,889 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:17:50,891 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:17:50,891 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:17:50,891 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:17:50,891 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:17:50,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:17:51,352 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 20 proven. 7 refuted. 0 times theorem prover too weak. 181 trivial. 0 not checked. [2019-10-03 04:17:51,353 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:17:51,353 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:17:51,353 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 324 with the following transitions: [2019-10-03 04:17:51,353 INFO L207 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [116], [118], [121], [132], [134], [136], [138], [142], [143], [148], [162], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [255], [257], [259], [260], [328], [331], [334], [336], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [369], [372], [377], [380], [383], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [594], [595], [596], [599], [604], [606], [608], [610], [611], [612], [621], [624], [627], [633], [639], [646], [652], [659], [665], [672], [675], [685], [688], [698], [701], [713], [716], [719], [721], [723], [725], [727], [728], [729], [730], [744], [746], [779], [780], [783], [784], [787], [789], [790], [791], [792], [793], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [813], [814], [821], [822], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [857], [858], [859] [2019-10-03 04:17:51,356 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:17:51,356 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:17:51,407 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-10-03 04:17:51,407 INFO L272 AbstractInterpreter]: Visited 161 different actions 177 times. Merged at 11 different actions 11 times. Never widened. Performed 1002 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1002 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 1 fixpoints after 1 different actions. Largest state had 72 variables. [2019-10-03 04:17:51,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:17:51,407 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-10-03 04:17:51,576 INFO L227 lantSequenceWeakener]: Weakened 186 states. On average, predicates are now at 69.77% of their original sizes. [2019-10-03 04:17:51,576 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-10-03 04:17:54,734 INFO L420 sIntCurrentIteration]: We unified 322 AI predicates to 322 [2019-10-03 04:17:54,734 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-10-03 04:17:54,735 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-03 04:17:54,735 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [83] imperfect sequences [4] total 85 [2019-10-03 04:17:54,735 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:17:54,737 INFO L454 AbstractCegarLoop]: Interpolant automaton has 83 states [2019-10-03 04:17:54,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2019-10-03 04:17:54,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1003, Invalid=5803, Unknown=0, NotChecked=0, Total=6806 [2019-10-03 04:17:54,741 INFO L87 Difference]: Start difference. First operand 129153 states and 150441 transitions. Second operand 83 states. [2019-10-03 04:18:27,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:18:27,833 INFO L93 Difference]: Finished difference Result 129544 states and 150895 transitions. [2019-10-03 04:18:27,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2019-10-03 04:18:27,833 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 323 [2019-10-03 04:18:27,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:18:28,042 INFO L225 Difference]: With dead ends: 129544 [2019-10-03 04:18:28,042 INFO L226 Difference]: Without dead ends: 129544 [2019-10-03 04:18:28,047 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 397 GetRequests, 241 SyntacticMatches, 0 SemanticMatches, 156 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7597 ImplicationChecksByTransitivity, 6.9s TimeCoverageRelationStatistics Valid=3140, Invalid=21666, Unknown=0, NotChecked=0, Total=24806 [2019-10-03 04:18:28,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129544 states. [2019-10-03 04:18:29,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129544 to 129007. [2019-10-03 04:18:29,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129007 states. [2019-10-03 04:18:29,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129007 states to 129007 states and 150286 transitions. [2019-10-03 04:18:29,835 INFO L78 Accepts]: Start accepts. Automaton has 129007 states and 150286 transitions. Word has length 323 [2019-10-03 04:18:29,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:18:29,836 INFO L475 AbstractCegarLoop]: Abstraction has 129007 states and 150286 transitions. [2019-10-03 04:18:29,836 INFO L476 AbstractCegarLoop]: Interpolant automaton has 83 states. [2019-10-03 04:18:29,836 INFO L276 IsEmpty]: Start isEmpty. Operand 129007 states and 150286 transitions. [2019-10-03 04:18:29,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 331 [2019-10-03 04:18:29,904 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:18:29,904 INFO L411 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:18:29,905 INFO L418 AbstractCegarLoop]: === Iteration 44 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:18:29,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:18:29,905 INFO L82 PathProgramCache]: Analyzing trace with hash -572385896, now seen corresponding path program 1 times [2019-10-03 04:18:29,906 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:18:29,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:18:29,907 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:18:29,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:18:29,907 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:18:29,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:18:30,041 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 19 proven. 7 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2019-10-03 04:18:30,042 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:18:30,042 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:18:30,042 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 331 with the following transitions: [2019-10-03 04:18:30,042 INFO L207 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [89], [91], [94], [105], [107], [113], [116], [118], [121], [132], [134], [136], [138], [142], [143], [148], [162], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [255], [257], [259], [260], [328], [331], [334], [336], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [369], [372], [377], [380], [383], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [433], [438], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [594], [595], [596], [599], [604], [606], [608], [610], [611], [612], [621], [624], [627], [633], [639], [646], [649], [655], [659], [665], [672], [675], [685], [688], [698], [701], [713], [716], [719], [721], [723], [725], [727], [728], [729], [730], [744], [746], [779], [780], [783], [784], [787], [789], [790], [791], [792], [793], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [813], [814], [817], [818], [821], [822], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [857], [858], [859] [2019-10-03 04:18:30,044 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:18:30,044 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:18:30,183 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2019-10-03 04:18:30,183 INFO L272 AbstractInterpreter]: Visited 191 different actions 623 times. Merged at 58 different actions 167 times. Never widened. Performed 3292 root evaluator evaluations with a maximum evaluation depth of 4. Performed 3292 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 19 fixpoints after 9 different actions. Largest state had 72 variables. [2019-10-03 04:18:30,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:18:30,184 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2019-10-03 04:18:30,184 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:18:30,184 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-10-03 04:18:30,276 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:18:30,276 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2019-10-03 04:18:30,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:18:30,461 INFO L256 TraceCheckSpWp]: Trace formula consists of 1546 conjuncts, 4 conjunts are in the unsatisfiable core [2019-10-03 04:18:30,468 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-03 04:18:31,234 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 146 proven. 0 refuted. 0 times theorem prover too weak. 62 trivial. 0 not checked. [2019-10-03 04:18:31,234 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-03 04:18:31,462 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 19 proven. 7 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2019-10-03 04:18:31,467 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-03 04:18:31,467 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2019-10-03 04:18:31,468 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:18:31,468 INFO L454 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-03 04:18:31,468 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-03 04:18:31,468 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2019-10-03 04:18:31,469 INFO L87 Difference]: Start difference. First operand 129007 states and 150286 transitions. Second operand 4 states. [2019-10-03 04:18:32,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:18:32,114 INFO L93 Difference]: Finished difference Result 105754 states and 123403 transitions. [2019-10-03 04:18:32,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:18:32,114 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 330 [2019-10-03 04:18:32,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:18:32,298 INFO L225 Difference]: With dead ends: 105754 [2019-10-03 04:18:32,298 INFO L226 Difference]: Without dead ends: 105754 [2019-10-03 04:18:32,298 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 666 GetRequests, 659 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2019-10-03 04:18:32,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105754 states. [2019-10-03 04:18:33,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105754 to 102767. [2019-10-03 04:18:33,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102767 states. [2019-10-03 04:18:33,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102767 states to 102767 states and 119856 transitions. [2019-10-03 04:18:33,816 INFO L78 Accepts]: Start accepts. Automaton has 102767 states and 119856 transitions. Word has length 330 [2019-10-03 04:18:33,817 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:18:33,817 INFO L475 AbstractCegarLoop]: Abstraction has 102767 states and 119856 transitions. [2019-10-03 04:18:33,817 INFO L476 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-03 04:18:33,817 INFO L276 IsEmpty]: Start isEmpty. Operand 102767 states and 119856 transitions. [2019-10-03 04:18:33,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 405 [2019-10-03 04:18:33,874 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:18:33,874 INFO L411 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:18:33,874 INFO L418 AbstractCegarLoop]: === Iteration 45 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:18:33,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:18:33,875 INFO L82 PathProgramCache]: Analyzing trace with hash -1174798747, now seen corresponding path program 1 times [2019-10-03 04:18:33,875 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:18:33,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:18:33,876 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:18:33,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:18:33,876 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:18:33,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:18:34,022 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 21 proven. 12 refuted. 0 times theorem prover too weak. 362 trivial. 0 not checked. [2019-10-03 04:18:34,022 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:18:34,022 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:18:34,022 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 405 with the following transitions: [2019-10-03 04:18:34,023 INFO L207 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [116], [118], [121], [132], [134], [136], [138], [142], [143], [148], [162], [165], [170], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [255], [257], [259], [260], [328], [331], [334], [336], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [369], [372], [375], [377], [380], [383], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [594], [595], [596], [599], [602], [604], [606], [608], [610], [611], [612], [621], [624], [627], [633], [639], [646], [652], [659], [662], [672], [675], [685], [688], [698], [701], [713], [716], [719], [721], [723], [725], [727], [728], [729], [730], [744], [746], [779], [780], [783], [784], [785], [786], [787], [789], [790], [791], [792], [793], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [813], [814], [819], [820], [821], [822], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [857], [858], [859] [2019-10-03 04:18:34,025 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:18:34,025 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:18:34,080 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-10-03 04:18:34,080 INFO L272 AbstractInterpreter]: Visited 170 different actions 184 times. Merged at 9 different actions 9 times. Never widened. Performed 1067 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1067 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 1 fixpoints after 1 different actions. Largest state had 72 variables. [2019-10-03 04:18:34,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:18:34,080 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-10-03 04:18:34,256 INFO L227 lantSequenceWeakener]: Weakened 198 states. On average, predicates are now at 70.05% of their original sizes. [2019-10-03 04:18:34,256 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-10-03 04:18:38,113 INFO L420 sIntCurrentIteration]: We unified 403 AI predicates to 403 [2019-10-03 04:18:38,114 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-10-03 04:18:38,114 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-03 04:18:38,114 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [87] imperfect sequences [4] total 89 [2019-10-03 04:18:38,114 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:18:38,114 INFO L454 AbstractCegarLoop]: Interpolant automaton has 87 states [2019-10-03 04:18:38,115 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2019-10-03 04:18:38,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=933, Invalid=6549, Unknown=0, NotChecked=0, Total=7482 [2019-10-03 04:18:38,116 INFO L87 Difference]: Start difference. First operand 102767 states and 119856 transitions. Second operand 87 states. [2019-10-03 04:19:20,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:19:20,340 INFO L93 Difference]: Finished difference Result 103254 states and 120412 transitions. [2019-10-03 04:19:20,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 103 states. [2019-10-03 04:19:20,341 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 404 [2019-10-03 04:19:20,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:19:20,495 INFO L225 Difference]: With dead ends: 103254 [2019-10-03 04:19:20,495 INFO L226 Difference]: Without dead ends: 103254 [2019-10-03 04:19:20,497 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 318 SyntacticMatches, 0 SemanticMatches, 172 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9531 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=3182, Invalid=26920, Unknown=0, NotChecked=0, Total=30102 [2019-10-03 04:19:20,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103254 states. [2019-10-03 04:19:21,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103254 to 102779. [2019-10-03 04:19:21,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102779 states. [2019-10-03 04:19:21,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102779 states to 102779 states and 119863 transitions. [2019-10-03 04:19:21,506 INFO L78 Accepts]: Start accepts. Automaton has 102779 states and 119863 transitions. Word has length 404 [2019-10-03 04:19:21,506 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:19:21,506 INFO L475 AbstractCegarLoop]: Abstraction has 102779 states and 119863 transitions. [2019-10-03 04:19:21,506 INFO L476 AbstractCegarLoop]: Interpolant automaton has 87 states. [2019-10-03 04:19:21,506 INFO L276 IsEmpty]: Start isEmpty. Operand 102779 states and 119863 transitions. [2019-10-03 04:19:21,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 413 [2019-10-03 04:19:21,563 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:19:21,563 INFO L411 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:19:21,563 INFO L418 AbstractCegarLoop]: === Iteration 46 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:19:21,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:19:21,564 INFO L82 PathProgramCache]: Analyzing trace with hash 497728695, now seen corresponding path program 1 times [2019-10-03 04:19:21,564 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:19:21,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:19:21,565 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:19:21,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:19:21,566 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:19:21,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:19:22,205 INFO L134 CoverageAnalysis]: Checked inductivity of 397 backedges. 20 proven. 12 refuted. 0 times theorem prover too weak. 365 trivial. 0 not checked. [2019-10-03 04:19:22,206 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:19:22,206 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:19:22,206 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 413 with the following transitions: [2019-10-03 04:19:22,206 INFO L207 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [116], [118], [121], [132], [134], [136], [138], [142], [143], [148], [162], [165], [170], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [255], [257], [259], [260], [328], [331], [334], [336], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [369], [372], [375], [377], [380], [383], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [433], [438], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [594], [595], [596], [599], [602], [604], [606], [608], [610], [611], [612], [621], [624], [627], [633], [639], [646], [649], [655], [659], [662], [672], [675], [685], [688], [698], [701], [713], [716], [719], [721], [723], [725], [727], [728], [729], [730], [744], [746], [779], [780], [783], [784], [785], [786], [787], [789], [790], [791], [792], [793], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [813], [814], [817], [818], [819], [820], [821], [822], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [857], [858], [859] [2019-10-03 04:19:22,208 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:19:22,208 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:19:22,287 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-10-03 04:19:22,288 INFO L272 AbstractInterpreter]: Visited 178 different actions 227 times. Merged at 19 different actions 19 times. Never widened. Performed 1410 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1410 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 2 fixpoints after 2 different actions. Largest state had 72 variables. [2019-10-03 04:19:22,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:19:22,288 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-10-03 04:19:22,435 INFO L227 lantSequenceWeakener]: Weakened 203 states. On average, predicates are now at 69.41% of their original sizes. [2019-10-03 04:19:22,436 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-10-03 04:19:25,848 INFO L420 sIntCurrentIteration]: We unified 411 AI predicates to 411 [2019-10-03 04:19:25,848 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-10-03 04:19:25,848 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-10-03 04:19:25,849 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [89] imperfect sequences [4] total 91 [2019-10-03 04:19:25,849 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:19:25,850 INFO L454 AbstractCegarLoop]: Interpolant automaton has 89 states [2019-10-03 04:19:25,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2019-10-03 04:19:25,852 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=787, Invalid=7045, Unknown=0, NotChecked=0, Total=7832 [2019-10-03 04:19:25,852 INFO L87 Difference]: Start difference. First operand 102779 states and 119863 transitions. Second operand 89 states. [2019-10-03 04:20:09,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:20:09,252 INFO L93 Difference]: Finished difference Result 102966 states and 120114 transitions. [2019-10-03 04:20:09,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 109 states. [2019-10-03 04:20:09,252 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 412 [2019-10-03 04:20:09,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:20:09,787 INFO L225 Difference]: With dead ends: 102966 [2019-10-03 04:20:09,787 INFO L226 Difference]: Without dead ends: 102966 [2019-10-03 04:20:09,788 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 509 GetRequests, 324 SyntacticMatches, 0 SemanticMatches, 185 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11102 ImplicationChecksByTransitivity, 7.9s TimeCoverageRelationStatistics Valid=2809, Invalid=31973, Unknown=0, NotChecked=0, Total=34782 [2019-10-03 04:20:09,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102966 states. [2019-10-03 04:20:10,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102966 to 102669. [2019-10-03 04:20:10,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102669 states. [2019-10-03 04:20:10,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102669 states to 102669 states and 119751 transitions. [2019-10-03 04:20:10,772 INFO L78 Accepts]: Start accepts. Automaton has 102669 states and 119751 transitions. Word has length 412 [2019-10-03 04:20:10,772 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:20:10,773 INFO L475 AbstractCegarLoop]: Abstraction has 102669 states and 119751 transitions. [2019-10-03 04:20:10,773 INFO L476 AbstractCegarLoop]: Interpolant automaton has 89 states. [2019-10-03 04:20:10,773 INFO L276 IsEmpty]: Start isEmpty. Operand 102669 states and 119751 transitions. [2019-10-03 04:20:10,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 414 [2019-10-03 04:20:10,831 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:20:10,831 INFO L411 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:20:10,831 INFO L418 AbstractCegarLoop]: === Iteration 47 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:20:10,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:20:10,832 INFO L82 PathProgramCache]: Analyzing trace with hash 1093464714, now seen corresponding path program 1 times [2019-10-03 04:20:10,833 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:20:10,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:20:10,835 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:20:10,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:20:10,835 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:20:10,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:20:10,990 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 21 proven. 12 refuted. 0 times theorem prover too weak. 365 trivial. 0 not checked. [2019-10-03 04:20:10,990 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:20:10,991 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:20:10,991 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 414 with the following transitions: [2019-10-03 04:20:10,991 INFO L207 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [116], [118], [121], [132], [134], [136], [138], [142], [143], [148], [162], [165], [170], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [255], [257], [259], [260], [328], [331], [334], [336], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [369], [372], [375], [377], [380], [383], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [433], [438], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [594], [595], [596], [599], [602], [604], [606], [608], [610], [611], [612], [621], [624], [627], [633], [639], [646], [649], [652], [659], [662], [672], [675], [685], [688], [698], [701], [713], [716], [719], [721], [723], [725], [727], [728], [729], [730], [744], [746], [779], [780], [783], [784], [785], [786], [787], [789], [790], [791], [792], [793], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [813], [814], [817], [818], [819], [820], [821], [822], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [857], [858], [859] [2019-10-03 04:20:10,995 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:20:10,995 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:20:11,929 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2019-10-03 04:20:11,930 INFO L272 AbstractInterpreter]: Visited 207 different actions 1763 times. Merged at 73 different actions 588 times. Never widened. Performed 9744 root evaluator evaluations with a maximum evaluation depth of 4. Performed 9744 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 69 fixpoints after 18 different actions. Largest state had 72 variables. [2019-10-03 04:20:11,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:20:11,930 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2019-10-03 04:20:11,930 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:20:11,930 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-10-03 04:20:12,051 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:20:12,051 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2019-10-03 04:20:12,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:20:12,264 INFO L256 TraceCheckSpWp]: Trace formula consists of 1823 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-03 04:20:12,272 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-03 04:20:12,347 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 209 proven. 0 refuted. 0 times theorem prover too weak. 189 trivial. 0 not checked. [2019-10-03 04:20:12,347 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-03 04:20:12,698 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 21 proven. 12 refuted. 0 times theorem prover too weak. 365 trivial. 0 not checked. [2019-10-03 04:20:12,703 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-03 04:20:12,703 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2019-10-03 04:20:12,703 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:20:12,704 INFO L454 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-03 04:20:12,704 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-03 04:20:12,704 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2019-10-03 04:20:12,704 INFO L87 Difference]: Start difference. First operand 102669 states and 119751 transitions. Second operand 4 states. [2019-10-03 04:20:13,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:20:13,427 INFO L93 Difference]: Finished difference Result 106600 states and 126436 transitions. [2019-10-03 04:20:13,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:20:13,428 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 413 [2019-10-03 04:20:13,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:20:13,604 INFO L225 Difference]: With dead ends: 106600 [2019-10-03 04:20:13,605 INFO L226 Difference]: Without dead ends: 106600 [2019-10-03 04:20:13,605 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 836 GetRequests, 829 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2019-10-03 04:20:13,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106600 states. [2019-10-03 04:20:14,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106600 to 97745. [2019-10-03 04:20:14,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97745 states. [2019-10-03 04:20:15,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97745 states to 97745 states and 115001 transitions. [2019-10-03 04:20:15,074 INFO L78 Accepts]: Start accepts. Automaton has 97745 states and 115001 transitions. Word has length 413 [2019-10-03 04:20:15,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:20:15,074 INFO L475 AbstractCegarLoop]: Abstraction has 97745 states and 115001 transitions. [2019-10-03 04:20:15,074 INFO L476 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-03 04:20:15,074 INFO L276 IsEmpty]: Start isEmpty. Operand 97745 states and 115001 transitions. [2019-10-03 04:20:15,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 500 [2019-10-03 04:20:15,135 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:20:15,135 INFO L411 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:20:15,135 INFO L418 AbstractCegarLoop]: === Iteration 48 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:20:15,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:20:15,136 INFO L82 PathProgramCache]: Analyzing trace with hash -734776026, now seen corresponding path program 1 times [2019-10-03 04:20:15,136 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:20:15,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:20:15,138 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:20:15,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:20:15,139 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:20:15,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:20:15,296 INFO L134 CoverageAnalysis]: Checked inductivity of 680 backedges. 38 proven. 54 refuted. 0 times theorem prover too weak. 588 trivial. 0 not checked. [2019-10-03 04:20:15,297 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:20:15,297 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:20:15,297 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 500 with the following transitions: [2019-10-03 04:20:15,297 INFO L207 CegarAbsIntRunner]: [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [116], [118], [121], [132], [134], [136], [138], [142], [143], [148], [162], [165], [170], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [248], [253], [255], [257], [259], [260], [328], [331], [334], [336], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [367], [369], [372], [375], [377], [380], [383], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [552], [568], [570], [572], [581], [583], [591], [594], [595], [596], [599], [602], [604], [606], [608], [610], [611], [612], [621], [624], [627], [633], [636], [639], [646], [652], [659], [662], [668], [672], [675], [681], [685], [688], [691], [698], [701], [707], [713], [716], [719], [721], [723], [725], [727], [728], [729], [730], [744], [746], [779], [780], [783], [784], [785], [786], [787], [789], [790], [791], [792], [793], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [811], [812], [813], [814], [815], [816], [819], [820], [821], [822], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [857], [858], [859] [2019-10-03 04:20:15,299 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:20:15,299 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:20:21,140 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2019-10-03 04:20:21,141 INFO L272 AbstractInterpreter]: Visited 217 different actions 15698 times. Merged at 92 different actions 5609 times. Widened at 3 different actions 13 times. Performed 95241 root evaluator evaluations with a maximum evaluation depth of 4. Performed 95241 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 793 fixpoints after 33 different actions. Largest state had 72 variables. [2019-10-03 04:20:21,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:20:21,141 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2019-10-03 04:20:21,141 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:20:21,141 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-10-03 04:20:21,282 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:20:21,282 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2019-10-03 04:20:21,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:20:21,520 INFO L256 TraceCheckSpWp]: Trace formula consists of 2046 conjuncts, 9 conjunts are in the unsatisfiable core [2019-10-03 04:20:21,530 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-03 04:20:21,623 INFO L134 CoverageAnalysis]: Checked inductivity of 680 backedges. 329 proven. 0 refuted. 0 times theorem prover too weak. 351 trivial. 0 not checked. [2019-10-03 04:20:21,624 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-03 04:20:22,122 INFO L134 CoverageAnalysis]: Checked inductivity of 680 backedges. 38 proven. 54 refuted. 0 times theorem prover too weak. 588 trivial. 0 not checked. [2019-10-03 04:20:22,137 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-03 04:20:22,137 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [6, 6] total 6 [2019-10-03 04:20:22,137 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:20:22,138 INFO L454 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-03 04:20:22,138 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-03 04:20:22,138 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-03 04:20:22,138 INFO L87 Difference]: Start difference. First operand 97745 states and 115001 transitions. Second operand 6 states. [2019-10-03 04:20:22,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:20:22,382 INFO L93 Difference]: Finished difference Result 80389 states and 90995 transitions. [2019-10-03 04:20:22,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-03 04:20:22,383 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 499 [2019-10-03 04:20:22,383 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:20:22,500 INFO L225 Difference]: With dead ends: 80389 [2019-10-03 04:20:22,501 INFO L226 Difference]: Without dead ends: 80389 [2019-10-03 04:20:22,501 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 1004 GetRequests, 999 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2019-10-03 04:20:22,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80389 states. [2019-10-03 04:20:23,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80389 to 80359. [2019-10-03 04:20:23,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80359 states. [2019-10-03 04:20:23,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80359 states to 80359 states and 90965 transitions. [2019-10-03 04:20:23,662 INFO L78 Accepts]: Start accepts. Automaton has 80359 states and 90965 transitions. Word has length 499 [2019-10-03 04:20:23,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:20:23,663 INFO L475 AbstractCegarLoop]: Abstraction has 80359 states and 90965 transitions. [2019-10-03 04:20:23,663 INFO L476 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-03 04:20:23,663 INFO L276 IsEmpty]: Start isEmpty. Operand 80359 states and 90965 transitions. [2019-10-03 04:20:23,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 504 [2019-10-03 04:20:23,700 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:20:23,700 INFO L411 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:20:23,701 INFO L418 AbstractCegarLoop]: === Iteration 49 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:20:23,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:20:23,701 INFO L82 PathProgramCache]: Analyzing trace with hash 1353204914, now seen corresponding path program 1 times [2019-10-03 04:20:23,701 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:20:23,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:20:23,703 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:20:23,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:20:23,703 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:20:23,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:20:23,877 INFO L134 CoverageAnalysis]: Checked inductivity of 680 backedges. 41 proven. 12 refuted. 0 times theorem prover too weak. 627 trivial. 0 not checked. [2019-10-03 04:20:23,877 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:20:23,877 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:20:23,877 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 504 with the following transitions: [2019-10-03 04:20:23,878 INFO L207 CegarAbsIntRunner]: [2], [4], [7], [18], [20], [22], [24], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [116], [118], [121], [132], [134], [136], [138], [142], [143], [148], [162], [165], [168], [170], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [224], [230], [236], [242], [244], [245], [255], [257], [259], [260], [328], [331], [334], [336], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [367], [369], [372], [375], [377], [380], [383], [385], [388], [391], [393], [395], [396], [399], [428], [429], [430], [433], [438], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [594], [595], [596], [599], [602], [604], [606], [608], [610], [611], [612], [621], [624], [627], [633], [639], [646], [649], [655], [659], [662], [668], [672], [675], [678], [685], [688], [691], [698], [701], [707], [713], [716], [719], [721], [723], [725], [727], [728], [729], [730], [744], [746], [779], [780], [781], [782], [783], [784], [785], [786], [787], [789], [790], [791], [792], [793], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [813], [814], [817], [818], [819], [820], [821], [822], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [857], [858], [859] [2019-10-03 04:20:23,880 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:20:23,880 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:20:24,067 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2019-10-03 04:20:24,067 INFO L272 AbstractInterpreter]: Visited 209 different actions 1060 times. Merged at 58 different actions 230 times. Never widened. Performed 5994 root evaluator evaluations with a maximum evaluation depth of 4. Performed 5994 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 43 fixpoints after 16 different actions. Largest state had 72 variables. [2019-10-03 04:20:24,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:20:24,067 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2019-10-03 04:20:24,067 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:20:24,067 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-10-03 04:20:24,233 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:20:24,234 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2019-10-03 04:20:24,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:20:24,479 INFO L256 TraceCheckSpWp]: Trace formula consists of 2088 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-03 04:20:24,487 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-03 04:20:24,624 INFO L134 CoverageAnalysis]: Checked inductivity of 680 backedges. 295 proven. 0 refuted. 0 times theorem prover too weak. 385 trivial. 0 not checked. [2019-10-03 04:20:24,624 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-03 04:20:25,451 INFO L134 CoverageAnalysis]: Checked inductivity of 680 backedges. 41 proven. 12 refuted. 0 times theorem prover too weak. 627 trivial. 0 not checked. [2019-10-03 04:20:25,455 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-03 04:20:25,456 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 4] total 8 [2019-10-03 04:20:25,456 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-10-03 04:20:25,456 INFO L454 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-03 04:20:25,457 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-03 04:20:25,457 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2019-10-03 04:20:25,457 INFO L87 Difference]: Start difference. First operand 80359 states and 90965 transitions. Second operand 4 states. [2019-10-03 04:20:25,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:20:25,864 INFO L93 Difference]: Finished difference Result 19916 states and 21950 transitions. [2019-10-03 04:20:25,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-03 04:20:25,864 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 503 [2019-10-03 04:20:25,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:20:25,901 INFO L225 Difference]: With dead ends: 19916 [2019-10-03 04:20:25,901 INFO L226 Difference]: Without dead ends: 19916 [2019-10-03 04:20:25,901 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 1014 GetRequests, 1007 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2019-10-03 04:20:25,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19916 states. [2019-10-03 04:20:26,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19916 to 19372. [2019-10-03 04:20:26,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19372 states. [2019-10-03 04:20:26,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19372 states to 19372 states and 21380 transitions. [2019-10-03 04:20:26,079 INFO L78 Accepts]: Start accepts. Automaton has 19372 states and 21380 transitions. Word has length 503 [2019-10-03 04:20:26,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:20:26,079 INFO L475 AbstractCegarLoop]: Abstraction has 19372 states and 21380 transitions. [2019-10-03 04:20:26,080 INFO L476 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-03 04:20:26,080 INFO L276 IsEmpty]: Start isEmpty. Operand 19372 states and 21380 transitions. [2019-10-03 04:20:26,095 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 632 [2019-10-03 04:20:26,095 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:20:26,096 INFO L411 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:20:26,096 INFO L418 AbstractCegarLoop]: === Iteration 50 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:20:26,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:20:26,096 INFO L82 PathProgramCache]: Analyzing trace with hash -1422043055, now seen corresponding path program 1 times [2019-10-03 04:20:26,096 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:20:26,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:20:26,098 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:20:26,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:20:26,098 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:20:26,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:20:26,314 INFO L134 CoverageAnalysis]: Checked inductivity of 1020 backedges. 37 proven. 18 refuted. 0 times theorem prover too weak. 965 trivial. 0 not checked. [2019-10-03 04:20:26,315 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:20:26,315 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-10-03 04:20:26,315 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 632 with the following transitions: [2019-10-03 04:20:26,315 INFO L207 CegarAbsIntRunner]: [2], [18], [20], [28], [31], [33], [36], [47], [49], [51], [53], [57], [60], [62], [65], [76], [78], [80], [82], [86], [89], [91], [94], [105], [107], [113], [116], [118], [121], [132], [134], [136], [138], [142], [143], [148], [151], [153], [156], [160], [161], [162], [165], [168], [170], [172], [174], [176], [177], [182], [188], [194], [200], [206], [212], [218], [222], [224], [230], [236], [242], [244], [245], [248], [253], [255], [257], [259], [260], [328], [331], [334], [336], [338], [340], [342], [343], [345], [346], [348], [353], [356], [361], [364], [367], [369], [372], [375], [377], [380], [383], [385], [388], [391], [393], [395], [396], [399], [401], [406], [411], [416], [421], [426], [428], [429], [430], [433], [438], [440], [442], [444], [445], [450], [456], [462], [468], [474], [480], [486], [490], [492], [498], [504], [510], [512], [515], [521], [527], [533], [539], [545], [549], [552], [554], [557], [568], [570], [572], [581], [583], [591], [594], [595], [596], [599], [602], [604], [606], [608], [610], [611], [612], [621], [624], [627], [629], [633], [636], [646], [649], [655], [659], [662], [672], [675], [685], [688], [698], [701], [712], [713], [716], [719], [721], [723], [725], [727], [728], [729], [730], [744], [746], [748], [750], [755], [763], [766], [771], [779], [780], [783], [784], [785], [786], [787], [789], [790], [791], [792], [793], [795], [796], [797], [798], [799], [800], [801], [802], [803], [804], [805], [806], [807], [808], [809], [810], [811], [812], [813], [814], [815], [816], [817], [818], [819], [820], [821], [822], [823], [824], [825], [826], [827], [828], [829], [830], [831], [832], [833], [834], [835], [836], [837], [838], [839], [840], [841], [842], [843], [844], [845], [846], [847], [848], [855], [856], [857], [858], [859] [2019-10-03 04:20:26,318 INFO L148 AbstractInterpreter]: Using domain IntervalDomain [2019-10-03 04:20:26,319 INFO L101 FixpointEngine]: Starting fixpoint engine with domain IntervalDomain (maxUnwinding=3, maxParallelStates=2) [2019-10-03 04:20:28,828 INFO L263 AbstractInterpreter]: Some error location(s) were reachable [2019-10-03 04:20:28,829 INFO L272 AbstractInterpreter]: Visited 260 different actions 12097 times. Merged at 110 different actions 4018 times. Widened at 1 different actions 1 times. Performed 66345 root evaluator evaluations with a maximum evaluation depth of 4. Performed 66345 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 486 fixpoints after 34 different actions. Largest state had 72 variables. [2019-10-03 04:20:28,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:20:28,829 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2019-10-03 04:20:28,829 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-10-03 04:20:28,829 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-10-03 04:20:29,024 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:20:29,024 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2019-10-03 04:20:29,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-03 04:20:29,319 INFO L256 TraceCheckSpWp]: Trace formula consists of 2510 conjuncts, 16 conjunts are in the unsatisfiable core [2019-10-03 04:20:29,330 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-03 04:20:29,580 INFO L134 CoverageAnalysis]: Checked inductivity of 1020 backedges. 549 proven. 62 refuted. 0 times theorem prover too weak. 409 trivial. 0 not checked. [2019-10-03 04:20:29,580 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-03 04:20:29,909 WARN L191 SmtUtils]: Spent 262.00 ms on a formula simplification that was a NOOP. DAG size: 1 [2019-10-03 04:20:30,167 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-03 04:20:30,178 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-03 04:20:30,182 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-03 04:20:30,185 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-03 04:20:30,188 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-03 04:20:30,197 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-03 04:20:30,246 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-03 04:20:30,288 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-03 04:20:30,692 INFO L134 CoverageAnalysis]: Checked inductivity of 1020 backedges. 34 proven. 13 refuted. 0 times theorem prover too weak. 973 trivial. 0 not checked. [2019-10-03 04:20:30,706 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-10-03 04:20:30,707 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 10 [2019-10-03 04:20:30,707 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-10-03 04:20:30,708 INFO L454 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-10-03 04:20:30,708 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-10-03 04:20:30,709 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-10-03 04:20:30,709 INFO L87 Difference]: Start difference. First operand 19372 states and 21380 transitions. Second operand 8 states. [2019-10-03 04:20:31,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-03 04:20:31,367 INFO L93 Difference]: Finished difference Result 16544 states and 18293 transitions. [2019-10-03 04:20:31,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-10-03 04:20:31,368 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 631 [2019-10-03 04:20:31,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-03 04:20:31,381 INFO L225 Difference]: With dead ends: 16544 [2019-10-03 04:20:31,381 INFO L226 Difference]: Without dead ends: 7319 [2019-10-03 04:20:31,382 INFO L640 BasicCegarLoop]: 0 DeclaredPredicates, 1276 GetRequests, 1261 SyntacticMatches, 5 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=89, Unknown=0, NotChecked=0, Total=132 [2019-10-03 04:20:31,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7319 states. [2019-10-03 04:20:31,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7319 to 7314. [2019-10-03 04:20:31,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7314 states. [2019-10-03 04:20:31,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7314 states to 7314 states and 7964 transitions. [2019-10-03 04:20:31,469 INFO L78 Accepts]: Start accepts. Automaton has 7314 states and 7964 transitions. Word has length 631 [2019-10-03 04:20:31,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-03 04:20:31,470 INFO L475 AbstractCegarLoop]: Abstraction has 7314 states and 7964 transitions. [2019-10-03 04:20:31,470 INFO L476 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-10-03 04:20:31,470 INFO L276 IsEmpty]: Start isEmpty. Operand 7314 states and 7964 transitions. [2019-10-03 04:20:31,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 566 [2019-10-03 04:20:31,485 INFO L403 BasicCegarLoop]: Found error trace [2019-10-03 04:20:31,486 INFO L411 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-03 04:20:31,486 INFO L418 AbstractCegarLoop]: === Iteration 51 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-03 04:20:31,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-03 04:20:31,487 INFO L82 PathProgramCache]: Analyzing trace with hash -1495638816, now seen corresponding path program 1 times [2019-10-03 04:20:31,487 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-10-03 04:20:31,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:20:31,491 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-03 04:20:31,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-03 04:20:31,491 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-10-03 04:20:31,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-03 04:20:31,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-03 04:20:32,005 INFO L478 BasicCegarLoop]: Counterexample might be feasible [2019-10-03 04:20:32,328 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.10 04:20:32 BoogieIcfgContainer [2019-10-03 04:20:32,328 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-10-03 04:20:32,330 INFO L168 Benchmark]: Toolchain (without parser) took 507645.32 ms. Allocated memory was 133.2 MB in the beginning and 5.8 GB in the end (delta: 5.6 GB). Free memory was 88.5 MB in the beginning and 2.0 GB in the end (delta: -1.9 GB). Peak memory consumption was 3.8 GB. Max. memory is 7.1 GB. [2019-10-03 04:20:32,331 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 133.2 MB. Free memory was 107.4 MB in the beginning and 107.2 MB in the end (delta: 212.8 kB). Peak memory consumption was 212.8 kB. Max. memory is 7.1 GB. [2019-10-03 04:20:32,332 INFO L168 Benchmark]: CACSL2BoogieTranslator took 603.78 ms. Allocated memory was 133.2 MB in the beginning and 201.3 MB in the end (delta: 68.2 MB). Free memory was 88.3 MB in the beginning and 173.3 MB in the end (delta: -85.0 MB). Peak memory consumption was 29.3 MB. Max. memory is 7.1 GB. [2019-10-03 04:20:32,333 INFO L168 Benchmark]: Boogie Preprocessor took 75.34 ms. Allocated memory is still 201.3 MB. Free memory was 173.3 MB in the beginning and 170.8 MB in the end (delta: 2.5 MB). Peak memory consumption was 2.5 MB. Max. memory is 7.1 GB. [2019-10-03 04:20:32,334 INFO L168 Benchmark]: RCFGBuilder took 906.66 ms. Allocated memory is still 201.3 MB. Free memory was 170.8 MB in the beginning and 116.5 MB in the end (delta: 54.3 MB). Peak memory consumption was 54.3 MB. Max. memory is 7.1 GB. [2019-10-03 04:20:32,341 INFO L168 Benchmark]: TraceAbstraction took 506055.20 ms. Allocated memory was 201.3 MB in the beginning and 5.8 GB in the end (delta: 5.6 GB). Free memory was 115.8 MB in the beginning and 2.0 GB in the end (delta: -1.8 GB). Peak memory consumption was 3.7 GB. Max. memory is 7.1 GB. [2019-10-03 04:20:32,348 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 133.2 MB. Free memory was 107.4 MB in the beginning and 107.2 MB in the end (delta: 212.8 kB). Peak memory consumption was 212.8 kB. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 603.78 ms. Allocated memory was 133.2 MB in the beginning and 201.3 MB in the end (delta: 68.2 MB). Free memory was 88.3 MB in the beginning and 173.3 MB in the end (delta: -85.0 MB). Peak memory consumption was 29.3 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 75.34 ms. Allocated memory is still 201.3 MB. Free memory was 173.3 MB in the beginning and 170.8 MB in the end (delta: 2.5 MB). Peak memory consumption was 2.5 MB. Max. memory is 7.1 GB. * RCFGBuilder took 906.66 ms. Allocated memory is still 201.3 MB. Free memory was 170.8 MB in the beginning and 116.5 MB in the end (delta: 54.3 MB). Peak memory consumption was 54.3 MB. Max. memory is 7.1 GB. * TraceAbstraction took 506055.20 ms. Allocated memory was 201.3 MB in the beginning and 5.8 GB in the end (delta: 5.6 GB). Free memory was 115.8 MB in the beginning and 2.0 GB in the end (delta: -1.8 GB). Peak memory consumption was 3.7 GB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int m_i ; [L28] int t1_i ; [L29] int t2_i ; [L30] int t3_i ; [L31] int t4_i ; [L32] int t5_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int T3_E = 2; [L37] int T4_E = 2; [L38] int T5_E = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; VAL [\old(E_1)=29, \old(E_2)=21, \old(E_3)=20, \old(E_4)=8, \old(E_5)=4, \old(M_E)=13, \old(m_i)=7, \old(m_pc)=25, \old(m_st)=12, \old(T1_E)=3, \old(t1_i)=26, \old(t1_pc)=24, \old(t1_st)=5, \old(T2_E)=27, \old(t2_i)=6, \old(t2_pc)=23, \old(t2_st)=10, \old(T3_E)=19, \old(t3_i)=30, \old(t3_pc)=22, \old(t3_st)=11, \old(T4_E)=31, \old(t4_i)=14, \old(t4_pc)=18, \old(t4_st)=9, \old(T5_E)=17, \old(t5_i)=28, \old(t5_pc)=15, \old(t5_st)=16, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L935] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L939] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L846] m_i = 1 [L847] t1_i = 1 [L848] t2_i = 1 [L849] t3_i = 1 [L850] t4_i = 1 [L851] t5_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L939] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L940] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L876] int kernel_st ; [L877] int tmp ; [L878] int tmp___0 ; [L882] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L883] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L884] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L391] COND TRUE m_i == 1 [L392] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L396] COND TRUE t1_i == 1 [L397] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L401] COND TRUE t2_i == 1 [L402] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t3_i == 1 [L407] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t4_i == 1 [L412] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t5_i == 1 [L417] t5_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L884] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L885] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L576] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L581] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L586] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T4_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T5_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_4 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_5 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L885] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L886] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L269] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L288] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L307] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L326] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L345] COND FALSE !(t4_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L364] COND FALSE !(t5_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L886] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L887] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L639] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L644] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L649] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T4_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T5_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L887] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L890] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L893] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L894] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L467] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L471] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L474] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L426] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L429] COND TRUE m_st == 0 [L430] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L462] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L474] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L474] tmp = exists_runnable_thread() [L476] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1] [L481] COND TRUE m_st == 0 [L482] int tmp_ndt_1; [L483] tmp_ndt_1 = __VERIFIER_nondet_int() [L484] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0] [L495] COND TRUE t1_st == 0 [L496] int tmp_ndt_2; [L497] tmp_ndt_2 = __VERIFIER_nondet_int() [L498] COND TRUE \read(tmp_ndt_2) [L500] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L501] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L96] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L107] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L109] t1_pc = 1 [L110] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L501] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L509] COND TRUE t2_st == 0 [L510] int tmp_ndt_3; [L511] tmp_ndt_3 = __VERIFIER_nondet_int() [L512] COND TRUE \read(tmp_ndt_3) [L514] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L515] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L131] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L142] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L144] t2_pc = 1 [L145] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L515] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L523] COND TRUE t3_st == 0 [L524] int tmp_ndt_4; [L525] tmp_ndt_4 = __VERIFIER_nondet_int() [L526] COND TRUE \read(tmp_ndt_4) [L528] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L529] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L166] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L177] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L179] t3_pc = 1 [L180] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L529] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L537] COND TRUE t4_st == 0 [L538] int tmp_ndt_5; [L539] tmp_ndt_5 = __VERIFIER_nondet_int() [L540] COND TRUE \read(tmp_ndt_5) [L542] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L543] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L201] COND TRUE t4_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L212] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L214] t4_pc = 1 [L215] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L543] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1] [L551] COND TRUE t5_st == 0 [L552] int tmp_ndt_6; [L553] tmp_ndt_6 = __VERIFIER_nondet_int() [L554] COND TRUE \read(tmp_ndt_6) [L556] t5_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L557] CALL transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1] [L236] COND TRUE t5_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1] [L247] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1] [L249] t5_pc = 1 [L250] t5_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L557] RET transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L471] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L474] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L426] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L429] COND TRUE m_st == 0 [L430] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L462] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L474] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L474] tmp = exists_runnable_thread() [L476] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L481] COND TRUE m_st == 0 [L482] int tmp_ndt_1; [L483] tmp_ndt_1 = __VERIFIER_nondet_int() [L484] COND TRUE \read(tmp_ndt_1) [L486] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L487] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L55] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L66] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L69] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L70] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND TRUE E_1 == 1 [L290] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND TRUE \read(tmp___0) [L719] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L70] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L71] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L74] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L76] m_pc = 1 [L77] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L487] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L495] COND TRUE t1_st == 0 [L496] int tmp_ndt_2; [L497] tmp_ndt_2 = __VERIFIER_nondet_int() [L498] COND TRUE \read(tmp_ndt_2) [L500] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L501] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L96] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L99] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L115] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L116] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND TRUE E_2 == 1 [L309] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND TRUE \read(tmp___1) [L727] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0, tmp___3=0, tmp___4=0] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L116] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L117] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L107] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L109] t1_pc = 1 [L110] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L501] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L509] COND TRUE t2_st == 0 [L510] int tmp_ndt_3; [L511] tmp_ndt_3 = __VERIFIER_nondet_int() [L512] COND TRUE \read(tmp_ndt_3) [L514] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L515] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L131] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L134] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L150] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L151] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND TRUE E_3 == 1 [L328] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND TRUE \read(tmp___2) [L735] t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1, tmp___3=0, tmp___4=0] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L151] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L152] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L142] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L144] t2_pc = 1 [L145] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L515] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L523] COND TRUE t3_st == 0 [L524] int tmp_ndt_4; [L525] tmp_ndt_4 = __VERIFIER_nondet_int() [L526] COND TRUE \read(tmp_ndt_4) [L528] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L529] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L166] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L169] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L185] E_4 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L186] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND TRUE E_4 == 1 [L347] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit4_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND TRUE \read(tmp___3) [L743] t4_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, is_transmit5_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=1, tmp___4=0] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L186] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L187] E_4 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L177] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L179] t3_pc = 1 [L180] t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=2, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L529] RET transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L537] COND TRUE t4_st == 0 [L538] int tmp_ndt_5; [L539] tmp_ndt_5 = __VERIFIER_nondet_int() [L540] COND TRUE \read(tmp_ndt_5) [L542] t4_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L543] CALL transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L201] COND FALSE !(t4_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L204] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L220] E_5 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L221] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L764] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L266] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] RET, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] CALL, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] RET, EXPR is_transmit4_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit4_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L748] CALL, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND TRUE E_5 == 1 [L366] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] RET, EXPR is_transmit5_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, is_transmit5_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND TRUE \read(tmp___4) [L751] t5_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=1] [L764] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L221] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L222] E_5 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L212] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L214] t4_pc = 1 [L215] t4_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=1, \old(t4_st)=1, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L543] RET transmit4() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L551] COND TRUE t5_st == 0 [L552] int tmp_ndt_6; [L553] tmp_ndt_6 = __VERIFIER_nondet_int() [L554] COND TRUE \read(tmp_ndt_6) [L556] t5_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=0, \old(t5_st)=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1, tmp_ndt_5=1, tmp_ndt_6=1] [L557] CALL transmit5() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L236] COND FALSE !(t5_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L239] COND TRUE t5_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L255] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \old(T4_E)=2, \old(t4_i)=0, \old(t4_pc)=0, \old(t4_st)=0, \old(T5_E)=2, \old(t5_i)=0, \old(t5_pc)=1, \old(t5_st)=1, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 29 procedures, 259 locations, 1 error locations. UNSAFE Result, 505.9s OverallTime, 51 OverallIterations, 6 TraceHistogramMax, 263.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 19670 SDtfs, 29790 SDslu, 49985 SDs, 0 SdLazy, 36443 SolverSat, 7947 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 40.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 9640 GetRequests, 8667 SyntacticMatches, 34 SemanticMatches, 939 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37669 ImplicationChecksByTransitivity, 34.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=458276occurred in iteration=40, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 11.0s AbstIntTime, 14 AbstIntIterations, 5 AbstIntStrong, 0.9953931459357362 AbsIntWeakeningRatio, 0.614856429463171 AbsIntAvgWeakeningVarsNumRemoved, 17.354556803995006 AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 183.7s AutomataMinimizationTime, 50 MinimizatonAttempts, 33799 StatesRemovedByMinimization, 44 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.9s SsaConstructionTime, 2.1s SatisfiabilityAnalysisTime, 8.7s InterpolantComputationTime, 14853 NumberOfCodeBlocks, 14853 NumberOfCodeBlocksAsserted, 60 NumberOfCheckSat, 17873 ConstructedInterpolants, 0 QuantifiedInterpolants, 7866124 SizeOfPredicates, 13 NumberOfNonLiveVariables, 15922 ConjunctsInSsa, 70 ConjunctsInUnsatCore, 68 InterpolantComputations, 45 PerfectInterpolantSequences, 12703/13159 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...