java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/avg10-2.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:23:25,195 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:23:25,198 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:23:25,210 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:23:25,211 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:23:25,212 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:23:25,213 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:23:25,215 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:23:25,217 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:23:25,218 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:23:25,219 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:23:25,222 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:23:25,222 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:23:25,223 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:23:25,229 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:23:25,230 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:23:25,234 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:23:25,235 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:23:25,238 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:23:25,240 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:23:25,241 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:23:25,242 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:23:25,243 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:23:25,244 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:23:25,246 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 15:23:25,254 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:23:25,255 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:23:25,255 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:23:25,256 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:23:25,271 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:23:25,272 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:23:25,274 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:23:25,274 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:23:25,274 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:23:25,275 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:23:25,275 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:23:25,275 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:23:25,275 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:23:25,275 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:23:25,276 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:23:25,276 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:23:25,276 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:23:25,276 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:23:25,276 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:23:25,277 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:23:25,277 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:23:25,277 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:23:25,277 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:23:25,278 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:23:25,278 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:23:25,278 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:23:25,278 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:23:25,279 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:23:25,279 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:23:25,279 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:23:25,279 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:23:25,279 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:23:25,280 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:23:25,599 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:23:25,614 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:23:25,618 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:23:25,620 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:23:25,621 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:23:25,621 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/avg10-2.i [2019-10-07 15:23:25,711 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6347200f4/d89e7d333f41460ca5f84c9222983d9b/FLAGdb17c31d9 [2019-10-07 15:23:26,193 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:23:26,193 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/avg10-2.i [2019-10-07 15:23:26,201 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6347200f4/d89e7d333f41460ca5f84c9222983d9b/FLAGdb17c31d9 [2019-10-07 15:23:26,506 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6347200f4/d89e7d333f41460ca5f84c9222983d9b [2019-10-07 15:23:26,518 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:23:26,522 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:23:26,525 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:23:26,525 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:23:26,529 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:23:26,530 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:23:26" (1/1) ... [2019-10-07 15:23:26,533 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@351bcc33 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:26, skipping insertion in model container [2019-10-07 15:23:26,533 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:23:26" (1/1) ... [2019-10-07 15:23:26,542 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:23:26,563 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:23:26,763 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:23:26,772 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:23:26,793 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:23:26,809 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:23:26,810 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:26 WrapperNode [2019-10-07 15:23:26,810 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:23:26,811 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:23:26,811 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:23:26,811 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:23:26,931 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:26" (1/1) ... [2019-10-07 15:23:26,932 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:26" (1/1) ... [2019-10-07 15:23:26,938 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:26" (1/1) ... [2019-10-07 15:23:26,939 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:26" (1/1) ... [2019-10-07 15:23:26,947 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:26" (1/1) ... [2019-10-07 15:23:26,952 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:26" (1/1) ... [2019-10-07 15:23:26,954 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:26" (1/1) ... [2019-10-07 15:23:26,956 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:23:26,957 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:23:26,957 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:23:26,957 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:23:26,958 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:26" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:23:27,018 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:23:27,018 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:23:27,018 INFO L138 BoogieDeclarations]: Found implementation of procedure avg [2019-10-07 15:23:27,018 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:23:27,018 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:23:27,018 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:23:27,019 INFO L130 BoogieDeclarations]: Found specification of procedure avg [2019-10-07 15:23:27,019 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:23:27,019 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:23:27,019 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:23:27,019 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:23:27,019 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:23:27,020 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:23:27,020 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:23:27,410 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:23:27,410 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:23:27,411 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:23:27 BoogieIcfgContainer [2019-10-07 15:23:27,411 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:23:27,412 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:23:27,413 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:23:27,415 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:23:27,415 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:23:26" (1/3) ... [2019-10-07 15:23:27,416 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@613b9339 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:23:27, skipping insertion in model container [2019-10-07 15:23:27,416 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:26" (2/3) ... [2019-10-07 15:23:27,417 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@613b9339 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:23:27, skipping insertion in model container [2019-10-07 15:23:27,417 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:23:27" (3/3) ... [2019-10-07 15:23:27,418 INFO L109 eAbstractionObserver]: Analyzing ICFG avg10-2.i [2019-10-07 15:23:27,426 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:23:27,434 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:23:27,446 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:23:27,474 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:23:27,475 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:23:27,475 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:23:27,475 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:23:27,475 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:23:27,475 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:23:27,476 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:23:27,476 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:23:27,497 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:23:27,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:23:27,503 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:27,504 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:27,505 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:27,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:27,510 INFO L82 PathProgramCache]: Analyzing trace with hash 2112018211, now seen corresponding path program 1 times [2019-10-07 15:23:27,517 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:27,517 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:27,518 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:27,518 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:27,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:27,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:27,706 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:23:27,706 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:27,707 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:23:27,707 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:23:27,710 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:27,720 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:27,721 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:27,723 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:23:27,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:27,761 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:23:27,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:27,765 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:23:27,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:27,773 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:23:27,773 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:23:27,777 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:27,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:23:27,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:23:27,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:23:27,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:23:27,819 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:23:27,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:27,819 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:23:27,820 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:27,820 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:23:27,822 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:23:27,822 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:27,823 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:27,823 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:27,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:27,824 INFO L82 PathProgramCache]: Analyzing trace with hash -2049651994, now seen corresponding path program 1 times [2019-10-07 15:23:27,824 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:27,824 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:27,824 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:27,825 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:27,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:27,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:27,947 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:27,948 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:27,948 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:23:27,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:28,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:28,059 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:23:28,069 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:23:28,101 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:28,102 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:23:28,164 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:28,166 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:23:28,167 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:23:28,170 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:28,172 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:28,174 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:23:28,175 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:23:28,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:28,200 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:23:28,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:28,202 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:23:28,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:28,204 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:23:28,204 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:23:28,208 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:23:28,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:23:28,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:23:28,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:23:28,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:23:28,228 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:23:28,229 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:28,229 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:23:28,229 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:28,230 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:23:28,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:23:28,232 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:28,232 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:28,440 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:28,441 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:28,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:28,442 INFO L82 PathProgramCache]: Analyzing trace with hash -575014574, now seen corresponding path program 1 times [2019-10-07 15:23:28,442 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:28,442 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:28,442 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:28,443 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:28,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:28,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:28,562 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:28,562 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:28,563 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:23:28,563 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:23:28,564 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:28,564 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:28,564 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:28,565 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:23:28,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:28,589 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:23:28,591 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:28,591 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:23:28,591 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:28,592 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:23:28,592 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:23:28,594 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:28,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:23:28,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:23:28,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:23:28,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:23:28,605 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:23:28,607 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:28,607 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:23:28,607 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:28,607 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:23:28,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:23:28,609 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:28,610 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:28,610 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:28,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:28,611 INFO L82 PathProgramCache]: Analyzing trace with hash -202958309, now seen corresponding path program 1 times [2019-10-07 15:23:28,611 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:28,611 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:28,611 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:28,611 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:28,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:28,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:28,725 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:28,725 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:28,726 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:23:28,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:28,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:28,844 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:23:28,848 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:23:28,872 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:28,872 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:23:28,911 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:28,911 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:23:28,939 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:23:28,939 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:23:28,946 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:23:28,954 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:23:28,955 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:23:29,096 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:23:45,839 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:23:45,866 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:23:45,870 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:23:45,870 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:23:45,870 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:23:45,871 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:23:45,871 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:23:45,871 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:23:45,871 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:23:45,871 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:23:45,872 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_1 10) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_1 10) 1) 4294967296) 2147483647) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_1 10))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 10) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_1 0) (not (< main_~i~1 10))) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 10) 4294967296) 2147483647)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_1 10) 1) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_1 10)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_1 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (<= (mod (div v_prenex_1 10) 4294967296) 2147483647) (not (< v_prenex_1 0)) (<= (mod (+ (div v_prenex_1 10) 1) 4294967296) 2147483647) (= (mod (div v_prenex_1 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10))) (and (not (= 0 (mod v_prenex_1 10))) (<= (mod (div v_prenex_1 10) 4294967296) 2147483647) (< v_prenex_1 0) (not (<= (mod (+ (div v_prenex_1 10) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_1 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_1 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 10) 4294967296) 2147483647)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_1 10) 1) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_1 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_1 10) 1) 4294967296) 2147483647) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 10) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_1 10)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_1 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (<= (mod (div v_prenex_1 10) 4294967296) 2147483647) (not (< v_prenex_1 0)) (not (<= (mod (+ (div v_prenex_1 10) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_1 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10))) (and (<= (mod (div v_prenex_1 10) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_1 10) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_1 10) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_1 10)) (not (< main_~i~1 10))) (and (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_1 10))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 10) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_1 0) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_1 10) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_1 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (<= (mod (div v_prenex_1 10) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_1 10) 1) 4294967296) 2147483647) (= (mod (div v_prenex_1 10) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_1 10)) (not (< main_~i~1 10))) (and (not (= 0 (mod v_prenex_1 10))) (<= (mod (div v_prenex_1 10) 4294967296) 2147483647) (< v_prenex_1 0) (<= (mod (+ (div v_prenex_1 10) 1) 4294967296) 2147483647) (not (< main_~i~1 10)) (= (mod (+ (div v_prenex_1 10) 1) 4294967296) |main_#t~ret4|)) (and (not (< v_avg_~ret~0_BEFORE_RETURN_1 0)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_1 10) 1) 4294967296) 2147483647) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 10) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_1 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))))) (exists ((v_avg_~ret~0_BEFORE_RETURN_2 Int) (v_prenex_2 Int)) (or (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_2 10)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_2 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 10) 4294967296) 2147483647)) (not (< main_~i~1 10))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_2 0)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 10) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_2 10) 4294967296)) (not (< main_~i~1 10))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_2 0)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_2 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 10) 4294967296) 2147483647)) (not (< main_~i~1 10))) (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_2 10)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 10) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_2 10) 4294967296)) (not (< main_~i~1 10))) (and (not (= 0 (mod v_prenex_2 10))) (not (<= (mod (+ (div v_prenex_2 10) 1) 4294967296) 2147483647)) (< v_prenex_2 0) (= (+ (mod (+ (div v_prenex_2 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (not (= 0 (mod v_prenex_2 10))) (<= (mod (+ (div v_prenex_2 10) 1) 4294967296) 2147483647) (< v_prenex_2 0) (not (< main_~i~1 10)) (= |main_#t~ret4| (mod (+ (div v_prenex_2 10) 1) 4294967296)))))) [2019-10-07 15:23:45,872 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:23:45,872 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:23:45,872 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 10 avg_~i~0) (<= 0 avg_~i~0) (not (< avg_~i~0 10)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:23:45,873 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:23:45,873 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:23:45,873 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:23:45,873 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:23:45,874 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:23:45,874 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:23:45,874 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:23:45,874 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:23:45,874 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:23:48,144 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:23:48,145 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:23:48,146 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-10-07 15:23:48,147 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-10-07 15:23:48,147 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=225, Unknown=1, NotChecked=0, Total=272 [2019-10-07 15:23:48,147 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 17 states. [2019-10-07 15:24:12,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:12,763 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:24:12,766 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-10-07 15:24:12,766 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 29 [2019-10-07 15:24:12,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:12,767 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:24:12,767 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:24:12,768 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 12.6s TimeCoverageRelationStatistics Valid=123, Invalid=627, Unknown=6, NotChecked=0, Total=756 [2019-10-07 15:24:12,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:24:12,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:24:12,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:24:12,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:24:12,776 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:24:12,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:12,777 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:24:12,777 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-10-07 15:24:12,777 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:24:12,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:24:12,778 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:12,779 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:12,989 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:12,989 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:12,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:12,989 INFO L82 PathProgramCache]: Analyzing trace with hash -892290920, now seen corresponding path program 2 times [2019-10-07 15:24:12,990 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:12,990 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:12,990 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:12,990 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:12,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:13,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:13,100 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:13,101 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:13,101 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:13,101 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:13,186 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:24:13,186 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:13,189 INFO L256 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:24:13,192 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:13,207 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:13,208 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:13,250 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:13,251 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:13,254 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:13,256 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:13,257 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:13,257 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:13,257 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:13,292 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:30,974 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:24:31,006 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:31,009 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:31,009 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:31,010 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:31,010 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:24:31,010 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:24:31,010 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:24:31,010 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:31,011 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:31,011 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_269 Int) (v_avg_~ret~0_BEFORE_RETURN_27 Int)) (or (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 10) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 10) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_27 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_avg_~ret~0_BEFORE_RETURN_27 10) 0) (not (< main_~i~1 10))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_27 0)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 10) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 10) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_27 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (= (+ (mod (+ (div v_prenex_269 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (div v_prenex_269 10) 4294967296) 2147483647) (not (= (mod v_prenex_269 10) 0)) (< v_prenex_269 0) (not (<= (mod (+ (div v_prenex_269 10) 1) 4294967296) 2147483647)) (not (< main_~i~1 10))) (and (<= (mod (div v_prenex_269 10) 4294967296) 2147483647) (not (< v_prenex_269 0)) (= (mod (div v_prenex_269 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10)) (<= (mod (+ (div v_prenex_269 10) 1) 4294967296) 2147483647)) (and (= (mod (+ (div v_prenex_269 10) 1) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_269 10) 4294967296) 2147483647) (not (= (mod v_prenex_269 10) 0)) (< v_prenex_269 0) (not (< main_~i~1 10)) (<= (mod (+ (div v_prenex_269 10) 1) 4294967296) 2147483647)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 10) 1) 4294967296) 2147483647) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 10) 4294967296) 2147483647)) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 10) 1) 4294967296) |main_#t~ret4|) (< v_avg_~ret~0_BEFORE_RETURN_27 0) (not (< main_~i~1 10)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_27 10) 0))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_27 0)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 10) 1) 4294967296) 2147483647) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 10) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_27 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (= (mod v_prenex_269 10) 0) (<= (mod (div v_prenex_269 10) 4294967296) 2147483647) (= (mod (div v_prenex_269 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10)) (<= (mod (+ (div v_prenex_269 10) 1) 4294967296) 2147483647)) (and (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 10) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 10) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_27 0) (not (< main_~i~1 10)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_27 10) 0))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 10) 1) 4294967296) 2147483647) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 10) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_27 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_avg_~ret~0_BEFORE_RETURN_27 10) 0) (not (< main_~i~1 10))) (and (<= (mod (div v_prenex_269 10) 4294967296) 2147483647) (not (< v_prenex_269 0)) (not (<= (mod (+ (div v_prenex_269 10) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_269 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10))) (and (= (mod v_prenex_269 10) 0) (<= (mod (div v_prenex_269 10) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_269 10) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_269 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10))))) (exists ((v_avg_~ret~0_BEFORE_RETURN_28 Int) (v_prenex_270 Int)) (or (and (not (<= (mod (div v_prenex_270 10) 4294967296) 2147483647)) (not (< v_prenex_270 0)) (= (+ (mod (div v_prenex_270 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (not (<= (mod (div v_prenex_270 10) 4294967296) 2147483647)) (= 0 (mod v_prenex_270 10)) (= (+ (mod (div v_prenex_270 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (<= (mod (div v_prenex_270 10) 4294967296) 2147483647) (= 0 (mod v_prenex_270 10)) (= (mod (div v_prenex_270 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10))) (and (<= (mod (div v_prenex_270 10) 4294967296) 2147483647) (= (mod (div v_prenex_270 10) 4294967296) |main_#t~ret4|) (not (< v_prenex_270 0)) (not (< main_~i~1 10))) (and (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_avg_~ret~0_BEFORE_RETURN_28 0) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 10) 1) 4294967296) 2147483647)) (not (< main_~i~1 10)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_28 10)))) (and (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 10) 1) 4294967296)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 10) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_28 0) (not (< main_~i~1 10)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_28 10))))))) [2019-10-07 15:24:31,011 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:24:31,012 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:31,012 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 10 avg_~i~0) (<= 0 avg_~i~0) (not (< avg_~i~0 10)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:24:31,012 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:31,012 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:24:31,012 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:24:31,012 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:24:31,013 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:24:31,013 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:24:31,013 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:24:31,013 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:24:31,014 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:33,422 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:33,423 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:24:33,424 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-10-07 15:24:33,425 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-10-07 15:24:33,425 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=359, Unknown=1, NotChecked=0, Total=420 [2019-10-07 15:24:33,425 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 21 states. [2019-10-07 15:25:02,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:02,291 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:25:02,293 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-10-07 15:25:02,293 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 32 [2019-10-07 15:25:02,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:02,295 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:25:02,295 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:25:02,296 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 14.9s TimeCoverageRelationStatistics Valid=200, Invalid=1125, Unknown=7, NotChecked=0, Total=1332 [2019-10-07 15:25:02,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:25:02,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:25:02,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:25:02,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:25:02,304 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:25:02,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:02,304 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:25:02,305 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-10-07 15:25:02,305 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:25:02,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:25:02,306 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:02,306 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:02,507 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:02,507 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:02,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:02,508 INFO L82 PathProgramCache]: Analyzing trace with hash -337812683, now seen corresponding path program 3 times [2019-10-07 15:25:02,508 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:02,509 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:02,509 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:02,509 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:02,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:02,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:02,604 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:02,604 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:02,605 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:02,605 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:02,711 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:25:02,711 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:25:02,712 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:25:02,715 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:02,752 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-10-07 15:25:02,753 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:02,820 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 62 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-10-07 15:25:02,821 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:02,822 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:02,823 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:02,823 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:02,823 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:02,823 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:02,847 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:19,877 WARN L160 IndexEqualityManager]: solver failed to check if following equality is implied: (= |main_~#x~0.offset| (+ |main_~#x~0.offset| 4)) [2019-10-07 15:25:32,773 WARN L160 IndexEqualityManager]: solver failed to check if following equality is implied: (let ((.cse0 (select |v_#memory_int_110| |main_~#x~0.base|))) (= (select .cse0 (+ |main_~#x~0.offset| 4)) (select .cse0 |main_~#x~0.offset|))) [2019-10-07 15:25:38,384 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:25:38,406 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:38,410 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:38,410 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:38,411 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:38,411 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:25:38,411 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:25:38,411 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:25:38,412 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:38,412 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:38,413 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_549 Int)) (or (and (not (< v_avg_~ret~0_BEFORE_RETURN_53 0)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 10) 1) 4294967296) 2147483647)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 10) 4294967296) 2147483647)) (and (not (<= (mod (div v_prenex_549 10) 4294967296) 2147483647)) (not (< v_prenex_549 0)) (= (+ (mod (div v_prenex_549 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10)) (<= (mod (+ (div v_prenex_549 10) 1) 4294967296) 2147483647)) (and (not (<= (mod (div v_prenex_549 10) 4294967296) 2147483647)) (= |main_#t~ret4| (mod (+ (div v_prenex_549 10) 1) 4294967296)) (not (= 0 (mod v_prenex_549 10))) (not (< main_~i~1 10)) (<= (mod (+ (div v_prenex_549 10) 1) 4294967296) 2147483647) (< v_prenex_549 0)) (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_53 10)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 10) 1) 4294967296) 2147483647)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 10) 4294967296) 2147483647)) (and (not (<= (mod (div v_prenex_549 10) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_549 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_prenex_549 10)) (not (< main_~i~1 10)) (<= (mod (+ (div v_prenex_549 10) 1) 4294967296) 2147483647)) (and (<= (mod (div v_prenex_549 10) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_prenex_549 10) 1) 4294967296)) (not (= 0 (mod v_prenex_549 10))) (not (< main_~i~1 10)) (< v_prenex_549 0) (<= (mod (+ (div v_prenex_549 10) 1) 4294967296) 2147483647)) (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_53 10)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_53 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 10) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 10) 4294967296) 2147483647)) (not (< main_~i~1 10))) (and (< v_avg_~ret~0_BEFORE_RETURN_53 0) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 10) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 10) 4294967296) 2147483647)) (not (< main_~i~1 10)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_53 10)))) (and (= (mod (div v_prenex_549 10) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_549 10) 4294967296) 2147483647) (= 0 (mod v_prenex_549 10)) (not (< main_~i~1 10)) (<= (mod (+ (div v_prenex_549 10) 1) 4294967296) 2147483647)) (and (not (< v_avg_~ret~0_BEFORE_RETURN_53 0)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_53 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 10) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 10) 4294967296) 2147483647)) (not (< main_~i~1 10))) (and (not (< v_prenex_549 0)) (= (mod (div v_prenex_549 10) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_549 10) 4294967296) 2147483647) (not (< main_~i~1 10)) (<= (mod (+ (div v_prenex_549 10) 1) 4294967296) 2147483647)) (and (< v_avg_~ret~0_BEFORE_RETURN_53 0) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 10) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_53 10))) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 10) 4294967296) 2147483647)))) (exists ((v_prenex_550 Int) (v_avg_~ret~0_BEFORE_RETURN_54 Int)) (or (and (< v_avg_~ret~0_BEFORE_RETURN_54 0) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_54 10))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 10) 4294967296) 2147483647)) (not (< main_~i~1 10)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 10) 1) 4294967296) 2147483647))) (and (= (+ (mod (+ (div v_prenex_550 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_550 10) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_550 10))) (not (< main_~i~1 10)) (< v_prenex_550 0) (<= (mod (div v_prenex_550 10) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_550 10) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_550 10) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_550 10)) (not (< main_~i~1 10)) (<= (mod (div v_prenex_550 10) 4294967296) 2147483647)) (and (not (= 0 (mod v_prenex_550 10))) (= |main_#t~ret4| (mod (+ (div v_prenex_550 10) 1) 4294967296)) (not (< main_~i~1 10)) (<= (mod (+ (div v_prenex_550 10) 1) 4294967296) 2147483647) (< v_prenex_550 0) (<= (mod (div v_prenex_550 10) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_54 10) 4294967296) (- 4294967296))) (not (< v_avg_~ret~0_BEFORE_RETURN_54 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 10) 4294967296) 2147483647)) (not (< main_~i~1 10)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 10) 1) 4294967296) 2147483647))) (and (= (mod (div v_prenex_550 10) 4294967296) |main_#t~ret4|) (not (< v_prenex_550 0)) (not (< main_~i~1 10)) (<= (mod (+ (div v_prenex_550 10) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_550 10) 4294967296) 2147483647)) (and (= (mod (div v_prenex_550 10) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_550 10)) (not (< main_~i~1 10)) (<= (mod (+ (div v_prenex_550 10) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_550 10) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_54 10) 4294967296) (- 4294967296))) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_54 10)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 10) 4294967296) 2147483647)) (not (< main_~i~1 10)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 10) 1) 4294967296) 2147483647))) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_54 10) 4294967296) (- 4294967296))) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_54 10)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 10) 4294967296) 2147483647)) (not (< main_~i~1 10)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 10) 1) 4294967296) 2147483647)) (and (< v_avg_~ret~0_BEFORE_RETURN_54 0) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 10) 1) 4294967296)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_54 10))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 10) 4294967296) 2147483647)) (not (< main_~i~1 10)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 10) 1) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_54 10) 4294967296) (- 4294967296))) (not (< v_avg_~ret~0_BEFORE_RETURN_54 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 10) 4294967296) 2147483647)) (not (< main_~i~1 10)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 10) 1) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_550 10) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_550 10) 4294967296) |main_#t~ret4|) (not (< v_prenex_550 0)) (not (< main_~i~1 10)) (<= (mod (div v_prenex_550 10) 4294967296) 2147483647))))) [2019-10-07 15:25:38,413 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:25:38,414 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:38,414 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 10 avg_~i~0) (<= 0 avg_~i~0) (not (< avg_~i~0 10)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:25:38,414 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:38,414 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:25:38,414 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:25:38,414 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:25:38,415 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:25:38,415 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:25:38,415 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:25:38,415 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:25:38,415 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:40,775 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:40,775 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7, 11] total 28 [2019-10-07 15:25:40,777 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-10-07 15:25:40,777 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-10-07 15:25:40,778 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=637, Unknown=1, NotChecked=0, Total=756 [2019-10-07 15:25:40,778 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 28 states. [2019-10-07 15:25:58,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:58,012 INFO L93 Difference]: Finished difference Result 54 states and 71 transitions. [2019-10-07 15:25:58,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-10-07 15:25:58,015 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 42 [2019-10-07 15:25:58,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:58,016 INFO L225 Difference]: With dead ends: 54 [2019-10-07 15:25:58,016 INFO L226 Difference]: Without dead ends: 36 [2019-10-07 15:25:58,019 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 108 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 578 ImplicationChecksByTransitivity, 9.9s TimeCoverageRelationStatistics Valid=410, Invalid=2136, Unknown=4, NotChecked=0, Total=2550 [2019-10-07 15:25:58,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-07 15:25:58,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-07 15:25:58,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-07 15:25:58,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-07 15:25:58,030 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-07 15:25:58,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:58,031 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-07 15:25:58,031 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-10-07 15:25:58,031 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-07 15:25:58,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-10-07 15:25:58,033 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:58,033 INFO L385 BasicCegarLoop]: trace histogram [30, 6, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:58,237 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:58,238 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:58,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:58,239 INFO L82 PathProgramCache]: Analyzing trace with hash 411616696, now seen corresponding path program 4 times [2019-10-07 15:25:58,239 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:58,239 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:58,239 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:58,240 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:58,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:58,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:58,449 INFO L134 CoverageAnalysis]: Checked inductivity of 556 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 535 trivial. 0 not checked. [2019-10-07 15:25:58,450 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:58,450 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:58,450 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:58,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:58,613 INFO L256 TraceCheckSpWp]: Trace formula consists of 307 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-07 15:25:58,621 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:58,638 INFO L134 CoverageAnalysis]: Checked inductivity of 556 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 535 trivial. 0 not checked. [2019-10-07 15:25:58,638 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:58,700 INFO L134 CoverageAnalysis]: Checked inductivity of 556 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 535 trivial. 0 not checked. [2019-10-07 15:25:58,701 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:58,703 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:58,703 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:58,703 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:58,704 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:58,704 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:58,725 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:33,148 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:26:33,170 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:33,172 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:33,173 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:33,173 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:33,173 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:26:33,173 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:26:33,173 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:26:33,174 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:33,174 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:33,174 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_871 Int)) (or (and (= (mod (+ (div v_prenex_871 10) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_prenex_871 10) 0)) (<= (mod (+ (div v_prenex_871 10) 1) 4294967296) 2147483647) (< v_prenex_871 0) (<= (mod (div v_prenex_871 10) 4294967296) 2147483647) (not (< main_~i~1 10))) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_79 10) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 10) 1) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_79 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 10) 4294967296) 2147483647)) (not (< main_~i~1 10))) (and (= (mod v_prenex_871 10) 0) (not (<= (mod (div v_prenex_871 10) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_871 10) 1) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (div v_prenex_871 10) 4294967296) (- 4294967296))) (not (< main_~i~1 10))) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 10) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_avg_~ret~0_BEFORE_RETURN_79 0) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 10) 4294967296) 2147483647)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_79 10) 0)) (not (< main_~i~1 10))) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 10) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_79 10) 4294967296)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 10) 4294967296) 2147483647) (= (mod v_avg_~ret~0_BEFORE_RETURN_79 10) 0) (not (< main_~i~1 10))) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 10) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_avg_~ret~0_BEFORE_RETURN_79 0) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 10) 4294967296) 2147483647) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_79 10) 0)) (not (< main_~i~1 10))) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 10) 1) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_79 0)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_79 10) 4294967296)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 10) 4294967296) 2147483647) (not (< main_~i~1 10))) (and (= (mod (+ (div v_prenex_871 10) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_prenex_871 10) 0)) (not (<= (mod (div v_prenex_871 10) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_871 10) 1) 4294967296) 2147483647) (< v_prenex_871 0) (not (< main_~i~1 10))) (and (= (mod v_prenex_871 10) 0) (<= (mod (+ (div v_prenex_871 10) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_871 10) 4294967296)) (<= (mod (div v_prenex_871 10) 4294967296) 2147483647) (not (< main_~i~1 10))) (and (not (< v_prenex_871 0)) (<= (mod (+ (div v_prenex_871 10) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_871 10) 4294967296)) (<= (mod (div v_prenex_871 10) 4294967296) 2147483647) (not (< main_~i~1 10))) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_79 10) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 10) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 10) 4294967296) 2147483647)) (= (mod v_avg_~ret~0_BEFORE_RETURN_79 10) 0) (not (< main_~i~1 10))) (and (not (< v_prenex_871 0)) (not (<= (mod (div v_prenex_871 10) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_871 10) 1) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (div v_prenex_871 10) 4294967296) (- 4294967296))) (not (< main_~i~1 10))))) (exists ((v_prenex_872 Int) (v_avg_~ret~0_BEFORE_RETURN_80 Int)) (or (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 10) 1) 4294967296) 2147483647) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 10) 4294967296) 2147483647)) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 10) 1) 4294967296) |main_#t~ret4|) (< v_avg_~ret~0_BEFORE_RETURN_80 0) (not (< main_~i~1 10)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_80 10) 0))) (and (not (= (mod v_prenex_872 10) 0)) (not (<= (mod (+ (div v_prenex_872 10) 1) 4294967296) 2147483647)) (< v_prenex_872 0) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_872 10) 1) 4294967296) (- 4294967296))) (<= (mod (div v_prenex_872 10) 4294967296) 2147483647) (not (< main_~i~1 10))) (and (not (= (mod v_prenex_872 10) 0)) (not (<= (mod (+ (div v_prenex_872 10) 1) 4294967296) 2147483647)) (< v_prenex_872 0) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_872 10) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 10)) (not (<= (mod (div v_prenex_872 10) 4294967296) 2147483647))) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 10) 4294967296) 2147483647) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 10) 1) 4294967296) 2147483647) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10)) (not (< v_avg_~ret~0_BEFORE_RETURN_80 0))) (and (= (mod (div v_prenex_872 10) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_872 10) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_872 10) 4294967296) 2147483647) (not (< main_~i~1 10)) (not (< v_prenex_872 0))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 10) 1) 4294967296) 2147483647) (= (mod v_avg_~ret~0_BEFORE_RETURN_80 10) 0) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 10) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_80 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 10) 4294967296) 2147483647) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 10) 1) 4294967296) 2147483647) (= (mod v_avg_~ret~0_BEFORE_RETURN_80 10) 0) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10))) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 10) 4294967296) 2147483647) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 10) 1) 4294967296) 2147483647) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 10) 1) 4294967296) |main_#t~ret4|) (< v_avg_~ret~0_BEFORE_RETURN_80 0) (not (< main_~i~1 10)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_80 10) 0))) (and (= (+ (mod (div v_prenex_872 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_872 10) 1) 4294967296) 2147483647)) (= (mod v_prenex_872 10) 0) (not (< main_~i~1 10)) (not (<= (mod (div v_prenex_872 10) 4294967296) 2147483647))) (and (= (mod (div v_prenex_872 10) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_872 10) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_872 10) 4294967296) 2147483647) (= (mod v_prenex_872 10) 0) (not (< main_~i~1 10))) (and (= (+ (mod (div v_prenex_872 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_872 10) 1) 4294967296) 2147483647)) (not (< main_~i~1 10)) (not (<= (mod (div v_prenex_872 10) 4294967296) 2147483647)) (not (< v_prenex_872 0))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 10) 1) 4294967296) 2147483647) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 10) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_80 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10)) (not (< v_avg_~ret~0_BEFORE_RETURN_80 0)))))) [2019-10-07 15:26:33,174 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:33,175 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:26:33,175 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 10 avg_~i~0) (<= 0 avg_~i~0) (not (< avg_~i~0 10)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:26:33,175 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:33,175 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:26:33,175 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:26:33,175 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:26:33,176 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:26:33,176 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:26:33,176 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:26:33,176 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:26:33,176 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:35,490 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:35,490 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 11] total 23 [2019-10-07 15:26:35,491 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-10-07 15:26:35,492 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-10-07 15:26:35,493 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=402, Unknown=1, NotChecked=0, Total=506 [2019-10-07 15:26:35,493 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 23 states. [2019-10-07 15:26:50,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:26:50,440 INFO L93 Difference]: Finished difference Result 64 states and 75 transitions. [2019-10-07 15:26:50,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:26:50,441 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 61 [2019-10-07 15:26:50,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:26:50,442 INFO L225 Difference]: With dead ends: 64 [2019-10-07 15:26:50,443 INFO L226 Difference]: Without dead ends: 40 [2019-10-07 15:26:50,444 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 210 GetRequests, 168 SyntacticMatches, 4 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 387 ImplicationChecksByTransitivity, 11.2s TimeCoverageRelationStatistics Valid=282, Invalid=1274, Unknown=4, NotChecked=0, Total=1560 [2019-10-07 15:26:50,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2019-10-07 15:26:50,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2019-10-07 15:26:50,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2019-10-07 15:26:50,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 44 transitions. [2019-10-07 15:26:50,452 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 44 transitions. Word has length 61 [2019-10-07 15:26:50,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:26:50,452 INFO L462 AbstractCegarLoop]: Abstraction has 40 states and 44 transitions. [2019-10-07 15:26:50,453 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-10-07 15:26:50,453 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 44 transitions. [2019-10-07 15:26:50,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-10-07 15:26:50,455 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:26:50,455 INFO L385 BasicCegarLoop]: trace histogram [30, 10, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:26:50,658 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:50,659 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:26:50,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:26:50,660 INFO L82 PathProgramCache]: Analyzing trace with hash 1301603576, now seen corresponding path program 5 times [2019-10-07 15:26:50,660 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:26:50,660 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:50,661 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:50,661 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:50,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:26:50,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:50,770 INFO L134 CoverageAnalysis]: Checked inductivity of 590 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-10-07 15:26:50,771 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:50,771 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:26:50,771 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:50,981 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:26:50,982 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:26:50,983 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:26:51,000 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:26:51,021 INFO L134 CoverageAnalysis]: Checked inductivity of 590 backedges. 246 proven. 1 refuted. 0 times theorem prover too weak. 343 trivial. 0 not checked. [2019-10-07 15:26:51,022 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:26:51,056 INFO L134 CoverageAnalysis]: Checked inductivity of 590 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-10-07 15:26:51,057 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:26:51,060 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:26:51,060 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:26:51,061 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:26:51,061 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:26:51,061 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:26:51,085 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:57,153 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:26:57,179 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:57,181 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:57,182 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:57,182 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:57,182 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:26:57,182 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:26:57,182 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:26:57,183 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:57,183 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:26:57,183 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1205 Int) (v_avg_~ret~0_BEFORE_RETURN_105 Int)) (or (and (< v_prenex_1205 0) (= (+ (mod (+ (div v_prenex_1205 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_1205 10) 1) 4294967296) 2147483647)) (not (= (mod v_prenex_1205 10) 0)) (not (< main_~i~1 10))) (and (= (mod v_avg_~ret~0_BEFORE_RETURN_105 10) 0) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_105 10) 4294967296) 2147483647) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_105 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10))) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_105 10) 4294967296) 2147483647)) (= (mod v_avg_~ret~0_BEFORE_RETURN_105 10) 0) (not (< main_~i~1 10)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_105 10) 4294967296) (- 4294967296)))) (and (<= (mod (+ (div v_prenex_1205 10) 1) 4294967296) 2147483647) (< v_prenex_1205 0) (= (mod (+ (div v_prenex_1205 10) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_prenex_1205 10) 0)) (not (< main_~i~1 10))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_105 0)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_105 10) 4294967296) 2147483647) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_105 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10))) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_105 10) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_105 0)) (not (< main_~i~1 10)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_105 10) 4294967296) (- 4294967296)))))) (exists ((v_prenex_1206 Int) (v_avg_~ret~0_BEFORE_RETURN_106 Int)) (or (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_106 10) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_106 10) 4294967296) 2147483647)) (= (mod v_avg_~ret~0_BEFORE_RETURN_106 10) 0) (not (< main_~i~1 10))) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_106 10) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_106 10) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_106 0)) (not (< main_~i~1 10))) (and (<= (mod (+ (div v_prenex_1206 10) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_1206 10) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_prenex_1206 10) 0)) (not (< main_~i~1 10)) (< v_prenex_1206 0)) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_106 10) 4294967296) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_106 0)) (not (< main_~i~1 10)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_106 10) 4294967296) 2147483647)) (and (not (= (mod v_prenex_1206 10) 0)) (not (<= (mod (+ (div v_prenex_1206 10) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_1206 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10)) (< v_prenex_1206 0)) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_106 10) 4294967296) |main_#t~ret4|) (= (mod v_avg_~ret~0_BEFORE_RETURN_106 10) 0) (not (< main_~i~1 10)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_106 10) 4294967296) 2147483647))))) [2019-10-07 15:26:57,183 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:57,184 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:26:57,184 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 10 avg_~i~0) (<= 0 avg_~i~0) (not (< avg_~i~0 10)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:26:57,184 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:57,184 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:26:57,184 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:26:57,184 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:26:57,185 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:26:57,185 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:26:57,185 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:26:57,185 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:26:57,185 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:59,429 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:59,430 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:26:59,431 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-10-07 15:26:59,431 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-10-07 15:26:59,431 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=225, Unknown=1, NotChecked=0, Total=272 [2019-10-07 15:26:59,431 INFO L87 Difference]: Start difference. First operand 40 states and 44 transitions. Second operand 17 states. [2019-10-07 15:27:44,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:27:44,042 INFO L93 Difference]: Finished difference Result 61 states and 68 transitions. [2019-10-07 15:27:44,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-10-07 15:27:44,045 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 65 [2019-10-07 15:27:44,045 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:27:44,046 INFO L225 Difference]: With dead ends: 61 [2019-10-07 15:27:44,046 INFO L226 Difference]: Without dead ends: 43 [2019-10-07 15:27:44,047 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 210 GetRequests, 184 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 153 ImplicationChecksByTransitivity, 28.6s TimeCoverageRelationStatistics Valid=131, Invalid=611, Unknown=14, NotChecked=0, Total=756 [2019-10-07 15:27:44,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2019-10-07 15:27:44,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2019-10-07 15:27:44,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2019-10-07 15:27:44,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 47 transitions. [2019-10-07 15:27:44,054 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 47 transitions. Word has length 65 [2019-10-07 15:27:44,055 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:27:44,055 INFO L462 AbstractCegarLoop]: Abstraction has 43 states and 47 transitions. [2019-10-07 15:27:44,055 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-10-07 15:27:44,055 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2019-10-07 15:27:44,056 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-10-07 15:27:44,056 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:27:44,057 INFO L385 BasicCegarLoop]: trace histogram [30, 10, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:27:44,267 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:27:44,268 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:27:44,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:27:44,268 INFO L82 PathProgramCache]: Analyzing trace with hash -529281277, now seen corresponding path program 6 times [2019-10-07 15:27:44,269 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:27:44,269 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:27:44,269 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:27:44,269 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:27:44,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:27:44,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:27:44,364 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-10-07 15:27:44,365 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:27:44,365 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:27:44,365 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:27:44,586 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:27:44,587 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:27:44,588 INFO L256 TraceCheckSpWp]: Trace formula consists of 343 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:27:44,589 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:27:44,601 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 246 proven. 10 refuted. 0 times theorem prover too weak. 343 trivial. 0 not checked. [2019-10-07 15:27:44,601 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:27:44,662 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-10-07 15:27:44,662 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:27:44,663 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:27:44,664 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:27:44,664 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:27:44,664 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:27:44,664 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:27:44,695 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:27:50,483 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:27:50,503 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:27:50,506 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:27:50,506 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:27:50,506 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:27:50,507 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:27:50,507 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:27:50,507 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:27:50,507 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:50,508 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:50,508 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1443 Int) (v_avg_~ret~0_BEFORE_RETURN_131 Int)) (or (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_131 10)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 10) 4294967296) 2147483647) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10))) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 10) 4294967296) 2147483647) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 10) 4294967296) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_131 0)) (not (< main_~i~1 10))) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_131 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 10) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_131 0)) (not (< main_~i~1 10))) (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_131 10)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_131 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 10) 4294967296) 2147483647)) (not (< main_~i~1 10))) (and (< v_prenex_1443 0) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1443 10) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_1443 10) 1) 4294967296) 2147483647)) (not (< main_~i~1 10)) (not (= 0 (mod v_prenex_1443 10)))) (and (< v_prenex_1443 0) (= (mod (+ (div v_prenex_1443 10) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1443 10) 1) 4294967296) 2147483647) (not (< main_~i~1 10)) (not (= 0 (mod v_prenex_1443 10)))))) (exists ((v_prenex_1444 Int) (v_avg_~ret~0_BEFORE_RETURN_132 Int)) (or (and (< v_prenex_1444 0) (not (<= (mod (+ (div v_prenex_1444 10) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_1444 10))) (= (+ (mod (+ (div v_prenex_1444 10) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_132 10)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 10) 4294967296) 2147483647) (not (< main_~i~1 10)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 10) 4294967296) |main_#t~ret4|)) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_132 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_132 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 10) 4294967296) 2147483647)) (not (< main_~i~1 10))) (and (< v_prenex_1444 0) (not (= 0 (mod v_prenex_1444 10))) (<= (mod (+ (div v_prenex_1444 10) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_1444 10) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10))) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_132 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_132 10)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 10) 4294967296) 2147483647)) (not (< main_~i~1 10))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_132 0)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 10) 4294967296) 2147483647) (not (< main_~i~1 10)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 10) 4294967296) |main_#t~ret4|))))) [2019-10-07 15:27:50,508 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:50,509 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:27:50,509 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 10 avg_~i~0) (<= 0 avg_~i~0) (not (< avg_~i~0 10)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:27:50,509 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:27:50,509 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:27:50,509 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:27:50,510 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:27:50,510 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:27:50,510 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:27:50,510 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:27:50,510 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:27:50,510 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:27:52,759 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:27:52,760 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 22 [2019-10-07 15:27:52,761 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-07 15:27:52,762 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-07 15:27:52,762 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=370, Unknown=1, NotChecked=0, Total=462 [2019-10-07 15:27:52,762 INFO L87 Difference]: Start difference. First operand 43 states and 47 transitions. Second operand 22 states. [2019-10-07 15:28:54,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:28:54,159 INFO L93 Difference]: Finished difference Result 66 states and 75 transitions. [2019-10-07 15:28:54,161 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-10-07 15:28:54,161 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 68 [2019-10-07 15:28:54,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:28:54,162 INFO L225 Difference]: With dead ends: 66 [2019-10-07 15:28:54,162 INFO L226 Difference]: Without dead ends: 48 [2019-10-07 15:28:54,163 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 227 GetRequests, 190 SyntacticMatches, 1 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 328 ImplicationChecksByTransitivity, 41.4s TimeCoverageRelationStatistics Valid=266, Invalid=1121, Unknown=19, NotChecked=0, Total=1406 [2019-10-07 15:28:54,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2019-10-07 15:28:54,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2019-10-07 15:28:54,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2019-10-07 15:28:54,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 52 transitions. [2019-10-07 15:28:54,171 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 52 transitions. Word has length 68 [2019-10-07 15:28:54,171 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:28:54,171 INFO L462 AbstractCegarLoop]: Abstraction has 48 states and 52 transitions. [2019-10-07 15:28:54,171 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-07 15:28:54,171 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 52 transitions. [2019-10-07 15:28:54,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-10-07 15:28:54,172 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:28:54,173 INFO L385 BasicCegarLoop]: trace histogram [30, 10, 9, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:28:54,373 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:28:54,373 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:28:54,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:28:54,374 INFO L82 PathProgramCache]: Analyzing trace with hash -1377858952, now seen corresponding path program 7 times [2019-10-07 15:28:54,374 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:28:54,374 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:28:54,374 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:28:54,374 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:28:54,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:28:56,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:29:01,769 WARN L191 SmtUtils]: Spent 127.00 ms on a formula simplification. DAG size of input: 98 DAG size of output: 48 [2019-10-07 15:29:03,627 WARN L191 SmtUtils]: Spent 433.00 ms on a formula simplification. DAG size of input: 125 DAG size of output: 33 [2019-10-07 15:29:06,939 WARN L191 SmtUtils]: Spent 2.87 s on a formula simplification. DAG size of input: 147 DAG size of output: 76 [2019-10-07 15:29:09,036 WARN L191 SmtUtils]: Spent 1.62 s on a formula simplification. DAG size of input: 180 DAG size of output: 97 [2019-10-07 15:29:10,686 WARN L191 SmtUtils]: Spent 1.20 s on a formula simplification. DAG size of input: 175 DAG size of output: 87 [2019-10-07 15:29:14,402 WARN L191 SmtUtils]: Spent 2.83 s on a formula simplification. DAG size of input: 181 DAG size of output: 77 [2019-10-07 15:29:16,135 WARN L191 SmtUtils]: Spent 1.47 s on a formula simplification. DAG size of input: 175 DAG size of output: 88 [2019-10-07 15:29:18,541 WARN L191 SmtUtils]: Spent 2.00 s on a formula simplification. DAG size of input: 195 DAG size of output: 87 [2019-10-07 15:29:20,819 WARN L191 SmtUtils]: Spent 1.82 s on a formula simplification. DAG size of input: 199 DAG size of output: 96 [2019-10-07 15:29:22,731 WARN L191 SmtUtils]: Spent 1.48 s on a formula simplification. DAG size of input: 193 DAG size of output: 101 [2019-10-07 15:29:24,415 WARN L191 SmtUtils]: Spent 1.27 s on a formula simplification. DAG size of input: 187 DAG size of output: 93 [2019-10-07 15:29:26,109 WARN L191 SmtUtils]: Spent 1.13 s on a formula simplification. DAG size of input: 189 DAG size of output: 100 [2019-10-07 15:29:28,419 WARN L191 SmtUtils]: Spent 1.85 s on a formula simplification. DAG size of input: 196 DAG size of output: 101 [2019-10-07 15:29:31,464 WARN L191 SmtUtils]: Spent 2.55 s on a formula simplification. DAG size of input: 202 DAG size of output: 114 [2019-10-07 15:29:34,602 WARN L191 SmtUtils]: Spent 2.68 s on a formula simplification. DAG size of input: 191 DAG size of output: 104 [2019-10-07 15:29:36,715 WARN L191 SmtUtils]: Spent 1.61 s on a formula simplification. DAG size of input: 174 DAG size of output: 97 [2019-10-07 15:29:38,184 WARN L191 SmtUtils]: Spent 779.00 ms on a formula simplification. DAG size of input: 157 DAG size of output: 88 [2019-10-07 15:29:39,482 WARN L191 SmtUtils]: Spent 655.00 ms on a formula simplification. DAG size of input: 150 DAG size of output: 81 [2019-10-07 15:29:41,700 WARN L191 SmtUtils]: Spent 813.00 ms on a formula simplification. DAG size of input: 143 DAG size of output: 106 [2019-10-07 15:29:42,070 INFO L134 CoverageAnalysis]: Checked inductivity of 634 backedges. 12 proven. 588 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2019-10-07 15:29:42,071 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:29:42,071 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:29:42,071 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:29:42,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:29:42,495 WARN L254 TraceCheckSpWp]: Trace formula consists of 363 conjuncts, 232 conjunts are in the unsatisfiable core [2019-10-07 15:29:42,500 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:29:52,240 WARN L191 SmtUtils]: Spent 412.00 ms on a formula simplification that was a NOOP. DAG size: 73 [2019-10-07 15:29:53,144 WARN L191 SmtUtils]: Spent 500.00 ms on a formula simplification that was a NOOP. DAG size: 73 [2019-10-07 15:29:57,594 WARN L191 SmtUtils]: Spent 1.61 s on a formula simplification that was a NOOP. DAG size: 104 [2019-10-07 15:30:00,354 WARN L191 SmtUtils]: Spent 2.40 s on a formula simplification that was a NOOP. DAG size: 108 [2019-10-07 15:30:12,856 WARN L176 IndexEqualityManager]: solver failed to check if following not equals relation is implied: (let ((.cse0 (select |v_#memory_int_212| |main_~#x~0.base|))) (= (select .cse0 (+ |main_~#x~0.offset| 8)) (select .cse0 (+ |main_~#x~0.offset| 32)))) [2019-10-07 15:30:16,407 WARN L191 SmtUtils]: Spent 3.43 s on a formula simplification. DAG size of input: 199 DAG size of output: 89 [2019-10-07 15:30:21,221 WARN L191 SmtUtils]: Spent 339.00 ms on a formula simplification that was a NOOP. DAG size: 89 [2019-10-07 15:30:24,088 WARN L191 SmtUtils]: Spent 871.00 ms on a formula simplification that was a NOOP. DAG size: 106 [2019-10-07 15:30:26,402 WARN L191 SmtUtils]: Spent 1.91 s on a formula simplification that was a NOOP. DAG size: 105 [2019-10-07 15:30:31,666 WARN L191 SmtUtils]: Spent 3.85 s on a formula simplification that was a NOOP. DAG size: 101 [2019-10-07 15:30:35,384 WARN L191 SmtUtils]: Spent 3.13 s on a formula simplification that was a NOOP. DAG size: 99 [2019-10-07 15:30:37,831 WARN L191 SmtUtils]: Spent 994.00 ms on a formula simplification that was a NOOP. DAG size: 102 [2019-10-07 15:30:39,309 WARN L191 SmtUtils]: Spent 1.07 s on a formula simplification that was a NOOP. DAG size: 99 [2019-10-07 15:30:44,214 WARN L191 SmtUtils]: Spent 3.55 s on a formula simplification that was a NOOP. DAG size: 101 [2019-10-07 15:30:50,282 WARN L191 SmtUtils]: Spent 5.61 s on a formula simplification that was a NOOP. DAG size: 100 [2019-10-07 15:30:57,304 WARN L191 SmtUtils]: Spent 5.32 s on a formula simplification that was a NOOP. DAG size: 107 [2019-10-07 15:31:03,616 WARN L191 SmtUtils]: Spent 5.79 s on a formula simplification that was a NOOP. DAG size: 105 [2019-10-07 15:31:07,228 WARN L191 SmtUtils]: Spent 2.06 s on a formula simplification that was a NOOP. DAG size: 92 [2019-10-07 15:31:09,310 WARN L191 SmtUtils]: Spent 1.66 s on a formula simplification that was a NOOP. DAG size: 90 [2019-10-07 15:31:17,242 WARN L191 SmtUtils]: Spent 5.99 s on a formula simplification that was a NOOP. DAG size: 104 [2019-10-07 15:31:21,740 WARN L191 SmtUtils]: Spent 3.89 s on a formula simplification that was a NOOP. DAG size: 102 [2019-10-07 15:31:22,944 WARN L191 SmtUtils]: Spent 909.00 ms on a formula simplification that was a NOOP. DAG size: 183 [2019-10-07 15:31:27,071 WARN L191 SmtUtils]: Spent 4.02 s on a formula simplification that was a NOOP. DAG size: 167 [2019-10-07 15:31:30,489 WARN L191 SmtUtils]: Spent 3.32 s on a formula simplification that was a NOOP. DAG size: 146 [2019-10-07 15:31:31,607 WARN L191 SmtUtils]: Spent 1.03 s on a formula simplification that was a NOOP. DAG size: 126 [2019-10-07 15:31:37,182 WARN L191 SmtUtils]: Spent 5.48 s on a formula simplification that was a NOOP. DAG size: 110 [2019-10-07 15:31:37,965 WARN L191 SmtUtils]: Spent 723.00 ms on a formula simplification that was a NOOP. DAG size: 94 [2019-10-07 15:31:42,459 WARN L191 SmtUtils]: Spent 1.71 s on a formula simplification that was a NOOP. DAG size: 94 [2019-10-07 15:31:44,698 WARN L191 SmtUtils]: Spent 350.00 ms on a formula simplification that was a NOOP. DAG size: 89 [2019-10-07 15:31:45,405 WARN L191 SmtUtils]: Spent 208.00 ms on a formula simplification that was a NOOP. DAG size: 87 [2019-10-07 15:31:48,222 WARN L191 SmtUtils]: Spent 1.41 s on a formula simplification. DAG size of input: 478 DAG size of output: 208 [2019-10-07 15:31:48,665 WARN L191 SmtUtils]: Spent 425.00 ms on a formula simplification that was a NOOP. DAG size: 205 [2019-10-07 15:31:49,088 WARN L191 SmtUtils]: Spent 400.00 ms on a formula simplification that was a NOOP. DAG size: 202 [2019-10-07 15:31:49,510 WARN L191 SmtUtils]: Spent 405.00 ms on a formula simplification that was a NOOP. DAG size: 199 [2019-10-07 15:31:49,895 WARN L191 SmtUtils]: Spent 358.00 ms on a formula simplification that was a NOOP. DAG size: 196 [2019-10-07 15:31:50,292 WARN L191 SmtUtils]: Spent 376.00 ms on a formula simplification that was a NOOP. DAG size: 193 [2019-10-07 15:31:50,672 WARN L191 SmtUtils]: Spent 352.00 ms on a formula simplification that was a NOOP. DAG size: 190 [2019-10-07 15:31:51,028 WARN L191 SmtUtils]: Spent 335.00 ms on a formula simplification that was a NOOP. DAG size: 178 [2019-10-07 15:32:12,463 WARN L191 SmtUtils]: Spent 20.50 s on a formula simplification. DAG size of input: 186 DAG size of output: 121 [2019-10-07 15:32:25,449 WARN L191 SmtUtils]: Spent 10.26 s on a formula simplification that was a NOOP. DAG size: 121 [2019-10-07 15:32:25,530 INFO L134 CoverageAnalysis]: Checked inductivity of 634 backedges. 0 proven. 595 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-10-07 15:32:25,531 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:32:25,841 WARN L191 SmtUtils]: Spent 105.00 ms on a formula simplification that was a NOOP. DAG size: 121 [2019-10-07 15:32:26,769 WARN L191 SmtUtils]: Spent 381.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 77 [2019-10-07 15:32:31,415 WARN L191 SmtUtils]: Spent 685.00 ms on a formula simplification. DAG size of input: 154 DAG size of output: 71 [2019-10-07 15:32:32,235 WARN L191 SmtUtils]: Spent 131.00 ms on a formula simplification that was a NOOP. DAG size: 80 [2019-10-07 15:32:35,511 WARN L191 SmtUtils]: Spent 126.00 ms on a formula simplification that was a NOOP. DAG size: 82 [2019-10-07 15:32:36,459 WARN L191 SmtUtils]: Spent 156.00 ms on a formula simplification that was a NOOP. DAG size: 83 [2019-10-07 15:32:37,483 WARN L191 SmtUtils]: Spent 136.00 ms on a formula simplification that was a NOOP. DAG size: 86 [2019-10-07 15:32:39,107 WARN L191 SmtUtils]: Spent 128.00 ms on a formula simplification that was a NOOP. DAG size: 88 [2019-10-07 15:32:40,782 WARN L191 SmtUtils]: Spent 137.00 ms on a formula simplification that was a NOOP. DAG size: 89 [2019-10-07 15:32:42,005 WARN L191 SmtUtils]: Spent 151.00 ms on a formula simplification that was a NOOP. DAG size: 91 [2019-10-07 15:32:45,038 WARN L191 SmtUtils]: Spent 147.00 ms on a formula simplification that was a NOOP. DAG size: 93 [2019-10-07 15:32:45,900 WARN L191 SmtUtils]: Spent 153.00 ms on a formula simplification that was a NOOP. DAG size: 95 [2019-10-07 15:32:49,306 WARN L191 SmtUtils]: Spent 244.00 ms on a formula simplification that was a NOOP. DAG size: 97 [2019-10-07 15:32:50,033 WARN L191 SmtUtils]: Spent 189.00 ms on a formula simplification that was a NOOP. DAG size: 78 [2019-10-07 15:32:53,391 WARN L191 SmtUtils]: Spent 227.00 ms on a formula simplification that was a NOOP. DAG size: 84 [2019-10-07 15:32:54,600 WARN L191 SmtUtils]: Spent 258.00 ms on a formula simplification that was a NOOP. DAG size: 87 [2019-10-07 15:32:55,765 WARN L191 SmtUtils]: Spent 266.00 ms on a formula simplification that was a NOOP. DAG size: 90 [2019-10-07 15:32:57,257 WARN L191 SmtUtils]: Spent 289.00 ms on a formula simplification that was a NOOP. DAG size: 93 [2019-10-07 15:33:00,730 WARN L191 SmtUtils]: Spent 317.00 ms on a formula simplification that was a NOOP. DAG size: 96 [2019-10-07 15:33:04,765 WARN L191 SmtUtils]: Spent 341.00 ms on a formula simplification that was a NOOP. DAG size: 99 [2019-10-07 15:33:09,101 WARN L191 SmtUtils]: Spent 395.00 ms on a formula simplification that was a NOOP. DAG size: 102 [2019-10-07 15:33:13,404 WARN L191 SmtUtils]: Spent 388.00 ms on a formula simplification that was a NOOP. DAG size: 105 [2019-10-07 15:33:18,564 WARN L191 SmtUtils]: Spent 409.00 ms on a formula simplification that was a NOOP. DAG size: 108 [2019-10-07 15:33:19,390 WARN L191 SmtUtils]: Spent 266.00 ms on a formula simplification that was a NOOP. DAG size: 96 [2019-10-07 15:33:19,501 WARN L191 SmtUtils]: Spent 109.00 ms on a formula simplification that was a NOOP. DAG size: 121 [2019-10-07 15:33:20,841 WARN L191 SmtUtils]: Spent 437.00 ms on a formula simplification. DAG size of input: 131 DAG size of output: 98 [2019-10-07 15:33:30,106 WARN L191 SmtUtils]: Spent 125.00 ms on a formula simplification that was a NOOP. DAG size: 99 [2019-10-07 15:33:30,218 WARN L191 SmtUtils]: Spent 109.00 ms on a formula simplification that was a NOOP. DAG size: 121 [2019-10-07 15:33:36,574 INFO L134 CoverageAnalysis]: Checked inductivity of 634 backedges. 0 proven. 540 refuted. 0 times theorem prover too weak. 94 trivial. 0 not checked. [2019-10-07 15:33:36,574 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:33:36,576 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:33:36,576 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:33:36,577 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:33:36,577 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:33:36,577 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:33:36,595 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:33:55,026 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:33:55,049 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:33:55,051 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:33:55,051 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:33:55,051 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:33:55,051 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:33:55,052 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:33:55,052 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:33:55,052 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:33:55,052 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:33:55,052 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_157 Int) (v_prenex_1738 Int)) (or (and (not (<= (mod (+ (div v_prenex_1738 10) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_1738 10) 4294967296) |main_#t~ret4|) (= (mod v_prenex_1738 10) 0) (<= (mod (div v_prenex_1738 10) 4294967296) 2147483647) (not (< main_~i~1 10))) (and (not (<= (mod (+ (div v_prenex_1738 10) 1) 4294967296) 2147483647)) (not (< v_prenex_1738 0)) (= (mod (div v_prenex_1738 10) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_1738 10) 4294967296) 2147483647) (not (< main_~i~1 10))) (and (not (<= (mod (+ (div v_prenex_1738 10) 1) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_1738 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_1738 10) 4294967296) 2147483647)) (= (mod v_prenex_1738 10) 0) (not (< main_~i~1 10))) (and (= (mod v_avg_~ret~0_BEFORE_RETURN_157 10) 0) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 10) 1) 4294967296) 2147483647) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 10) 4294967296) 2147483647) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10))) (and (not (<= (mod (+ (div v_prenex_1738 10) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1738 10) 1) 4294967296) (- 4294967296))) (< v_prenex_1738 0) (<= (mod (div v_prenex_1738 10) 4294967296) 2147483647) (not (= (mod v_prenex_1738 10) 0)) (not (< main_~i~1 10))) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_157 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 10) 1) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_157 0)) (not (< main_~i~1 10)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 10) 4294967296) 2147483647))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 10) 1) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_157 0)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 10) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 10) 4294967296) 2147483647) (not (< main_~i~1 10))) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_157 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_avg_~ret~0_BEFORE_RETURN_157 10) 0) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 10) 1) 4294967296) 2147483647) (not (< main_~i~1 10)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 10) 4294967296) 2147483647))) (and (not (<= (mod (+ (div v_prenex_1738 10) 1) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_1738 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_1738 0)) (not (<= (mod (div v_prenex_1738 10) 4294967296) 2147483647)) (not (< main_~i~1 10))) (and (not (<= (mod (+ (div v_prenex_1738 10) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1738 10) 1) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_1738 10) 4294967296) 2147483647)) (< v_prenex_1738 0) (not (= (mod v_prenex_1738 10) 0)) (not (< main_~i~1 10))) (and (< v_avg_~ret~0_BEFORE_RETURN_157 0) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 10) 1) 4294967296) 2147483647) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_157 10) 0)) (not (< main_~i~1 10)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 10) 4294967296) 2147483647)) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 10) 1) 4294967296) |main_#t~ret4|)) (and (< v_avg_~ret~0_BEFORE_RETURN_157 0) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 10) 1) 4294967296) 2147483647) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_157 10) 0)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 10) 4294967296) 2147483647) (not (< main_~i~1 10)) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 10) 1) 4294967296) |main_#t~ret4|)))) (exists ((v_avg_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1739 Int)) (or (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 10) 4294967296) 2147483647) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 10) 4294967296) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_158 0)) (not (< main_~i~1 10))) (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_158 10)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 10) 4294967296) 2147483647) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 10) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10))) (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_158 10)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 10) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_158 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 10) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_158 0)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_158 10) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10))) (and (= (mod (+ (div v_prenex_1739 10) 1) 4294967296) |main_#t~ret4|) (< v_prenex_1739 0) (<= (mod (+ (div v_prenex_1739 10) 1) 4294967296) 2147483647) (not (= 0 (mod v_prenex_1739 10))) (not (< main_~i~1 10))) (and (not (<= (mod (+ (div v_prenex_1739 10) 1) 4294967296) 2147483647)) (< v_prenex_1739 0) (not (= 0 (mod v_prenex_1739 10))) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1739 10) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 10)))))) [2019-10-07 15:33:55,053 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:33:55,053 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:33:55,053 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 10 avg_~i~0) (<= 0 avg_~i~0) (not (< avg_~i~0 10)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 10) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 10) 1) (div avg_~ret~0 10)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:33:55,053 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:33:55,053 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:33:55,053 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:33:55,053 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:33:55,054 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:33:55,054 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:33:55,054 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:33:55,054 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:33:55,054 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:34:05,088 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:34:05,088 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 41, 30, 11] total 118 [2019-10-07 15:34:05,090 INFO L442 AbstractCegarLoop]: Interpolant automaton has 118 states [2019-10-07 15:34:05,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 118 interpolants. [2019-10-07 15:34:05,095 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=431, Invalid=13365, Unknown=10, NotChecked=0, Total=13806 [2019-10-07 15:34:05,095 INFO L87 Difference]: Start difference. First operand 48 states and 52 transitions. Second operand 118 states. [2019-10-07 15:34:15,567 WARN L191 SmtUtils]: Spent 736.00 ms on a formula simplification. DAG size of input: 126 DAG size of output: 44 [2019-10-07 15:34:21,037 WARN L191 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 106 DAG size of output: 78 [2019-10-07 15:34:33,649 WARN L191 SmtUtils]: Spent 10.21 s on a formula simplification. DAG size of input: 174 DAG size of output: 155 [2019-10-07 15:34:34,962 WARN L191 SmtUtils]: Spent 743.00 ms on a formula simplification. DAG size of input: 126 DAG size of output: 106 [2019-10-07 15:34:43,502 WARN L191 SmtUtils]: Spent 664.00 ms on a formula simplification. DAG size of input: 109 DAG size of output: 97 [2019-10-07 15:34:47,828 WARN L191 SmtUtils]: Spent 1.44 s on a formula simplification. DAG size of input: 217 DAG size of output: 129 [2019-10-07 15:34:58,566 WARN L191 SmtUtils]: Spent 1.29 s on a formula simplification. DAG size of input: 218 DAG size of output: 96 [2019-10-07 15:35:05,399 WARN L191 SmtUtils]: Spent 791.00 ms on a formula simplification. DAG size of input: 181 DAG size of output: 104 [2019-10-07 15:35:13,842 WARN L191 SmtUtils]: Spent 2.54 s on a formula simplification. DAG size of input: 201 DAG size of output: 104 [2019-10-07 15:35:21,442 WARN L191 SmtUtils]: Spent 3.85 s on a formula simplification. DAG size of input: 192 DAG size of output: 127 [2019-10-07 15:35:26,047 WARN L191 SmtUtils]: Spent 923.00 ms on a formula simplification. DAG size of input: 201 DAG size of output: 101 [2019-10-07 15:35:33,924 WARN L191 SmtUtils]: Spent 5.27 s on a formula simplification. DAG size of input: 259 DAG size of output: 164 [2019-10-07 15:35:41,670 WARN L191 SmtUtils]: Spent 2.03 s on a formula simplification. DAG size of input: 282 DAG size of output: 141 [2019-10-07 15:35:45,034 WARN L191 SmtUtils]: Spent 1.78 s on a formula simplification. DAG size of input: 197 DAG size of output: 131 [2019-10-07 15:35:50,216 WARN L191 SmtUtils]: Spent 2.78 s on a formula simplification. DAG size of input: 209 DAG size of output: 142 [2019-10-07 15:36:58,953 WARN L191 SmtUtils]: Spent 58.40 s on a formula simplification. DAG size of input: 701 DAG size of output: 162