java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/avg20-2.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:23:27,033 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:23:27,036 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:23:27,049 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:23:27,049 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:23:27,050 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:23:27,052 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:23:27,054 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:23:27,055 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:23:27,056 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:23:27,057 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:23:27,061 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:23:27,061 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:23:27,062 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:23:27,063 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:23:27,064 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:23:27,066 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:23:27,070 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:23:27,071 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:23:27,073 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:23:27,075 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:23:27,076 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:23:27,077 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:23:27,080 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:23:27,086 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 15:23:27,100 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:23:27,102 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:23:27,105 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:23:27,106 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:23:27,126 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:23:27,126 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:23:27,129 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:23:27,129 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:23:27,129 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:23:27,129 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:23:27,130 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:23:27,130 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:23:27,130 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:23:27,130 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:23:27,131 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:23:27,131 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:23:27,132 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:23:27,132 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:23:27,132 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:23:27,132 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:23:27,133 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:23:27,133 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:23:27,133 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:23:27,133 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:23:27,133 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:23:27,134 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:23:27,134 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:23:27,134 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:23:27,134 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:23:27,134 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:23:27,135 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:23:27,135 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:23:27,135 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:23:27,430 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:23:27,443 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:23:27,446 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:23:27,448 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:23:27,448 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:23:27,449 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/avg20-2.i [2019-10-07 15:23:27,508 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3b6c21a1f/b405d159910b49deb8bd1b34198ad093/FLAGc862116a7 [2019-10-07 15:23:27,979 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:23:27,979 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/avg20-2.i [2019-10-07 15:23:27,985 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3b6c21a1f/b405d159910b49deb8bd1b34198ad093/FLAGc862116a7 [2019-10-07 15:23:28,363 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3b6c21a1f/b405d159910b49deb8bd1b34198ad093 [2019-10-07 15:23:28,373 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:23:28,375 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:23:28,376 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:23:28,376 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:23:28,380 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:23:28,381 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:23:28" (1/1) ... [2019-10-07 15:23:28,384 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@fac7d7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:28, skipping insertion in model container [2019-10-07 15:23:28,384 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:23:28" (1/1) ... [2019-10-07 15:23:28,391 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:23:28,407 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:23:28,593 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:23:28,602 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:23:28,622 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:23:28,634 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:23:28,635 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:28 WrapperNode [2019-10-07 15:23:28,635 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:23:28,636 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:23:28,636 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:23:28,636 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:23:28,729 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:28" (1/1) ... [2019-10-07 15:23:28,729 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:28" (1/1) ... [2019-10-07 15:23:28,739 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:28" (1/1) ... [2019-10-07 15:23:28,741 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:28" (1/1) ... [2019-10-07 15:23:28,762 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:28" (1/1) ... [2019-10-07 15:23:28,766 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:28" (1/1) ... [2019-10-07 15:23:28,768 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:28" (1/1) ... [2019-10-07 15:23:28,770 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:23:28,771 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:23:28,771 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:23:28,771 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:23:28,772 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:28" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:23:28,837 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:23:28,837 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:23:28,837 INFO L138 BoogieDeclarations]: Found implementation of procedure avg [2019-10-07 15:23:28,838 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:23:28,838 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:23:28,838 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:23:28,838 INFO L130 BoogieDeclarations]: Found specification of procedure avg [2019-10-07 15:23:28,838 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:23:28,838 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:23:28,839 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:23:28,839 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:23:28,839 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:23:28,839 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:23:28,839 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:23:29,220 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:23:29,221 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:23:29,222 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:23:29 BoogieIcfgContainer [2019-10-07 15:23:29,222 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:23:29,223 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:23:29,224 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:23:29,226 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:23:29,227 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:23:28" (1/3) ... [2019-10-07 15:23:29,227 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@16c76120 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:23:29, skipping insertion in model container [2019-10-07 15:23:29,228 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:28" (2/3) ... [2019-10-07 15:23:29,229 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@16c76120 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:23:29, skipping insertion in model container [2019-10-07 15:23:29,229 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:23:29" (3/3) ... [2019-10-07 15:23:29,231 INFO L109 eAbstractionObserver]: Analyzing ICFG avg20-2.i [2019-10-07 15:23:29,240 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:23:29,246 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:23:29,257 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:23:29,281 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:23:29,282 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:23:29,282 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:23:29,282 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:23:29,282 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:23:29,282 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:23:29,282 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:23:29,282 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:23:29,299 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:23:29,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:23:29,305 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:29,306 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:29,308 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:29,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:29,312 INFO L82 PathProgramCache]: Analyzing trace with hash 2112018211, now seen corresponding path program 1 times [2019-10-07 15:23:29,319 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:29,319 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:29,319 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:29,319 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:29,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:29,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:29,529 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:23:29,530 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:29,530 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:23:29,531 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:23:29,537 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:29,557 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:29,558 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:29,560 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:23:29,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:29,614 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:23:29,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:29,617 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:23:29,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:29,629 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:23:29,629 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:23:29,638 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:29,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:23:29,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:23:29,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:23:29,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:23:29,697 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:23:29,697 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:29,698 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:23:29,698 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:29,699 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:23:29,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:23:29,702 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:29,702 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:29,702 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:29,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:29,704 INFO L82 PathProgramCache]: Analyzing trace with hash -2049651994, now seen corresponding path program 1 times [2019-10-07 15:23:29,705 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:29,705 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:29,705 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:29,705 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:29,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:29,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:29,850 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:29,851 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:29,853 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:23:29,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:29,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:29,953 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:23:29,963 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:23:29,993 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:29,993 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:23:30,034 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:30,034 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:23:30,034 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:23:30,036 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:30,036 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:30,037 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:23:30,037 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:23:30,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:30,048 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:23:30,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:30,048 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:23:30,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:30,050 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:23:30,050 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:23:30,051 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:23:30,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:23:30,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:23:30,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:23:30,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:23:30,057 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:23:30,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:30,057 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:23:30,057 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:30,058 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:23:30,059 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:23:30,059 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:30,059 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:30,266 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:30,267 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:30,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:30,267 INFO L82 PathProgramCache]: Analyzing trace with hash -575014574, now seen corresponding path program 1 times [2019-10-07 15:23:30,268 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:30,268 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:30,268 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:30,268 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:30,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:30,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:30,351 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:30,352 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:30,352 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:23:30,352 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:23:30,353 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:30,354 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:30,354 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:30,355 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:23:30,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:30,375 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:23:30,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:30,375 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:23:30,378 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:30,379 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:23:30,379 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:23:30,380 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:30,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:23:30,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:23:30,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:23:30,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:23:30,385 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:23:30,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:30,387 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:23:30,387 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:30,387 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:23:30,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:23:30,388 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:30,389 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:30,389 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:30,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:30,389 INFO L82 PathProgramCache]: Analyzing trace with hash -202958309, now seen corresponding path program 1 times [2019-10-07 15:23:30,390 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:30,390 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:30,390 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:30,390 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:30,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:30,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:30,485 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:30,485 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:30,485 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:23:30,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:30,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:30,573 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:23:30,575 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:23:30,588 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:30,588 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:23:30,621 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:30,621 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:23:30,648 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:23:30,648 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:23:30,654 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:23:30,662 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:23:30,663 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:23:30,794 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:23:48,009 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:23:48,061 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:23:48,066 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:23:48,066 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:23:48,066 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:23:48,066 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:23:48,067 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:23:48,067 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:23:48,067 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:23:48,067 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:23:48,068 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_2 Int) (v_prenex_2 Int)) (or (and (= |main_#t~ret4| (mod (div v_prenex_2 20) 4294967296)) (not (< main_~i~1 20)) (not (<= (mod (+ (div v_prenex_2 20) 1) 4294967296) 2147483647)) (= (mod v_prenex_2 20) 0) (<= (mod (div v_prenex_2 20) 4294967296) 2147483647)) (and (= |main_#t~ret4| (mod (div v_prenex_2 20) 4294967296)) (not (< main_~i~1 20)) (not (< v_prenex_2 0)) (not (<= (mod (+ (div v_prenex_2 20) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2 20) 4294967296) 2147483647)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 20) 1) 4294967296) 2147483647) (not (< main_~i~1 20)) (< v_avg_~ret~0_BEFORE_RETURN_2 0) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 20) 1) 4294967296)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 20) 4294967296) 2147483647) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_2 20) 0))) (and (not (< main_~i~1 20)) (not (<= (mod (div v_prenex_2 20) 4294967296) 2147483647)) (not (<= (mod (+ (div v_prenex_2 20) 1) 4294967296) 2147483647)) (= (mod v_prenex_2 20) 0) (= |main_#t~ret4| (+ (mod (div v_prenex_2 20) 4294967296) (- 4294967296)))) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_2 20) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 20) 4294967296) 2147483647)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 20) 1) 4294967296) 2147483647) (not (< main_~i~1 20)) (= (mod v_avg_~ret~0_BEFORE_RETURN_2 20) 0)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 20) 1) 4294967296) 2147483647) (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_2 20) 4294967296)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 20) 4294967296) 2147483647) (= (mod v_avg_~ret~0_BEFORE_RETURN_2 20) 0)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_2 20) 4294967296) (- 4294967296))) (not (< v_avg_~ret~0_BEFORE_RETURN_2 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 20) 4294967296) 2147483647)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 20) 1) 4294967296) 2147483647) (not (< main_~i~1 20))) (and (not (< main_~i~1 20)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2 20) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_2 20) 1) 4294967296) 2147483647)) (< v_prenex_2 0) (not (= (mod v_prenex_2 20) 0)) (<= (mod (div v_prenex_2 20) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (not (<= (mod (div v_prenex_2 20) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2 20) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_2 20) 1) 4294967296) 2147483647)) (< v_prenex_2 0) (not (= (mod v_prenex_2 20) 0))) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 20) 4294967296) 2147483647)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 20) 1) 4294967296) 2147483647) (not (< main_~i~1 20)) (< v_avg_~ret~0_BEFORE_RETURN_2 0) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 20) 1) 4294967296)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_2 20) 0))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_2 0)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 20) 1) 4294967296) 2147483647) (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_2 20) 4294967296)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 20) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (not (< v_prenex_2 0)) (not (<= (mod (div v_prenex_2 20) 4294967296) 2147483647)) (not (<= (mod (+ (div v_prenex_2 20) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_2 20) 4294967296) (- 4294967296)))))) (exists ((v_avg_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (not (< main_~i~1 20)) (= (mod v_prenex_1 20) 0) (<= (mod (div v_prenex_1 20) 4294967296) 2147483647) (= (mod (div v_prenex_1 20) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_1 20) 0)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_1 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_avg_~ret~0_BEFORE_RETURN_1 0) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_1 20) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (not (< v_prenex_1 0)) (<= (mod (div v_prenex_1 20) 4294967296) 2147483647) (= (mod (div v_prenex_1 20) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_1 20) 1) 4294967296) 2147483647) (not (< main_~i~1 20)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_1 20) 0)) (< v_avg_~ret~0_BEFORE_RETURN_1 0) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_1 20) 1) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (div v_prenex_1 20) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_1 20) 4294967296) (- 4294967296))) (not (< main_~i~1 20)) (not (< v_prenex_1 0))) (and (not (<= (mod (div v_prenex_1 20) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_1 20) 4294967296) (- 4294967296))) (not (< main_~i~1 20)) (= (mod v_prenex_1 20) 0))))) [2019-10-07 15:23:48,068 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:23:48,069 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:23:48,069 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 20 avg_~i~0) (= (ite (<= (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) 2147483647) (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (+ (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (- 4294967296))) |avg_#res|) (not (< avg_~i~0 20))) [2019-10-07 15:23:48,070 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:23:48,070 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:23:48,070 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:23:48,070 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:23:48,071 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:23:48,071 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:23:48,071 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:23:48,071 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:23:48,071 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:23:50,320 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:23:50,321 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:23:50,322 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-10-07 15:23:50,322 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-10-07 15:23:50,325 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=225, Unknown=1, NotChecked=0, Total=272 [2019-10-07 15:23:50,325 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 17 states. [2019-10-07 15:24:21,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:21,483 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:24:21,486 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-10-07 15:24:21,486 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 29 [2019-10-07 15:24:21,486 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:21,487 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:24:21,487 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:24:21,488 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 14.6s TimeCoverageRelationStatistics Valid=123, Invalid=626, Unknown=7, NotChecked=0, Total=756 [2019-10-07 15:24:21,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:24:21,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:24:21,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:24:21,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:24:21,500 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:24:21,500 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:21,500 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:24:21,501 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-10-07 15:24:21,501 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:24:21,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:24:21,502 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:21,502 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:21,703 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:21,705 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:21,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:21,706 INFO L82 PathProgramCache]: Analyzing trace with hash -892290920, now seen corresponding path program 2 times [2019-10-07 15:24:21,706 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:21,706 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:21,706 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:21,707 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:21,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:21,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:21,797 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:21,798 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:21,799 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:21,799 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:21,880 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:24:21,880 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:21,884 INFO L256 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:24:21,887 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:21,902 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:21,902 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:21,941 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:21,942 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:21,944 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:21,944 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:21,944 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:21,945 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:21,945 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:21,966 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:28,221 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:24:28,268 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:28,272 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:28,272 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:28,272 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:28,272 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:24:28,273 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:24:28,284 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:24:28,284 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:28,284 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:28,285 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_282 Int) (v_avg_~ret~0_BEFORE_RETURN_28 Int)) (or (and (= |main_#t~ret4| (+ (mod (div v_prenex_282 20) 4294967296) (- 4294967296))) (not (< main_~i~1 20)) (not (< v_prenex_282 0)) (not (<= (mod (div v_prenex_282 20) 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_28 20))) (< v_avg_~ret~0_BEFORE_RETURN_28 0) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 20) 1) 4294967296)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 20) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (= 0 (mod v_prenex_282 20)) (= (mod (div v_prenex_282 20) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_282 20) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_prenex_282 20) 4294967296) (- 4294967296))) (not (< main_~i~1 20)) (not (<= (mod (div v_prenex_282 20) 4294967296) 2147483647)) (= 0 (mod v_prenex_282 20))) (and (not (< main_~i~1 20)) (not (< v_prenex_282 0)) (= (mod (div v_prenex_282 20) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_282 20) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 20) 1) 4294967296) (- 4294967296))) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_28 20))) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 20) 1) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_28 0)))) (exists ((v_avg_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_281 Int)) (or (and (not (< main_~i~1 20)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_27 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_27 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 20) 4294967296) 2147483647))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_27 0)) (not (< main_~i~1 20)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 20) 4294967296) 2147483647) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 20) 4294967296) |main_#t~ret4|)) (and (not (< v_avg_~ret~0_BEFORE_RETURN_27 0)) (not (< main_~i~1 20)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_27 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 20) 4294967296) 2147483647))) (and (< v_prenex_281 0) (not (< main_~i~1 20)) (not (= 0 (mod v_prenex_281 20))) (not (<= (mod (+ (div v_prenex_281 20) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_281 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (< v_prenex_281 0) (= (mod (+ (div v_prenex_281 20) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 20)) (not (= 0 (mod v_prenex_281 20))) (<= (mod (+ (div v_prenex_281 20) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 20) 4294967296) 2147483647) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_27 20)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 20) 4294967296) |main_#t~ret4|))))) [2019-10-07 15:24:28,285 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:24:28,285 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:28,286 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 20 avg_~i~0) (= (ite (<= (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) 2147483647) (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (+ (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (- 4294967296))) |avg_#res|) (not (< avg_~i~0 20))) [2019-10-07 15:24:28,286 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:28,288 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:24:28,288 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:24:28,288 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:24:28,289 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:24:28,289 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:24:28,289 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:24:28,290 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:24:28,290 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:30,721 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:30,722 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:24:30,724 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-10-07 15:24:30,724 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-10-07 15:24:30,725 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=359, Unknown=1, NotChecked=0, Total=420 [2019-10-07 15:24:30,725 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 21 states. [2019-10-07 15:24:49,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:49,519 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:24:49,521 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-10-07 15:24:49,521 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 32 [2019-10-07 15:24:49,521 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:49,522 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:24:49,522 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:24:49,524 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 11.0s TimeCoverageRelationStatistics Valid=200, Invalid=1127, Unknown=5, NotChecked=0, Total=1332 [2019-10-07 15:24:49,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:24:49,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:24:49,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:24:49,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:24:49,531 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:24:49,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:49,531 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:24:49,531 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-10-07 15:24:49,531 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:24:49,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:24:49,533 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:49,533 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:49,735 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:49,736 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:49,736 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:49,737 INFO L82 PathProgramCache]: Analyzing trace with hash -337812683, now seen corresponding path program 3 times [2019-10-07 15:24:49,737 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:49,737 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:49,738 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:49,738 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:49,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:49,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:49,869 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:49,870 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:49,870 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:49,870 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:49,977 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:24:49,978 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:49,979 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:24:49,981 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:49,990 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:49,990 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:50,067 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:50,068 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:50,069 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:50,070 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:50,070 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:50,071 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:50,071 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:50,090 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:02,619 WARN L176 IndexEqualityManager]: solver failed to check if following not equals relation is implied: (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) [2019-10-07 15:25:30,412 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:25:30,438 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:30,440 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:30,441 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:30,441 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:30,441 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:25:30,441 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:25:30,441 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:25:30,442 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:30,442 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:30,442 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_531 Int)) (or (and (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_53 20) 4294967296)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 20) 1) 4294967296) 2147483647)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 20) 4294967296) 2147483647) (= (mod v_avg_~ret~0_BEFORE_RETURN_53 20) 0)) (and (not (< main_~i~1 20)) (<= (mod (+ (div v_prenex_531 20) 1) 4294967296) 2147483647) (= (+ (mod (div v_prenex_531 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_531 20) 4294967296) 2147483647)) (= (mod v_prenex_531 20) 0)) (and (not (< main_~i~1 20)) (<= (mod (+ (div v_prenex_531 20) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_531 20) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_531 20) 4294967296)) (= (mod v_prenex_531 20) 0)) (and (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (+ (div v_prenex_531 20) 1) 4294967296)) (<= (mod (+ (div v_prenex_531 20) 1) 4294967296) 2147483647) (not (= (mod v_prenex_531 20) 0)) (not (<= (mod (div v_prenex_531 20) 4294967296) 2147483647)) (< v_prenex_531 0)) (and (not (< main_~i~1 20)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_53 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 20) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 20) 4294967296) 2147483647)) (= (mod v_avg_~ret~0_BEFORE_RETURN_53 20) 0)) (and (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (+ (div v_prenex_531 20) 1) 4294967296)) (<= (mod (+ (div v_prenex_531 20) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_531 20) 4294967296) 2147483647) (not (= (mod v_prenex_531 20) 0)) (< v_prenex_531 0)) (and (not (= (mod v_avg_~ret~0_BEFORE_RETURN_53 20) 0)) (< v_avg_~ret~0_BEFORE_RETURN_53 0) (not (< main_~i~1 20)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 20) 1) 4294967296) 2147483647)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 20) 4294967296) 2147483647)) (and (not (< v_prenex_531 0)) (not (< main_~i~1 20)) (<= (mod (+ (div v_prenex_531 20) 1) 4294967296) 2147483647) (= (+ (mod (div v_prenex_531 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_531 20) 4294967296) 2147483647))) (and (not (< v_prenex_531 0)) (not (< main_~i~1 20)) (<= (mod (+ (div v_prenex_531 20) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_531 20) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_531 20) 4294967296))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_53 0)) (not (< main_~i~1 20)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_53 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 20) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 20) 4294967296) 2147483647))) (and (not (= (mod v_avg_~ret~0_BEFORE_RETURN_53 20) 0)) (< v_avg_~ret~0_BEFORE_RETURN_53 0) (not (< main_~i~1 20)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 20) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 20) 4294967296) 2147483647))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_53 0)) (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_53 20) 4294967296)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 20) 1) 4294967296) 2147483647)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 20) 4294967296) 2147483647)))) (exists ((v_prenex_532 Int) (v_avg_~ret~0_BEFORE_RETURN_54 Int)) (or (and (not (< main_~i~1 20)) (<= (mod (div v_prenex_532 20) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_532 20) 1) 4294967296) 2147483647)) (= 0 (mod v_prenex_532 20)) (= |main_#t~ret4| (mod (div v_prenex_532 20) 4294967296))) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 20) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_54 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_54 20))) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 20) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 20) 1) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 20)) (<= (mod (div v_prenex_532 20) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_532 20) 4294967296)) (<= (mod (+ (div v_prenex_532 20) 1) 4294967296) 2147483647) (not (< v_prenex_532 0))) (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_54 20)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_54 20) 4294967296) (- 4294967296))) (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 20) 4294967296) 2147483647)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 20) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 20) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_54 0) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 20) 1) 4294967296)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_54 20))) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 20) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (<= (mod (div v_prenex_532 20) 4294967296) 2147483647) (= 0 (mod v_prenex_532 20)) (= |main_#t~ret4| (mod (div v_prenex_532 20) 4294967296)) (<= (mod (+ (div v_prenex_532 20) 1) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (+ (div v_prenex_532 20) 1) 4294967296) (- 4294967296))) (not (= 0 (mod v_prenex_532 20))) (not (< main_~i~1 20)) (<= (mod (div v_prenex_532 20) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_532 20) 1) 4294967296) 2147483647)) (< v_prenex_532 0)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_54 20) 4294967296) (- 4294967296))) (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 20) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_54 0)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 20) 1) 4294967296) 2147483647)) (and (not (= 0 (mod v_prenex_532 20))) (not (< main_~i~1 20)) (<= (mod (div v_prenex_532 20) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_prenex_532 20) 1) 4294967296)) (< v_prenex_532 0) (<= (mod (+ (div v_prenex_532 20) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (<= (mod (div v_prenex_532 20) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_532 20) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (mod (div v_prenex_532 20) 4294967296)) (not (< v_prenex_532 0))) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_54 20) 4294967296) (- 4294967296))) (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 20) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_54 0)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 20) 1) 4294967296) 2147483647))) (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_54 20)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_54 20) 4294967296) (- 4294967296))) (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 20) 4294967296) 2147483647)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 20) 1) 4294967296) 2147483647))))) [2019-10-07 15:25:30,442 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:25:30,443 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:30,443 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 20 avg_~i~0) (= (ite (<= (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) 2147483647) (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (+ (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (- 4294967296))) |avg_#res|) (not (< avg_~i~0 20))) [2019-10-07 15:25:30,443 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:30,443 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:25:30,443 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:25:30,443 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:25:30,443 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:25:30,444 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:25:30,444 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:25:30,444 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:25:30,444 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:32,726 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:32,726 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-07 15:25:32,727 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-10-07 15:25:32,728 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-10-07 15:25:32,729 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=469, Unknown=1, NotChecked=0, Total=600 [2019-10-07 15:25:32,729 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 25 states. [2019-10-07 15:25:56,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:56,058 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-07 15:25:56,060 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-10-07 15:25:56,060 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 42 [2019-10-07 15:25:56,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:56,062 INFO L225 Difference]: With dead ends: 54 [2019-10-07 15:25:56,062 INFO L226 Difference]: Without dead ends: 36 [2019-10-07 15:25:56,064 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 487 ImplicationChecksByTransitivity, 12.9s TimeCoverageRelationStatistics Valid=359, Invalid=1527, Unknown=6, NotChecked=0, Total=1892 [2019-10-07 15:25:56,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-07 15:25:56,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-07 15:25:56,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-07 15:25:56,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-07 15:25:56,071 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-07 15:25:56,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:56,071 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-07 15:25:56,071 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-10-07 15:25:56,072 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-07 15:25:56,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-07 15:25:56,073 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:56,073 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:56,276 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:56,277 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:56,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:56,278 INFO L82 PathProgramCache]: Analyzing trace with hash -1325230312, now seen corresponding path program 4 times [2019-10-07 15:25:56,278 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:56,278 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:56,279 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:56,279 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:56,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:56,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:56,478 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:56,479 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:56,479 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:56,479 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:56,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:56,642 INFO L256 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:25:56,645 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:56,656 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:56,657 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:56,864 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:56,865 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:56,866 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:56,866 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:56,867 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:56,867 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:56,867 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:56,884 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:13,744 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:26:13,764 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:13,767 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:13,767 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:13,767 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:13,767 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:26:13,767 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:26:13,767 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:26:13,768 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:13,768 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:13,768 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_842 Int) (v_avg_~ret~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 20) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_80 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_80 0))) (and (not (< main_~i~1 20)) (not (= (mod v_prenex_842 20) 0)) (< v_prenex_842 0) (= (mod (+ (div v_prenex_842 20) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_842 20) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (not (= (mod v_prenex_842 20) 0)) (< v_prenex_842 0) (not (<= (mod (+ (div v_prenex_842 20) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_842 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 20) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 20) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_80 0))) (and (not (< main_~i~1 20)) (= (mod v_avg_~ret~0_BEFORE_RETURN_80 20) 0) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 20) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_80 20) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (= (mod v_avg_~ret~0_BEFORE_RETURN_80 20) 0) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 20) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_80 20) 4294967296) 2147483647)))) (exists ((v_avg_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_841 Int)) (or (and (not (< main_~i~1 20)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 20) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 20) 4294967296) 2147483647) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_79 20)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 20) 1) 4294967296) 2147483647))) (and (< v_prenex_841 0) (not (< main_~i~1 20)) (not (= 0 (mod v_prenex_841 20))) (<= (mod (div v_prenex_841 20) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_841 20) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_841 20) 1) 4294967296) |main_#t~ret4|)) (and (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 20) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_79 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_79 20))) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 20) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 20) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_79 0)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 20) 1) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_79 20) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (div v_prenex_841 20) 4294967296) 2147483647)) (not (< main_~i~1 20)) (= (+ (mod (div v_prenex_841 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_prenex_841 20) 1) 4294967296) 2147483647) (= 0 (mod v_prenex_841 20))) (and (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 20)) (< v_avg_~ret~0_BEFORE_RETURN_79 0) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 20) 4294967296) 2147483647) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_79 20))) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 20) 1) 4294967296) 2147483647))) (and (< v_prenex_841 0) (not (<= (mod (div v_prenex_841 20) 4294967296) 2147483647)) (not (< main_~i~1 20)) (not (= 0 (mod v_prenex_841 20))) (= (mod (+ (div v_prenex_841 20) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_841 20) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 20) 4294967296) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_79 0)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 20) 4294967296) 2147483647) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 20) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= (mod (div v_prenex_841 20) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_841 20) 4294967296) 2147483647) (not (< v_prenex_841 0)) (<= (mod (+ (div v_prenex_841 20) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 20) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_79 20)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 20) 1) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_79 20) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (div v_prenex_841 20) 4294967296) 2147483647)) (not (< main_~i~1 20)) (= (+ (mod (div v_prenex_841 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_841 0)) (<= (mod (+ (div v_prenex_841 20) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (= (mod (div v_prenex_841 20) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_841 20) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_841 20) 1) 4294967296) 2147483647) (= 0 (mod v_prenex_841 20)))))) [2019-10-07 15:26:13,768 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:13,768 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:26:13,768 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 20 avg_~i~0) (= (ite (<= (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) 2147483647) (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (+ (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (- 4294967296))) |avg_#res|) (not (< avg_~i~0 20))) [2019-10-07 15:26:13,768 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:13,769 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:26:13,769 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:26:13,769 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:26:13,769 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:26:13,769 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:26:13,769 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:26:13,769 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:26:13,769 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:14,089 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:14,090 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 33 [2019-10-07 15:26:14,091 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-10-07 15:26:14,092 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-10-07 15:26:14,092 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=278, Invalid=778, Unknown=0, NotChecked=0, Total=1056 [2019-10-07 15:26:14,093 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 33 states. [2019-10-07 15:26:23,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:26:23,193 INFO L93 Difference]: Finished difference Result 62 states and 77 transitions. [2019-10-07 15:26:23,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-10-07 15:26:23,194 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 49 [2019-10-07 15:26:23,194 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:26:23,195 INFO L225 Difference]: With dead ends: 62 [2019-10-07 15:26:23,195 INFO L226 Difference]: Without dead ends: 44 [2019-10-07 15:26:23,198 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 189 GetRequests, 125 SyntacticMatches, 6 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 892 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=783, Invalid=2755, Unknown=2, NotChecked=0, Total=3540 [2019-10-07 15:26:23,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2019-10-07 15:26:23,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2019-10-07 15:26:23,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2019-10-07 15:26:23,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 48 transitions. [2019-10-07 15:26:23,206 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 48 transitions. Word has length 49 [2019-10-07 15:26:23,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:26:23,206 INFO L462 AbstractCegarLoop]: Abstraction has 44 states and 48 transitions. [2019-10-07 15:26:23,206 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-10-07 15:26:23,206 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 48 transitions. [2019-10-07 15:26:23,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-10-07 15:26:23,208 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:26:23,208 INFO L385 BasicCegarLoop]: trace histogram [20, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:26:23,411 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:23,412 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:26:23,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:26:23,412 INFO L82 PathProgramCache]: Analyzing trace with hash 1737684376, now seen corresponding path program 5 times [2019-10-07 15:26:23,413 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:26:23,413 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:23,413 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:23,413 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:23,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:26:23,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:23,533 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 26 proven. 36 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2019-10-07 15:26:23,533 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:23,533 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:26:23,534 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:23,716 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:26:23,716 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:26:23,717 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:26:23,720 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:26:23,731 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2019-10-07 15:26:23,731 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:26:23,800 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2019-10-07 15:26:23,801 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:26:23,802 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:26:23,802 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:26:23,803 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:26:23,803 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:26:23,803 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:26:23,818 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:40,315 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:26:40,338 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:40,340 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:40,340 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:40,340 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:40,340 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:26:40,340 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:26:40,341 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:26:40,341 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:40,341 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:26:40,341 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_1134 Int)) (or (and (not (< main_~i~1 20)) (< v_prenex_1134 0) (<= (mod (+ (div v_prenex_1134 20) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_1134 20) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_prenex_1134 20)))) (and (not (< main_~i~1 20)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_106 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_106 20) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_106 20) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 20)) (not (< v_avg_~ret~0_BEFORE_RETURN_106 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_106 20) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_106 20) 4294967296) (- 4294967296)))) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_106 20) 4294967296) |main_#t~ret4|) (not (< main_~i~1 20)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_106 20) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_106 0))) (and (not (< main_~i~1 20)) (not (<= (mod (+ (div v_prenex_1134 20) 1) 4294967296) 2147483647)) (< v_prenex_1134 0) (= (+ (mod (+ (div v_prenex_1134 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_prenex_1134 20)))) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_106 20) 4294967296) |main_#t~ret4|) (not (< main_~i~1 20)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_106 20)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_106 20) 4294967296) 2147483647)))) (exists ((v_avg_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_1133 Int)) (or (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_105 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_105 20)) (not (< main_~i~1 20)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 20) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_105 20) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_1133 20) 4294967296) 2147483647) (not (< main_~i~1 20)) (= 0 (mod v_prenex_1133 20)) (not (<= (mod (+ (div v_prenex_1133 20) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (mod (div v_prenex_1133 20) 4294967296))) (and (<= (mod (+ (div v_prenex_1133 20) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1133 20) 4294967296) 2147483647) (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (div v_prenex_1133 20) 4294967296)) (not (< v_prenex_1133 0))) (and (<= (mod (div v_prenex_1133 20) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_1133 20) 1) 4294967296) 2147483647) (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (+ (div v_prenex_1133 20) 1) 4294967296)) (not (= 0 (mod v_prenex_1133 20))) (< v_prenex_1133 0)) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_105 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_105 0)) (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_105 20) 4294967296) 2147483647)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 20) 1) 4294967296) 2147483647)) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_105 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_105 20)) (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_105 20) 4294967296) 2147483647)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 20) 1) 4294967296) 2147483647)) (and (<= (mod (+ (div v_prenex_1133 20) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1133 20) 4294967296) 2147483647) (not (< main_~i~1 20)) (= 0 (mod v_prenex_1133 20)) (= |main_#t~ret4| (mod (div v_prenex_1133 20) 4294967296))) (and (= (+ (mod (+ (div v_prenex_1133 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (div v_prenex_1133 20) 4294967296) 2147483647) (not (< main_~i~1 20)) (not (<= (mod (+ (div v_prenex_1133 20) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_1133 20))) (< v_prenex_1133 0)) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_105 20) 4294967296) 2147483647)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 20) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 20) 1) 4294967296)) (< v_avg_~ret~0_BEFORE_RETURN_105 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_105 20)))) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_105 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_105 0)) (not (< main_~i~1 20)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 20) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_105 20) 4294967296) 2147483647))) (and (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 20)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 20) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_105 20) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_105 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_105 20)))) (and (<= (mod (div v_prenex_1133 20) 4294967296) 2147483647) (not (< main_~i~1 20)) (not (<= (mod (+ (div v_prenex_1133 20) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (mod (div v_prenex_1133 20) 4294967296)) (not (< v_prenex_1133 0)))))) [2019-10-07 15:26:40,341 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:40,342 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:26:40,342 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 20 avg_~i~0) (= (ite (<= (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) 2147483647) (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (+ (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (- 4294967296))) |avg_#res|) (not (< avg_~i~0 20))) [2019-10-07 15:26:40,342 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:40,342 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:26:40,342 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:26:40,342 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:26:40,343 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:26:40,343 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:26:40,343 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:26:40,343 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:26:40,343 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:40,622 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:40,622 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 23 [2019-10-07 15:26:40,623 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-10-07 15:26:40,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-10-07 15:26:40,624 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=104, Invalid=402, Unknown=0, NotChecked=0, Total=506 [2019-10-07 15:26:40,624 INFO L87 Difference]: Start difference. First operand 44 states and 48 transitions. Second operand 23 states. [2019-10-07 15:27:07,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:27:07,522 INFO L93 Difference]: Finished difference Result 67 states and 82 transitions. [2019-10-07 15:27:07,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:27:07,522 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 57 [2019-10-07 15:27:07,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:27:07,524 INFO L225 Difference]: With dead ends: 67 [2019-10-07 15:27:07,524 INFO L226 Difference]: Without dead ends: 50 [2019-10-07 15:27:07,525 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 194 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 370 ImplicationChecksByTransitivity, 12.9s TimeCoverageRelationStatistics Valid=343, Invalid=1211, Unknown=6, NotChecked=0, Total=1560 [2019-10-07 15:27:07,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-07 15:27:07,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-07 15:27:07,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-07 15:27:07,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-07 15:27:07,533 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 57 [2019-10-07 15:27:07,533 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:27:07,533 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-07 15:27:07,533 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-10-07 15:27:07,534 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-07 15:27:07,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-10-07 15:27:07,535 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:27:07,535 INFO L385 BasicCegarLoop]: trace histogram [30, 20, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:27:07,735 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:27:07,736 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:27:07,736 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:27:07,737 INFO L82 PathProgramCache]: Analyzing trace with hash -1147726056, now seen corresponding path program 6 times [2019-10-07 15:27:07,737 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:27:07,737 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:27:07,737 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:27:07,738 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:27:07,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:27:07,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:27:07,837 INFO L134 CoverageAnalysis]: Checked inductivity of 745 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 744 trivial. 0 not checked. [2019-10-07 15:27:07,837 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:27:07,837 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:27:07,837 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:27:08,090 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:27:08,091 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:27:08,092 INFO L256 TraceCheckSpWp]: Trace formula consists of 391 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-07 15:27:08,095 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:27:08,192 INFO L134 CoverageAnalysis]: Checked inductivity of 745 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 446 trivial. 0 not checked. [2019-10-07 15:27:08,193 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:27:08,397 INFO L134 CoverageAnalysis]: Checked inductivity of 745 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 446 trivial. 0 not checked. [2019-10-07 15:27:08,397 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:27:08,399 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:27:08,399 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:27:08,399 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:27:08,400 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:27:08,400 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:27:08,413 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:27:19,852 WARN L160 IndexEqualityManager]: solver failed to check if following equality is implied: (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) [2019-10-07 15:27:26,564 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:27:26,582 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:27:26,585 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:27:26,585 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:27:26,585 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:27:26,585 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:27:26,586 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:27:26,586 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:27:26,586 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:26,586 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:26,587 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_131 Int) (v_prenex_1407 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 20) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_131 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_avg_~ret~0_BEFORE_RETURN_131 20) 0) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_131 20) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= (mod v_prenex_1407 20) 0) (<= (mod (div v_prenex_1407 20) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_1407 20) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_1407 20) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 20) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_131 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_131 0)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_131 20) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (<= (mod (div v_prenex_1407 20) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_1407 20) 1) 4294967296) 2147483647)) (< v_prenex_1407 0) (not (= (mod v_prenex_1407 20) 0)) (= (+ (mod (+ (div v_prenex_1407 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (not (< v_prenex_1407 0)) (<= (mod (div v_prenex_1407 20) 4294967296) 2147483647) (= (mod (div v_prenex_1407 20) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1407 20) 1) 4294967296) 2147483647)) (and (< v_avg_~ret~0_BEFORE_RETURN_131 0) (not (< main_~i~1 20)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_131 20) 1) 4294967296) 2147483647) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 20) 4294967296) 2147483647)) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_131 20) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_131 20) 0))) (and (not (< main_~i~1 20)) (not (< v_prenex_1407 0)) (<= (mod (div v_prenex_1407 20) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_1407 20) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_1407 20) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_131 20) 1) 4294967296) 2147483647) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 20) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_131 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_131 0))) (and (not (< main_~i~1 20)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_131 20) 1) 4294967296) 2147483647) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 20) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_131 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_avg_~ret~0_BEFORE_RETURN_131 20) 0)) (and (< v_avg_~ret~0_BEFORE_RETURN_131 0) (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 20) 4294967296) 2147483647)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_131 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_131 20) 1) 4294967296) 2147483647)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_131 20) 0))) (and (not (< main_~i~1 20)) (<= (mod (div v_prenex_1407 20) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_1407 20) 1) 4294967296) 2147483647) (< v_prenex_1407 0) (not (= (mod v_prenex_1407 20) 0)) (= (mod (+ (div v_prenex_1407 20) 1) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (= (mod v_prenex_1407 20) 0) (<= (mod (div v_prenex_1407 20) 4294967296) 2147483647) (= (mod (div v_prenex_1407 20) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1407 20) 1) 4294967296) 2147483647)))) (exists ((v_avg_~ret~0_BEFORE_RETURN_132 Int) (v_prenex_1408 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod (div v_prenex_1408 20) 4294967296) 2147483647)) (= 0 (mod v_prenex_1408 20)) (= (+ (mod (div v_prenex_1408 20) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_132 20) 1) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_132 20))) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_132 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_avg_~ret~0_BEFORE_RETURN_132 0)) (and (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_132 20) 1) 4294967296)) (not (< main_~i~1 20)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_132 20))) (< v_avg_~ret~0_BEFORE_RETURN_132 0) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_132 20) 1) 4294967296) 2147483647)) (and (not (< v_prenex_1408 0)) (not (< main_~i~1 20)) (not (<= (mod (div v_prenex_1408 20) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_1408 20) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (div v_prenex_1408 20) 4294967296)) (= 0 (mod v_prenex_1408 20)) (<= (mod (div v_prenex_1408 20) 4294967296) 2147483647)) (and (not (< v_prenex_1408 0)) (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (div v_prenex_1408 20) 4294967296)) (<= (mod (div v_prenex_1408 20) 4294967296) 2147483647))))) [2019-10-07 15:27:26,587 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:26,587 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:27:26,587 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 20 avg_~i~0) (= (ite (<= (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) 2147483647) (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (+ (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (- 4294967296))) |avg_#res|) (not (< avg_~i~0 20))) [2019-10-07 15:27:26,587 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:27:26,587 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:27:26,587 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:27:26,588 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:27:26,588 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:27:26,588 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:27:26,588 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:27:26,588 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:27:26,588 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:27:28,943 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:27:28,944 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 13, 13, 11] total 34 [2019-10-07 15:27:28,945 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2019-10-07 15:27:28,946 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-10-07 15:27:28,947 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=261, Invalid=860, Unknown=1, NotChecked=0, Total=1122 [2019-10-07 15:27:28,947 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 34 states. [2019-10-07 15:28:04,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:28:04,890 INFO L93 Difference]: Finished difference Result 84 states and 104 transitions. [2019-10-07 15:28:04,891 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-10-07 15:28:04,892 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 75 [2019-10-07 15:28:04,892 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:28:04,893 INFO L225 Difference]: With dead ends: 84 [2019-10-07 15:28:04,893 INFO L226 Difference]: Without dead ends: 61 [2019-10-07 15:28:04,895 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 258 GetRequests, 195 SyntacticMatches, 2 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 845 ImplicationChecksByTransitivity, 24.0s TimeCoverageRelationStatistics Valid=903, Invalid=2992, Unknown=11, NotChecked=0, Total=3906 [2019-10-07 15:28:04,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2019-10-07 15:28:04,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2019-10-07 15:28:04,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2019-10-07 15:28:04,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 65 transitions. [2019-10-07 15:28:04,904 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 65 transitions. Word has length 75 [2019-10-07 15:28:04,904 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:28:04,904 INFO L462 AbstractCegarLoop]: Abstraction has 61 states and 65 transitions. [2019-10-07 15:28:04,904 INFO L463 AbstractCegarLoop]: Interpolant automaton has 34 states. [2019-10-07 15:28:04,905 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 65 transitions. [2019-10-07 15:28:04,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2019-10-07 15:28:04,906 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:28:04,906 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:28:05,110 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:28:05,111 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:28:05,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:28:05,112 INFO L82 PathProgramCache]: Analyzing trace with hash 1997744899, now seen corresponding path program 7 times [2019-10-07 15:28:05,112 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:28:05,112 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:28:05,112 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:28:05,113 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:28:05,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:28:05,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:28:05,226 INFO L134 CoverageAnalysis]: Checked inductivity of 2172 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:28:05,227 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:28:05,227 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:28:05,227 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:28:05,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:28:05,544 INFO L256 TraceCheckSpWp]: Trace formula consists of 545 conjuncts, 4 conjunts are in the unsatisfiable core [2019-10-07 15:28:05,548 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:28:05,577 INFO L134 CoverageAnalysis]: Checked inductivity of 2172 backedges. 886 proven. 3 refuted. 0 times theorem prover too weak. 1283 trivial. 0 not checked. [2019-10-07 15:28:05,577 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:28:05,616 INFO L134 CoverageAnalysis]: Checked inductivity of 2172 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:28:05,616 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:28:05,621 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:28:05,622 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:28:05,624 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:28:05,624 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:28:05,625 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:28:05,639 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:28:39,632 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:28:39,671 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:28:39,673 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:28:39,674 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:28:39,674 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:28:39,674 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:28:39,674 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:28:39,674 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:28:39,674 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:39,675 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:39,675 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1711 Int) (v_avg_~ret~0_BEFORE_RETURN_157 Int)) (or (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 20) 1) 4294967296) 2147483647) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_157 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 20)) (not (< v_avg_~ret~0_BEFORE_RETURN_157 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 20) 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (<= (mod (div v_prenex_1711 20) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_1711 20) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_1711 20) 4294967296) |main_#t~ret4|) (not (< v_prenex_1711 0))) (and (= (+ (mod (div v_prenex_1711 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 20)) (not (<= (mod (div v_prenex_1711 20) 4294967296) 2147483647)) (not (<= (mod (+ (div v_prenex_1711 20) 1) 4294967296) 2147483647)) (not (< v_prenex_1711 0))) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_157 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 20) 1) 4294967296) 2147483647) (not (< main_~i~1 20)) (= (mod v_avg_~ret~0_BEFORE_RETURN_157 20) 0) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 20) 4294967296) 2147483647))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 20) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_157 0) (not (< main_~i~1 20)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 20) 4294967296) 2147483647) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 20) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_157 20) 0))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 20) 1) 4294967296) 2147483647) (not (< main_~i~1 20)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 20) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_157 0)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 20) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 20) 1) 4294967296) 2147483647) (not (< main_~i~1 20)) (= (mod v_avg_~ret~0_BEFORE_RETURN_157 20) 0) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 20) 4294967296) 2147483647) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 20) 4294967296) |main_#t~ret4|)) (and (= (+ (mod (+ (div v_prenex_1711 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 20)) (< v_prenex_1711 0) (<= (mod (div v_prenex_1711 20) 4294967296) 2147483647) (not (= (mod v_prenex_1711 20) 0)) (not (<= (mod (+ (div v_prenex_1711 20) 1) 4294967296) 2147483647))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 20) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_157 0) (not (< main_~i~1 20)) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 20) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_157 20) 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 20) 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (<= (mod (div v_prenex_1711 20) 4294967296) 2147483647) (= (mod v_prenex_1711 20) 0) (not (<= (mod (+ (div v_prenex_1711 20) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_1711 20) 4294967296) |main_#t~ret4|)) (and (= (+ (mod (+ (div v_prenex_1711 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 20)) (< v_prenex_1711 0) (not (<= (mod (div v_prenex_1711 20) 4294967296) 2147483647)) (not (= (mod v_prenex_1711 20) 0)) (not (<= (mod (+ (div v_prenex_1711 20) 1) 4294967296) 2147483647))) (and (= (+ (mod (div v_prenex_1711 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 20)) (not (<= (mod (div v_prenex_1711 20) 4294967296) 2147483647)) (= (mod v_prenex_1711 20) 0) (not (<= (mod (+ (div v_prenex_1711 20) 1) 4294967296) 2147483647))))) (exists ((v_prenex_1712 Int) (v_avg_~ret~0_BEFORE_RETURN_158 Int)) (or (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 20) 1) 4294967296) 2147483647)) (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 20) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_158 20))) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_avg_~ret~0_BEFORE_RETURN_158 0)) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 20) 1) 4294967296) 2147483647)) (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 20) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_158 20) 4294967296) (- 4294967296))) (not (< v_avg_~ret~0_BEFORE_RETURN_158 0))) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 20) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_158 20)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_158 20) 4294967296) (- 4294967296))) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 20) 1) 4294967296) 2147483647)) (and (= 0 (mod v_prenex_1712 20)) (not (< main_~i~1 20)) (not (<= (mod (+ (div v_prenex_1712 20) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_1712 20) 4294967296) 2147483647) (= (mod (div v_prenex_1712 20) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 20) 1) 4294967296) 2147483647)) (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 20) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_158 20)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_158 20) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 20)) (not (< v_prenex_1712 0)) (<= (mod (+ (div v_prenex_1712 20) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1712 20) 4294967296) 2147483647) (= (mod (div v_prenex_1712 20) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (not (<= (mod (+ (div v_prenex_1712 20) 1) 4294967296) 2147483647)) (not (< v_prenex_1712 0)) (<= (mod (div v_prenex_1712 20) 4294967296) 2147483647) (= (mod (div v_prenex_1712 20) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 20) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_158 20) 4294967296) (- 4294967296))) (not (< v_avg_~ret~0_BEFORE_RETURN_158 0)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 20) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 20) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_158 20))) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 20) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 20) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_158 0)) (and (= 0 (mod v_prenex_1712 20)) (not (< main_~i~1 20)) (<= (mod (+ (div v_prenex_1712 20) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1712 20) 4294967296) 2147483647) (= (mod (div v_prenex_1712 20) 4294967296) |main_#t~ret4|)) (and (= (+ (mod (+ (div v_prenex_1712 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 20)) (not (<= (mod (+ (div v_prenex_1712 20) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_1712 20) 4294967296) 2147483647) (not (= 0 (mod v_prenex_1712 20))) (< v_prenex_1712 0)) (and (not (< main_~i~1 20)) (<= (mod (+ (div v_prenex_1712 20) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1712 20) 4294967296) 2147483647) (not (= 0 (mod v_prenex_1712 20))) (< v_prenex_1712 0) (= (mod (+ (div v_prenex_1712 20) 1) 4294967296) |main_#t~ret4|))))) [2019-10-07 15:28:39,675 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:28:39,675 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:39,675 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 20 avg_~i~0) (= (ite (<= (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) 2147483647) (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (+ (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (- 4294967296))) |avg_#res|) (not (< avg_~i~0 20))) [2019-10-07 15:28:39,676 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:28:39,676 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:28:39,676 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:28:39,676 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:28:39,676 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:28:39,676 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:28:39,677 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:28:39,677 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:28:39,677 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:28:41,861 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:28:41,862 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 11] total 19 [2019-10-07 15:28:41,863 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-10-07 15:28:41,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-10-07 15:28:41,864 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=281, Unknown=0, NotChecked=0, Total=342 [2019-10-07 15:28:41,864 INFO L87 Difference]: Start difference. First operand 61 states and 65 transitions. Second operand 19 states. [2019-10-07 15:29:17,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:29:17,886 INFO L93 Difference]: Finished difference Result 93 states and 101 transitions. [2019-10-07 15:29:17,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-10-07 15:29:17,887 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 106 [2019-10-07 15:29:17,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:29:17,888 INFO L225 Difference]: With dead ends: 93 [2019-10-07 15:29:17,888 INFO L226 Difference]: Without dead ends: 65 [2019-10-07 15:29:17,889 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 336 GetRequests, 306 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 222 ImplicationChecksByTransitivity, 29.6s TimeCoverageRelationStatistics Valid=176, Invalid=803, Unknown=13, NotChecked=0, Total=992 [2019-10-07 15:29:17,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2019-10-07 15:29:17,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 65. [2019-10-07 15:29:17,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65 states. [2019-10-07 15:29:17,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 69 transitions. [2019-10-07 15:29:17,903 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 69 transitions. Word has length 106 [2019-10-07 15:29:17,903 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:29:17,903 INFO L462 AbstractCegarLoop]: Abstraction has 65 states and 69 transitions. [2019-10-07 15:29:17,903 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-10-07 15:29:17,904 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 69 transitions. [2019-10-07 15:29:17,905 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-10-07 15:29:17,905 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:29:17,906 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 6, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:29:18,108 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:29:18,109 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:29:18,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:29:18,110 INFO L82 PathProgramCache]: Analyzing trace with hash 1198325827, now seen corresponding path program 8 times [2019-10-07 15:29:18,110 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:29:18,110 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:29:18,111 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:29:18,111 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:29:18,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:29:18,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:29:18,255 INFO L134 CoverageAnalysis]: Checked inductivity of 2190 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:29:18,255 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:29:18,255 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:29:18,255 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:29:18,575 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-10-07 15:29:18,575 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:29:18,577 INFO L256 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-07 15:29:18,579 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:29:18,604 INFO L134 CoverageAnalysis]: Checked inductivity of 2190 backedges. 886 proven. 21 refuted. 0 times theorem prover too weak. 1283 trivial. 0 not checked. [2019-10-07 15:29:18,605 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:29:18,697 INFO L134 CoverageAnalysis]: Checked inductivity of 2190 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:29:18,697 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:29:18,699 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:29:18,699 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:29:18,699 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:29:18,699 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:29:18,700 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:29:18,714 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:29:24,688 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:29:24,725 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:29:24,727 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:29:24,727 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:29:24,728 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:29:24,728 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:29:24,728 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:29:24,728 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:29:24,728 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:29:24,728 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:29:24,729 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_2057 Int) (v_avg_~ret~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 20)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_183 20)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 20) 4294967296) 2147483647) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 20) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (<= (mod (+ (div v_prenex_2057 20) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_prenex_2057 20) 1) 4294967296)) (not (= 0 (mod v_prenex_2057 20))) (< v_prenex_2057 0)) (and (not (< main_~i~1 20)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_183 20)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_183 20) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 20) 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 20) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_183 0)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 20) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_183 20) 4294967296) (- 4294967296))) (not (< v_avg_~ret~0_BEFORE_RETURN_183 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 20) 4294967296) 2147483647))) (and (not (<= (mod (+ (div v_prenex_2057 20) 1) 4294967296) 2147483647)) (not (< main_~i~1 20)) (not (= 0 (mod v_prenex_2057 20))) (< v_prenex_2057 0) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2057 20) 1) 4294967296) (- 4294967296)))))) (exists ((v_prenex_2058 Int) (v_avg_~ret~0_BEFORE_RETURN_184 Int)) (or (and (not (< main_~i~1 20)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_184 20) 4294967296) 2147483647) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_184 20)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_184 20) 4294967296) |main_#t~ret4|)) (and (not (= 0 (mod v_prenex_2058 20))) (not (< main_~i~1 20)) (<= (mod (+ (div v_prenex_2058 20) 1) 4294967296) 2147483647) (< v_prenex_2058 0) (= (mod (+ (div v_prenex_2058 20) 1) 4294967296) |main_#t~ret4|)) (and (not (= 0 (mod v_prenex_2058 20))) (= (+ (mod (+ (div v_prenex_2058 20) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 20)) (not (<= (mod (+ (div v_prenex_2058 20) 1) 4294967296) 2147483647)) (< v_prenex_2058 0)) (and (not (< main_~i~1 20)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_184 20) 4294967296) 2147483647) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_184 20) 4294967296) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_184 0))) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_184 20) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_184 20) 4294967296) (- 4294967296))) (not (< v_avg_~ret~0_BEFORE_RETURN_184 0))) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_184 20) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_184 20)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_184 20) 4294967296) (- 4294967296))))))) [2019-10-07 15:29:24,729 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:29:24,729 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:29:24,729 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 20 avg_~i~0) (= (ite (<= (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) 2147483647) (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (+ (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (- 4294967296))) |avg_#res|) (not (< avg_~i~0 20))) [2019-10-07 15:29:24,729 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:29:24,729 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:29:24,729 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:29:24,730 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:29:24,730 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:29:24,730 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:29:24,730 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:29:24,730 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:29:24,730 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:29:26,999 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:29:27,000 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 11] total 27 [2019-10-07 15:29:27,001 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2019-10-07 15:29:27,001 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-10-07 15:29:27,002 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=161, Invalid=540, Unknown=1, NotChecked=0, Total=702 [2019-10-07 15:29:27,002 INFO L87 Difference]: Start difference. First operand 65 states and 69 transitions. Second operand 27 states. [2019-10-07 15:30:54,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:30:54,146 INFO L93 Difference]: Finished difference Result 101 states and 113 transitions. [2019-10-07 15:30:54,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-10-07 15:30:54,148 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 110 [2019-10-07 15:30:54,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:30:54,149 INFO L225 Difference]: With dead ends: 101 [2019-10-07 15:30:54,149 INFO L226 Difference]: Without dead ends: 73 [2019-10-07 15:30:54,151 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 360 GetRequests, 314 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 539 ImplicationChecksByTransitivity, 67.1s TimeCoverageRelationStatistics Valid=476, Invalid=1747, Unknown=33, NotChecked=0, Total=2256 [2019-10-07 15:30:54,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2019-10-07 15:30:54,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2019-10-07 15:30:54,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2019-10-07 15:30:54,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 77 transitions. [2019-10-07 15:30:54,164 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 77 transitions. Word has length 110 [2019-10-07 15:30:54,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:30:54,165 INFO L462 AbstractCegarLoop]: Abstraction has 73 states and 77 transitions. [2019-10-07 15:30:54,165 INFO L463 AbstractCegarLoop]: Interpolant automaton has 27 states. [2019-10-07 15:30:54,165 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 77 transitions. [2019-10-07 15:30:54,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2019-10-07 15:30:54,166 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:30:54,166 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 14, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:30:54,371 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:30:54,371 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:30:54,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:30:54,372 INFO L82 PathProgramCache]: Analyzing trace with hash 1764412099, now seen corresponding path program 9 times [2019-10-07 15:30:54,373 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:30:54,373 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:30:54,373 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:30:54,373 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:30:54,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:30:54,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:30:54,666 INFO L134 CoverageAnalysis]: Checked inductivity of 2274 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:30:54,667 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:30:54,667 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:30:54,667 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:30:54,992 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:30:54,992 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:30:54,995 INFO L256 TraceCheckSpWp]: Trace formula consists of 593 conjuncts, 16 conjunts are in the unsatisfiable core [2019-10-07 15:30:55,000 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:30:55,018 INFO L134 CoverageAnalysis]: Checked inductivity of 2274 backedges. 886 proven. 105 refuted. 0 times theorem prover too weak. 1283 trivial. 0 not checked. [2019-10-07 15:30:55,019 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:30:55,250 INFO L134 CoverageAnalysis]: Checked inductivity of 2274 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:30:55,251 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:30:55,255 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:30:55,255 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:30:55,256 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:30:55,256 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:30:55,257 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:30:55,270 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:31:01,245 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:31:01,268 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:31:01,271 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:31:01,271 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:31:01,271 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:31:01,271 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:31:01,272 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:31:01,272 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:31:01,272 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:31:01,272 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:31:01,272 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_2302 Int) (v_avg_~ret~0_BEFORE_RETURN_210 Int)) (or (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_210 20) 4294967296) 2147483647) (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_210 20) 4294967296)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_210 20))) (and (<= (mod (+ (div v_prenex_2302 20) 1) 4294967296) 2147483647) (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (+ (div v_prenex_2302 20) 1) 4294967296)) (< v_prenex_2302 0) (not (= 0 (mod v_prenex_2302 20)))) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_210 20) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_210 20) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_210 20))) (and (not (< main_~i~1 20)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2302 20) 1) 4294967296) (- 4294967296))) (< v_prenex_2302 0) (not (<= (mod (+ (div v_prenex_2302 20) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_2302 20)))) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_210 20) 4294967296) 2147483647) (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_210 20) 4294967296)) (not (< v_avg_~ret~0_BEFORE_RETURN_210 0))) (and (not (< main_~i~1 20)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_210 20) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_210 0)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_210 20) 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_prenex_2301 Int) (v_avg_~ret~0_BEFORE_RETURN_209 Int)) (or (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_209 20) 1) 4294967296) 2147483647)) (not (< main_~i~1 20)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_209 20))) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_209 20) 1) 4294967296) (- 4294967296))) (< v_avg_~ret~0_BEFORE_RETURN_209 0)) (and (not (< v_prenex_2301 0)) (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (div v_prenex_2301 20) 4294967296)) (<= (mod (div v_prenex_2301 20) 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_209 20) 1) 4294967296) 2147483647) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_209 20))) (< v_avg_~ret~0_BEFORE_RETURN_209 0) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_209 20) 1) 4294967296) |main_#t~ret4|)) (and (not (< v_prenex_2301 0)) (not (< main_~i~1 20)) (= |main_#t~ret4| (+ (mod (div v_prenex_2301 20) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_2301 20) 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= 0 (mod v_prenex_2301 20)) (= |main_#t~ret4| (+ (mod (div v_prenex_2301 20) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_2301 20) 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= |main_#t~ret4| (mod (div v_prenex_2301 20) 4294967296)) (= 0 (mod v_prenex_2301 20)) (<= (mod (div v_prenex_2301 20) 4294967296) 2147483647))))) [2019-10-07 15:31:01,273 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:31:01,273 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:31:01,273 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 20 avg_~i~0) (= (ite (<= (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) 2147483647) (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (+ (mod (ite (and (< avg_~ret~0 0) (not (= (mod avg_~ret~0 20) 0))) (+ (div avg_~ret~0 20) 1) (div avg_~ret~0 20)) 4294967296) (- 4294967296))) |avg_#res|) (not (< avg_~i~0 20))) [2019-10-07 15:31:01,273 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:31:01,273 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:31:01,274 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:31:01,274 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:31:01,274 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:31:01,274 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:31:01,274 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:31:01,274 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:31:01,275 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:31:03,642 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:31:03,642 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 11] total 32 [2019-10-07 15:31:03,644 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2019-10-07 15:31:03,644 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2019-10-07 15:31:03,644 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=256, Invalid=735, Unknown=1, NotChecked=0, Total=992 [2019-10-07 15:31:03,645 INFO L87 Difference]: Start difference. First operand 73 states and 77 transitions. Second operand 32 states. [2019-10-07 15:32:47,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:32:47,893 INFO L93 Difference]: Finished difference Result 106 states and 115 transitions. [2019-10-07 15:32:47,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-10-07 15:32:47,895 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 118 [2019-10-07 15:32:47,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:32:47,896 INFO L225 Difference]: With dead ends: 106 [2019-10-07 15:32:47,896 INFO L226 Difference]: Without dead ends: 78 [2019-10-07 15:32:47,898 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 397 GetRequests, 330 SyntacticMatches, 11 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 777 ImplicationChecksByTransitivity, 87.9s TimeCoverageRelationStatistics Valid=761, Invalid=2502, Unknown=43, NotChecked=0, Total=3306 [2019-10-07 15:32:47,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2019-10-07 15:32:47,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 78. [2019-10-07 15:32:47,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2019-10-07 15:32:47,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 82 transitions. [2019-10-07 15:32:47,907 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 82 transitions. Word has length 118 [2019-10-07 15:32:47,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:32:47,908 INFO L462 AbstractCegarLoop]: Abstraction has 78 states and 82 transitions. [2019-10-07 15:32:47,908 INFO L463 AbstractCegarLoop]: Interpolant automaton has 32 states. [2019-10-07 15:32:47,908 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 82 transitions. [2019-10-07 15:32:47,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2019-10-07 15:32:47,910 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:32:47,910 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 19, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:32:48,115 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:32:48,115 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:32:48,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:32:48,116 INFO L82 PathProgramCache]: Analyzing trace with hash -86822408, now seen corresponding path program 10 times [2019-10-07 15:32:48,116 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:32:48,116 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:32:48,117 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:32:48,117 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:32:48,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:32:56,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:33:15,250 WARN L191 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 48 [2019-10-07 15:33:15,576 WARN L191 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 100 DAG size of output: 48 [2019-10-07 15:33:15,785 WARN L191 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 107 DAG size of output: 52 [2019-10-07 15:33:15,988 WARN L191 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 112 DAG size of output: 54 [2019-10-07 15:33:16,235 WARN L191 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 123 DAG size of output: 58 [2019-10-07 15:33:16,481 WARN L191 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 128 DAG size of output: 61 [2019-10-07 15:33:16,746 WARN L191 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 140 DAG size of output: 64 [2019-10-07 15:33:17,054 WARN L191 SmtUtils]: Spent 185.00 ms on a formula simplification. DAG size of input: 145 DAG size of output: 67 [2019-10-07 15:33:17,380 WARN L191 SmtUtils]: Spent 188.00 ms on a formula simplification. DAG size of input: 153 DAG size of output: 71 [2019-10-07 15:33:17,690 WARN L191 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 158 DAG size of output: 72 [2019-10-07 15:33:18,009 WARN L191 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 164 DAG size of output: 76 [2019-10-07 15:33:20,376 WARN L191 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 69 [2019-10-07 15:33:20,653 WARN L191 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 90 DAG size of output: 58 [2019-10-07 15:33:20,952 WARN L191 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 77 [2019-10-07 15:33:21,251 WARN L191 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 64 [2019-10-07 15:33:21,564 WARN L191 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 103 DAG size of output: 67 [2019-10-07 15:33:21,913 WARN L191 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 110 DAG size of output: 88 [2019-10-07 15:33:22,267 WARN L191 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 115 DAG size of output: 93 [2019-10-07 15:33:22,654 WARN L191 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 121 DAG size of output: 97 [2019-10-07 15:33:23,064 WARN L191 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 131 DAG size of output: 101 [2019-10-07 15:33:23,981 WARN L191 SmtUtils]: Spent 414.00 ms on a formula simplification. DAG size of input: 224 DAG size of output: 53 [2019-10-07 15:33:30,602 WARN L191 SmtUtils]: Spent 898.00 ms on a formula simplification. DAG size of input: 236 DAG size of output: 99 [2019-10-07 15:33:59,688 WARN L191 SmtUtils]: Spent 13.28 s on a formula simplification. DAG size of input: 431 DAG size of output: 115 [2019-10-07 15:34:31,960 WARN L191 SmtUtils]: Spent 16.44 s on a formula simplification. DAG size of input: 402 DAG size of output: 117 [2019-10-07 15:34:56,444 WARN L191 SmtUtils]: Spent 8.32 s on a formula simplification. DAG size of input: 222 DAG size of output: 149 [2019-10-07 15:35:04,490 WARN L191 SmtUtils]: Spent 4.04 s on a formula simplification. DAG size of input: 278 DAG size of output: 135 [2019-10-07 15:35:18,914 WARN L191 SmtUtils]: Spent 5.72 s on a formula simplification. DAG size of input: 342 DAG size of output: 113 [2019-10-07 15:35:34,389 WARN L191 SmtUtils]: Spent 12.28 s on a formula simplification. DAG size of input: 400 DAG size of output: 116 [2019-10-07 15:35:47,118 WARN L191 SmtUtils]: Spent 10.92 s on a formula simplification. DAG size of input: 387 DAG size of output: 118 [2019-10-07 15:35:54,347 WARN L191 SmtUtils]: Spent 4.84 s on a formula simplification. DAG size of input: 387 DAG size of output: 117 [2019-10-07 15:36:01,234 WARN L191 SmtUtils]: Spent 4.96 s on a formula simplification. DAG size of input: 375 DAG size of output: 115 [2019-10-07 15:36:13,270 WARN L191 SmtUtils]: Spent 8.57 s on a formula simplification. DAG size of input: 369 DAG size of output: 116 [2019-10-07 15:36:21,555 WARN L191 SmtUtils]: Spent 5.71 s on a formula simplification. DAG size of input: 355 DAG size of output: 114 [2019-10-07 15:36:31,599 WARN L191 SmtUtils]: Spent 6.52 s on a formula simplification. DAG size of input: 352 DAG size of output: 111 [2019-10-07 15:36:40,236 WARN L191 SmtUtils]: Spent 6.77 s on a formula simplification. DAG size of input: 342 DAG size of output: 112 [2019-10-07 15:36:50,150 WARN L191 SmtUtils]: Spent 3.90 s on a formula simplification. DAG size of input: 340 DAG size of output: 112 [2019-10-07 15:36:56,126 WARN L191 SmtUtils]: Spent 3.70 s on a formula simplification. DAG size of input: 329 DAG size of output: 114 [2019-10-07 15:37:05,567 WARN L191 SmtUtils]: Spent 5.65 s on a formula simplification. DAG size of input: 319 DAG size of output: 115 [2019-10-07 15:37:20,050 WARN L191 SmtUtils]: Spent 7.29 s on a formula simplification. DAG size of input: 308 DAG size of output: 114