java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/avg40-2.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:23:29,096 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:23:29,100 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:23:29,118 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:23:29,118 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:23:29,121 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:23:29,122 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:23:29,132 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:23:29,135 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:23:29,137 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:23:29,139 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:23:29,140 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:23:29,141 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:23:29,145 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:23:29,148 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:23:29,149 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:23:29,150 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:23:29,151 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:23:29,154 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:23:29,158 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:23:29,159 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:23:29,161 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:23:29,166 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:23:29,167 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:23:29,169 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 15:23:29,181 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:23:29,184 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:23:29,185 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:23:29,186 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:23:29,223 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:23:29,223 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:23:29,225 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:23:29,225 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:23:29,225 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:23:29,225 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:23:29,226 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:23:29,226 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:23:29,226 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:23:29,226 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:23:29,226 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:23:29,227 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:23:29,227 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:23:29,227 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:23:29,231 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:23:29,232 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:23:29,232 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:23:29,232 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:23:29,232 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:23:29,232 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:23:29,233 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:23:29,233 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:23:29,233 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:23:29,233 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:23:29,233 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:23:29,234 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:23:29,234 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:23:29,236 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:23:29,236 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:23:29,549 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:23:29,562 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:23:29,565 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:23:29,567 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:23:29,567 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:23:29,568 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/avg40-2.i [2019-10-07 15:23:29,632 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3b8411330/daf04183d15d44a0953bcc7ca475344e/FLAGf6db0377e [2019-10-07 15:23:30,070 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:23:30,070 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/avg40-2.i [2019-10-07 15:23:30,078 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3b8411330/daf04183d15d44a0953bcc7ca475344e/FLAGf6db0377e [2019-10-07 15:23:30,444 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3b8411330/daf04183d15d44a0953bcc7ca475344e [2019-10-07 15:23:30,454 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:23:30,455 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:23:30,456 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:23:30,457 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:23:30,460 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:23:30,461 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:23:30" (1/1) ... [2019-10-07 15:23:30,464 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@760969a2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:30, skipping insertion in model container [2019-10-07 15:23:30,464 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:23:30" (1/1) ... [2019-10-07 15:23:30,472 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:23:30,493 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:23:30,699 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:23:30,709 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:23:30,733 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:23:30,749 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:23:30,750 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:30 WrapperNode [2019-10-07 15:23:30,750 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:23:30,751 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:23:30,751 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:23:30,751 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:23:30,845 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:30" (1/1) ... [2019-10-07 15:23:30,845 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:30" (1/1) ... [2019-10-07 15:23:30,852 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:30" (1/1) ... [2019-10-07 15:23:30,852 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:30" (1/1) ... [2019-10-07 15:23:30,860 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:30" (1/1) ... [2019-10-07 15:23:30,866 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:30" (1/1) ... [2019-10-07 15:23:30,868 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:30" (1/1) ... [2019-10-07 15:23:30,870 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:23:30,871 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:23:30,871 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:23:30,871 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:23:30,872 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:30" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:23:30,933 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:23:30,933 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:23:30,933 INFO L138 BoogieDeclarations]: Found implementation of procedure avg [2019-10-07 15:23:30,933 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:23:30,934 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:23:30,934 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:23:30,934 INFO L130 BoogieDeclarations]: Found specification of procedure avg [2019-10-07 15:23:30,934 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:23:30,934 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:23:30,935 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:23:30,935 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:23:30,935 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:23:30,936 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:23:30,937 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:23:31,298 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:23:31,299 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:23:31,300 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:23:31 BoogieIcfgContainer [2019-10-07 15:23:31,300 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:23:31,302 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:23:31,302 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:23:31,305 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:23:31,305 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:23:30" (1/3) ... [2019-10-07 15:23:31,306 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@59ae6f77 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:23:31, skipping insertion in model container [2019-10-07 15:23:31,307 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:30" (2/3) ... [2019-10-07 15:23:31,307 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@59ae6f77 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:23:31, skipping insertion in model container [2019-10-07 15:23:31,307 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:23:31" (3/3) ... [2019-10-07 15:23:31,309 INFO L109 eAbstractionObserver]: Analyzing ICFG avg40-2.i [2019-10-07 15:23:31,322 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:23:31,330 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:23:31,339 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:23:31,363 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:23:31,363 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:23:31,363 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:23:31,363 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:23:31,364 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:23:31,364 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:23:31,364 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:23:31,364 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:23:31,379 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:23:31,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:23:31,384 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:31,385 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:31,387 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:31,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:31,391 INFO L82 PathProgramCache]: Analyzing trace with hash 2112018211, now seen corresponding path program 1 times [2019-10-07 15:23:31,398 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:31,399 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:31,399 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:31,399 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:31,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:31,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:31,602 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:23:31,603 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:31,604 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:23:31,605 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:23:31,609 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:31,626 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:31,627 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:31,630 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:23:31,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:31,681 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:23:31,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:31,687 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:23:31,688 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:31,697 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:23:31,698 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:23:31,704 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:31,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:23:31,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:23:31,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:23:31,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:23:31,762 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:23:31,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:31,764 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:23:31,764 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:31,765 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:23:31,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:23:31,769 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:31,770 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:31,770 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:31,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:31,772 INFO L82 PathProgramCache]: Analyzing trace with hash -2049651994, now seen corresponding path program 1 times [2019-10-07 15:23:31,772 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:31,772 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:31,773 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:31,773 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:31,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:31,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:31,923 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:31,923 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:31,926 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:23:31,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:32,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:32,009 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:23:32,016 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:23:32,056 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:32,057 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:23:32,104 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:32,105 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:23:32,105 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:23:32,106 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:32,107 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:32,107 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:23:32,107 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:23:32,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:32,124 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:23:32,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:32,124 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:23:32,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:32,125 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:23:32,126 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:23:32,127 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:23:32,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:23:32,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:23:32,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:23:32,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:23:32,133 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:23:32,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:32,133 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:23:32,134 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:32,134 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:23:32,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:23:32,135 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:32,135 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:32,344 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:32,345 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:32,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:32,346 INFO L82 PathProgramCache]: Analyzing trace with hash -575014574, now seen corresponding path program 1 times [2019-10-07 15:23:32,347 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:32,347 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:32,348 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:32,348 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:32,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:32,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:32,459 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:32,459 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:32,460 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:23:32,460 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:23:32,460 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:32,461 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:32,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:32,461 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:23:32,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:32,481 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:23:32,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:32,481 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:23:32,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:32,483 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:23:32,483 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:23:32,483 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:32,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:23:32,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:23:32,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:23:32,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:23:32,490 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:23:32,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:32,492 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:23:32,492 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:32,493 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:23:32,494 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:23:32,494 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:32,494 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:32,494 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:32,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:32,495 INFO L82 PathProgramCache]: Analyzing trace with hash -202958309, now seen corresponding path program 1 times [2019-10-07 15:23:32,495 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:32,495 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:32,495 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:32,496 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:32,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:32,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:32,597 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:32,597 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:32,598 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:23:32,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:32,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:32,684 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:23:32,702 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:23:32,718 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:32,719 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:23:32,751 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:32,751 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:23:32,777 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:23:32,777 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:23:32,784 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:23:32,792 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:23:32,793 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:23:32,923 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:23:50,278 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:23:50,325 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:23:50,328 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:23:50,328 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:23:50,329 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:23:50,329 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:23:50,329 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:23:50,329 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:23:50,330 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:23:50,330 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:23:50,330 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:23:50,330 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_2 Int) (v_prenex_2 Int)) (or (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 40) 4294967296) |main_#t~ret4|) (not (< main_~i~1 40)) (= (mod v_avg_~ret~0_BEFORE_RETURN_2 40) 0) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 40) 1) 4294967296) 2147483647) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 40) 4294967296) 2147483647)) (and (not (< v_prenex_2 0)) (<= (mod (div v_prenex_2 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_prenex_2 40) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_2 40) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2 40) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_2 40) 1) 4294967296) 2147483647)) (not (= (mod v_prenex_2 40) 0)) (< v_prenex_2 0) (not (<= (mod (div v_prenex_2 40) 4294967296) 2147483647))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_2 0)) (not (< main_~i~1 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 40) 4294967296) 2147483647)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 40) 1) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_2 40) 4294967296) (- 4294967296)))) (and (<= (mod (div v_prenex_2 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2 40) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_2 40) 1) 4294967296) 2147483647)) (not (= (mod v_prenex_2 40) 0)) (< v_prenex_2 0)) (and (not (< main_~i~1 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 40) 4294967296) 2147483647)) (= (mod v_avg_~ret~0_BEFORE_RETURN_2 40) 0) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 40) 1) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_2 40) 4294967296) (- 4294967296)))) (and (not (= (mod v_avg_~ret~0_BEFORE_RETURN_2 40) 0)) (not (< main_~i~1 40)) (< v_avg_~ret~0_BEFORE_RETURN_2 0) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 40) 1) 4294967296) 2147483647) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 40) 4294967296) 2147483647) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 40) 1) 4294967296) |main_#t~ret4|)) (and (not (= (mod v_avg_~ret~0_BEFORE_RETURN_2 40) 0)) (not (< main_~i~1 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 40) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_2 0) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 40) 1) 4294967296) 2147483647) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 40) 1) 4294967296) |main_#t~ret4|)) (and (<= (mod (div v_prenex_2 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_2 40) 0) (not (<= (mod (+ (div v_prenex_2 40) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_2 40) 4294967296) |main_#t~ret4|)) (and (not (< v_prenex_2 0)) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_prenex_2 40) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_2 40) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_2 40) 4294967296) 2147483647))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_2 0)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 40) 4294967296) |main_#t~ret4|) (not (< main_~i~1 40)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 40) 1) 4294967296) 2147483647) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 40) 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (= (mod v_prenex_2 40) 0) (not (<= (mod (+ (div v_prenex_2 40) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_2 40) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_2 40) 4294967296) 2147483647))))) (exists ((v_avg_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (not (< main_~i~1 40)) (<= (mod (+ (div v_prenex_1 40) 1) 4294967296) 2147483647) (< v_prenex_1 0) (not (= (mod v_prenex_1 40) 0)) (= (mod (+ (div v_prenex_1 40) 1) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (not (<= (mod (+ (div v_prenex_1 40) 1) 4294967296) 2147483647)) (< v_prenex_1 0) (= (+ (mod (+ (div v_prenex_1 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_prenex_1 40) 0))) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_1 40) 4294967296) (- 4294967296))) (= (mod v_avg_~ret~0_BEFORE_RETURN_1 40) 0) (not (< main_~i~1 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 40) 4294967296) 2147483647))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_1 0)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 40) 4294967296) |main_#t~ret4|)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_1 40) 4294967296) (- 4294967296))) (not (< v_avg_~ret~0_BEFORE_RETURN_1 0)) (not (< main_~i~1 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 40) 4294967296) 2147483647))) (and (= (mod v_avg_~ret~0_BEFORE_RETURN_1 40) 0) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 40) 4294967296) |main_#t~ret4|))))) [2019-10-07 15:23:50,330 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:23:50,331 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:23:50,331 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 40 avg_~i~0) (not (< avg_~i~0 40)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:23:50,331 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:23:50,331 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:23:50,331 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:23:50,331 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:23:50,331 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:23:50,332 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:23:50,332 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:23:50,332 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:23:52,586 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:23:52,586 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:23:52,588 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-10-07 15:23:52,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-10-07 15:23:52,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=225, Unknown=1, NotChecked=0, Total=272 [2019-10-07 15:23:52,589 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 17 states. [2019-10-07 15:24:03,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:03,967 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:24:03,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-10-07 15:24:03,969 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 29 [2019-10-07 15:24:03,969 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:03,970 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:24:03,970 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:24:03,971 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 167 ImplicationChecksByTransitivity, 7.3s TimeCoverageRelationStatistics Valid=123, Invalid=630, Unknown=3, NotChecked=0, Total=756 [2019-10-07 15:24:03,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:24:03,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:24:03,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:24:03,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:24:03,979 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:24:03,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:03,979 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:24:03,979 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-10-07 15:24:03,980 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:24:03,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:24:03,981 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:03,981 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:04,184 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:04,188 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:04,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:04,188 INFO L82 PathProgramCache]: Analyzing trace with hash -892290920, now seen corresponding path program 2 times [2019-10-07 15:24:04,189 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:04,189 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:04,189 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:04,189 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:04,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:04,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:04,278 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:04,279 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:04,279 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:04,279 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:04,350 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:24:04,351 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:04,352 INFO L256 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:24:04,354 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:04,374 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:04,375 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:04,407 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:04,408 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:04,409 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:04,409 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:04,410 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:04,410 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:04,411 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:04,432 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:11,808 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:24:11,836 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:11,839 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:11,839 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:11,839 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:11,840 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:24:11,840 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:24:11,840 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:24:11,840 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:24:11,841 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:11,841 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:11,841 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_300 Int) (v_avg_~ret~0_BEFORE_RETURN_28 Int)) (or (and (= (mod (div v_prenex_300 40) 4294967296) |main_#t~ret4|) (not (< main_~i~1 40)) (<= (mod (div v_prenex_300 40) 4294967296) 2147483647) (not (< v_prenex_300 0))) (and (= (mod (div v_prenex_300 40) 4294967296) |main_#t~ret4|) (not (< main_~i~1 40)) (= (mod v_prenex_300 40) 0) (<= (mod (div v_prenex_300 40) 4294967296) 2147483647)) (and (not (<= (mod (div v_prenex_300 40) 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (mod v_prenex_300 40) 0) (= (+ (mod (div v_prenex_300 40) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 40) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 40) 1) 4294967296)) (not (< main_~i~1 40)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_28 40) 0)) (< v_avg_~ret~0_BEFORE_RETURN_28 0)) (and (not (< main_~i~1 40)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 40) 1) 4294967296) 2147483647)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_28 40) 0)) (< v_avg_~ret~0_BEFORE_RETURN_28 0)) (and (not (<= (mod (div v_prenex_300 40) 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod (div v_prenex_300 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_300 0))))) (exists ((v_prenex_299 Int) (v_avg_~ret~0_BEFORE_RETURN_27 Int)) (or (and (not (< main_~i~1 40)) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 40) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 40) 1) 4294967296) 2147483647) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_27 40) 0)) (< v_avg_~ret~0_BEFORE_RETURN_27 0)) (and (not (< main_~i~1 40)) (not (<= (mod (div v_prenex_299 40) 4294967296) 2147483647)) (not (< v_prenex_299 0)) (= (+ (mod (div v_prenex_299 40) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (not (<= (mod (div v_prenex_299 40) 4294967296) 2147483647)) (= (mod v_prenex_299 40) 0) (= (+ (mod (div v_prenex_299 40) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (div v_prenex_299 40) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_299 40) 4294967296)) (not (< main_~i~1 40)) (not (< v_prenex_299 0))) (and (<= (mod (div v_prenex_299 40) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_299 40) 4294967296)) (not (< main_~i~1 40)) (= (mod v_prenex_299 40) 0)) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 40) 1) 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_27 40) 0)) (< v_avg_~ret~0_BEFORE_RETURN_27 0))))) [2019-10-07 15:24:11,841 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:24:11,842 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:11,842 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 40 avg_~i~0) (not (< avg_~i~0 40)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:24:11,842 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:11,842 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:24:11,842 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:24:11,843 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:24:11,843 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:24:11,843 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:24:11,843 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:24:11,843 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:14,146 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:14,146 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:24:14,148 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-10-07 15:24:14,148 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-10-07 15:24:14,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=359, Unknown=1, NotChecked=0, Total=420 [2019-10-07 15:24:14,149 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 21 states. [2019-10-07 15:24:44,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:44,998 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:24:45,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-10-07 15:24:45,000 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 32 [2019-10-07 15:24:45,000 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:45,001 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:24:45,001 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:24:45,002 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 14.8s TimeCoverageRelationStatistics Valid=200, Invalid=1125, Unknown=7, NotChecked=0, Total=1332 [2019-10-07 15:24:45,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:24:45,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:24:45,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:24:45,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:24:45,007 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:24:45,007 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:45,007 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:24:45,007 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-10-07 15:24:45,007 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:24:45,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:24:45,008 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:45,008 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:45,209 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:45,210 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:45,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:45,210 INFO L82 PathProgramCache]: Analyzing trace with hash -337812683, now seen corresponding path program 3 times [2019-10-07 15:24:45,211 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:45,211 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:45,211 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:45,211 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:45,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:45,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:45,312 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:45,312 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:45,312 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:45,312 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:45,443 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:24:45,443 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:45,444 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:24:45,447 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:45,460 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:45,460 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:45,534 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:45,534 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:45,536 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:45,536 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:45,536 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:45,537 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:45,537 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:45,559 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:51,534 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:24:51,573 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:51,575 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:51,575 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:51,575 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:51,575 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:24:51,576 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:24:51,576 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:24:51,576 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:24:51,576 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:51,576 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:51,576 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_520 Int) (v_avg_~ret~0_BEFORE_RETURN_54 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod (+ (div v_prenex_520 40) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_520 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_prenex_520 0) (not (= (mod v_prenex_520 40) 0))) (and (not (< main_~i~1 40)) (< v_prenex_520 0) (not (= (mod v_prenex_520 40) 0)) (= (mod (+ (div v_prenex_520 40) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_520 40) 1) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_54 40) 4294967296) (- 4294967296))) (= (mod v_avg_~ret~0_BEFORE_RETURN_54 40) 0) (not (< main_~i~1 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 40) 4294967296) 2147483647))) (and (= (mod v_avg_~ret~0_BEFORE_RETURN_54 40) 0) (not (< main_~i~1 40)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_54 40) 4294967296)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 40) 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (not (< v_avg_~ret~0_BEFORE_RETURN_54 0)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_54 40) 4294967296)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 40) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_54 40) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (< v_avg_~ret~0_BEFORE_RETURN_54 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_54 40) 4294967296) 2147483647))))) (exists ((v_avg_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_519 Int)) (or (and (not (< main_~i~1 40)) (= (+ (mod (+ (div v_prenex_519 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_prenex_519 0) (not (<= (mod (+ (div v_prenex_519 40) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_519 40)))) (and (not (< main_~i~1 40)) (= (mod (+ (div v_prenex_519 40) 1) 4294967296) |main_#t~ret4|) (< v_prenex_519 0) (not (= 0 (mod v_prenex_519 40))) (<= (mod (+ (div v_prenex_519 40) 1) 4294967296) 2147483647)) (and (not (< v_avg_~ret~0_BEFORE_RETURN_53 0)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_53 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 40) 4294967296) 2147483647))) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_53 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_53 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 40) 4294967296) 2147483647))) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 40) 4294967296) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_53 0)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 40) 4294967296) 2147483647) (not (< main_~i~1 40))) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_53 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_53 40)))))) [2019-10-07 15:24:51,577 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:24:51,577 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:51,577 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 40 avg_~i~0) (not (< avg_~i~0 40)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:24:51,577 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:51,577 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:24:51,577 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:24:51,577 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:24:51,577 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:24:51,578 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:24:51,578 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:24:51,578 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:53,839 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:53,839 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-07 15:24:53,841 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-10-07 15:24:53,841 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-10-07 15:24:53,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=469, Unknown=1, NotChecked=0, Total=600 [2019-10-07 15:24:53,842 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 25 states. [2019-10-07 15:25:21,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:21,019 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-07 15:25:21,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-10-07 15:25:21,021 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 42 [2019-10-07 15:25:21,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:21,022 INFO L225 Difference]: With dead ends: 54 [2019-10-07 15:25:21,022 INFO L226 Difference]: Without dead ends: 36 [2019-10-07 15:25:21,024 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 487 ImplicationChecksByTransitivity, 14.8s TimeCoverageRelationStatistics Valid=359, Invalid=1526, Unknown=7, NotChecked=0, Total=1892 [2019-10-07 15:25:21,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-07 15:25:21,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-07 15:25:21,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-07 15:25:21,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-07 15:25:21,031 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-07 15:25:21,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:21,032 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-07 15:25:21,032 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-10-07 15:25:21,032 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-07 15:25:21,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-07 15:25:21,034 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:21,034 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:21,237 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:21,238 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:21,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:21,238 INFO L82 PathProgramCache]: Analyzing trace with hash -1325230312, now seen corresponding path program 4 times [2019-10-07 15:25:21,239 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:21,239 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:21,239 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:21,239 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:21,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:21,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:21,466 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:21,467 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:21,467 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:21,467 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:21,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:21,620 INFO L256 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:25:21,629 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:21,646 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:21,646 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:21,905 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:21,905 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:21,907 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:21,907 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:21,908 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:21,908 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:21,908 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:21,948 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:27,857 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:25:27,881 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:27,885 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:27,885 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:27,885 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:27,885 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:25:27,886 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:25:27,886 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:25:27,886 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:25:27,886 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:27,887 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:27,887 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_745 Int)) (or (and (not (< main_~i~1 40)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 40) 4294967296) 2147483647) (= (mod v_avg_~ret~0_BEFORE_RETURN_79 40) 0)) (and (not (< main_~i~1 40)) (not (= (mod v_prenex_745 40) 0)) (<= (mod (+ (div v_prenex_745 40) 1) 4294967296) 2147483647) (< v_prenex_745 0) (= |main_#t~ret4| (mod (+ (div v_prenex_745 40) 1) 4294967296))) (and (not (< main_~i~1 40)) (not (< v_avg_~ret~0_BEFORE_RETURN_79 0)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 40) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_79 40) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 40) 4294967296) 2147483647)) (= (mod v_avg_~ret~0_BEFORE_RETURN_79 40) 0)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_79 40) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (< v_avg_~ret~0_BEFORE_RETURN_79 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 40) 4294967296) 2147483647))) (and (not (<= (mod (+ (div v_prenex_745 40) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_745 40) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (= (mod v_prenex_745 40) 0)) (< v_prenex_745 0)))) (exists ((v_avg_~ret~0_BEFORE_RETURN_80 Int) (v_prenex_746 Int)) (or (and (not (< main_~i~1 40)) (not (< v_prenex_746 0)) (= (+ (mod (div v_prenex_746 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_746 40) 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 40) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 40) 1) 4294967296) (- 4294967296))) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_80 40) 0)) (< v_avg_~ret~0_BEFORE_RETURN_80 0)) (and (not (< main_~i~1 40)) (= (+ (mod (div v_prenex_746 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_prenex_746 40) 0) (not (<= (mod (div v_prenex_746 40) 4294967296) 2147483647))) (and (= |main_#t~ret4| (mod (div v_prenex_746 40) 4294967296)) (<= (mod (div v_prenex_746 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_746 40) 0)) (and (= |main_#t~ret4| (mod (div v_prenex_746 40) 4294967296)) (<= (mod (div v_prenex_746 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (not (< v_prenex_746 0))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 40) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_80 40) 0)) (< v_avg_~ret~0_BEFORE_RETURN_80 0))))) [2019-10-07 15:25:27,887 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:27,887 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:25:27,887 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 40 avg_~i~0) (not (< avg_~i~0 40)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:25:27,888 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:27,888 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:25:27,888 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:25:27,888 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:25:27,888 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:25:27,889 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:25:27,889 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:25:27,889 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:30,213 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:30,214 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-07 15:25:30,215 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2019-10-07 15:25:30,216 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-10-07 15:25:30,217 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=431, Invalid=1050, Unknown=1, NotChecked=0, Total=1482 [2019-10-07 15:25:30,217 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 39 states. [2019-10-07 15:25:57,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:57,597 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-07 15:25:57,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-10-07 15:25:57,599 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 49 [2019-10-07 15:25:57,599 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:57,600 INFO L225 Difference]: With dead ends: 68 [2019-10-07 15:25:57,600 INFO L226 Difference]: Without dead ends: 50 [2019-10-07 15:25:57,605 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1243 ImplicationChecksByTransitivity, 15.7s TimeCoverageRelationStatistics Valid=1234, Invalid=3871, Unknown=7, NotChecked=0, Total=5112 [2019-10-07 15:25:57,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-07 15:25:57,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-07 15:25:57,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-07 15:25:57,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-07 15:25:57,614 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-07 15:25:57,614 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:57,614 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-07 15:25:57,614 INFO L463 AbstractCegarLoop]: Interpolant automaton has 39 states. [2019-10-07 15:25:57,614 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-07 15:25:57,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-07 15:25:57,616 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:57,616 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:57,820 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:57,821 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:57,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:57,821 INFO L82 PathProgramCache]: Analyzing trace with hash -2064123784, now seen corresponding path program 5 times [2019-10-07 15:25:57,822 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:57,822 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:57,822 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:57,822 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:57,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:57,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:58,293 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:58,294 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:58,294 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:58,294 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:58,468 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:25:58,469 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:25:58,470 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:25:58,473 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:58,502 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-07 15:25:58,502 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:58,557 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-07 15:25:58,557 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:58,559 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:58,559 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:58,559 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:58,559 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:58,560 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:58,572 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:04,366 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:26:04,388 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:04,389 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:04,390 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:04,390 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:04,390 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:26:04,390 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:26:04,390 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:26:04,390 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:26:04,391 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:04,391 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:26:04,391 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_960 Int)) (or (and (not (<= (mod (div v_prenex_960 40) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_960 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (= 0 (mod v_prenex_960 40))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_106 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_106 40) 1) 4294967296)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_106 40))) (< v_avg_~ret~0_BEFORE_RETURN_106 0)) (and (not (< main_~i~1 40)) (= (mod (div v_prenex_960 40) 4294967296) |main_#t~ret4|) (not (< v_prenex_960 0)) (<= (mod (div v_prenex_960 40) 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (= (mod (div v_prenex_960 40) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_960 40)) (<= (mod (div v_prenex_960 40) 4294967296) 2147483647)) (and (not (<= (mod (div v_prenex_960 40) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_960 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (not (< v_prenex_960 0))) (and (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_106 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_106 40) 1) 4294967296) 2147483647)) (not (< main_~i~1 40)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_106 40))) (< v_avg_~ret~0_BEFORE_RETURN_106 0)))) (exists ((v_avg_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_959 Int)) (or (and (not (<= (mod (div v_prenex_959 40) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_959 40) 4294967296) (- 4294967296))) (= (mod v_prenex_959 40) 0) (not (< main_~i~1 40))) (and (not (= (mod v_avg_~ret~0_BEFORE_RETURN_105 40) 0)) (not (< main_~i~1 40)) (< v_avg_~ret~0_BEFORE_RETURN_105 0) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 40) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 40) 1) 4294967296))) (and (not (= (mod v_avg_~ret~0_BEFORE_RETURN_105 40) 0)) (not (< main_~i~1 40)) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 40) 1) 4294967296) (- 4294967296))) (< v_avg_~ret~0_BEFORE_RETURN_105 0) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 40) 1) 4294967296) 2147483647))) (and (not (<= (mod (div v_prenex_959 40) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_959 40) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (< v_prenex_959 0))) (and (<= (mod (div v_prenex_959 40) 4294967296) 2147483647) (= (mod v_prenex_959 40) 0) (not (< main_~i~1 40)) (= |main_#t~ret4| (mod (div v_prenex_959 40) 4294967296))) (and (<= (mod (div v_prenex_959 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (= |main_#t~ret4| (mod (div v_prenex_959 40) 4294967296)) (not (< v_prenex_959 0)))))) [2019-10-07 15:26:04,391 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:04,392 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:26:04,392 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 40 avg_~i~0) (not (< avg_~i~0 40)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:26:04,392 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:04,392 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:26:04,392 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:26:04,392 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:26:04,392 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:26:04,392 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:26:04,393 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:26:04,393 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:06,779 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:06,779 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-07 15:26:06,780 INFO L442 AbstractCegarLoop]: Interpolant automaton has 43 states [2019-10-07 15:26:06,781 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2019-10-07 15:26:06,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=445, Invalid=1360, Unknown=1, NotChecked=0, Total=1806 [2019-10-07 15:26:06,782 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 43 states. [2019-10-07 15:26:54,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:26:54,859 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-07 15:26:54,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2019-10-07 15:26:54,859 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 63 [2019-10-07 15:26:54,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:26:54,860 INFO L225 Difference]: With dead ends: 72 [2019-10-07 15:26:54,860 INFO L226 Difference]: Without dead ends: 54 [2019-10-07 15:26:54,863 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 177 SyntacticMatches, 0 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1240 ImplicationChecksByTransitivity, 30.2s TimeCoverageRelationStatistics Valid=1339, Invalid=5127, Unknown=14, NotChecked=0, Total=6480 [2019-10-07 15:26:54,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-07 15:26:54,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-07 15:26:54,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-07 15:26:54,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-07 15:26:54,873 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-07 15:26:54,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:26:54,874 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-07 15:26:54,874 INFO L463 AbstractCegarLoop]: Interpolant automaton has 43 states. [2019-10-07 15:26:54,874 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-07 15:26:54,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-07 15:26:54,875 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:26:54,875 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:26:55,078 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:55,079 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:26:55,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:26:55,079 INFO L82 PathProgramCache]: Analyzing trace with hash -1786233658, now seen corresponding path program 6 times [2019-10-07 15:26:55,080 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:26:55,080 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:55,080 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:55,080 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:55,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:26:55,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:55,527 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:26:55,527 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:55,527 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:26:55,527 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:55,750 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:26:55,750 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:26:55,751 INFO L256 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-07 15:26:55,755 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:26:55,774 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:26:55,775 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:26:56,401 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:26:56,401 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:26:56,403 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:26:56,403 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:26:56,403 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:26:56,404 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:26:56,404 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:26:56,424 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:27:02,660 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:27:02,684 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:27:02,686 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:27:02,687 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:27:02,687 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:27:02,687 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:27:02,687 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:27:02,687 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:27:02,688 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:27:02,688 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:02,688 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:02,688 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1186 Int) (v_avg_~ret~0_BEFORE_RETURN_132 Int)) (or (and (not (< main_~i~1 40)) (not (< v_avg_~ret~0_BEFORE_RETURN_132 0)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_132 40) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 40) 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (not (< v_avg_~ret~0_BEFORE_RETURN_132 0)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 40) 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (= (mod v_avg_~ret~0_BEFORE_RETURN_132 40) 0) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_132 40) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 40) 4294967296) 2147483647))) (and (< v_prenex_1186 0) (not (< main_~i~1 40)) (= (mod (+ (div v_prenex_1186 40) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_prenex_1186 40) 0)) (<= (mod (+ (div v_prenex_1186 40) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (= (mod v_avg_~ret~0_BEFORE_RETURN_132 40) 0) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 40) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_1186 40) 1) 4294967296) 2147483647)) (< v_prenex_1186 0) (not (< main_~i~1 40)) (= (+ (mod (+ (div v_prenex_1186 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_prenex_1186 40) 0))))) (exists ((v_prenex_1185 Int) (v_avg_~ret~0_BEFORE_RETURN_131 Int)) (or (and (not (< main_~i~1 40)) (<= (mod (div v_prenex_1185 40) 4294967296) 2147483647) (not (< v_prenex_1185 0)) (= (mod (div v_prenex_1185 40) 4294967296) |main_#t~ret4|)) (and (= 0 (mod v_prenex_1185 40)) (not (< main_~i~1 40)) (<= (mod (div v_prenex_1185 40) 4294967296) 2147483647) (= (mod (div v_prenex_1185 40) 4294967296) |main_#t~ret4|)) (and (< v_avg_~ret~0_BEFORE_RETURN_131 0) (not (< main_~i~1 40)) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_131 40) 1) 4294967296)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_131 40))) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_131 40) 1) 4294967296) 2147483647)) (and (= (+ (mod (div v_prenex_1185 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (not (<= (mod (div v_prenex_1185 40) 4294967296) 2147483647)) (not (< v_prenex_1185 0))) (and (= (+ (mod (div v_prenex_1185 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_prenex_1185 40)) (not (< main_~i~1 40)) (not (<= (mod (div v_prenex_1185 40) 4294967296) 2147483647))) (and (< v_avg_~ret~0_BEFORE_RETURN_131 0) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_131 40) 1) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_131 40))) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_131 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|))))) [2019-10-07 15:27:02,688 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:02,689 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:27:02,689 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 40 avg_~i~0) (not (< avg_~i~0 40)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:27:02,689 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:27:02,689 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:27:02,689 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:27:02,689 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:27:02,689 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:27:02,690 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:27:02,690 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:27:02,690 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:27:05,106 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:27:05,107 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 53 [2019-10-07 15:27:05,108 INFO L442 AbstractCegarLoop]: Interpolant automaton has 53 states [2019-10-07 15:27:05,108 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2019-10-07 15:27:05,109 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=928, Invalid=1827, Unknown=1, NotChecked=0, Total=2756 [2019-10-07 15:27:05,110 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 53 states. [2019-10-07 15:27:35,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:27:35,383 INFO L93 Difference]: Finished difference Result 88 states and 108 transitions. [2019-10-07 15:27:35,385 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2019-10-07 15:27:35,385 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 67 [2019-10-07 15:27:35,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:27:35,386 INFO L225 Difference]: With dead ends: 88 [2019-10-07 15:27:35,386 INFO L226 Difference]: Without dead ends: 67 [2019-10-07 15:27:35,390 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 279 GetRequests, 165 SyntacticMatches, 16 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2336 ImplicationChecksByTransitivity, 17.8s TimeCoverageRelationStatistics Valid=2697, Invalid=7196, Unknown=7, NotChecked=0, Total=9900 [2019-10-07 15:27:35,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2019-10-07 15:27:35,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2019-10-07 15:27:35,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2019-10-07 15:27:35,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 71 transitions. [2019-10-07 15:27:35,406 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 71 transitions. Word has length 67 [2019-10-07 15:27:35,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:27:35,406 INFO L462 AbstractCegarLoop]: Abstraction has 67 states and 71 transitions. [2019-10-07 15:27:35,406 INFO L463 AbstractCegarLoop]: Interpolant automaton has 53 states. [2019-10-07 15:27:35,406 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 71 transitions. [2019-10-07 15:27:35,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2019-10-07 15:27:35,408 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:27:35,408 INFO L385 BasicCegarLoop]: trace histogram [40, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:27:35,608 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:27:35,609 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:27:35,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:27:35,610 INFO L82 PathProgramCache]: Analyzing trace with hash 1072445283, now seen corresponding path program 7 times [2019-10-07 15:27:35,610 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:27:35,610 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:27:35,611 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:27:35,611 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:27:35,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:27:35,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:27:35,730 INFO L134 CoverageAnalysis]: Checked inductivity of 941 backedges. 26 proven. 36 refuted. 0 times theorem prover too weak. 879 trivial. 0 not checked. [2019-10-07 15:27:35,731 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:27:35,731 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:27:35,731 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:27:35,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:27:35,964 INFO L256 TraceCheckSpWp]: Trace formula consists of 433 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:27:35,976 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:27:35,986 INFO L134 CoverageAnalysis]: Checked inductivity of 941 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 879 trivial. 0 not checked. [2019-10-07 15:27:35,987 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:27:36,075 INFO L134 CoverageAnalysis]: Checked inductivity of 941 backedges. 0 proven. 62 refuted. 0 times theorem prover too weak. 879 trivial. 0 not checked. [2019-10-07 15:27:36,075 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:27:36,079 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:27:36,079 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:27:36,080 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:27:36,080 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:27:36,080 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:27:36,099 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:28:09,079 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:28:09,106 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:28:09,108 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:28:09,109 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:28:09,109 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:28:09,109 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:28:09,109 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:28:09,109 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:28:09,110 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:28:09,110 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:09,110 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:09,111 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1436 Int) (v_avg_~ret~0_BEFORE_RETURN_158 Int)) (or (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_158 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 40) 1) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_158 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 40) 4294967296) 2147483647))) (and (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 40) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 40)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 40) 1) 4294967296) 2147483647) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_158 40))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 40) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_158 0)) (and (<= (mod (div v_prenex_1436 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (not (< v_prenex_1436 0)) (<= (mod (+ (div v_prenex_1436 40) 1) 4294967296) 2147483647) (= (mod (div v_prenex_1436 40) 4294967296) |main_#t~ret4|)) (and (<= (mod (div v_prenex_1436 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_prenex_1436 40) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_1436 40) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_1436 40))) (and (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1436 40) 1) 4294967296) (- 4294967296))) (<= (mod (div v_prenex_1436 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_prenex_1436 40) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_1436 40))) (< v_prenex_1436 0)) (and (<= (mod (div v_prenex_1436 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (not (< v_prenex_1436 0)) (not (<= (mod (+ (div v_prenex_1436 40) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_1436 40) 4294967296) |main_#t~ret4|)) (and (<= (mod (div v_prenex_1436 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (<= (mod (+ (div v_prenex_1436 40) 1) 4294967296) 2147483647) (= (mod (div v_prenex_1436 40) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_1436 40))) (and (<= (mod (div v_prenex_1436 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod (+ (div v_prenex_1436 40) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1436 40) 1) 4294967296) 2147483647) (not (= 0 (mod v_prenex_1436 40))) (< v_prenex_1436 0)) (and (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 40) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 40) 1) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_158 40))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 40) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_158 0)) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_158 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 40) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 40) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_158 40))) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_158 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 40) 1) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_158 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 40) 4294967296) 2147483647))) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_158 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 40) 1) 4294967296) 2147483647) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_158 40) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_158 40))))) (exists ((v_prenex_1435 Int) (v_avg_~ret~0_BEFORE_RETURN_157 Int)) (or (and (<= (mod (div v_prenex_1435 40) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_1435 40) 1) 4294967296) 2147483647)) (not (< main_~i~1 40)) (= 0 (mod v_prenex_1435 40)) (= (mod (div v_prenex_1435 40) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 40) 1) 4294967296) 2147483647)) (not (< main_~i~1 40)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_157 40) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 40) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_157 40))) (and (<= (mod (div v_prenex_1435 40) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_1435 40) 1) 4294967296) 2147483647)) (not (< main_~i~1 40)) (not (< v_prenex_1435 0)) (= (mod (div v_prenex_1435 40) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (not (< v_avg_~ret~0_BEFORE_RETURN_157 0)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_157 40) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 40) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_1435 40) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_1435 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (not (< v_prenex_1435 0)) (= (mod (div v_prenex_1435 40) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_157 40) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 40) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_157 40))) (and (<= (mod (div v_prenex_1435 40) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_1435 40) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_prenex_1435 40) 1) 4294967296)) (not (< main_~i~1 40)) (< v_prenex_1435 0) (not (= 0 (mod v_prenex_1435 40)))) (and (< v_avg_~ret~0_BEFORE_RETURN_157 0) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 40) 1) 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 40) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_157 40)))) (and (<= (mod (div v_prenex_1435 40) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_1435 40) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_1435 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (< v_prenex_1435 0) (not (= 0 (mod v_prenex_1435 40)))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 40) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_157 0) (not (< main_~i~1 40)) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 40) 1) 4294967296)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 40) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_157 40)))) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_157 40) 1) 4294967296) 2147483647)) (not (< main_~i~1 40)) (not (< v_avg_~ret~0_BEFORE_RETURN_157 0)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_157 40) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 40) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_1435 40) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_1435 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (= 0 (mod v_prenex_1435 40)) (= (mod (div v_prenex_1435 40) 4294967296) |main_#t~ret4|))))) [2019-10-07 15:28:09,111 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:09,111 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:28:09,111 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 40 avg_~i~0) (not (< avg_~i~0 40)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:28:09,112 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:28:09,112 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:28:09,112 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:28:09,112 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:28:09,112 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:28:09,112 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:28:09,113 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:28:09,113 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:28:09,431 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:28:09,431 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 23 [2019-10-07 15:28:09,432 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-10-07 15:28:09,433 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-10-07 15:28:09,433 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=104, Invalid=402, Unknown=0, NotChecked=0, Total=506 [2019-10-07 15:28:09,433 INFO L87 Difference]: Start difference. First operand 67 states and 71 transitions. Second operand 23 states. [2019-10-07 15:28:26,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:28:26,309 INFO L93 Difference]: Finished difference Result 93 states and 108 transitions. [2019-10-07 15:28:26,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:28:26,310 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 80 [2019-10-07 15:28:26,310 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:28:26,311 INFO L225 Difference]: With dead ends: 93 [2019-10-07 15:28:26,311 INFO L226 Difference]: Without dead ends: 73 [2019-10-07 15:28:26,312 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 264 GetRequests, 226 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 370 ImplicationChecksByTransitivity, 9.0s TimeCoverageRelationStatistics Valid=343, Invalid=1213, Unknown=4, NotChecked=0, Total=1560 [2019-10-07 15:28:26,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2019-10-07 15:28:26,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2019-10-07 15:28:26,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2019-10-07 15:28:26,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 77 transitions. [2019-10-07 15:28:26,321 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 77 transitions. Word has length 80 [2019-10-07 15:28:26,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:28:26,322 INFO L462 AbstractCegarLoop]: Abstraction has 73 states and 77 transitions. [2019-10-07 15:28:26,322 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-10-07 15:28:26,322 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 77 transitions. [2019-10-07 15:28:26,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2019-10-07 15:28:26,324 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:28:26,324 INFO L385 BasicCegarLoop]: trace histogram [40, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:28:26,528 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:28:26,528 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:28:26,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:28:26,529 INFO L82 PathProgramCache]: Analyzing trace with hash -500525917, now seen corresponding path program 8 times [2019-10-07 15:28:26,529 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:28:26,530 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:28:26,530 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:28:26,530 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:28:26,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:28:26,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:28:26,726 INFO L134 CoverageAnalysis]: Checked inductivity of 1364 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 1065 trivial. 0 not checked. [2019-10-07 15:28:26,726 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:28:26,726 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:28:26,726 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:28:26,976 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2019-10-07 15:28:26,976 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:28:26,978 INFO L256 TraceCheckSpWp]: Trace formula consists of 193 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:28:26,981 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:28:27,063 INFO L134 CoverageAnalysis]: Checked inductivity of 1364 backedges. 246 proven. 10 refuted. 0 times theorem prover too weak. 1108 trivial. 0 not checked. [2019-10-07 15:28:27,063 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:28:27,152 INFO L134 CoverageAnalysis]: Checked inductivity of 1364 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 1354 trivial. 0 not checked. [2019-10-07 15:28:27,152 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:28:27,153 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:28:27,153 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:28:27,154 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:28:27,154 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:28:27,154 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:28:27,168 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:28:43,015 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:28:43,041 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:28:43,043 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:28:43,043 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:28:43,043 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:28:43,043 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:28:43,043 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:28:43,044 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:28:43,044 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:28:43,044 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:43,044 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:43,044 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_184 Int) (v_prenex_1758 Int)) (or (and (= 0 (mod v_prenex_1758 40)) (not (< main_~i~1 40)) (not (<= (mod (div v_prenex_1758 40) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_1758 40) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= 0 (mod v_prenex_1758 40)) (not (< main_~i~1 40)) (<= (mod (div v_prenex_1758 40) 4294967296) 2147483647) (= (mod (div v_prenex_1758 40) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (not (<= (mod (div v_prenex_1758 40) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_1758 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_1758 0))) (and (not (< main_~i~1 40)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_184 40) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_184 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_184 40))) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_184 40) 1) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (<= (mod (div v_prenex_1758 40) 4294967296) 2147483647) (= (mod (div v_prenex_1758 40) 4294967296) |main_#t~ret4|) (not (< v_prenex_1758 0))) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_184 40) 1) 4294967296) 2147483647)) (not (< main_~i~1 40)) (< v_avg_~ret~0_BEFORE_RETURN_184 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_184 40))) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_184 40) 1) 4294967296) (- 4294967296)))))) (exists ((v_avg_~ret~0_BEFORE_RETURN_183 Int) (v_prenex_1757 Int)) (or (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_183 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_183 40))) (< v_avg_~ret~0_BEFORE_RETURN_183 0) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_183 40) 1) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 40) 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_183 40) 1) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_183 40))) (< v_avg_~ret~0_BEFORE_RETURN_183 0) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 40) 4294967296) 2147483647) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_183 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_183 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 40) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_183 0))) (and (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_183 40) 1) 4294967296) 2147483647)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 40) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_183 0))) (and (not (<= (mod (div v_prenex_1757 40) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_1757 40))) (= (+ (mod (+ (div v_prenex_1757 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (< v_prenex_1757 0) (not (<= (mod (+ (div v_prenex_1757 40) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_183 40) 1) 4294967296) 2147483647)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 40) 4294967296) 2147483647) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_183 40))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_183 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 40) 4294967296) 2147483647) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_183 40))) (and (not (<= (mod (div v_prenex_1757 40) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_1757 40))) (= (mod (+ (div v_prenex_1757 40) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 40)) (< v_prenex_1757 0) (<= (mod (+ (div v_prenex_1757 40) 1) 4294967296) 2147483647)) (and (= (+ (mod (div v_prenex_1757 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_1757 40) 4294967296) 2147483647)) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_prenex_1757 40) 1) 4294967296) 2147483647)) (not (< v_prenex_1757 0))) (and (= (+ (mod (div v_prenex_1757 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_1757 40) 4294967296) 2147483647)) (not (< main_~i~1 40)) (<= (mod (+ (div v_prenex_1757 40) 1) 4294967296) 2147483647) (= 0 (mod v_prenex_1757 40))) (and (= (+ (mod (div v_prenex_1757 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_1757 40) 4294967296) 2147483647)) (not (< main_~i~1 40)) (not (< v_prenex_1757 0)) (<= (mod (+ (div v_prenex_1757 40) 1) 4294967296) 2147483647)) (and (= (+ (mod (div v_prenex_1757 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_1757 40) 4294967296) 2147483647)) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_prenex_1757 40) 1) 4294967296) 2147483647)) (= 0 (mod v_prenex_1757 40)))))) [2019-10-07 15:28:43,045 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:28:43,045 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:43,045 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 40 avg_~i~0) (not (< avg_~i~0 40)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:28:43,045 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:28:43,045 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:28:43,045 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:28:43,045 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:28:43,046 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:28:43,046 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:28:43,046 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:28:43,046 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:28:45,395 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:28:45,395 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 7, 7, 11] total 33 [2019-10-07 15:28:45,396 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-10-07 15:28:45,396 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-10-07 15:28:45,397 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=169, Invalid=886, Unknown=1, NotChecked=0, Total=1056 [2019-10-07 15:28:45,397 INFO L87 Difference]: Start difference. First operand 73 states and 77 transitions. Second operand 33 states. [2019-10-07 15:29:59,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:29:59,482 INFO L93 Difference]: Finished difference Result 106 states and 122 transitions. [2019-10-07 15:29:59,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-10-07 15:29:59,484 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 98 [2019-10-07 15:29:59,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:29:59,485 INFO L225 Difference]: With dead ends: 106 [2019-10-07 15:29:59,485 INFO L226 Difference]: Without dead ends: 80 [2019-10-07 15:29:59,487 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 335 GetRequests, 276 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 806 ImplicationChecksByTransitivity, 53.8s TimeCoverageRelationStatistics Valid=587, Invalid=3047, Unknown=26, NotChecked=0, Total=3660 [2019-10-07 15:29:59,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2019-10-07 15:29:59,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 80. [2019-10-07 15:29:59,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2019-10-07 15:29:59,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 84 transitions. [2019-10-07 15:29:59,497 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 84 transitions. Word has length 98 [2019-10-07 15:29:59,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:29:59,497 INFO L462 AbstractCegarLoop]: Abstraction has 80 states and 84 transitions. [2019-10-07 15:29:59,497 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-10-07 15:29:59,498 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 84 transitions. [2019-10-07 15:29:59,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2019-10-07 15:29:59,499 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:29:59,499 INFO L385 BasicCegarLoop]: trace histogram [40, 33, 10, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:29:59,703 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:29:59,704 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:29:59,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:29:59,705 INFO L82 PathProgramCache]: Analyzing trace with hash 1394119573, now seen corresponding path program 9 times [2019-10-07 15:29:59,705 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:29:59,705 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:29:59,705 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:29:59,706 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:29:59,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:29:59,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:29:59,929 INFO L134 CoverageAnalysis]: Checked inductivity of 1511 backedges. 0 proven. 356 refuted. 0 times theorem prover too weak. 1155 trivial. 0 not checked. [2019-10-07 15:29:59,929 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:29:59,929 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:29:59,929 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:30:00,283 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:30:00,283 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:30:00,286 INFO L256 TraceCheckSpWp]: Trace formula consists of 562 conjuncts, 13 conjunts are in the unsatisfiable core [2019-10-07 15:30:00,288 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:30:00,308 INFO L134 CoverageAnalysis]: Checked inductivity of 1511 backedges. 290 proven. 66 refuted. 0 times theorem prover too weak. 1155 trivial. 0 not checked. [2019-10-07 15:30:00,308 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:30:00,529 INFO L134 CoverageAnalysis]: Checked inductivity of 1511 backedges. 0 proven. 356 refuted. 0 times theorem prover too weak. 1155 trivial. 0 not checked. [2019-10-07 15:30:00,529 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:30:00,530 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:30:00,530 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:30:00,531 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:30:00,531 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:30:00,531 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:30:00,543 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:30:06,557 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:30:06,576 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:30:06,579 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:30:06,579 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:30:06,579 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:30:06,579 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:30:06,580 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:30:06,580 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:30:06,580 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:30:06,580 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:30:06,580 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:30:06,581 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_2032 Int) (v_avg_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (< main_~i~1 40)) (not (< v_prenex_2032 0)) (= (+ (mod (div v_prenex_2032 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2032 40) 4294967296) 2147483647))) (and (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_210 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_210 40) 1) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_210 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_210 40)))) (and (not (< main_~i~1 40)) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_210 40) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_210 40) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_210 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_210 40)))) (and (not (< main_~i~1 40)) (= (+ (mod (div v_prenex_2032 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2032 40) 4294967296) 2147483647)) (= 0 (mod v_prenex_2032 40))) (and (not (< main_~i~1 40)) (not (< v_prenex_2032 0)) (<= (mod (div v_prenex_2032 40) 4294967296) 2147483647) (= (mod (div v_prenex_2032 40) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (<= (mod (div v_prenex_2032 40) 4294967296) 2147483647) (= (mod (div v_prenex_2032 40) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_2032 40))))) (exists ((v_prenex_2031 Int) (v_avg_~ret~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 40)) (< v_prenex_2031 0) (not (= 0 (mod v_prenex_2031 40))) (= (+ (mod (+ (div v_prenex_2031 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_2031 40) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_209 40) 4294967296) |main_#t~ret4|) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_209 40)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_209 40) 4294967296) 2147483647)) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_209 40) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_209 40) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_209 40))) (and (not (< main_~i~1 40)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_209 40) 4294967296) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_209 0)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_209 40) 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (< v_prenex_2031 0) (= (mod (+ (div v_prenex_2031 40) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_prenex_2031 40))) (<= (mod (+ (div v_prenex_2031 40) 1) 4294967296) 2147483647)) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_209 40) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_209 40) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (< v_avg_~ret~0_BEFORE_RETURN_209 0)))))) [2019-10-07 15:30:06,581 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:30:06,581 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:30:06,581 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 40 avg_~i~0) (not (< avg_~i~0 40)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:30:06,582 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:30:06,582 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:30:06,582 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:30:06,582 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:30:06,583 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:30:06,583 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:30:06,583 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:30:06,583 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:30:08,873 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:30:08,874 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 11] total 37 [2019-10-07 15:30:08,875 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2019-10-07 15:30:08,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2019-10-07 15:30:08,877 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=377, Invalid=954, Unknown=1, NotChecked=0, Total=1332 [2019-10-07 15:30:08,877 INFO L87 Difference]: Start difference. First operand 80 states and 84 transitions. Second operand 37 states. [2019-10-07 15:30:36,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:30:36,545 INFO L93 Difference]: Finished difference Result 126 states and 148 transitions. [2019-10-07 15:30:36,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-10-07 15:30:36,546 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 107 [2019-10-07 15:30:36,547 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:30:36,547 INFO L225 Difference]: With dead ends: 126 [2019-10-07 15:30:36,547 INFO L226 Difference]: Without dead ends: 93 [2019-10-07 15:30:36,550 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 366 GetRequests, 300 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1049 ImplicationChecksByTransitivity, 15.9s TimeCoverageRelationStatistics Valid=1218, Invalid=3331, Unknown=7, NotChecked=0, Total=4556 [2019-10-07 15:30:36,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2019-10-07 15:30:36,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2019-10-07 15:30:36,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2019-10-07 15:30:36,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 97 transitions. [2019-10-07 15:30:36,562 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 97 transitions. Word has length 107 [2019-10-07 15:30:36,562 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:30:36,562 INFO L462 AbstractCegarLoop]: Abstraction has 93 states and 97 transitions. [2019-10-07 15:30:36,562 INFO L463 AbstractCegarLoop]: Interpolant automaton has 37 states. [2019-10-07 15:30:36,563 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 97 transitions. [2019-10-07 15:30:36,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2019-10-07 15:30:36,564 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:30:36,564 INFO L385 BasicCegarLoop]: trace histogram [72, 40, 10, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:30:36,764 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:30:36,765 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:30:36,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:30:36,766 INFO L82 PathProgramCache]: Analyzing trace with hash 1018049731, now seen corresponding path program 10 times [2019-10-07 15:30:36,766 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:30:36,767 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:30:36,767 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:30:36,767 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:30:36,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:30:36,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:30:37,326 INFO L134 CoverageAnalysis]: Checked inductivity of 3656 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 2104 trivial. 0 not checked. [2019-10-07 15:30:37,326 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:30:37,327 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:30:37,327 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:30:37,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:30:37,787 INFO L256 TraceCheckSpWp]: Trace formula consists of 757 conjuncts, 26 conjunts are in the unsatisfiable core [2019-10-07 15:30:37,789 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:30:37,807 INFO L134 CoverageAnalysis]: Checked inductivity of 3656 backedges. 1252 proven. 300 refuted. 0 times theorem prover too weak. 2104 trivial. 0 not checked. [2019-10-07 15:30:37,808 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:30:38,386 INFO L134 CoverageAnalysis]: Checked inductivity of 3656 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 2104 trivial. 0 not checked. [2019-10-07 15:30:38,387 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:30:38,388 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:30:38,388 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:30:38,388 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:30:38,389 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:30:38,389 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:30:38,408 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:30:54,263 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:30:54,279 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:30:54,282 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:30:54,282 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:30:54,282 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:30:54,283 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:30:54,283 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:30:54,283 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:30:54,283 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:30:54,283 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:30:54,284 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:30:54,284 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_235 Int) (v_prenex_2275 Int)) (or (and (= (mod (+ (div v_prenex_2275 40) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_prenex_2275 40))) (not (< main_~i~1 40)) (<= (mod (+ (div v_prenex_2275 40) 1) 4294967296) 2147483647) (< v_prenex_2275 0)) (and (not (< main_~i~1 40)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_235 40) 4294967296) 2147483647) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_235 40)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_235 40) 4294967296) |main_#t~ret4|)) (and (not (= 0 (mod v_prenex_2275 40))) (not (<= (mod (+ (div v_prenex_2275 40) 1) 4294967296) 2147483647)) (not (< main_~i~1 40)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2275 40) 1) 4294967296) (- 4294967296))) (< v_prenex_2275 0)) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_235 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (not (< v_avg_~ret~0_BEFORE_RETURN_235 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_235 40) 4294967296) 2147483647))) (and (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_235 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_235 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_235 40) 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_235 40) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_235 0)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_235 40) 4294967296) |main_#t~ret4|)))) (exists ((v_avg_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_2276 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod (+ (div v_prenex_2276 40) 1) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_2276 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_2276 0)) (not (<= (mod (div v_prenex_2276 40) 4294967296) 2147483647))) (and (< v_prenex_2276 0) (not (= 0 (mod v_prenex_2276 40))) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_prenex_2276 40) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_2276 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2276 40) 4294967296) 2147483647))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_236 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_236 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_236 40) 4294967296) 2147483647) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_236 40))) (and (not (< main_~i~1 40)) (not (<= (mod (+ (div v_prenex_2276 40) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2276 40) 4294967296) 2147483647) (= (mod (div v_prenex_2276 40) 4294967296) |main_#t~ret4|) (not (< v_prenex_2276 0))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_236 0)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_236 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_236 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_236 40) 4294967296) 2147483647))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_236 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (< v_avg_~ret~0_BEFORE_RETURN_236 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_236 40))) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_236 40) 1) 4294967296)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_236 40) 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (= 0 (mod v_prenex_2276 40)) (not (<= (mod (+ (div v_prenex_2276 40) 1) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_2276 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2276 40) 4294967296) 2147483647))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_236 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_236 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_236 40) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_236 40))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_236 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_236 40) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_236 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_236 40))) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_236 40) 1) 4294967296))) (and (< v_prenex_2276 0) (not (= 0 (mod v_prenex_2276 40))) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_prenex_2276 40) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2276 40) 4294967296) 2147483647) (= (+ (mod (+ (div v_prenex_2276 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (= 0 (mod v_prenex_2276 40)) (not (<= (mod (+ (div v_prenex_2276 40) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2276 40) 4294967296) 2147483647) (= (mod (div v_prenex_2276 40) 4294967296) |main_#t~ret4|)) (and (not (< v_avg_~ret~0_BEFORE_RETURN_236 0)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_236 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_236 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_236 40) 4294967296) 2147483647))))) [2019-10-07 15:30:54,284 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:30:54,284 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:30:54,284 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 40 avg_~i~0) (not (< avg_~i~0 40)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:30:54,284 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:30:54,284 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:30:54,284 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:30:54,285 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:30:54,285 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:30:54,285 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:30:54,285 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:30:54,285 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:30:56,737 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:30:56,737 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 11] total 53 [2019-10-07 15:30:56,738 INFO L442 AbstractCegarLoop]: Interpolant automaton has 53 states [2019-10-07 15:30:56,739 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2019-10-07 15:30:56,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=929, Invalid=1826, Unknown=1, NotChecked=0, Total=2756 [2019-10-07 15:30:56,740 INFO L87 Difference]: Start difference. First operand 93 states and 97 transitions. Second operand 53 states. [2019-10-07 15:31:25,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:31:25,841 INFO L93 Difference]: Finished difference Result 155 states and 180 transitions. [2019-10-07 15:31:25,843 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2019-10-07 15:31:25,844 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 146 [2019-10-07 15:31:25,844 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:31:25,845 INFO L225 Difference]: With dead ends: 155 [2019-10-07 15:31:25,845 INFO L226 Difference]: Without dead ends: 109 [2019-10-07 15:31:25,849 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 512 GetRequests, 404 SyntacticMatches, 10 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2175 ImplicationChecksByTransitivity, 17.9s TimeCoverageRelationStatistics Valid=2938, Invalid=6956, Unknown=6, NotChecked=0, Total=9900 [2019-10-07 15:31:25,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2019-10-07 15:31:25,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 109. [2019-10-07 15:31:25,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2019-10-07 15:31:25,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 113 transitions. [2019-10-07 15:31:25,862 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 113 transitions. Word has length 146 [2019-10-07 15:31:25,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:31:25,863 INFO L462 AbstractCegarLoop]: Abstraction has 109 states and 113 transitions. [2019-10-07 15:31:25,863 INFO L463 AbstractCegarLoop]: Interpolant automaton has 53 states. [2019-10-07 15:31:25,863 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 113 transitions. [2019-10-07 15:31:25,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2019-10-07 15:31:25,865 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:31:25,865 INFO L385 BasicCegarLoop]: trace histogram [120, 40, 10, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:31:26,077 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:31:26,077 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:31:26,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:31:26,077 INFO L82 PathProgramCache]: Analyzing trace with hash -1383300413, now seen corresponding path program 11 times [2019-10-07 15:31:26,077 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:31:26,077 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:31:26,078 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:31:26,078 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:31:26,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:31:26,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:31:26,422 INFO L134 CoverageAnalysis]: Checked inductivity of 8384 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:31:26,422 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:31:26,422 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:31:26,423 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:31:27,300 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2019-10-07 15:31:27,301 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:31:27,304 INFO L256 TraceCheckSpWp]: Trace formula consists of 313 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-07 15:31:27,309 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:31:27,344 INFO L134 CoverageAnalysis]: Checked inductivity of 8384 backedges. 3366 proven. 55 refuted. 0 times theorem prover too weak. 4963 trivial. 0 not checked. [2019-10-07 15:31:27,345 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:31:27,553 INFO L134 CoverageAnalysis]: Checked inductivity of 8384 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:31:27,553 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:31:27,555 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:31:27,555 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:31:27,555 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:31:27,555 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:31:27,555 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:31:27,567 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:31:33,756 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:31:33,784 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:31:33,787 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:31:33,788 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:31:33,788 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:31:33,788 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:31:33,788 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:31:33,789 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:31:33,789 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:31:33,789 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:31:33,789 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:31:33,790 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_2562 Int) (v_avg_~ret~0_BEFORE_RETURN_262 Int)) (or (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_262 40) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (< v_avg_~ret~0_BEFORE_RETURN_262 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_262 40) 4294967296) 2147483647))) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_262 40) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_262 40) 4294967296) 2147483647)) (= (mod v_avg_~ret~0_BEFORE_RETURN_262 40) 0)) (and (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_262 40) 4294967296)) (not (< main_~i~1 40)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_262 40) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_262 0))) (and (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_262 40) 4294967296)) (not (< main_~i~1 40)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_262 40) 4294967296) 2147483647) (= (mod v_avg_~ret~0_BEFORE_RETURN_262 40) 0)) (and (not (< main_~i~1 40)) (< v_prenex_2562 0) (= (mod (+ (div v_prenex_2562 40) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_2562 40) 1) 4294967296) 2147483647) (not (= (mod v_prenex_2562 40) 0))) (and (not (< main_~i~1 40)) (< v_prenex_2562 0) (not (<= (mod (+ (div v_prenex_2562 40) 1) 4294967296) 2147483647)) (not (= (mod v_prenex_2562 40) 0)) (= (+ (mod (+ (div v_prenex_2562 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_prenex_2561 Int) (v_avg_~ret~0_BEFORE_RETURN_261 Int)) (or (and (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2561 40) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (= 0 (mod v_prenex_2561 40))) (< v_prenex_2561 0) (not (<= (mod (+ (div v_prenex_2561 40) 1) 4294967296) 2147483647))) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_261 40) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_261 0)) (not (< main_~i~1 40)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_261 40) 4294967296))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_261 0)) (not (< main_~i~1 40)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_261 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_261 40) 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_261 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_261 40)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_261 40) 4294967296) 2147483647))) (and (<= (mod (+ (div v_prenex_2561 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (not (= 0 (mod v_prenex_2561 40))) (= (mod (+ (div v_prenex_2561 40) 1) 4294967296) |main_#t~ret4|) (< v_prenex_2561 0)) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_261 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_261 40)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_261 40) 4294967296)))))) [2019-10-07 15:31:33,790 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:31:33,790 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:31:33,790 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 40 avg_~i~0) (not (< avg_~i~0 40)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:31:33,791 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:31:33,791 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:31:33,791 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:31:33,791 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:31:33,792 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:31:33,792 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:31:33,792 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:31:33,792 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:31:36,189 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:31:36,190 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 11] total 35 [2019-10-07 15:31:36,191 INFO L442 AbstractCegarLoop]: Interpolant automaton has 35 states [2019-10-07 15:31:36,192 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2019-10-07 15:31:36,192 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=864, Unknown=1, NotChecked=0, Total=1190 [2019-10-07 15:31:36,192 INFO L87 Difference]: Start difference. First operand 109 states and 113 transitions. Second operand 35 states. [2019-10-07 15:33:39,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:33:39,775 INFO L93 Difference]: Finished difference Result 169 states and 185 transitions. [2019-10-07 15:33:39,776 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-10-07 15:33:39,777 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 194 [2019-10-07 15:33:39,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:33:39,778 INFO L225 Difference]: With dead ends: 169 [2019-10-07 15:33:39,778 INFO L226 Difference]: Without dead ends: 121 [2019-10-07 15:33:39,781 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 624 GetRequests, 562 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 936 ImplicationChecksByTransitivity, 99.9s TimeCoverageRelationStatistics Valid=968, Invalid=3015, Unknown=49, NotChecked=0, Total=4032 [2019-10-07 15:33:39,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2019-10-07 15:33:39,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 121. [2019-10-07 15:33:39,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2019-10-07 15:33:39,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 125 transitions. [2019-10-07 15:33:39,793 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 125 transitions. Word has length 194 [2019-10-07 15:33:39,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:33:39,794 INFO L462 AbstractCegarLoop]: Abstraction has 121 states and 125 transitions. [2019-10-07 15:33:39,794 INFO L463 AbstractCegarLoop]: Interpolant automaton has 35 states. [2019-10-07 15:33:39,794 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 125 transitions. [2019-10-07 15:33:39,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2019-10-07 15:33:39,795 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:33:39,796 INFO L385 BasicCegarLoop]: trace histogram [120, 40, 22, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:33:40,002 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:33:40,002 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:33:40,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:33:40,003 INFO L82 PathProgramCache]: Analyzing trace with hash -719887741, now seen corresponding path program 12 times [2019-10-07 15:33:40,003 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:33:40,004 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:33:40,004 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:33:40,004 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:33:40,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:33:40,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:33:40,594 INFO L134 CoverageAnalysis]: Checked inductivity of 8582 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:33:40,594 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:33:40,594 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:33:40,594 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:33:41,086 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:33:41,086 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:33:41,089 INFO L256 TraceCheckSpWp]: Trace formula consists of 1045 conjuncts, 24 conjunts are in the unsatisfiable core [2019-10-07 15:33:41,092 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:33:41,118 INFO L134 CoverageAnalysis]: Checked inductivity of 8582 backedges. 3366 proven. 253 refuted. 0 times theorem prover too weak. 4963 trivial. 0 not checked. [2019-10-07 15:33:41,119 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:33:41,731 INFO L134 CoverageAnalysis]: Checked inductivity of 8582 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:33:41,731 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:33:41,732 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:33:41,732 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:33:41,733 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:33:41,733 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:33:41,733 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:33:41,749 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:33:59,506 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:33:59,524 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:33:59,527 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:33:59,527 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:33:59,527 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:33:59,527 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:33:59,527 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:33:59,527 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:33:59,527 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:33:59,527 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:33:59,527 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:33:59,528 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_287 Int) (v_prenex_2805 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod (div v_prenex_2805 40) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_2805 40) 1) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (div v_prenex_2805 40) 4294967296) (- 4294967296))) (not (< v_prenex_2805 0))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_287 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 40) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_287 40) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_287 40) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (not (<= (mod (div v_prenex_2805 40) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_2805 40) 1) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (div v_prenex_2805 40) 4294967296) (- 4294967296))) (= (mod v_prenex_2805 40) 0)) (and (<= (mod (div v_prenex_2805 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod (div v_prenex_2805 40) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_2805 40) 1) 4294967296) 2147483647) (= (mod v_prenex_2805 40) 0)) (and (<= (mod (div v_prenex_2805 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (<= (mod (+ (div v_prenex_2805 40) 1) 4294967296) 2147483647) (= (mod (div v_prenex_2805 40) 4294967296) |main_#t~ret4|) (not (< v_prenex_2805 0))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_287 0)) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_287 40) 1) 4294967296) 2147483647)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 40) 4294967296) 2147483647)) (and (< v_prenex_2805 0) (= |main_#t~ret4| (mod (+ (div v_prenex_2805 40) 1) 4294967296)) (not (< main_~i~1 40)) (not (<= (mod (div v_prenex_2805 40) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_2805 40) 1) 4294967296) 2147483647) (not (= (mod v_prenex_2805 40) 0))) (and (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_287 40) 1) 4294967296) 2147483647)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 40) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 40) 4294967296) 2147483647) (= (mod v_avg_~ret~0_BEFORE_RETURN_287 40) 0)) (and (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_287 40) 1) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_287 0) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_287 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 40) 4294967296) 2147483647) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_287 40) 0))) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 40) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_287 40) 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_287 40) 1) 4294967296) 2147483647)) (= (mod v_avg_~ret~0_BEFORE_RETURN_287 40) 0)) (and (< v_prenex_2805 0) (<= (mod (div v_prenex_2805 40) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_prenex_2805 40) 1) 4294967296)) (not (< main_~i~1 40)) (<= (mod (+ (div v_prenex_2805 40) 1) 4294967296) 2147483647) (not (= (mod v_prenex_2805 40) 0))) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 40) 4294967296) 2147483647)) (not (< main_~i~1 40)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_287 40) 1) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_287 0) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_287 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_287 40) 0))))) (exists ((v_prenex_2806 Int) (v_avg_~ret~0_BEFORE_RETURN_288 Int)) (or (and (not (< v_prenex_2806 0)) (<= (mod (div v_prenex_2806 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod (div v_prenex_2806 40) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_288 40) 1) 4294967296) 2147483647)) (not (< main_~i~1 40)) (< v_avg_~ret~0_BEFORE_RETURN_288 0) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_288 40) 0)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_288 40) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (div v_prenex_2806 40) 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod (div v_prenex_2806 40) 4294967296) |main_#t~ret4|) (= (mod v_prenex_2806 40) 0)) (and (not (< main_~i~1 40)) (= (+ (mod (div v_prenex_2806 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2806 40) 4294967296) 2147483647)) (= (mod v_prenex_2806 40) 0)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_288 40) 1) 4294967296) 2147483647) (not (< main_~i~1 40)) (< v_avg_~ret~0_BEFORE_RETURN_288 0) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_288 40) 1) 4294967296)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_288 40) 0))) (and (not (< v_prenex_2806 0)) (not (< main_~i~1 40)) (= (+ (mod (div v_prenex_2806 40) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2806 40) 4294967296) 2147483647)))))) [2019-10-07 15:33:59,528 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:33:59,528 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:33:59,528 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 40 avg_~i~0) (not (< avg_~i~0 40)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 40) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 40) 1) (div avg_~ret~0 40)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:33:59,528 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:33:59,528 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:33:59,528 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:33:59,528 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:33:59,529 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:33:59,529 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:33:59,529 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:33:59,529 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:34:01,919 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:34:01,920 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 11] total 52 [2019-10-07 15:34:01,921 INFO L442 AbstractCegarLoop]: Interpolant automaton has 52 states [2019-10-07 15:34:01,921 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2019-10-07 15:34:01,922 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=886, Invalid=1765, Unknown=1, NotChecked=0, Total=2652 [2019-10-07 15:34:01,922 INFO L87 Difference]: Start difference. First operand 121 states and 125 transitions. Second operand 52 states. [2019-10-07 15:37:17,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:17,183 INFO L93 Difference]: Finished difference Result 186 states and 207 transitions. [2019-10-07 15:37:17,186 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-10-07 15:37:17,186 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 206 [2019-10-07 15:37:17,186 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:17,187 INFO L225 Difference]: With dead ends: 186 [2019-10-07 15:37:17,187 INFO L226 Difference]: Without dead ends: 138 [2019-10-07 15:37:17,191 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 689 GetRequests, 586 SyntacticMatches, 7 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2078 ImplicationChecksByTransitivity, 169.9s TimeCoverageRelationStatistics Valid=2651, Invalid=6772, Unknown=83, NotChecked=0, Total=9506 [2019-10-07 15:37:17,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2019-10-07 15:37:17,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2019-10-07 15:37:17,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2019-10-07 15:37:17,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 142 transitions. [2019-10-07 15:37:17,207 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 142 transitions. Word has length 206 [2019-10-07 15:37:17,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:17,207 INFO L462 AbstractCegarLoop]: Abstraction has 138 states and 142 transitions. [2019-10-07 15:37:17,207 INFO L463 AbstractCegarLoop]: Interpolant automaton has 52 states. [2019-10-07 15:37:17,207 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 142 transitions. [2019-10-07 15:37:17,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 224 [2019-10-07 15:37:17,209 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:17,209 INFO L385 BasicCegarLoop]: trace histogram [120, 40, 39, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:17,420 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:17,420 INFO L410 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:17,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:17,421 INFO L82 PathProgramCache]: Analyzing trace with hash -853315336, now seen corresponding path program 13 times [2019-10-07 15:37:17,421 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:17,422 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:17,422 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:17,422 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:17,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY