java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/avg60-1.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:23:43,152 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:23:43,155 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:23:43,172 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:23:43,172 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:23:43,174 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:23:43,176 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:23:43,178 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:23:43,179 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:23:43,180 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:23:43,181 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:23:43,182 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:23:43,182 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:23:43,183 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:23:43,184 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:23:43,185 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:23:43,186 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:23:43,187 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:23:43,189 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:23:43,191 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:23:43,193 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:23:43,198 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:23:43,200 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:23:43,202 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:23:43,204 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 15:23:43,217 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:23:43,220 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:23:43,223 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:23:43,224 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:23:43,248 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:23:43,248 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:23:43,251 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:23:43,252 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:23:43,252 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:23:43,253 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:23:43,253 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:23:43,253 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:23:43,253 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:23:43,254 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:23:43,255 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:23:43,255 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:23:43,255 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:23:43,255 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:23:43,255 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:23:43,256 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:23:43,256 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:23:43,256 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:23:43,256 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:23:43,256 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:23:43,257 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:23:43,257 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:23:43,257 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:23:43,258 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:23:43,258 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:23:43,258 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:23:43,258 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:23:43,258 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:23:43,259 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:23:43,522 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:23:43,543 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:23:43,546 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:23:43,547 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:23:43,548 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:23:43,548 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/avg60-1.i [2019-10-07 15:23:43,623 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4375050c1/9a7eb82362bf457c900cb4ff78b1015e/FLAGa121d6eae [2019-10-07 15:23:44,041 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:23:44,042 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/avg60-1.i [2019-10-07 15:23:44,047 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4375050c1/9a7eb82362bf457c900cb4ff78b1015e/FLAGa121d6eae [2019-10-07 15:23:44,419 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4375050c1/9a7eb82362bf457c900cb4ff78b1015e [2019-10-07 15:23:44,427 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:23:44,428 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:23:44,429 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:23:44,429 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:23:44,433 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:23:44,433 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:23:44" (1/1) ... [2019-10-07 15:23:44,436 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3e9683c3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:44, skipping insertion in model container [2019-10-07 15:23:44,437 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:23:44" (1/1) ... [2019-10-07 15:23:44,444 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:23:44,461 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:23:44,675 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:23:44,689 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:23:44,736 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:23:44,754 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:23:44,754 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:44 WrapperNode [2019-10-07 15:23:44,755 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:23:44,756 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:23:44,756 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:23:44,756 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:23:44,890 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:44" (1/1) ... [2019-10-07 15:23:44,890 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:44" (1/1) ... [2019-10-07 15:23:44,899 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:44" (1/1) ... [2019-10-07 15:23:44,899 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:44" (1/1) ... [2019-10-07 15:23:44,920 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:44" (1/1) ... [2019-10-07 15:23:44,927 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:44" (1/1) ... [2019-10-07 15:23:44,936 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:44" (1/1) ... [2019-10-07 15:23:44,939 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:23:44,939 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:23:44,939 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:23:44,939 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:23:44,940 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:44" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:23:45,004 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:23:45,004 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:23:45,004 INFO L138 BoogieDeclarations]: Found implementation of procedure avg [2019-10-07 15:23:45,004 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:23:45,005 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:23:45,005 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:23:45,005 INFO L130 BoogieDeclarations]: Found specification of procedure avg [2019-10-07 15:23:45,005 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:23:45,005 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:23:45,005 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:23:45,006 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:23:45,006 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:23:45,006 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:23:45,006 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:23:45,377 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:23:45,378 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:23:45,379 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:23:45 BoogieIcfgContainer [2019-10-07 15:23:45,379 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:23:45,381 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:23:45,381 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:23:45,384 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:23:45,384 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:23:44" (1/3) ... [2019-10-07 15:23:45,385 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5322f189 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:23:45, skipping insertion in model container [2019-10-07 15:23:45,385 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:44" (2/3) ... [2019-10-07 15:23:45,385 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5322f189 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:23:45, skipping insertion in model container [2019-10-07 15:23:45,385 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:23:45" (3/3) ... [2019-10-07 15:23:45,387 INFO L109 eAbstractionObserver]: Analyzing ICFG avg60-1.i [2019-10-07 15:23:45,396 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:23:45,404 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:23:45,414 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:23:45,439 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:23:45,439 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:23:45,439 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:23:45,439 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:23:45,440 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:23:45,440 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:23:45,440 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:23:45,440 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:23:45,456 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:23:45,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:23:45,461 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:45,462 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:45,463 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:45,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:45,467 INFO L82 PathProgramCache]: Analyzing trace with hash 2112018211, now seen corresponding path program 1 times [2019-10-07 15:23:45,474 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:45,474 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:45,474 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:45,474 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:45,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:45,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:45,667 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:23:45,668 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:45,672 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:23:45,672 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:23:45,676 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:45,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:45,690 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:45,692 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:23:45,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:45,727 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:23:45,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:45,729 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:23:45,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:45,737 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:23:45,738 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:23:45,741 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:45,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:23:45,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:23:45,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:23:45,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:23:45,780 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:23:45,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:45,781 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:23:45,781 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:45,781 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:23:45,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:23:45,783 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:45,784 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:45,784 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:45,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:45,785 INFO L82 PathProgramCache]: Analyzing trace with hash -2049651994, now seen corresponding path program 1 times [2019-10-07 15:23:45,785 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:45,785 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:45,785 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:45,786 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:45,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:45,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:45,881 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:45,882 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:45,882 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:23:45,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:45,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:45,953 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:23:45,961 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:23:45,991 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:45,991 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:23:46,028 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:46,029 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:23:46,029 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:23:46,031 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:46,031 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:46,031 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:23:46,032 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:23:46,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:46,043 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:23:46,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:46,044 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:23:46,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:46,045 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:23:46,045 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:23:46,046 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:23:46,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:23:46,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:23:46,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:23:46,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:23:46,052 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:23:46,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:46,053 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:23:46,053 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:46,053 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:23:46,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:23:46,054 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:46,054 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:46,258 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:46,262 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:46,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:46,263 INFO L82 PathProgramCache]: Analyzing trace with hash -575014574, now seen corresponding path program 1 times [2019-10-07 15:23:46,263 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:46,263 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:46,263 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:46,264 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:46,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:46,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:46,369 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:46,370 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:46,370 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:23:46,370 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:23:46,371 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:46,372 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:46,372 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:46,373 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:23:46,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:46,389 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:23:46,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:46,390 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:23:46,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:46,391 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:23:46,392 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:23:46,392 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:46,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:23:46,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:23:46,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:23:46,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:23:46,403 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:23:46,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:46,408 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:23:46,409 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:46,409 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:23:46,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:23:46,410 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:46,410 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:46,410 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:46,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:46,411 INFO L82 PathProgramCache]: Analyzing trace with hash -202958309, now seen corresponding path program 1 times [2019-10-07 15:23:46,411 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:46,411 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:46,411 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:46,411 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:46,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:46,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:46,527 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:46,527 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:46,528 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:23:46,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:46,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:46,616 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:23:46,621 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:23:46,650 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:46,651 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:23:46,684 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:46,684 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:23:46,709 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:23:46,709 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:23:46,716 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:23:46,723 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:23:46,724 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:23:46,853 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:02,841 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:24:02,885 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:02,889 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:02,889 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:02,890 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:02,890 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:24:02,890 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:24:02,890 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:24:02,890 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:02,891 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:02,891 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_2 Int) (v_prenex_2 Int)) (or (and (= (+ (mod (div v_prenex_2 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_2 0)) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_2 60) 4294967296) 2147483647)) (not (<= (mod (+ (div v_prenex_2 60) 1) 4294967296) 2147483647))) (and (= (+ (mod (div v_prenex_2 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_2 0)) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_2 60) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_2 60) 1) 4294967296) 2147483647)) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_avg_~ret~0_BEFORE_RETURN_2 60) 0) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 60) 1) 4294967296) 2147483647))) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_avg_~ret~0_BEFORE_RETURN_2 60) 0) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 60) 1) 4294967296) 2147483647)) (and (not (< v_avg_~ret~0_BEFORE_RETURN_2 0)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 60) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 60)) (not (= (mod v_prenex_2 60) 0)) (not (<= (mod (div v_prenex_2 60) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_2 60) 1) 4294967296) 2147483647) (< v_prenex_2 0) (= |main_#t~ret4| (mod (+ (div v_prenex_2 60) 1) 4294967296))) (and (< v_avg_~ret~0_BEFORE_RETURN_2 0) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 60) 1) 4294967296)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_2 60) 0)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 60) 1) 4294967296) 2147483647)) (and (= (+ (mod (div v_prenex_2 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_prenex_2 60) 0) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_2 60) 4294967296) 2147483647)) (not (<= (mod (+ (div v_prenex_2 60) 1) 4294967296) 2147483647))) (and (< v_avg_~ret~0_BEFORE_RETURN_2 0) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_2 60) 0)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 60) 1) 4294967296) 2147483647))) (and (= (+ (mod (+ (div v_prenex_2 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (not (= (mod v_prenex_2 60) 0)) (not (<= (mod (div v_prenex_2 60) 4294967296) 2147483647)) (not (<= (mod (+ (div v_prenex_2 60) 1) 4294967296) 2147483647)) (< v_prenex_2 0)) (and (= (+ (mod (div v_prenex_2 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_prenex_2 60) 0) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_2 60) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_2 60) 1) 4294967296) 2147483647)) (and (not (< v_avg_~ret~0_BEFORE_RETURN_2 0)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_2 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_2 60) 1) 4294967296) 2147483647)))) (exists ((v_avg_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (not (< v_avg_~ret~0_BEFORE_RETURN_1 0)) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_1 60) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 60) 4294967296) 2147483647))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_1 0)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 60) 4294967296) 2147483647) (not (< main_~i~1 60))) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_avg_~ret~0_BEFORE_RETURN_1 60) 0)) (and (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_1 60) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_1 60) 4294967296) 2147483647)) (= (mod v_avg_~ret~0_BEFORE_RETURN_1 60) 0)) (and (< v_prenex_1 0) (not (< main_~i~1 60)) (<= (mod (+ (div v_prenex_1 60) 1) 4294967296) 2147483647) (not (= (mod v_prenex_1 60) 0)) (= (mod (+ (div v_prenex_1 60) 1) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (+ (div v_prenex_1 60) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_1 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_prenex_1 0) (not (< main_~i~1 60)) (not (= (mod v_prenex_1 60) 0)))))) [2019-10-07 15:24:02,891 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:24:02,891 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:02,892 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:24:02,892 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:02,892 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:24:02,892 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:24:02,892 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:24:02,892 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:24:02,893 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:24:02,894 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:24:02,895 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:02,895 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:24:05,120 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:05,121 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:24:05,122 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-10-07 15:24:05,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-10-07 15:24:05,123 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=225, Unknown=1, NotChecked=0, Total=272 [2019-10-07 15:24:05,123 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 17 states. [2019-10-07 15:24:33,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:33,763 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:24:33,765 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-10-07 15:24:33,766 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 29 [2019-10-07 15:24:33,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:33,766 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:24:33,767 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:24:33,768 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 14.5s TimeCoverageRelationStatistics Valid=123, Invalid=626, Unknown=7, NotChecked=0, Total=756 [2019-10-07 15:24:33,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:24:33,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:24:33,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:24:33,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:24:33,773 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:24:33,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:33,774 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:24:33,774 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-10-07 15:24:33,774 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:24:33,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:24:33,775 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:33,775 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:33,976 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:33,977 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:33,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:33,977 INFO L82 PathProgramCache]: Analyzing trace with hash -892290920, now seen corresponding path program 2 times [2019-10-07 15:24:33,978 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:33,978 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:33,978 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:33,979 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:33,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:34,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:34,103 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:34,103 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:34,104 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:34,104 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:34,175 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:24:34,175 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:34,177 INFO L256 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:24:34,179 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:34,200 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:34,201 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:34,230 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:34,230 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:34,231 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:34,232 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:34,232 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:34,232 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:34,233 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:34,256 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:08,613 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:25:08,632 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:08,635 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:08,635 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:08,635 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:08,636 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:25:08,636 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:25:08,636 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:25:08,636 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:08,636 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:08,637 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_287 Int) (v_avg_~ret~0_BEFORE_RETURN_27 Int)) (or (and (not (< v_avg_~ret~0_BEFORE_RETURN_27 0)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_27 60) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 60) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_287 60) 4294967296) 2147483647) (not (< v_prenex_287 0)) (= (mod (div v_prenex_287 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_prenex_287 60) 1) 4294967296) 2147483647))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 60) 1) 4294967296) 2147483647) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_27 60)) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_27 60) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 60) 4294967296) 2147483647))) (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_27 60)) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 60) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_27 60) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 60) 4294967296) 2147483647))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_27 60))) (< v_avg_~ret~0_BEFORE_RETURN_27 0) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 60) 4294967296) 2147483647)) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 60) 1) 4294967296))) (and (<= (mod (div v_prenex_287 60) 4294967296) 2147483647) (not (< v_prenex_287 0)) (= (mod (div v_prenex_287 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (<= (mod (+ (div v_prenex_287 60) 1) 4294967296) 2147483647)) (and (<= (mod (div v_prenex_287 60) 4294967296) 2147483647) (= (mod (div v_prenex_287 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_prenex_287 60) 1) 4294967296) 2147483647)) (= 0 (mod v_prenex_287 60))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_27 0)) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 60) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_27 60) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 60) 4294967296) 2147483647))) (and (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 60) 1) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_27 60))) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_27 60) 1) 4294967296) (- 4294967296))) (< v_avg_~ret~0_BEFORE_RETURN_27 0) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_27 60) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_287 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (< v_prenex_287 0) (= |main_#t~ret4| (mod (+ (div v_prenex_287 60) 1) 4294967296)) (not (= 0 (mod v_prenex_287 60))) (<= (mod (+ (div v_prenex_287 60) 1) 4294967296) 2147483647)) (and (<= (mod (div v_prenex_287 60) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_287 60) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (< v_prenex_287 0) (not (= 0 (mod v_prenex_287 60))) (not (<= (mod (+ (div v_prenex_287 60) 1) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_287 60) 4294967296) 2147483647) (= (mod (div v_prenex_287 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (= 0 (mod v_prenex_287 60)) (<= (mod (+ (div v_prenex_287 60) 1) 4294967296) 2147483647)))) (exists ((v_prenex_288 Int) (v_avg_~ret~0_BEFORE_RETURN_28 Int)) (or (and (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 60) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_28 60) 4294967296) 2147483647)) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_28 60) 0)) (< v_avg_~ret~0_BEFORE_RETURN_28 0)) (and (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 60) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_28 60) 4294967296) 2147483647)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 60) 1) 4294967296) 2147483647) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_28 60) 0)) (< v_avg_~ret~0_BEFORE_RETURN_28 0)) (and (not (= (mod v_prenex_288 60) 0)) (= (mod (+ (div v_prenex_288 60) 1) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_288 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (< v_prenex_288 0) (<= (mod (+ (div v_prenex_288 60) 1) 4294967296) 2147483647)) (and (<= (mod (div v_prenex_288 60) 4294967296) 2147483647) (= (mod (div v_prenex_288 60) 4294967296) |main_#t~ret4|) (not (< v_prenex_288 0)) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_prenex_288 60) 1) 4294967296) 2147483647))) (and (= (+ (mod (+ (div v_prenex_288 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_prenex_288 60) 0)) (<= (mod (div v_prenex_288 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_prenex_288 60) 1) 4294967296) 2147483647)) (< v_prenex_288 0)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_28 60) 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 60) 1) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_28 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_28 60) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_288 60) 4294967296) 2147483647) (= (mod (div v_prenex_288 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_prenex_288 60) 1) 4294967296) 2147483647)) (= (mod v_prenex_288 60) 0)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_28 60) 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_28 60) 4294967296) 2147483647)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 60) 1) 4294967296) 2147483647) (= (mod v_avg_~ret~0_BEFORE_RETURN_28 60) 0)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_28 60) 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (not (< v_avg_~ret~0_BEFORE_RETURN_28 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_28 60) 4294967296) 2147483647)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 60) 1) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_28 60) 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_28 60) 1) 4294967296) 2147483647)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_28 60) 4294967296) 2147483647)) (= (mod v_avg_~ret~0_BEFORE_RETURN_28 60) 0)) (and (= (mod (div v_prenex_288 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_288 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_prenex_288 60) 0) (<= (mod (+ (div v_prenex_288 60) 1) 4294967296) 2147483647)) (and (= (mod (div v_prenex_288 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_288 60) 4294967296) 2147483647) (not (< v_prenex_288 0)) (not (< main_~i~1 60)) (<= (mod (+ (div v_prenex_288 60) 1) 4294967296) 2147483647))))) [2019-10-07 15:25:08,637 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:25:08,637 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:08,638 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:25:08,638 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:08,638 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:25:08,638 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:25:08,638 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:25:08,638 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:25:08,639 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:25:08,639 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:25:08,639 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:08,639 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:25:10,940 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:10,941 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:25:10,942 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-10-07 15:25:10,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-10-07 15:25:10,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=359, Unknown=1, NotChecked=0, Total=420 [2019-10-07 15:25:10,943 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 21 states. [2019-10-07 15:25:27,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:27,758 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:25:27,760 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-10-07 15:25:27,760 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 32 [2019-10-07 15:25:27,760 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:27,760 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:25:27,761 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:25:27,762 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 10.8s TimeCoverageRelationStatistics Valid=200, Invalid=1127, Unknown=5, NotChecked=0, Total=1332 [2019-10-07 15:25:27,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:25:27,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:25:27,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:25:27,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:25:27,768 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:25:27,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:27,769 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:25:27,769 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-10-07 15:25:27,769 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:25:27,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:25:27,770 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:27,770 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:27,971 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:27,972 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:27,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:27,973 INFO L82 PathProgramCache]: Analyzing trace with hash -337812683, now seen corresponding path program 3 times [2019-10-07 15:25:27,973 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:27,973 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:27,973 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:27,974 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:27,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:28,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:28,085 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:28,085 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:28,085 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:28,085 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:28,190 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:25:28,190 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:25:28,191 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:25:28,194 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:28,203 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:28,203 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:28,275 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:28,275 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:28,277 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:28,277 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:28,277 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:28,278 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:28,278 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:28,301 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:34,546 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:25:34,575 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:34,599 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:34,599 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:34,600 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:34,600 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:25:34,600 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:25:34,600 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:25:34,600 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:34,601 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:34,601 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_616 Int)) (or (and (= |main_#t~ret4| (mod (div v_prenex_616 60) 4294967296)) (not (< v_prenex_616 0)) (<= (mod (div v_prenex_616 60) 4294967296) 2147483647) (not (< main_~i~1 60))) (and (not (= (mod v_avg_~ret~0_BEFORE_RETURN_54 60) 0)) (< v_avg_~ret~0_BEFORE_RETURN_54 0) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 60) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= |main_#t~ret4| (mod (div v_prenex_616 60) 4294967296)) (= (mod v_prenex_616 60) 0) (<= (mod (div v_prenex_616 60) 4294967296) 2147483647) (not (< main_~i~1 60))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 60) 1) 4294967296) 2147483647) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_54 60) 0)) (< v_avg_~ret~0_BEFORE_RETURN_54 0) (not (< main_~i~1 60)) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_54 60) 1) 4294967296))) (and (not (< v_prenex_616 0)) (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_616 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_616 60) 4294967296) 2147483647))) (and (= (mod v_prenex_616 60) 0) (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_616 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_616 60) 4294967296) 2147483647))))) (exists ((v_avg_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_615 Int)) (or (and (not (< v_prenex_615 0)) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_615 60) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_615 60) 4294967296) (- 4294967296)))) (and (= |main_#t~ret4| (mod (div v_prenex_615 60) 4294967296)) (not (< v_prenex_615 0)) (not (< main_~i~1 60)) (<= (mod (div v_prenex_615 60) 4294967296) 2147483647)) (and (< v_avg_~ret~0_BEFORE_RETURN_53 0) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 60) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_53 60))) (not (< main_~i~1 60)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 60) 1) 4294967296) 2147483647)) (and (< v_avg_~ret~0_BEFORE_RETURN_53 0) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 60) 1) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_53 60))) (not (< main_~i~1 60)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_53 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= |main_#t~ret4| (mod (div v_prenex_615 60) 4294967296)) (not (< main_~i~1 60)) (<= (mod (div v_prenex_615 60) 4294967296) 2147483647) (= 0 (mod v_prenex_615 60))) (and (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_615 60) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_615 60) 4294967296) (- 4294967296))) (= 0 (mod v_prenex_615 60)))))) [2019-10-07 15:25:34,601 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:25:34,601 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:34,601 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:25:34,602 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:34,602 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:25:34,602 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:25:34,602 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:25:34,602 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:25:34,603 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:25:34,603 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:25:34,603 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:34,603 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:25:36,956 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:36,957 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-07 15:25:36,958 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-10-07 15:25:36,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-10-07 15:25:36,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=469, Unknown=1, NotChecked=0, Total=600 [2019-10-07 15:25:36,959 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 25 states. [2019-10-07 15:26:03,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:26:03,711 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-07 15:26:03,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-10-07 15:26:03,713 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 42 [2019-10-07 15:26:03,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:26:03,714 INFO L225 Difference]: With dead ends: 54 [2019-10-07 15:26:03,714 INFO L226 Difference]: Without dead ends: 36 [2019-10-07 15:26:03,716 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 487 ImplicationChecksByTransitivity, 14.9s TimeCoverageRelationStatistics Valid=359, Invalid=1526, Unknown=7, NotChecked=0, Total=1892 [2019-10-07 15:26:03,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-07 15:26:03,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-07 15:26:03,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-07 15:26:03,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-07 15:26:03,728 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-07 15:26:03,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:26:03,728 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-07 15:26:03,730 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-10-07 15:26:03,730 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-07 15:26:03,731 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-07 15:26:03,731 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:26:03,731 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:26:03,932 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:03,932 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:26:03,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:26:03,933 INFO L82 PathProgramCache]: Analyzing trace with hash -1325230312, now seen corresponding path program 4 times [2019-10-07 15:26:03,933 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:26:03,934 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:03,934 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:03,934 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:03,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:26:03,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:04,108 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:26:04,109 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:04,109 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:26:04,109 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:04,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:04,264 INFO L256 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:26:04,267 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:26:04,278 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:26:04,279 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:26:04,519 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:26:04,519 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:26:04,521 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:26:04,521 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:26:04,521 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:26:04,522 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:26:04,522 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:26:04,537 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:16,172 WARN L160 IndexEqualityManager]: solver failed to check if following equality is implied: (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) |main_~#x~0.offset|)) [2019-10-07 15:26:22,221 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:26:22,242 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:22,245 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:22,245 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:22,245 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:22,246 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:26:22,246 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:26:22,246 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:26:22,246 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:22,247 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:22,247 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_847 Int)) (or (and (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_79 60) 4294967296)) (not (< main_~i~1 60)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_79 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 60) 1) 4294967296) 2147483647)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 60) 4294967296) 2147483647)) (and (<= (mod (+ (div v_prenex_847 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_847 60) 4294967296) 2147483647)) (not (< v_prenex_847 0)) (= (+ (mod (div v_prenex_847 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_79 60) 4294967296)) (not (< v_avg_~ret~0_BEFORE_RETURN_79 0)) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 60) 1) 4294967296) 2147483647)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 60) 4294967296) 2147483647)) (and (< v_avg_~ret~0_BEFORE_RETURN_79 0) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 60) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 60) 1) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_79 60))) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 60) 4294967296) 2147483647)) (and (<= (mod (+ (div v_prenex_847 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (= 0 (mod v_prenex_847 60)) (= |main_#t~ret4| (mod (div v_prenex_847 60) 4294967296)) (<= (mod (div v_prenex_847 60) 4294967296) 2147483647)) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 60) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_79 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_79 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 60) 1) 4294967296) 2147483647))) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 60) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_79 0) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 60) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 60) 1) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_79 60)))) (and (<= (mod (+ (div v_prenex_847 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_847 60) 4294967296) 2147483647)) (= (mod (+ (div v_prenex_847 60) 1) 4294967296) |main_#t~ret4|) (< v_prenex_847 0) (not (= 0 (mod v_prenex_847 60)))) (and (<= (mod (+ (div v_prenex_847 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (not (< v_prenex_847 0)) (= |main_#t~ret4| (mod (div v_prenex_847 60) 4294967296)) (<= (mod (div v_prenex_847 60) 4294967296) 2147483647)) (and (<= (mod (+ (div v_prenex_847 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (= 0 (mod v_prenex_847 60)) (not (<= (mod (div v_prenex_847 60) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_847 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_79 60) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_79 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_79 0)) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_79 60) 1) 4294967296) 2147483647))) (and (<= (mod (+ (div v_prenex_847 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod (+ (div v_prenex_847 60) 1) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_847 60) 4294967296) 2147483647) (< v_prenex_847 0) (not (= 0 (mod v_prenex_847 60)))))) (exists ((v_prenex_848 Int) (v_avg_~ret~0_BEFORE_RETURN_80 Int)) (or (and (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_80 60))) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 60) 1) 4294967296) 2147483647)) (not (< main_~i~1 60)) (< v_avg_~ret~0_BEFORE_RETURN_80 0) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 60) 1) 4294967296) (- 4294967296)))) (and (not (< v_prenex_848 0)) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_848 60) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_848 60) 4294967296) (- 4294967296)))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 60) 1) 4294967296) 2147483647) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_80 60))) (not (< main_~i~1 60)) (< v_avg_~ret~0_BEFORE_RETURN_80 0) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_80 60) 1) 4294967296) |main_#t~ret4|)) (and (<= (mod (div v_prenex_848 60) 4294967296) 2147483647) (not (< v_prenex_848 0)) (not (< main_~i~1 60)) (= |main_#t~ret4| (mod (div v_prenex_848 60) 4294967296))) (and (<= (mod (div v_prenex_848 60) 4294967296) 2147483647) (= 0 (mod v_prenex_848 60)) (not (< main_~i~1 60)) (= |main_#t~ret4| (mod (div v_prenex_848 60) 4294967296))) (and (= 0 (mod v_prenex_848 60)) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_848 60) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_848 60) 4294967296) (- 4294967296))))))) [2019-10-07 15:26:22,247 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:22,247 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:26:22,247 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:26:22,248 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:22,248 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:26:22,248 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:26:22,248 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:26:22,248 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:26:22,248 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:26:22,249 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:26:22,249 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:22,249 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:26:24,555 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:24,555 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-07 15:26:24,556 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2019-10-07 15:26:24,556 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-10-07 15:26:24,557 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=431, Invalid=1050, Unknown=1, NotChecked=0, Total=1482 [2019-10-07 15:26:24,557 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 39 states. [2019-10-07 15:26:53,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:26:53,989 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-07 15:26:53,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-10-07 15:26:53,991 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 49 [2019-10-07 15:26:53,991 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:26:53,992 INFO L225 Difference]: With dead ends: 68 [2019-10-07 15:26:53,992 INFO L226 Difference]: Without dead ends: 50 [2019-10-07 15:26:53,995 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1243 ImplicationChecksByTransitivity, 15.6s TimeCoverageRelationStatistics Valid=1234, Invalid=3871, Unknown=7, NotChecked=0, Total=5112 [2019-10-07 15:26:53,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-07 15:26:54,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-07 15:26:54,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-07 15:26:54,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-07 15:26:54,002 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-07 15:26:54,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:26:54,002 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-07 15:26:54,003 INFO L463 AbstractCegarLoop]: Interpolant automaton has 39 states. [2019-10-07 15:26:54,003 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-07 15:26:54,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-07 15:26:54,004 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:26:54,004 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:26:54,205 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:54,206 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:26:54,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:26:54,207 INFO L82 PathProgramCache]: Analyzing trace with hash -2064123784, now seen corresponding path program 5 times [2019-10-07 15:26:54,207 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:26:54,207 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:54,208 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:54,208 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:54,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:26:54,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:54,726 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:26:54,726 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:54,727 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:26:54,727 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:54,899 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:26:54,899 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:26:54,901 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:26:54,911 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:26:54,959 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-07 15:26:54,959 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:26:55,004 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-07 15:26:55,004 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:26:55,007 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:26:55,007 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:26:55,007 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:26:55,007 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:26:55,008 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:26:55,024 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:27:00,641 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:27:00,686 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:27:00,688 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:27:00,688 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:27:00,689 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:27:00,689 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:27:00,689 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:27:00,689 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:27:00,689 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:00,689 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:27:00,690 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1127 Int) (v_avg_~ret~0_BEFORE_RETURN_105 Int)) (or (and (= |main_#t~ret4| (+ (mod (div v_prenex_1127 60) 4294967296) (- 4294967296))) (= 0 (mod v_prenex_1127 60)) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_1127 60) 4294967296) 2147483647))) (and (= 0 (mod v_prenex_1127 60)) (<= (mod (div v_prenex_1127 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod (div v_prenex_1127 60) 4294967296) |main_#t~ret4|)) (and (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 60) 1) 4294967296)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_105 60))) (not (< main_~i~1 60)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 60) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_105 0)) (and (= |main_#t~ret4| (+ (mod (div v_prenex_1127 60) 4294967296) (- 4294967296))) (not (< v_prenex_1127 0)) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_1127 60) 4294967296) 2147483647))) (and (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_105 60))) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 60) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_105 60) 1) 4294967296) (- 4294967296))) (< v_avg_~ret~0_BEFORE_RETURN_105 0)) (and (<= (mod (div v_prenex_1127 60) 4294967296) 2147483647) (not (< v_prenex_1127 0)) (not (< main_~i~1 60)) (= (mod (div v_prenex_1127 60) 4294967296) |main_#t~ret4|)))) (exists ((v_prenex_1128 Int) (v_avg_~ret~0_BEFORE_RETURN_106 Int)) (or (and (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_1128 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_1128 60) 4294967296) 2147483647)) (not (< v_prenex_1128 0))) (and (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_106 60) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_106 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (< v_avg_~ret~0_BEFORE_RETURN_106 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_106 60)))) (and (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_106 60) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_106 60) 1) 4294967296) (- 4294967296))) (< v_avg_~ret~0_BEFORE_RETURN_106 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_106 60)))) (and (= 0 (mod v_prenex_1128 60)) (not (< main_~i~1 60)) (<= (mod (div v_prenex_1128 60) 4294967296) 2147483647) (= (mod (div v_prenex_1128 60) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 60)) (<= (mod (div v_prenex_1128 60) 4294967296) 2147483647) (not (< v_prenex_1128 0)) (= (mod (div v_prenex_1128 60) 4294967296) |main_#t~ret4|)) (and (= 0 (mod v_prenex_1128 60)) (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_1128 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_1128 60) 4294967296) 2147483647)))))) [2019-10-07 15:27:00,690 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:00,690 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:27:00,690 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:27:00,690 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:27:00,691 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:27:00,691 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:27:00,691 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:27:00,691 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:27:00,691 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:27:00,691 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:27:00,692 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:27:00,692 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:27:03,138 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:27:03,139 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-07 15:27:03,140 INFO L442 AbstractCegarLoop]: Interpolant automaton has 43 states [2019-10-07 15:27:03,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2019-10-07 15:27:03,141 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=445, Invalid=1360, Unknown=1, NotChecked=0, Total=1806 [2019-10-07 15:27:03,142 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 43 states. [2019-10-07 15:27:53,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:27:53,210 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-07 15:27:53,210 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2019-10-07 15:27:53,210 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 63 [2019-10-07 15:27:53,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:27:53,212 INFO L225 Difference]: With dead ends: 72 [2019-10-07 15:27:53,212 INFO L226 Difference]: Without dead ends: 54 [2019-10-07 15:27:53,215 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 177 SyntacticMatches, 0 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1240 ImplicationChecksByTransitivity, 32.4s TimeCoverageRelationStatistics Valid=1339, Invalid=5126, Unknown=15, NotChecked=0, Total=6480 [2019-10-07 15:27:53,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-07 15:27:53,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-07 15:27:53,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-07 15:27:53,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-07 15:27:53,222 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-07 15:27:53,223 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:27:53,223 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-07 15:27:53,223 INFO L463 AbstractCegarLoop]: Interpolant automaton has 43 states. [2019-10-07 15:27:53,223 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-07 15:27:53,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-07 15:27:53,224 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:27:53,224 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:27:53,426 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:27:53,427 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:27:53,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:27:53,428 INFO L82 PathProgramCache]: Analyzing trace with hash -1786233658, now seen corresponding path program 6 times [2019-10-07 15:27:53,428 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:27:53,428 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:27:53,429 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:27:53,429 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:27:53,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:27:53,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:27:53,835 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:27:53,835 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:27:53,835 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:27:53,836 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:27:54,063 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:27:54,063 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:27:54,065 INFO L256 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-07 15:27:54,067 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:27:54,081 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:27:54,082 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:27:55,022 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:27:55,022 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:27:55,024 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:27:55,024 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:27:55,024 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:27:55,024 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:27:55,024 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:27:55,043 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:28:00,447 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:28:00,464 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:28:00,466 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:28:00,467 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:28:00,467 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:28:00,467 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:28:00,467 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:28:00,467 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:28:00,468 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:00,468 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:00,468 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1353 Int) (v_avg_~ret~0_BEFORE_RETURN_131 Int)) (or (and (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_131 60) 4294967296) (- 4294967296))) (not (< v_avg_~ret~0_BEFORE_RETURN_131 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 60) 4294967296) 2147483647))) (and (= (mod v_avg_~ret~0_BEFORE_RETURN_131 60) 0) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_131 60) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 60) 4294967296) 2147483647))) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 60) 4294967296) |main_#t~ret4|) (= (mod v_avg_~ret~0_BEFORE_RETURN_131 60) 0) (not (< main_~i~1 60)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 60) 4294967296) 2147483647)) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_131 60) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_131 0))) (and (not (< main_~i~1 60)) (= (mod (+ (div v_prenex_1353 60) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1353 60) 1) 4294967296) 2147483647) (not (= (mod v_prenex_1353 60) 0)) (< v_prenex_1353 0)) (and (not (<= (mod (+ (div v_prenex_1353 60) 1) 4294967296) 2147483647)) (not (< main_~i~1 60)) (not (= (mod v_prenex_1353 60) 0)) (< v_prenex_1353 0) (= (+ (mod (+ (div v_prenex_1353 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_prenex_1354 Int) (v_avg_~ret~0_BEFORE_RETURN_132 Int)) (or (and (not (<= (mod (+ (div v_prenex_1354 60) 1) 4294967296) 2147483647)) (< v_prenex_1354 0) (not (< main_~i~1 60)) (not (= (mod v_prenex_1354 60) 0)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1354 60) 1) 4294967296) (- 4294967296)))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_132 0)) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_132 60) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 60) 4294967296) 2147483647))) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 60) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_132 0)) (not (< main_~i~1 60)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 60) 4294967296) |main_#t~ret4|)) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_avg_~ret~0_BEFORE_RETURN_132 60) 0) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 60) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 60)) (= (mod v_avg_~ret~0_BEFORE_RETURN_132 60) 0) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_132 60) 4294967296) (- 4294967296))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_132 60) 4294967296) 2147483647))) (and (< v_prenex_1354 0) (not (< main_~i~1 60)) (<= (mod (+ (div v_prenex_1354 60) 1) 4294967296) 2147483647) (not (= (mod v_prenex_1354 60) 0)) (= |main_#t~ret4| (mod (+ (div v_prenex_1354 60) 1) 4294967296)))))) [2019-10-07 15:28:00,468 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:00,468 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:28:00,468 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:28:00,469 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:28:00,469 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:28:00,469 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:28:00,469 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:28:00,469 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:28:00,469 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:28:00,469 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:28:00,469 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:28:00,470 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:28:02,857 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:28:02,857 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-07 15:28:02,858 INFO L442 AbstractCegarLoop]: Interpolant automaton has 69 states [2019-10-07 15:28:02,859 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2019-10-07 15:28:02,860 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1736, Invalid=2955, Unknown=1, NotChecked=0, Total=4692 [2019-10-07 15:28:02,861 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 69 states. [2019-10-07 15:28:32,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:28:32,224 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-07 15:28:32,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2019-10-07 15:28:32,226 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 67 [2019-10-07 15:28:32,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:28:32,227 INFO L225 Difference]: With dead ends: 104 [2019-10-07 15:28:32,227 INFO L226 Difference]: Without dead ends: 83 [2019-10-07 15:28:32,232 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 295 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3688 ImplicationChecksByTransitivity, 18.6s TimeCoverageRelationStatistics Valid=5089, Invalid=12196, Unknown=7, NotChecked=0, Total=17292 [2019-10-07 15:28:32,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-07 15:28:32,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-07 15:28:32,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-07 15:28:32,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-07 15:28:32,250 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-07 15:28:32,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:28:32,251 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-07 15:28:32,251 INFO L463 AbstractCegarLoop]: Interpolant automaton has 69 states. [2019-10-07 15:28:32,251 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-07 15:28:32,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-07 15:28:32,252 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:28:32,253 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:28:32,453 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:28:32,454 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:28:32,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:28:32,455 INFO L82 PathProgramCache]: Analyzing trace with hash 466246243, now seen corresponding path program 7 times [2019-10-07 15:28:32,455 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:28:32,455 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:28:32,455 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:28:32,456 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:28:32,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:28:32,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:28:33,885 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:28:33,886 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:28:33,886 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:28:33,886 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:28:34,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:28:34,155 INFO L256 TraceCheckSpWp]: Trace formula consists of 529 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-07 15:28:34,158 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:28:34,176 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:28:34,177 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:28:35,638 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:28:35,639 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:28:35,640 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:28:35,640 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:28:35,641 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:28:35,641 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:28:35,641 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:28:35,659 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:28:40,948 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:28:40,972 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:28:40,975 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:28:40,975 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:28:40,975 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:28:40,975 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:28:40,975 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:28:40,975 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:28:40,976 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:40,976 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:40,976 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1592 Int)) (or (and (not (< main_~i~1 60)) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 60) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 60) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_158 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_158 60)))) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 60) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_158 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (< v_avg_~ret~0_BEFORE_RETURN_158 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_158 60)))) (and (= 0 (mod v_prenex_1592 60)) (<= (mod (div v_prenex_1592 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod (div v_prenex_1592 60) 4294967296) |main_#t~ret4|)) (and (not (< v_prenex_1592 0)) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (div v_prenex_1592 60) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_1592 60) 4294967296) 2147483647))) (and (not (< v_prenex_1592 0)) (<= (mod (div v_prenex_1592 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod (div v_prenex_1592 60) 4294967296) |main_#t~ret4|)) (and (= 0 (mod v_prenex_1592 60)) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (div v_prenex_1592 60) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_1592 60) 4294967296) 2147483647))))) (exists ((v_avg_~ret~0_BEFORE_RETURN_157 Int) (v_prenex_1591 Int)) (or (and (= |main_#t~ret4| (mod (+ (div v_prenex_1591 60) 1) 4294967296)) (not (< main_~i~1 60)) (<= (mod (+ (div v_prenex_1591 60) 1) 4294967296) 2147483647) (not (= (mod v_prenex_1591 60) 0)) (< v_prenex_1591 0)) (and (= (mod v_avg_~ret~0_BEFORE_RETURN_157 60) 0) (not (< main_~i~1 60)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_157 60) 4294967296)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 60) 4294967296) 2147483647)) (and (not (< main_~i~1 60)) (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_157 60) 4294967296)) (not (< v_avg_~ret~0_BEFORE_RETURN_157 0)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 60) 4294967296) 2147483647)) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 60) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_157 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (not (< v_avg_~ret~0_BEFORE_RETURN_157 0))) (and (not (<= (mod (+ (div v_prenex_1591 60) 1) 4294967296) 2147483647)) (not (< main_~i~1 60)) (not (= (mod v_prenex_1591 60) 0)) (< v_prenex_1591 0) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1591 60) 1) 4294967296) (- 4294967296)))) (and (= (mod v_avg_~ret~0_BEFORE_RETURN_157 60) 0) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_157 60) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_157 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)))))) [2019-10-07 15:28:40,976 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:28:40,976 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:28:40,977 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:28:40,977 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:28:40,977 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:28:40,977 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:28:40,977 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:28:40,977 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:28:40,977 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:28:40,978 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:28:40,978 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:28:40,978 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:28:43,521 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:28:43,521 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 73 [2019-10-07 15:28:43,523 INFO L442 AbstractCegarLoop]: Interpolant automaton has 73 states [2019-10-07 15:28:43,523 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2019-10-07 15:28:43,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1978, Invalid=3277, Unknown=1, NotChecked=0, Total=5256 [2019-10-07 15:28:43,525 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 73 states. [2019-10-07 15:29:13,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:29:13,745 INFO L93 Difference]: Finished difference Result 108 states and 119 transitions. [2019-10-07 15:29:13,747 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2019-10-07 15:29:13,747 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 96 [2019-10-07 15:29:13,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:29:13,748 INFO L225 Difference]: With dead ends: 108 [2019-10-07 15:29:13,748 INFO L226 Difference]: Without dead ends: 87 [2019-10-07 15:29:13,757 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 415 GetRequests, 223 SyntacticMatches, 54 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4936 ImplicationChecksByTransitivity, 20.7s TimeCoverageRelationStatistics Valid=5807, Invalid=13646, Unknown=7, NotChecked=0, Total=19460 [2019-10-07 15:29:13,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2019-10-07 15:29:13,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2019-10-07 15:29:13,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2019-10-07 15:29:13,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 91 transitions. [2019-10-07 15:29:13,773 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 91 transitions. Word has length 96 [2019-10-07 15:29:13,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:29:13,773 INFO L462 AbstractCegarLoop]: Abstraction has 87 states and 91 transitions. [2019-10-07 15:29:13,773 INFO L463 AbstractCegarLoop]: Interpolant automaton has 73 states. [2019-10-07 15:29:13,773 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 91 transitions. [2019-10-07 15:29:13,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2019-10-07 15:29:13,775 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:29:13,775 INFO L385 BasicCegarLoop]: trace histogram [60, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:29:13,979 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:29:13,980 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:29:13,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:29:13,981 INFO L82 PathProgramCache]: Analyzing trace with hash 585102115, now seen corresponding path program 8 times [2019-10-07 15:29:13,981 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:29:13,981 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:29:13,981 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:29:13,982 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:29:13,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:29:14,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:29:14,110 INFO L134 CoverageAnalysis]: Checked inductivity of 1951 backedges. 26 proven. 36 refuted. 0 times theorem prover too weak. 1889 trivial. 0 not checked. [2019-10-07 15:29:14,111 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:29:14,111 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:29:14,111 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:29:14,366 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:29:14,366 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:29:14,367 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:29:14,370 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:29:14,385 INFO L134 CoverageAnalysis]: Checked inductivity of 1951 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 1889 trivial. 0 not checked. [2019-10-07 15:29:14,386 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:29:14,441 INFO L134 CoverageAnalysis]: Checked inductivity of 1951 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 1889 trivial. 0 not checked. [2019-10-07 15:29:14,442 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:29:14,443 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:29:14,443 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:29:14,444 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:29:14,444 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:29:14,444 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:29:14,456 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:29:20,026 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:29:20,057 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:29:20,059 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:29:20,060 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:29:20,060 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:29:20,060 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:29:20,060 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:29:20,060 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:29:20,060 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:29:20,060 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:29:20,061 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1829 Int) (v_avg_~ret~0_BEFORE_RETURN_183 Int)) (or (and (< v_prenex_1829 0) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1829 60) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (not (= (mod v_prenex_1829 60) 0)) (not (<= (mod (+ (div v_prenex_1829 60) 1) 4294967296) 2147483647))) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 60) 4294967296) |main_#t~ret4|) (= (mod v_avg_~ret~0_BEFORE_RETURN_183 60) 0)) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 60) 4294967296) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_183 0))) (and (not (< main_~i~1 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 60) 4294967296) 2147483647)) (= (mod v_avg_~ret~0_BEFORE_RETURN_183 60) 0) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_183 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_183 60) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_183 0)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_183 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (< v_prenex_1829 0) (= |main_#t~ret4| (mod (+ (div v_prenex_1829 60) 1) 4294967296)) (not (< main_~i~1 60)) (not (= (mod v_prenex_1829 60) 0)) (<= (mod (+ (div v_prenex_1829 60) 1) 4294967296) 2147483647)))) (exists ((v_prenex_1830 Int) (v_avg_~ret~0_BEFORE_RETURN_184 Int)) (or (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_184 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_avg_~ret~0_BEFORE_RETURN_184 60) 0) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_184 60) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_184 60) 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_184 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_avg_~ret~0_BEFORE_RETURN_184 60) 0)) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_184 60) 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_184 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_184 0))) (and (< v_prenex_1830 0) (not (= (mod v_prenex_1830 60) 0)) (= (mod (+ (div v_prenex_1830 60) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (<= (mod (+ (div v_prenex_1830 60) 1) 4294967296) 2147483647)) (and (< v_prenex_1830 0) (not (= (mod v_prenex_1830 60) 0)) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_prenex_1830 60) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_1830 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_184 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_184 60) 4294967296) |main_#t~ret4|) (not (< v_avg_~ret~0_BEFORE_RETURN_184 0)))))) [2019-10-07 15:29:20,061 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:29:20,061 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:29:20,061 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:29:20,061 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:29:20,061 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:29:20,062 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:29:20,062 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:29:20,062 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:29:20,062 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:29:20,062 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:29:20,062 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:29:20,062 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:29:22,296 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:29:22,297 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 23 [2019-10-07 15:29:22,298 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-10-07 15:29:22,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-10-07 15:29:22,299 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=104, Invalid=401, Unknown=1, NotChecked=0, Total=506 [2019-10-07 15:29:22,299 INFO L87 Difference]: Start difference. First operand 87 states and 91 transitions. Second operand 23 states. [2019-10-07 15:29:53,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:29:53,114 INFO L93 Difference]: Finished difference Result 113 states and 128 transitions. [2019-10-07 15:29:53,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:29:53,115 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 100 [2019-10-07 15:29:53,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:29:53,117 INFO L225 Difference]: With dead ends: 113 [2019-10-07 15:29:53,117 INFO L226 Difference]: Without dead ends: 93 [2019-10-07 15:29:53,117 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 323 GetRequests, 285 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 370 ImplicationChecksByTransitivity, 14.9s TimeCoverageRelationStatistics Valid=343, Invalid=1210, Unknown=7, NotChecked=0, Total=1560 [2019-10-07 15:29:53,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2019-10-07 15:29:53,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2019-10-07 15:29:53,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2019-10-07 15:29:53,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 97 transitions. [2019-10-07 15:29:53,127 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 97 transitions. Word has length 100 [2019-10-07 15:29:53,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:29:53,128 INFO L462 AbstractCegarLoop]: Abstraction has 93 states and 97 transitions. [2019-10-07 15:29:53,128 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-10-07 15:29:53,128 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 97 transitions. [2019-10-07 15:29:53,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2019-10-07 15:29:53,130 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:29:53,130 INFO L385 BasicCegarLoop]: trace histogram [60, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:29:53,333 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:29:53,334 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:29:53,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:29:53,335 INFO L82 PathProgramCache]: Analyzing trace with hash -1014046621, now seen corresponding path program 9 times [2019-10-07 15:29:53,335 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:29:53,335 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:29:53,336 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:29:53,336 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:29:53,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:29:53,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:29:53,599 INFO L134 CoverageAnalysis]: Checked inductivity of 2374 backedges. 122 proven. 177 refuted. 0 times theorem prover too weak. 2075 trivial. 0 not checked. [2019-10-07 15:29:53,599 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:29:53,600 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:29:53,600 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:29:53,921 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:29:53,921 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:29:53,923 INFO L256 TraceCheckSpWp]: Trace formula consists of 643 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-07 15:29:53,925 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:29:53,940 INFO L134 CoverageAnalysis]: Checked inductivity of 2374 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 2075 trivial. 0 not checked. [2019-10-07 15:29:53,940 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:29:54,122 INFO L134 CoverageAnalysis]: Checked inductivity of 2374 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 2075 trivial. 0 not checked. [2019-10-07 15:29:54,122 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:29:54,123 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:29:54,123 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:29:54,124 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:29:54,124 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:29:54,124 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:29:54,136 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:29:59,530 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:29:59,563 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:29:59,565 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:29:59,565 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:29:59,565 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:29:59,565 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:29:59,565 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:29:59,565 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:29:59,565 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:29:59,566 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:29:59,566 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_210 Int) (v_prenex_2056 Int)) (or (and (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_210 60))) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_210 60) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_210 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_avg_~ret~0_BEFORE_RETURN_210 0)) (and (not (<= (mod (div v_prenex_2056 60) 4294967296) 2147483647)) (not (< main_~i~1 60)) (not (< v_prenex_2056 0)) (= (+ (mod (div v_prenex_2056 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (div v_prenex_2056 60) 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_2056 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_prenex_2056 60))) (and (<= (mod (div v_prenex_2056 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (not (< v_prenex_2056 0)) (= (mod (div v_prenex_2056 60) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_210 60) 1) 4294967296) 2147483647) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_210 60))) (not (< main_~i~1 60)) (< v_avg_~ret~0_BEFORE_RETURN_210 0) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_210 60) 1) 4294967296))) (and (<= (mod (div v_prenex_2056 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= 0 (mod v_prenex_2056 60)) (= (mod (div v_prenex_2056 60) 4294967296) |main_#t~ret4|)))) (exists ((v_prenex_2055 Int) (v_avg_~ret~0_BEFORE_RETURN_209 Int)) (or (and (= (mod (div v_prenex_2055 60) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_2055 60)) (not (< main_~i~1 60)) (<= (mod (div v_prenex_2055 60) 4294967296) 2147483647)) (and (= 0 (mod v_prenex_2055 60)) (= (+ (mod (div v_prenex_2055 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_2055 60) 4294967296) 2147483647))) (and (= (+ (mod (div v_prenex_2055 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_2055 60) 4294967296) 2147483647)) (not (< v_prenex_2055 0))) (and (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_209 60) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (< v_avg_~ret~0_BEFORE_RETURN_209 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_209 60))) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_209 60) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 60)) (< v_avg_~ret~0_BEFORE_RETURN_209 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_209 60))) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_209 60) 1) 4294967296)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_209 60) 1) 4294967296) 2147483647)) (and (= (mod (div v_prenex_2055 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (<= (mod (div v_prenex_2055 60) 4294967296) 2147483647) (not (< v_prenex_2055 0)))))) [2019-10-07 15:29:59,566 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:29:59,566 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:29:59,566 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:29:59,567 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:29:59,567 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:29:59,567 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:29:59,567 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:29:59,567 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:29:59,567 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:29:59,568 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:29:59,568 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:29:59,568 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:30:01,841 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:30:01,842 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 11] total 35 [2019-10-07 15:30:01,843 INFO L442 AbstractCegarLoop]: Interpolant automaton has 35 states [2019-10-07 15:30:01,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2019-10-07 15:30:01,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=326, Invalid=863, Unknown=1, NotChecked=0, Total=1190 [2019-10-07 15:30:01,844 INFO L87 Difference]: Start difference. First operand 93 states and 97 transitions. Second operand 35 states. [2019-10-07 15:30:29,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:30:29,446 INFO L93 Difference]: Finished difference Result 131 states and 152 transitions. [2019-10-07 15:30:29,448 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-10-07 15:30:29,448 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 118 [2019-10-07 15:30:29,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:30:29,449 INFO L225 Difference]: With dead ends: 131 [2019-10-07 15:30:29,449 INFO L226 Difference]: Without dead ends: 105 [2019-10-07 15:30:29,451 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 396 GetRequests, 334 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 937 ImplicationChecksByTransitivity, 15.8s TimeCoverageRelationStatistics Valid=1057, Invalid=2968, Unknown=7, NotChecked=0, Total=4032 [2019-10-07 15:30:29,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2019-10-07 15:30:29,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2019-10-07 15:30:29,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2019-10-07 15:30:29,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 109 transitions. [2019-10-07 15:30:29,461 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 109 transitions. Word has length 118 [2019-10-07 15:30:29,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:30:29,461 INFO L462 AbstractCegarLoop]: Abstraction has 105 states and 109 transitions. [2019-10-07 15:30:29,461 INFO L463 AbstractCegarLoop]: Interpolant automaton has 35 states. [2019-10-07 15:30:29,462 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 109 transitions. [2019-10-07 15:30:29,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2019-10-07 15:30:29,463 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:30:29,463 INFO L385 BasicCegarLoop]: trace histogram [66, 60, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:30:29,671 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:30:29,672 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:30:29,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:30:29,673 INFO L82 PathProgramCache]: Analyzing trace with hash 1226869475, now seen corresponding path program 10 times [2019-10-07 15:30:29,673 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:30:29,673 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:30:29,674 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:30:29,674 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:30:29,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:30:29,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:30:29,863 INFO L134 CoverageAnalysis]: Checked inductivity of 4192 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 4182 trivial. 0 not checked. [2019-10-07 15:30:29,863 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:30:29,863 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:30:29,863 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:30:30,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:30:30,274 INFO L256 TraceCheckSpWp]: Trace formula consists of 823 conjuncts, 24 conjunts are in the unsatisfiable core [2019-10-07 15:30:30,277 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:30:30,579 INFO L134 CoverageAnalysis]: Checked inductivity of 4192 backedges. 1060 proven. 253 refuted. 0 times theorem prover too weak. 2879 trivial. 0 not checked. [2019-10-07 15:30:30,579 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:30:31,276 INFO L134 CoverageAnalysis]: Checked inductivity of 4192 backedges. 0 proven. 1313 refuted. 0 times theorem prover too weak. 2879 trivial. 0 not checked. [2019-10-07 15:30:31,276 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:30:31,277 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:30:31,277 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:30:31,278 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:30:31,278 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:30:31,278 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:30:31,293 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:30:36,701 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:30:36,717 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:30:36,720 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:30:36,720 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:30:36,720 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:30:36,720 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:30:36,720 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:30:36,721 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:30:36,721 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:30:36,721 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:30:36,721 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_2282 Int)) (or (and (not (< v_prenex_2282 0)) (= (+ (mod (div v_prenex_2282 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2282 60) 4294967296) 2147483647)) (not (< main_~i~1 60))) (and (<= (mod (div v_prenex_2282 60) 4294967296) 2147483647) (= (mod (div v_prenex_2282 60) 4294967296) |main_#t~ret4|) (not (< v_prenex_2282 0)) (not (< main_~i~1 60))) (and (= (+ (mod (div v_prenex_2282 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2282 60) 4294967296) 2147483647)) (not (< main_~i~1 60)) (= 0 (mod v_prenex_2282 60))) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_236 60) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_236 60) 1) 4294967296)) (not (< main_~i~1 60)) (< v_avg_~ret~0_BEFORE_RETURN_236 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_236 60)))) (and (<= (mod (div v_prenex_2282 60) 4294967296) 2147483647) (= (mod (div v_prenex_2282 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (= 0 (mod v_prenex_2282 60))) (and (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_236 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (< v_avg_~ret~0_BEFORE_RETURN_236 0) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_236 60) 1) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_236 60)))))) (exists ((v_avg_~ret~0_BEFORE_RETURN_235 Int) (v_prenex_2281 Int)) (or (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_235 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_235 60) 4294967296) 2147483647) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_235 60))) (and (not (<= (mod (+ (div v_prenex_2281 60) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_2281 60))) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2281 60) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (< v_prenex_2281 0)) (and (not (< main_~i~1 60)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_235 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_235 60) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_235 60))) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_235 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (not (< v_avg_~ret~0_BEFORE_RETURN_235 0)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_235 60) 4294967296) 2147483647)) (and (not (< main_~i~1 60)) (not (< v_avg_~ret~0_BEFORE_RETURN_235 0)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_235 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_235 60) 4294967296) 2147483647))) (and (not (= 0 (mod v_prenex_2281 60))) (<= (mod (+ (div v_prenex_2281 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret4| (mod (+ (div v_prenex_2281 60) 1) 4294967296)) (< v_prenex_2281 0))))) [2019-10-07 15:30:36,721 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:30:36,721 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:30:36,722 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:30:36,722 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:30:36,722 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:30:36,722 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:30:36,722 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:30:36,722 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:30:36,723 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:30:36,723 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:30:36,723 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:30:36,723 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:30:39,110 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:30:39,111 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 25, 25, 11] total 63 [2019-10-07 15:30:39,112 INFO L442 AbstractCegarLoop]: Interpolant automaton has 63 states [2019-10-07 15:30:39,113 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2019-10-07 15:30:39,113 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1173, Invalid=2732, Unknown=1, NotChecked=0, Total=3906 [2019-10-07 15:30:39,114 INFO L87 Difference]: Start difference. First operand 105 states and 109 transitions. Second operand 63 states. [2019-10-07 15:31:41,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:31:41,131 INFO L93 Difference]: Finished difference Result 168 states and 202 transitions. [2019-10-07 15:31:41,132 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2019-10-07 15:31:41,132 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 154 [2019-10-07 15:31:41,133 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:31:41,134 INFO L225 Difference]: With dead ends: 168 [2019-10-07 15:31:41,134 INFO L226 Difference]: Without dead ends: 130 [2019-10-07 15:31:41,136 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 527 GetRequests, 408 SyntacticMatches, 0 SemanticMatches, 119 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3060 ImplicationChecksByTransitivity, 38.9s TimeCoverageRelationStatistics Valid=3801, Invalid=10702, Unknown=17, NotChecked=0, Total=14520 [2019-10-07 15:31:41,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2019-10-07 15:31:41,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 130. [2019-10-07 15:31:41,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2019-10-07 15:31:41,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 134 transitions. [2019-10-07 15:31:41,150 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 134 transitions. Word has length 154 [2019-10-07 15:31:41,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:31:41,150 INFO L462 AbstractCegarLoop]: Abstraction has 130 states and 134 transitions. [2019-10-07 15:31:41,150 INFO L463 AbstractCegarLoop]: Interpolant automaton has 63 states. [2019-10-07 15:31:41,150 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 134 transitions. [2019-10-07 15:31:41,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 228 [2019-10-07 15:31:41,153 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:31:41,153 INFO L385 BasicCegarLoop]: trace histogram [138, 60, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:31:41,353 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:31:41,354 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:31:41,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:31:41,355 INFO L82 PathProgramCache]: Analyzing trace with hash 2039917400, now seen corresponding path program 11 times [2019-10-07 15:31:41,355 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:31:41,355 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:31:41,355 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:31:41,356 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:31:41,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:31:41,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:31:42,747 INFO L134 CoverageAnalysis]: Checked inductivity of 11721 backedges. 2210 proven. 3291 refuted. 0 times theorem prover too weak. 6220 trivial. 0 not checked. [2019-10-07 15:31:42,747 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:31:42,747 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:31:42,747 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:31:43,153 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-10-07 15:31:43,153 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:31:43,154 INFO L256 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:31:43,157 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:31:43,335 INFO L134 CoverageAnalysis]: Checked inductivity of 11721 backedges. 4422 proven. 15 refuted. 0 times theorem prover too weak. 7284 trivial. 0 not checked. [2019-10-07 15:31:43,336 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:31:43,555 INFO L134 CoverageAnalysis]: Checked inductivity of 11721 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 11706 trivial. 0 not checked. [2019-10-07 15:31:43,555 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:31:43,556 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:31:43,557 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:31:43,557 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:31:43,557 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:31:43,557 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:31:43,567 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:31:59,086 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:31:59,104 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:31:59,106 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:31:59,107 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:31:59,107 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:31:59,107 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:31:59,107 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:31:59,107 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:31:59,107 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:31:59,108 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:31:59,108 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_2526 Int) (v_avg_~ret~0_BEFORE_RETURN_262 Int)) (or (and (not (<= (mod (div v_prenex_2526 60) 4294967296) 2147483647)) (not (< v_prenex_2526 0)) (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_2526 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< v_prenex_2526 0)) (not (< main_~i~1 60)) (<= (mod (div v_prenex_2526 60) 4294967296) 2147483647) (= (mod (div v_prenex_2526 60) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 60)) (<= (mod (div v_prenex_2526 60) 4294967296) 2147483647) (= (mod (div v_prenex_2526 60) 4294967296) |main_#t~ret4|) (= (mod v_prenex_2526 60) 0)) (and (< v_avg_~ret~0_BEFORE_RETURN_262 0) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_262 60) 0)) (not (< main_~i~1 60)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_262 60) 1) 4294967296) 2147483647) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_262 60) 1) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (div v_prenex_2526 60) 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_2526 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_prenex_2526 60) 0)) (and (< v_avg_~ret~0_BEFORE_RETURN_262 0) (not (= (mod v_avg_~ret~0_BEFORE_RETURN_262 60) 0)) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_262 60) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_262 60) 1) 4294967296) (- 4294967296)))))) (exists ((v_prenex_2525 Int) (v_avg_~ret~0_BEFORE_RETURN_261 Int)) (or (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_261 60)) (not (< main_~i~1 60)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_261 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_261 60) 4294967296) 2147483647) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_261 60) 1) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_2525 60) 1) 4294967296) 2147483647)) (< v_prenex_2525 0) (<= (mod (div v_prenex_2525 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2525 60) 1) 4294967296) (- 4294967296))) (not (= 0 (mod v_prenex_2525 60)))) (and (not (<= (mod (+ (div v_prenex_2525 60) 1) 4294967296) 2147483647)) (not (< main_~i~1 60)) (not (< v_prenex_2525 0)) (not (<= (mod (div v_prenex_2525 60) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_2525 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_261 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_261 60) 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_261 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_261 60) 1) 4294967296) 2147483647)) (and (not (< v_avg_~ret~0_BEFORE_RETURN_261 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_261 60) 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_261 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_261 60) 1) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_2525 60) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2525 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod (div v_prenex_2525 60) 4294967296) |main_#t~ret4|) (not (< v_prenex_2525 0))) (and (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_261 60))) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_261 60) 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_261 60) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_261 60) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_261 0)) (and (not (<= (mod (+ (div v_prenex_2525 60) 1) 4294967296) 2147483647)) (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_2525 60) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_2525 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_prenex_2525 60))) (and (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_261 60))) (not (< main_~i~1 60)) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_261 60) 1) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_261 60) 4294967296) 2147483647) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_261 60) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_261 0)) (and (not (<= (mod (+ (div v_prenex_2525 60) 1) 4294967296) 2147483647)) (< v_prenex_2525 0) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2525 60) 1) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_2525 60) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_2525 60)))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_261 0)) (not (< main_~i~1 60)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_261 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_261 60) 4294967296) 2147483647) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_261 60) 1) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_2525 60) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2525 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod (div v_prenex_2525 60) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_2525 60)))))) [2019-10-07 15:31:59,108 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:31:59,108 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:31:59,108 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:31:59,109 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:31:59,109 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:31:59,109 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:31:59,109 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:31:59,109 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:31:59,109 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:31:59,109 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:31:59,109 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:31:59,110 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:32:01,684 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:32:01,685 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 8, 8, 11] total 71 [2019-10-07 15:32:01,686 INFO L442 AbstractCegarLoop]: Interpolant automaton has 71 states [2019-10-07 15:32:01,687 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2019-10-07 15:32:01,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1292, Invalid=3677, Unknown=1, NotChecked=0, Total=4970 [2019-10-07 15:32:01,688 INFO L87 Difference]: Start difference. First operand 130 states and 134 transitions. Second operand 71 states. [2019-10-07 15:33:30,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:33:30,895 INFO L93 Difference]: Finished difference Result 201 states and 218 transitions. [2019-10-07 15:33:30,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2019-10-07 15:33:30,897 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 227 [2019-10-07 15:33:30,897 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:33:30,898 INFO L225 Difference]: With dead ends: 201 [2019-10-07 15:33:30,898 INFO L226 Difference]: Without dead ends: 138 [2019-10-07 15:33:30,900 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 796 GetRequests, 661 SyntacticMatches, 0 SemanticMatches, 135 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3617 ImplicationChecksByTransitivity, 68.4s TimeCoverageRelationStatistics Valid=4176, Invalid=14425, Unknown=31, NotChecked=0, Total=18632 [2019-10-07 15:33:30,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2019-10-07 15:33:30,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2019-10-07 15:33:30,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2019-10-07 15:33:30,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 142 transitions. [2019-10-07 15:33:30,912 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 142 transitions. Word has length 227 [2019-10-07 15:33:30,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:33:30,913 INFO L462 AbstractCegarLoop]: Abstraction has 138 states and 142 transitions. [2019-10-07 15:33:30,913 INFO L463 AbstractCegarLoop]: Interpolant automaton has 71 states. [2019-10-07 15:33:30,913 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 142 transitions. [2019-10-07 15:33:30,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 238 [2019-10-07 15:33:30,916 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:33:30,916 INFO L385 BasicCegarLoop]: trace histogram [141, 60, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:33:31,121 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:33:31,121 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:33:31,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:33:31,121 INFO L82 PathProgramCache]: Analyzing trace with hash 1496729781, now seen corresponding path program 12 times [2019-10-07 15:33:31,122 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:33:31,122 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:33:31,122 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:33:31,122 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:33:31,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:33:31,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:33:32,388 INFO L134 CoverageAnalysis]: Checked inductivity of 12210 backedges. 2305 proven. 3433 refuted. 0 times theorem prover too weak. 6472 trivial. 0 not checked. [2019-10-07 15:33:32,388 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:33:32,388 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:33:32,389 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:33:32,927 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:33:32,928 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:33:32,930 INFO L256 TraceCheckSpWp]: Trace formula consists of 1230 conjuncts, 49 conjunts are in the unsatisfiable core [2019-10-07 15:33:32,935 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:33:32,965 INFO L134 CoverageAnalysis]: Checked inductivity of 12210 backedges. 4610 proven. 1128 refuted. 0 times theorem prover too weak. 6472 trivial. 0 not checked. [2019-10-07 15:33:32,966 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:33:34,376 INFO L134 CoverageAnalysis]: Checked inductivity of 12210 backedges. 0 proven. 5738 refuted. 0 times theorem prover too weak. 6472 trivial. 0 not checked. [2019-10-07 15:33:34,376 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:33:34,378 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:33:34,378 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:33:34,378 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:33:34,378 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:33:34,379 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:33:34,395 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:33:50,130 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:33:50,148 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:33:50,150 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:33:50,150 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:33:50,150 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:33:50,151 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:33:50,151 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:33:50,151 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:33:50,151 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:33:50,151 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:33:50,151 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_2787 Int) (v_avg_~ret~0_BEFORE_RETURN_287 Int)) (or (and (not (< v_avg_~ret~0_BEFORE_RETURN_287 0)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 60) 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_287 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (mod (+ (div v_prenex_2787 60) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (not (= 0 (mod v_prenex_2787 60))) (<= (mod (+ (div v_prenex_2787 60) 1) 4294967296) 2147483647) (< v_prenex_2787 0)) (and (not (< v_avg_~ret~0_BEFORE_RETURN_287 0)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 60) 4294967296) 2147483647)) (and (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 60) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_287 60)) (not (< main_~i~1 60)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_287 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 60) 4294967296) |main_#t~ret4|) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_287 60)) (not (< main_~i~1 60)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_287 60) 4294967296) 2147483647)) (and (not (< main_~i~1 60)) (= (+ (mod (+ (div v_prenex_2787 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_prenex_2787 60))) (not (<= (mod (+ (div v_prenex_2787 60) 1) 4294967296) 2147483647)) (< v_prenex_2787 0)))) (exists ((v_prenex_2788 Int) (v_avg_~ret~0_BEFORE_RETURN_288 Int)) (or (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_288 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_288 60) 4294967296) 2147483647) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_288 60)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_288 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60))) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_288 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_288 60) 4294967296) 2147483647) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_288 60) 1) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_288 0)) (not (< main_~i~1 60))) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_288 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_288 60) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_288 0)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_288 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60))) (and (= (mod (div v_avg_~ret~0_BEFORE_RETURN_288 60) 4294967296) |main_#t~ret4|) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_288 60)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_288 60) 4294967296) 2147483647) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_288 60) 1) 4294967296) 2147483647)) (not (< main_~i~1 60))) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_288 60) 4294967296) 2147483647) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_288 60) 1) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_288 60))) (< v_avg_~ret~0_BEFORE_RETURN_288 0) (not (< main_~i~1 60)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_288 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_288 60) 4294967296) 2147483647) (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_288 60) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_288 60))) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_288 60) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_288 0) (not (< main_~i~1 60))) (and (<= (mod (+ (div v_prenex_2788 60) 1) 4294967296) 2147483647) (not (< v_prenex_2788 0)) (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_2788 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2788 60) 4294967296) 2147483647))) (and (not (< main_~i~1 60)) (not (= 0 (mod v_prenex_2788 60))) (not (<= (mod (div v_prenex_2788 60) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_2788 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_2788 60) 1) 4294967296) 2147483647)) (< v_prenex_2788 0)) (and (<= (mod (+ (div v_prenex_2788 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_2788 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2788 60) 4294967296) 2147483647)) (= 0 (mod v_prenex_2788 60))) (and (not (< v_prenex_2788 0)) (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_2788 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2788 60) 4294967296) 2147483647)) (not (<= (mod (+ (div v_prenex_2788 60) 1) 4294967296) 2147483647))) (and (<= (mod (+ (div v_prenex_2788 60) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_2788 60) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (not (= 0 (mod v_prenex_2788 60))) (not (<= (mod (div v_prenex_2788 60) 4294967296) 2147483647)) (< v_prenex_2788 0)) (and (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_2788 60) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2788 60) 4294967296) 2147483647)) (= 0 (mod v_prenex_2788 60)) (not (<= (mod (+ (div v_prenex_2788 60) 1) 4294967296) 2147483647)))))) [2019-10-07 15:33:50,152 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:33:50,152 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:33:50,152 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:33:50,152 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:33:50,152 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:33:50,152 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:33:50,152 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:33:50,153 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:33:50,153 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:33:50,153 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:33:50,153 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:33:50,153 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:33:52,706 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:33:52,706 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50, 11] total 73 [2019-10-07 15:33:52,707 INFO L442 AbstractCegarLoop]: Interpolant automaton has 73 states [2019-10-07 15:33:52,708 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2019-10-07 15:33:52,709 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1979, Invalid=3276, Unknown=1, NotChecked=0, Total=5256 [2019-10-07 15:33:52,709 INFO L87 Difference]: Start difference. First operand 138 states and 142 transitions. Second operand 73 states. [2019-10-07 15:34:24,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:34:24,048 INFO L93 Difference]: Finished difference Result 222 states and 244 transitions. [2019-10-07 15:34:24,050 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2019-10-07 15:34:24,050 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 237 [2019-10-07 15:34:24,050 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:34:24,051 INFO L225 Difference]: With dead ends: 222 [2019-10-07 15:34:24,052 INFO L226 Difference]: Without dead ends: 151 [2019-10-07 15:34:24,053 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 828 GetRequests, 654 SyntacticMatches, 36 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4397 ImplicationChecksByTransitivity, 21.7s TimeCoverageRelationStatistics Valid=6168, Invalid=13285, Unknown=7, NotChecked=0, Total=19460 [2019-10-07 15:34:24,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2019-10-07 15:34:24,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 151. [2019-10-07 15:34:24,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2019-10-07 15:34:24,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 155 transitions. [2019-10-07 15:34:24,065 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 155 transitions. Word has length 237 [2019-10-07 15:34:24,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:34:24,066 INFO L462 AbstractCegarLoop]: Abstraction has 151 states and 155 transitions. [2019-10-07 15:34:24,066 INFO L463 AbstractCegarLoop]: Interpolant automaton has 73 states. [2019-10-07 15:34:24,066 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 155 transitions. [2019-10-07 15:34:24,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 277 [2019-10-07 15:34:24,068 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:34:24,068 INFO L385 BasicCegarLoop]: trace histogram [180, 60, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:34:24,271 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:34:24,272 INFO L410 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:34:24,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:34:24,273 INFO L82 PathProgramCache]: Analyzing trace with hash 218025635, now seen corresponding path program 13 times [2019-10-07 15:34:24,273 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:34:24,273 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:34:24,273 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:34:24,274 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:34:24,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:34:24,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:34:24,867 INFO L134 CoverageAnalysis]: Checked inductivity of 18567 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:34:24,868 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:34:24,868 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:34:24,868 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:34:25,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:34:25,399 INFO L256 TraceCheckSpWp]: Trace formula consists of 1425 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:34:25,404 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:34:25,500 INFO L134 CoverageAnalysis]: Checked inductivity of 18567 backedges. 7446 proven. 78 refuted. 0 times theorem prover too weak. 11043 trivial. 0 not checked. [2019-10-07 15:34:25,500 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:34:25,924 INFO L134 CoverageAnalysis]: Checked inductivity of 18567 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:34:25,924 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:34:25,926 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:34:25,926 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:34:25,927 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:34:25,928 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:34:25,928 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:34:25,947 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:34:31,542 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:34:31,562 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:34:31,563 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:34:31,563 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:34:31,564 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:34:31,564 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:34:31,564 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:34:31,564 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:34:31,564 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:34:31,564 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:34:31,564 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_314 Int) (v_prenex_3086 Int)) (or (and (not (< main_~i~1 60)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_314 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_314 60) 4294967296) 2147483647)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_314 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_314 60) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_314 0)) (= (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_314 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_314 60) 4294967296)) (not (< main_~i~1 60)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_314 60)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_314 60) 4294967296) 2147483647)) (and (<= (mod (+ (div v_prenex_3086 60) 1) 4294967296) 2147483647) (< v_prenex_3086 0) (= |main_#t~ret4| (mod (+ (div v_prenex_3086 60) 1) 4294967296)) (not (< main_~i~1 60)) (not (= 0 (mod v_prenex_3086 60)))) (and (< v_prenex_3086 0) (= (+ (mod (+ (div v_prenex_3086 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_prenex_3086 60) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_3086 60)))) (and (= |main_#t~ret4| (mod (div v_avg_~ret~0_BEFORE_RETURN_314 60) 4294967296)) (not (< main_~i~1 60)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_314 60) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_314 0))))) (exists ((v_avg_~ret~0_BEFORE_RETURN_313 Int) (v_prenex_3085 Int)) (or (and (= (mod (div v_prenex_3085 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_3085 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (not (< v_prenex_3085 0))) (and (= (mod (div v_prenex_3085 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_3085 60) 4294967296) 2147483647) (not (< main_~i~1 60)) (= 0 (mod v_prenex_3085 60))) (and (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_313 60) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_313 60))) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_313 60) 1) 4294967296) 2147483647) (< v_avg_~ret~0_BEFORE_RETURN_313 0)) (and (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_3085 60) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_3085 60) 4294967296) (- 4294967296))) (= 0 (mod v_prenex_3085 60))) (and (not (< main_~i~1 60)) (not (<= (mod (div v_prenex_3085 60) 4294967296) 2147483647)) (not (< v_prenex_3085 0)) (= |main_#t~ret4| (+ (mod (div v_prenex_3085 60) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 60)) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_313 60) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_313 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_313 60))) (< v_avg_~ret~0_BEFORE_RETURN_313 0))))) [2019-10-07 15:34:31,564 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:34:31,564 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:34:31,565 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:34:31,565 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:34:31,565 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:34:31,565 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:34:31,565 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:34:31,565 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:34:31,565 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:34:31,565 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:34:31,565 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:34:31,566 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:34:33,856 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:34:33,856 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-07 15:34:33,857 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2019-10-07 15:34:33,858 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-10-07 15:34:33,858 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=431, Invalid=1050, Unknown=1, NotChecked=0, Total=1482 [2019-10-07 15:34:33,858 INFO L87 Difference]: Start difference. First operand 151 states and 155 transitions. Second operand 39 states. [2019-10-07 15:36:55,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:55,161 INFO L93 Difference]: Finished difference Result 233 states and 251 transitions. [2019-10-07 15:36:55,163 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-10-07 15:36:55,163 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 276 [2019-10-07 15:36:55,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:55,164 INFO L225 Difference]: With dead ends: 233 [2019-10-07 15:36:55,164 INFO L226 Difference]: Without dead ends: 165 [2019-10-07 15:36:55,165 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 876 GetRequests, 806 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1165 ImplicationChecksByTransitivity, 120.1s TimeCoverageRelationStatistics Valid=1286, Invalid=3767, Unknown=59, NotChecked=0, Total=5112 [2019-10-07 15:36:55,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2019-10-07 15:36:55,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 165. [2019-10-07 15:36:55,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2019-10-07 15:36:55,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 169 transitions. [2019-10-07 15:36:55,177 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 169 transitions. Word has length 276 [2019-10-07 15:36:55,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:55,178 INFO L462 AbstractCegarLoop]: Abstraction has 165 states and 169 transitions. [2019-10-07 15:36:55,178 INFO L463 AbstractCegarLoop]: Interpolant automaton has 39 states. [2019-10-07 15:36:55,178 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 169 transitions. [2019-10-07 15:36:55,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2019-10-07 15:36:55,180 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:55,180 INFO L385 BasicCegarLoop]: trace histogram [180, 60, 26, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:55,385 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:55,385 INFO L410 AbstractCegarLoop]: === Iteration 17 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:55,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:55,386 INFO L82 PathProgramCache]: Analyzing trace with hash -1402895101, now seen corresponding path program 14 times [2019-10-07 15:36:55,386 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:55,386 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:55,387 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:55,387 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:55,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:55,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:56,370 INFO L134 CoverageAnalysis]: Checked inductivity of 18840 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:36:56,371 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:56,371 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:56,371 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:59,988 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2019-10-07 15:36:59,988 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:59,996 INFO L256 TraceCheckSpWp]: Trace formula consists of 633 conjuncts, 52 conjunts are in the unsatisfiable core [2019-10-07 15:37:00,000 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:37:00,098 INFO L134 CoverageAnalysis]: Checked inductivity of 18840 backedges. 7506 proven. 351 refuted. 0 times theorem prover too weak. 10983 trivial. 0 not checked. [2019-10-07 15:37:00,098 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:37:01,105 INFO L134 CoverageAnalysis]: Checked inductivity of 18840 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:37:01,105 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:37:01,106 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:37:01,106 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:37:01,107 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:37:01,107 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:37:01,108 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:37:01,117 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:37:32,343 INFO L199 IcfgInterpreter]: Interpreting procedure avg with input of size 1 for LOIs [2019-10-07 15:37:32,359 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:37:32,362 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:37:32,362 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:37:32,362 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 695#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:37:32,362 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 460#true [2019-10-07 15:37:32,362 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 602#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:37:32,362 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 686#(<= 0 avg_~i~0) [2019-10-07 15:37:32,363 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:32,363 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:32,363 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_avg_~ret~0_BEFORE_RETURN_339 Int) (v_prenex_3323 Int)) (or (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_339 60) 1) 4294967296) 2147483647)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_339 60)) (not (< main_~i~1 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_339 60) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_339 60) 4294967296) (- 4294967296)))) (and (= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_339 60) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_339 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_339 60) 4294967296) 2147483647)) (< v_avg_~ret~0_BEFORE_RETURN_339 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_339 60)))) (and (not (< v_avg_~ret~0_BEFORE_RETURN_339 0)) (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_339 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_339 60) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_339 60) 4294967296) (- 4294967296)))) (and (= (+ (mod (+ (div v_prenex_3323 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_prenex_3323 60) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_3323 60))) (< v_prenex_3323 0) (<= (mod (div v_prenex_3323 60) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_339 60) 1) 4294967296) 2147483647)) (not (< main_~i~1 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_339 60) 4294967296) 2147483647)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_339 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_avg_~ret~0_BEFORE_RETURN_339 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_339 60)))) (and (= (mod (+ (div v_prenex_3323 60) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (not (= 0 (mod v_prenex_3323 60))) (<= (mod (+ (div v_prenex_3323 60) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_3323 60) 4294967296) 2147483647) (< v_prenex_3323 0)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_339 60) 1) 4294967296) 2147483647) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_339 60)) (not (< main_~i~1 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_339 60) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_339 60) 4294967296) (- 4294967296)))) (and (= (mod (div v_prenex_3323 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (= 0 (mod v_prenex_3323 60)) (not (<= (mod (+ (div v_prenex_3323 60) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_3323 60) 4294967296) 2147483647)) (and (= (mod (div v_prenex_3323 60) 4294967296) |main_#t~ret4|) (not (< v_prenex_3323 0)) (not (< main_~i~1 60)) (not (<= (mod (+ (div v_prenex_3323 60) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_3323 60) 4294967296) 2147483647)) (and (= (mod (div v_prenex_3323 60) 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (= 0 (mod v_prenex_3323 60)) (<= (mod (+ (div v_prenex_3323 60) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_3323 60) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_339 60) 1) 4294967296) 2147483647)) (not (< v_avg_~ret~0_BEFORE_RETURN_339 0)) (not (< main_~i~1 60)) (not (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_339 60) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_avg_~ret~0_BEFORE_RETURN_339 60) 4294967296) (- 4294967296)))) (and (= (mod (div v_prenex_3323 60) 4294967296) |main_#t~ret4|) (not (< v_prenex_3323 0)) (not (< main_~i~1 60)) (<= (mod (+ (div v_prenex_3323 60) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_3323 60) 4294967296) 2147483647)))) (exists ((v_prenex_3324 Int) (v_avg_~ret~0_BEFORE_RETURN_340 Int)) (or (and (not (<= (mod (div v_prenex_3324 60) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_3324 60))) (not (<= (mod (+ (div v_prenex_3324 60) 1) 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod (+ (div v_prenex_3324 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_prenex_3324 0)) (and (not (<= (mod (div v_prenex_3324 60) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_3324 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (= 0 (mod v_prenex_3324 60)) (= (+ (mod (div v_prenex_3324 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (div v_prenex_3324 60) 4294967296) 2147483647)) (= |main_#t~ret4| (mod (+ (div v_prenex_3324 60) 1) 4294967296)) (not (= 0 (mod v_prenex_3324 60))) (<= (mod (+ (div v_prenex_3324 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (< v_prenex_3324 0)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_340 60) 1) 4294967296) 2147483647) (not (< v_avg_~ret~0_BEFORE_RETURN_340 0)) (not (< main_~i~1 60)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_340 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_340 60) 4294967296) 2147483647)) (and (not (< main_~i~1 60)) (= (+ (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_340 60) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_avg_~ret~0_BEFORE_RETURN_340 0) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_340 60) 1) 4294967296) 2147483647)) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_340 60))) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_340 60) 4294967296) 2147483647)) (and (not (<= (mod (div v_prenex_3324 60) 4294967296) 2147483647)) (not (<= (mod (+ (div v_prenex_3324 60) 1) 4294967296) 2147483647)) (not (< main_~i~1 60)) (= 0 (mod v_prenex_3324 60)) (= (+ (mod (div v_prenex_3324 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_340 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_340 60)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_340 60) 4294967296) |main_#t~ret4|) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_340 60) 4294967296) 2147483647)) (and (not (<= (mod (div v_prenex_3324 60) 4294967296) 2147483647)) (not (< v_prenex_3324 0)) (not (<= (mod (+ (div v_prenex_3324 60) 1) 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_3324 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 60)) (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_340 60)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_340 60) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_340 60) 1) 4294967296) 2147483647)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_340 60) 4294967296) 2147483647)) (and (not (< v_prenex_3324 0)) (not (<= (mod (div v_prenex_3324 60) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_3324 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (= (+ (mod (div v_prenex_3324 60) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_340 60) 1) 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret4| (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_340 60) 1) 4294967296)) (< v_avg_~ret~0_BEFORE_RETURN_340 0) (not (= 0 (mod v_avg_~ret~0_BEFORE_RETURN_340 60))) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_340 60) 4294967296) 2147483647)) (and (not (< v_avg_~ret~0_BEFORE_RETURN_340 0)) (not (< main_~i~1 60)) (= (mod (div v_avg_~ret~0_BEFORE_RETURN_340 60) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_avg_~ret~0_BEFORE_RETURN_340 60) 1) 4294967296) 2147483647)) (<= (mod (div v_avg_~ret~0_BEFORE_RETURN_340 60) 4294967296) 2147483647))))) [2019-10-07 15:37:32,363 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 700#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:32,364 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 399#true [2019-10-07 15:37:32,364 INFO L193 IcfgInterpreter]: Reachable states at location avgEXIT satisfy 691#(and (<= 0 avg_~i~0) (<= 60 avg_~i~0) (not (< avg_~i~0 60)) (= (ite (<= (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) 2147483647) (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (+ (mod (ite (and (not (= (mod avg_~ret~0 60) 0)) (< avg_~ret~0 0)) (+ (div avg_~ret~0 60) 1) (div avg_~ret~0 60)) 4294967296) (- 4294967296))) |avg_#res|)) [2019-10-07 15:37:32,364 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:37:32,364 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 323#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:37:32,364 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 634#true [2019-10-07 15:37:32,364 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 597#true [2019-10-07 15:37:32,365 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:37:32,365 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 639#true [2019-10-07 15:37:32,365 INFO L193 IcfgInterpreter]: Reachable states at location avgENTRY satisfy 648#true [2019-10-07 15:37:32,365 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:37:32,365 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 239#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-07 15:37:33,325 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:37:33,325 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 30, 29, 11] total 68 [2019-10-07 15:37:33,327 INFO L442 AbstractCegarLoop]: Interpolant automaton has 68 states [2019-10-07 15:37:33,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2019-10-07 15:37:33,327 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1623, Invalid=2933, Unknown=0, NotChecked=0, Total=4556 [2019-10-07 15:37:33,328 INFO L87 Difference]: Start difference. First operand 165 states and 169 transitions. Second operand 68 states.