java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/array-crafted/bAnd1.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-06 22:48:36,999 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-06 22:48:37,002 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-06 22:48:37,020 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-06 22:48:37,021 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-06 22:48:37,023 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-06 22:48:37,025 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-06 22:48:37,037 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-06 22:48:37,040 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-06 22:48:37,042 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-06 22:48:37,043 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-06 22:48:37,044 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-06 22:48:37,044 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-06 22:48:37,045 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-06 22:48:37,046 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-06 22:48:37,047 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-06 22:48:37,049 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-06 22:48:37,050 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-06 22:48:37,053 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-06 22:48:37,056 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-06 22:48:37,058 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-06 22:48:37,059 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-06 22:48:37,060 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-06 22:48:37,061 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-06 22:48:37,067 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-06 22:48:37,080 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-06 22:48:37,082 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-06 22:48:37,086 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-06 22:48:37,087 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-06 22:48:37,107 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-06 22:48:37,108 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-06 22:48:37,110 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-06 22:48:37,110 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-06 22:48:37,111 INFO L138 SettingsManager]: * Use SBE=true [2019-10-06 22:48:37,111 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-06 22:48:37,111 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-06 22:48:37,111 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-06 22:48:37,111 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-06 22:48:37,112 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-06 22:48:37,113 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-06 22:48:37,113 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-06 22:48:37,113 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-06 22:48:37,114 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-06 22:48:37,114 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-06 22:48:37,114 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-06 22:48:37,114 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-06 22:48:37,114 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-06 22:48:37,115 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-06 22:48:37,115 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-06 22:48:37,115 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-06 22:48:37,115 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:37,115 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-06 22:48:37,115 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-06 22:48:37,116 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-06 22:48:37,116 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-06 22:48:37,116 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-06 22:48:37,116 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-06 22:48:37,116 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-06 22:48:37,432 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-06 22:48:37,446 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-06 22:48:37,449 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-06 22:48:37,451 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-06 22:48:37,451 INFO L275 PluginConnector]: CDTParser initialized [2019-10-06 22:48:37,452 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-crafted/bAnd1.i [2019-10-06 22:48:37,516 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cff8e0ab0/c101fe45abf741d890cbf8db9db172b8/FLAG9b2317d0a [2019-10-06 22:48:38,005 INFO L306 CDTParser]: Found 1 translation units. [2019-10-06 22:48:38,006 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-crafted/bAnd1.i [2019-10-06 22:48:38,012 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cff8e0ab0/c101fe45abf741d890cbf8db9db172b8/FLAG9b2317d0a [2019-10-06 22:48:38,375 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cff8e0ab0/c101fe45abf741d890cbf8db9db172b8 [2019-10-06 22:48:38,385 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-06 22:48:38,386 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-06 22:48:38,387 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,387 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-06 22:48:38,391 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-06 22:48:38,392 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,395 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@43c118f8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38, skipping insertion in model container [2019-10-06 22:48:38,395 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,402 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-06 22:48:38,420 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-06 22:48:38,648 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,663 INFO L188 MainTranslator]: Completed pre-run [2019-10-06 22:48:38,687 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,790 INFO L192 MainTranslator]: Completed translation [2019-10-06 22:48:38,790 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38 WrapperNode [2019-10-06 22:48:38,791 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,791 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-06 22:48:38,792 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-06 22:48:38,792 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-06 22:48:38,802 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,803 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,811 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,812 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,821 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,827 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,828 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,830 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-06 22:48:38,831 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-06 22:48:38,831 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-06 22:48:38,831 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-06 22:48:38,832 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:38,890 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-06 22:48:38,890 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-06 22:48:38,890 INFO L138 BoogieDeclarations]: Found implementation of procedure bAnd [2019-10-06 22:48:38,890 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-06 22:48:38,891 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-06 22:48:38,891 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-06 22:48:38,891 INFO L130 BoogieDeclarations]: Found specification of procedure bAnd [2019-10-06 22:48:38,891 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-06 22:48:38,891 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-06 22:48:38,891 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-06 22:48:38,892 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-06 22:48:38,892 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-06 22:48:38,892 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-06 22:48:38,892 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-06 22:48:39,299 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-06 22:48:39,299 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-06 22:48:39,300 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39 BoogieIcfgContainer [2019-10-06 22:48:39,301 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-06 22:48:39,302 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-06 22:48:39,302 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-06 22:48:39,305 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-06 22:48:39,306 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.10 10:48:38" (1/3) ... [2019-10-06 22:48:39,306 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1b694f7c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,307 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (2/3) ... [2019-10-06 22:48:39,307 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1b694f7c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,307 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39" (3/3) ... [2019-10-06 22:48:39,309 INFO L109 eAbstractionObserver]: Analyzing ICFG bAnd1.i [2019-10-06 22:48:39,319 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-06 22:48:39,327 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-06 22:48:39,338 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-06 22:48:39,363 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-06 22:48:39,363 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-06 22:48:39,363 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-06 22:48:39,364 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-06 22:48:39,364 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-06 22:48:39,364 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-06 22:48:39,364 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-06 22:48:39,364 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-06 22:48:39,379 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-06 22:48:39,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-06 22:48:39,384 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,385 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,386 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,391 INFO L82 PathProgramCache]: Analyzing trace with hash -1674969442, now seen corresponding path program 1 times [2019-10-06 22:48:39,398 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,399 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,399 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,399 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,572 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-06 22:48:39,572 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,573 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:39,577 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:39,585 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:39,599 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:39,600 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,603 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-06 22:48:39,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:39,640 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-06 22:48:39,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:39,642 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-06 22:48:39,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:39,652 INFO L225 Difference]: With dead ends: 41 [2019-10-06 22:48:39,652 INFO L226 Difference]: Without dead ends: 20 [2019-10-06 22:48:39,656 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-06 22:48:39,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-06 22:48:39,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-06 22:48:39,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-06 22:48:39,698 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-06 22:48:39,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:39,698 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-06 22:48:39,698 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:39,699 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-06 22:48:39,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-06 22:48:39,701 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,701 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,701 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,702 INFO L82 PathProgramCache]: Analyzing trace with hash -2035795135, now seen corresponding path program 1 times [2019-10-06 22:48:39,702 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,703 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,703 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,703 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,785 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:39,786 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,786 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:39,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:39,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,865 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-06 22:48:39,872 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:39,901 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:39,902 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:39,960 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:39,960 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-06 22:48:39,960 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-06 22:48:39,963 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:39,963 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:39,964 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:39,964 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-06 22:48:39,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:39,985 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-06 22:48:39,987 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:39,987 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-06 22:48:39,987 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:39,988 INFO L225 Difference]: With dead ends: 33 [2019-10-06 22:48:39,988 INFO L226 Difference]: Without dead ends: 21 [2019-10-06 22:48:39,989 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:39,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-06 22:48:39,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-06 22:48:39,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-06 22:48:40,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-06 22:48:40,001 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-06 22:48:40,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,002 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-06 22:48:40,002 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,003 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-06 22:48:40,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-06 22:48:40,006 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,006 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,207 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,207 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,209 INFO L82 PathProgramCache]: Analyzing trace with hash -629127273, now seen corresponding path program 1 times [2019-10-06 22:48:40,209 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,209 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,210 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,210 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,341 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,342 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,342 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:40,343 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:40,343 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,343 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,344 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,344 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-06 22:48:40,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,364 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-06 22:48:40,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,365 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-06 22:48:40,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,367 INFO L225 Difference]: With dead ends: 31 [2019-10-06 22:48:40,367 INFO L226 Difference]: Without dead ends: 22 [2019-10-06 22:48:40,368 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-06 22:48:40,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-06 22:48:40,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-06 22:48:40,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-06 22:48:40,381 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-06 22:48:40,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,388 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-06 22:48:40,388 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,393 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-06 22:48:40,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-06 22:48:40,394 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,395 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,395 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,395 INFO L82 PathProgramCache]: Analyzing trace with hash -1942163656, now seen corresponding path program 1 times [2019-10-06 22:48:40,396 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,396 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,399 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,400 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,552 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,552 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,552 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:40,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,641 INFO L256 TraceCheckSpWp]: Trace formula consists of 136 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,647 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,668 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,668 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,720 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,720 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:40,749 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:40,749 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:40,756 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:40,765 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:40,766 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:40,941 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:43,197 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:43,259 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:43,264 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:43,264 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:43,265 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:43,265 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_29 Int) (v_bAnd_~res~0_BEFORE_RETURN_6 Int) (v_bAnd_~res~0_BEFORE_RETURN_5 Int) (v_prenex_30 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (<= (mod v_prenex_29 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_29 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (not (< main_~i~2 99)) (<= (mod v_prenex_30 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (not (< main_~i~2 99)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_bAnd_~res~0_BEFORE_RETURN_6 Int) (v_bAnd_~res~0_BEFORE_RETURN_5 Int) (v_prenex_30 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (<= (mod v_prenex_29 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_29 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (not (< main_~i~2 99)) (<= (mod v_prenex_30 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (not (< main_~i~2 99)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 22:48:43,266 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:48:43,266 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_2 Int) (v_bAnd_~res~0_BEFORE_RETURN_1 Int) (v_prenex_2 Int) (v_prenex_1 Int)) (or (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) main_~ret~0) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1 4294967296) 2147483647))))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_2 Int) (v_bAnd_~res~0_BEFORE_RETURN_1 Int) (v_prenex_2 Int) (v_prenex_1 Int)) (or (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) main_~ret~0) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) main_~ret~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647))))) [2019-10-06 22:48:43,266 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:43,266 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:43,267 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:43,267 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:43,267 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:43,267 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:43,267 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:43,268 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:43,268 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:48:43,268 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:48:43,268 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) |main_#t~ret5|) (not (< main_~i~1 100))) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_1 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_1 4294967296) 2147483647))))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_2 Int) (v_prenex_2 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) |main_#t~ret5|)) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 22:48:43,269 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:43,269 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:43,269 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:43,269 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:45,906 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:45,906 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-06 22:48:45,908 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-06 22:48:45,910 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-06 22:48:45,911 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=255, Unknown=1, NotChecked=0, Total=306 [2019-10-06 22:48:45,911 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-06 22:48:46,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:46,660 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-06 22:48:46,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-06 22:48:46,660 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-06 22:48:46,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:46,661 INFO L225 Difference]: With dead ends: 40 [2019-10-06 22:48:46,661 INFO L226 Difference]: Without dead ends: 25 [2019-10-06 22:48:46,662 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=133, Invalid=736, Unknown=1, NotChecked=0, Total=870 [2019-10-06 22:48:46,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-06 22:48:46,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-06 22:48:46,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-06 22:48:46,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-06 22:48:46,669 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-06 22:48:46,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:46,669 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-06 22:48:46,670 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-06 22:48:46,670 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-06 22:48:46,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-06 22:48:46,671 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:46,671 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:46,873 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:46,874 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:46,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:46,875 INFO L82 PathProgramCache]: Analyzing trace with hash 143191253, now seen corresponding path program 2 times [2019-10-06 22:48:46,875 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:46,876 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:46,876 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:46,876 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:46,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:46,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:46,980 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:46,980 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:46,980 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:46,980 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:47,058 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-06 22:48:47,058 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:48:47,060 INFO L256 TraceCheckSpWp]: Trace formula consists of 106 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:47,062 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:47,082 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:48:47,082 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:47,117 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:48:47,117 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:47,120 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:47,120 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:47,121 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:47,121 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:47,121 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:47,147 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:48,567 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:48,593 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:48,597 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:48,597 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:48,597 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:48,598 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_prenex_223 Int) (v_bAnd_~res~0_BEFORE_RETURN_32 Int)) (or (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (< main_~i~2 99)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_prenex_223 Int) (v_bAnd_~res~0_BEFORE_RETURN_32 Int)) (or (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (< main_~i~2 99)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 22:48:48,598 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:48:48,598 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_196 Int) (v_bAnd_~res~0_BEFORE_RETURN_27 Int) (v_bAnd_~res~0_BEFORE_RETURN_28 Int) (v_prenex_195 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296))) (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_195 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_195 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296) 2147483647)))) [2019-10-06 22:48:48,599 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:48,599 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:48,599 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:48,599 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:48,599 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:48,600 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:48,600 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:48,600 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:48,600 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:48:48,600 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:48:48,600 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (not (< main_~i~1 100)) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296) 2147483647)) (and (= (+ (mod v_prenex_195 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 100)) (not (<= (mod v_prenex_195 4294967296) 2147483647))))) (exists ((v_prenex_196 Int) (v_bAnd_~res~0_BEFORE_RETURN_28 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296) |main_#t~ret5|))))) [2019-10-06 22:48:48,601 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:48,601 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:48,601 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:48,601 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:49,019 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:49,019 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-06 22:48:49,022 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-06 22:48:49,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-06 22:48:49,023 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-06 22:48:49,023 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-06 22:48:51,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:51,978 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-06 22:48:51,978 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-06 22:48:51,978 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-06 22:48:51,979 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:51,979 INFO L225 Difference]: With dead ends: 44 [2019-10-06 22:48:51,979 INFO L226 Difference]: Without dead ends: 29 [2019-10-06 22:48:51,980 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-06 22:48:51,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-06 22:48:51,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-06 22:48:51,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-06 22:48:51,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-06 22:48:51,987 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-06 22:48:51,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:51,988 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-06 22:48:51,988 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-06 22:48:51,988 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-06 22:48:51,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-06 22:48:51,989 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:51,989 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:52,193 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:52,193 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:52,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:52,194 INFO L82 PathProgramCache]: Analyzing trace with hash 766317228, now seen corresponding path program 3 times [2019-10-06 22:48:52,194 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:52,194 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:52,194 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:52,195 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:52,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:52,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:52,288 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:52,288 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:52,289 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:52,289 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:52,410 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:48:52,410 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:48:52,411 INFO L256 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-06 22:48:52,427 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:52,438 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:52,439 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:52,507 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:52,507 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:52,510 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:52,510 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:52,510 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:52,511 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:52,511 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:52,535 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:54,279 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:54,306 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:54,309 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:54,309 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:54,309 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:54,310 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_58 Int) (v_prenex_417 Int) (v_bAnd_~res~0_BEFORE_RETURN_57 Int) (v_prenex_418 Int)) (or (and (not (< main_~i~2 99)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) 2147483647))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= (mod v_prenex_417 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_prenex_418 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_418 4294967296) 2147483647))))) (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_58 Int) (v_prenex_417 Int) (v_bAnd_~res~0_BEFORE_RETURN_57 Int) (v_prenex_418 Int)) (or (and (not (< main_~i~2 99)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) 2147483647))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= (mod v_prenex_417 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_prenex_418 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_418 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:48:54,310 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:48:54,310 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int) (v_prenex_390 Int) (v_bAnd_~res~0_BEFORE_RETURN_54 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= (mod v_prenex_389 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) main_~ret~0) (<= main_~ret~0 2147483647) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) 2147483647)))) [2019-10-06 22:48:54,310 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:54,311 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:54,311 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:54,311 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:54,311 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:54,311 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:54,312 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:54,312 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:54,312 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:48:54,312 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:48:54,312 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_390 Int) (v_bAnd_~res~0_BEFORE_RETURN_54 Int)) (or (and (not (< main_~i~1 100)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) |main_#t~ret5|) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_prenex_390 4294967296) (- 4294967296)))))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_prenex_389 4294967296) 2147483647) (= (mod v_prenex_389 4294967296) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) (- 4294967296))))))) [2019-10-06 22:48:54,312 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:54,313 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:54,313 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:54,313 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:54,650 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:54,650 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-06 22:48:54,652 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-06 22:48:54,652 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-06 22:48:54,653 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-06 22:48:54,653 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-06 22:48:55,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:55,685 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-06 22:48:55,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-06 22:48:55,685 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-06 22:48:55,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:55,687 INFO L225 Difference]: With dead ends: 54 [2019-10-06 22:48:55,687 INFO L226 Difference]: Without dead ends: 36 [2019-10-06 22:48:55,688 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-06 22:48:55,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-06 22:48:55,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-06 22:48:55,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-06 22:48:55,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-06 22:48:55,696 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-06 22:48:55,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:55,696 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-06 22:48:55,696 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-06 22:48:55,696 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-06 22:48:55,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-06 22:48:55,698 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:55,698 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:55,906 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:55,907 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:55,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:55,907 INFO L82 PathProgramCache]: Analyzing trace with hash 615727983, now seen corresponding path program 4 times [2019-10-06 22:48:55,908 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:55,908 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:55,908 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:55,908 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:55,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:55,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:56,067 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:56,067 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:56,067 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:56,067 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:56,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:56,220 INFO L256 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-06 22:48:56,230 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:56,243 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:56,243 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:56,551 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:56,551 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:56,553 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:56,553 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:56,553 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:56,554 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:56,554 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:56,576 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:57,902 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:57,922 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:57,925 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:57,926 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:57,926 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:57,927 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_bAnd_~res~0_BEFORE_RETURN_83 Int) (v_bAnd_~res~0_BEFORE_RETURN_84 Int)) (or (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (<= (mod v_prenex_611 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (not (< main_~i~2 99)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) 2147483647)) (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647)))))) (and (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_bAnd_~res~0_BEFORE_RETURN_83 Int) (v_bAnd_~res~0_BEFORE_RETURN_84 Int)) (or (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (<= (mod v_prenex_611 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (not (< main_~i~2 99)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) 2147483647)) (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:48:57,927 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:48:57,927 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_583 Int) (v_bAnd_~res~0_BEFORE_RETURN_80 Int) (v_prenex_584 Int) (v_bAnd_~res~0_BEFORE_RETURN_79 Int)) (or (and (not (< main_~i~1 100)) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) main_~ret~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_prenex_584 4294967296) main_~ret~0) (<= (mod v_prenex_584 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (<= (mod v_prenex_583 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_583 4294967296)) (<= main_~ret~0 2147483647)))) [2019-10-06 22:48:57,927 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:57,927 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:57,928 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:57,928 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:57,928 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:57,928 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:57,928 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:57,928 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:57,929 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:48:57,929 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:48:57,929 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_80 Int) (v_prenex_584 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (= |main_#t~ret5| (mod v_prenex_584 4294967296)) (<= (mod v_prenex_584 4294967296) 2147483647)))) (exists ((v_prenex_583 Int) (v_bAnd_~res~0_BEFORE_RETURN_79 Int)) (or (and (not (< main_~i~1 100)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (<= (mod v_prenex_583 4294967296) 2147483647) (= |main_#t~ret5| (mod v_prenex_583 4294967296)))))) [2019-10-06 22:48:57,929 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:57,929 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:57,930 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:57,930 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:58,311 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:58,312 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-06 22:48:58,313 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-06 22:48:58,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-06 22:48:58,316 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-06 22:48:58,316 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 40 states. [2019-10-06 22:48:59,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:59,894 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-06 22:48:59,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-06 22:48:59,894 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 49 [2019-10-06 22:48:59,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:59,896 INFO L225 Difference]: With dead ends: 68 [2019-10-06 22:48:59,896 INFO L226 Difference]: Without dead ends: 50 [2019-10-06 22:48:59,898 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-06 22:48:59,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-06 22:48:59,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-06 22:48:59,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-06 22:48:59,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-06 22:48:59,908 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-06 22:48:59,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:59,908 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-06 22:48:59,909 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-06 22:48:59,909 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-06 22:48:59,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-06 22:48:59,911 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:59,911 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:00,120 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:00,121 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:00,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:00,121 INFO L82 PathProgramCache]: Analyzing trace with hash 2121294031, now seen corresponding path program 5 times [2019-10-06 22:49:00,121 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:00,121 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:00,121 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:00,122 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:00,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:00,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:00,542 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:49:00,542 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:00,542 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:00,542 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:00,719 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:49:00,719 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:00,720 INFO L256 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:49:00,729 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:00,774 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-06 22:49:00,774 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:00,816 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-06 22:49:00,816 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:00,817 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:00,818 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:00,818 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:00,818 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:00,818 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:00,847 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:02,060 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:02,087 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:02,089 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:02,089 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:02,089 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:02,090 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_806 Int) (v_prenex_805 Int) (v_bAnd_~res~0_BEFORE_RETURN_109 Int) (v_bAnd_~res~0_BEFORE_RETURN_110 Int)) (or (and (not (< main_~i~2 99)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_prenex_805 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) (- 4294967296))) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) 2147483647))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_806 Int) (v_prenex_805 Int) (v_bAnd_~res~0_BEFORE_RETURN_109 Int) (v_bAnd_~res~0_BEFORE_RETURN_110 Int)) (or (and (not (< main_~i~2 99)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_prenex_805 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) (- 4294967296))) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) 2147483647))))))) [2019-10-06 22:49:02,090 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:49:02,090 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_777 Int) (v_bAnd_~res~0_BEFORE_RETURN_106 Int) (v_bAnd_~res~0_BEFORE_RETURN_105 Int) (v_prenex_778 Int)) (or (and (<= (mod v_prenex_777 4294967296) 2147483647) (not (< main_~i~1 100)) (= main_~ret~0 (mod v_prenex_777 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 100)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-06 22:49:02,090 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:02,091 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:02,091 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:02,091 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:49:02,091 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:02,091 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:02,091 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:02,092 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:02,092 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:49:02,092 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:49:02,092 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_777 Int) (v_bAnd_~res~0_BEFORE_RETURN_105 Int)) (or (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 100)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) 2147483647))) (and (<= (mod v_prenex_777 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod v_prenex_777 4294967296) |main_#t~ret5|)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296) 2147483647) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296)))))) [2019-10-06 22:49:02,092 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:02,092 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:02,093 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:02,093 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:02,603 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:02,604 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-06 22:49:02,605 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-06 22:49:02,605 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-06 22:49:02,606 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-06 22:49:02,607 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 44 states. [2019-10-06 22:49:08,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:08,778 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-06 22:49:08,778 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-06 22:49:08,778 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 63 [2019-10-06 22:49:08,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:08,780 INFO L225 Difference]: With dead ends: 72 [2019-10-06 22:49:08,780 INFO L226 Difference]: Without dead ends: 54 [2019-10-06 22:49:08,783 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1348 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=1349, Invalid=5455, Unknown=2, NotChecked=0, Total=6806 [2019-10-06 22:49:08,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-06 22:49:08,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-06 22:49:08,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-06 22:49:08,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-06 22:49:08,792 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-06 22:49:08,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:08,792 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-06 22:49:08,792 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-06 22:49:08,792 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-06 22:49:08,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-06 22:49:08,794 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:08,794 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:08,997 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:08,998 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:08,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:08,998 INFO L82 PathProgramCache]: Analyzing trace with hash -1728770399, now seen corresponding path program 6 times [2019-10-06 22:49:08,999 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:08,999 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:08,999 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:08,999 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:09,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:09,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:09,394 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:09,395 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:09,395 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:09,395 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:09,631 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:49:09,631 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:09,632 INFO L256 TraceCheckSpWp]: Trace formula consists of 331 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-06 22:49:09,635 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:09,650 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:09,651 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:10,673 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:10,674 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:10,675 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:10,675 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:10,676 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:10,676 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:10,676 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:10,700 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:12,049 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:12,076 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:12,079 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:12,079 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:12,079 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:12,080 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_135 Int) (v_bAnd_~res~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_1000 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 99)) (= (mod v_prenex_999 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_135 Int) (v_bAnd_~res~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_1000 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 99)) (= (mod v_prenex_999 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 22:49:12,080 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:49:12,080 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_bAnd_~res~0_BEFORE_RETURN_131 Int) (v_bAnd_~res~0_BEFORE_RETURN_132 Int)) (or (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) main_~ret~0) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296) 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) (exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_bAnd_~res~0_BEFORE_RETURN_131 Int) (v_bAnd_~res~0_BEFORE_RETURN_132 Int)) (or (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) main_~ret~0) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647))))) [2019-10-06 22:49:12,080 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:12,081 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:12,081 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:12,081 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:12,081 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:12,081 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:12,081 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:12,082 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:12,082 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:49:12,082 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:49:12,082 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_971 Int) (v_bAnd_~res~0_BEFORE_RETURN_131 Int)) (or (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (= (+ (mod v_prenex_971 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 100))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) |main_#t~ret5|) (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) 2147483647)))) (exists ((v_prenex_972 Int) (v_bAnd_~res~0_BEFORE_RETURN_132 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296) 2147483647) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296))) (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (= (+ (mod v_prenex_972 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 22:49:12,082 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:12,083 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:12,083 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:12,083 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:12,673 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:12,673 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-06 22:49:12,674 INFO L442 AbstractCegarLoop]: Interpolant automaton has 70 states [2019-10-06 22:49:12,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2019-10-06 22:49:12,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1740, Invalid=3090, Unknown=0, NotChecked=0, Total=4830 [2019-10-06 22:49:12,677 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 70 states. [2019-10-06 22:49:16,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:16,142 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-06 22:49:16,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2019-10-06 22:49:16,143 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 67 [2019-10-06 22:49:16,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:16,144 INFO L225 Difference]: With dead ends: 104 [2019-10-06 22:49:16,144 INFO L226 Difference]: Without dead ends: 83 [2019-10-06 22:49:16,149 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3929 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=5099, Invalid=12723, Unknown=0, NotChecked=0, Total=17822 [2019-10-06 22:49:16,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-06 22:49:16,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-06 22:49:16,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-06 22:49:16,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-06 22:49:16,159 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-06 22:49:16,160 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:16,160 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-06 22:49:16,160 INFO L463 AbstractCegarLoop]: Interpolant automaton has 70 states. [2019-10-06 22:49:16,160 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-06 22:49:16,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-06 22:49:16,162 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:16,162 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:16,364 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:16,365 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:16,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:16,366 INFO L82 PathProgramCache]: Analyzing trace with hash 1695588190, now seen corresponding path program 7 times [2019-10-06 22:49:16,366 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:16,366 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:16,367 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:16,367 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:16,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:16,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:17,725 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:17,726 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:17,726 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:17,726 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:18,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:18,002 INFO L256 TraceCheckSpWp]: Trace formula consists of 505 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-06 22:49:18,005 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:18,025 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:18,026 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:21,000 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:21,000 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:21,002 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:21,002 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:21,002 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:21,002 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:21,003 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:21,017 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:22,137 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:22,161 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:22,163 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:22,164 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:22,164 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:22,164 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_161 Int) (v_prenex_1194 Int) (v_prenex_1193 Int) (v_bAnd_~res~0_BEFORE_RETURN_162 Int)) (or (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_162 4294967296) 2147483647))) (and (not (< main_~i~2 99)) (<= (mod v_prenex_1193 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296))) (and (not (< main_~i~2 99)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_161 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)))))) (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_161 Int) (v_prenex_1194 Int) (v_prenex_1193 Int) (v_bAnd_~res~0_BEFORE_RETURN_162 Int)) (or (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_162 4294967296) 2147483647))) (and (not (< main_~i~2 99)) (<= (mod v_prenex_1193 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296))) (and (not (< main_~i~2 99)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_161 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:49:22,164 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:49:22,164 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_157 Int) (v_bAnd_~res~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int) (v_prenex_1165 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_157 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_bAnd_~res~0_BEFORE_RETURN_157 4294967296) main_~ret~0) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_prenex_1166 4294967296))) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1165 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_158 4294967296) 2147483647)) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_158 4294967296) (- 4294967296)))))) [2019-10-06 22:49:22,165 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:22,165 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:22,165 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:22,165 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:22,165 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:22,165 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:22,166 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:22,166 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:22,166 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:49:22,166 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:49:22,166 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_157 Int) (v_prenex_1165 Int)) (or (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_157 4294967296) |main_#t~ret5|) (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_157 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_1165 4294967296) 2147483647)) (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) |main_#t~ret5|)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int)) (or (and (not (< main_~i~1 100)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_158 4294967296) 2147483647))) (and (= (mod v_prenex_1166 4294967296) |main_#t~ret5|) (not (< main_~i~1 100)) (<= (mod v_prenex_1166 4294967296) 2147483647))))) [2019-10-06 22:49:22,166 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:22,166 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:22,167 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:22,167 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:22,913 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:22,914 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 113 [2019-10-06 22:49:22,915 INFO L442 AbstractCegarLoop]: Interpolant automaton has 114 states [2019-10-06 22:49:22,916 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 114 interpolants. [2019-10-06 22:49:22,921 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5282, Invalid=7600, Unknown=0, NotChecked=0, Total=12882 [2019-10-06 22:49:22,921 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 114 states. [2019-10-06 22:49:30,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:30,988 INFO L93 Difference]: Finished difference Result 148 states and 199 transitions. [2019-10-06 22:49:30,988 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 113 states. [2019-10-06 22:49:30,988 INFO L78 Accepts]: Start accepts. Automaton has 114 states. Word has length 96 [2019-10-06 22:49:30,989 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:30,990 INFO L225 Difference]: With dead ends: 148 [2019-10-06 22:49:30,990 INFO L226 Difference]: Without dead ends: 127 [2019-10-06 22:49:30,995 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 457 GetRequests, 223 SyntacticMatches, 14 SemanticMatches, 220 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9999 ImplicationChecksByTransitivity, 12.4s TimeCoverageRelationStatistics Valid=15637, Invalid=33425, Unknown=0, NotChecked=0, Total=49062 [2019-10-06 22:49:30,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2019-10-06 22:49:31,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 127. [2019-10-06 22:49:31,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127 states. [2019-10-06 22:49:31,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 131 transitions. [2019-10-06 22:49:31,009 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 131 transitions. Word has length 96 [2019-10-06 22:49:31,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:31,009 INFO L462 AbstractCegarLoop]: Abstraction has 127 states and 131 transitions. [2019-10-06 22:49:31,009 INFO L463 AbstractCegarLoop]: Interpolant automaton has 114 states. [2019-10-06 22:49:31,010 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 131 transitions. [2019-10-06 22:49:31,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-10-06 22:49:31,012 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:31,012 INFO L385 BasicCegarLoop]: trace histogram [100, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:31,217 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:31,217 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:31,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:31,218 INFO L82 PathProgramCache]: Analyzing trace with hash -473761890, now seen corresponding path program 8 times [2019-10-06 22:49:31,218 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:31,219 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:31,219 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:31,219 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:31,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:31,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:31,406 INFO L134 CoverageAnalysis]: Checked inductivity of 5171 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 5109 trivial. 0 not checked. [2019-10-06 22:49:31,406 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:31,406 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:31,407 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:31,672 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:49:31,672 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:31,673 INFO L256 TraceCheckSpWp]: Trace formula consists of 141 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 22:49:31,677 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:31,703 INFO L134 CoverageAnalysis]: Checked inductivity of 5171 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 5109 trivial. 0 not checked. [2019-10-06 22:49:31,704 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:31,770 INFO L134 CoverageAnalysis]: Checked inductivity of 5171 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 5109 trivial. 0 not checked. [2019-10-06 22:49:31,770 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:31,773 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:31,773 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:31,773 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:31,774 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:31,774 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:31,790 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:32,941 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:32,973 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:32,974 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:32,975 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:32,975 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:32,975 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_188 Int) (v_prenex_1388 Int) (v_prenex_1387 Int) (v_bAnd_~res~0_BEFORE_RETURN_187 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_187 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_187 4294967296) 2147483647))) (and (not (< main_~i~2 99)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_188 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= (mod v_prenex_1388 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_188 Int) (v_prenex_1388 Int) (v_prenex_1387 Int) (v_bAnd_~res~0_BEFORE_RETURN_187 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_187 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_187 4294967296) 2147483647))) (and (not (< main_~i~2 99)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_188 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= (mod v_prenex_1388 4294967296) 2147483647)))))) [2019-10-06 22:49:32,975 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:49:32,975 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_prenex_1359 Int) (v_bAnd_~res~0_BEFORE_RETURN_183 Int) (v_prenex_1360 Int) (v_bAnd_~res~0_BEFORE_RETURN_184 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1360 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) main_~ret~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 100)) (= main_~ret~0 (mod v_prenex_1359 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1359 4294967296) 2147483647)))) (exists ((v_prenex_1359 Int) (v_bAnd_~res~0_BEFORE_RETURN_183 Int) (v_prenex_1360 Int) (v_bAnd_~res~0_BEFORE_RETURN_184 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1360 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) main_~ret~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= main_~ret~0 (mod v_prenex_1359 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1359 4294967296) 2147483647)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)) main_~ret~0))))) [2019-10-06 22:49:32,976 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:32,976 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:32,976 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:32,976 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:32,977 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:32,977 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:32,977 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:32,977 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:32,977 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:49:32,977 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:49:32,977 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1360 Int) (v_bAnd_~res~0_BEFORE_RETURN_184 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_1360 4294967296) 2147483647))))) (exists ((v_prenex_1359 Int) (v_bAnd_~res~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 100)) (= (mod v_prenex_1359 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1359 4294967296) 2147483647)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 22:49:32,978 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:32,978 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:32,978 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:32,978 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:33,266 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:33,266 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 23 [2019-10-06 22:49:33,268 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-10-06 22:49:33,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-10-06 22:49:33,269 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=108, Invalid=444, Unknown=0, NotChecked=0, Total=552 [2019-10-06 22:49:33,269 INFO L87 Difference]: Start difference. First operand 127 states and 131 transitions. Second operand 24 states. [2019-10-06 22:49:34,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:34,225 INFO L93 Difference]: Finished difference Result 153 states and 168 transitions. [2019-10-06 22:49:34,225 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-10-06 22:49:34,225 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 140 [2019-10-06 22:49:34,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:34,227 INFO L225 Difference]: With dead ends: 153 [2019-10-06 22:49:34,228 INFO L226 Difference]: Without dead ends: 133 [2019-10-06 22:49:34,229 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 444 GetRequests, 404 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 428 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=353, Invalid=1369, Unknown=0, NotChecked=0, Total=1722 [2019-10-06 22:49:34,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2019-10-06 22:49:34,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 133. [2019-10-06 22:49:34,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2019-10-06 22:49:34,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 137 transitions. [2019-10-06 22:49:34,244 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 137 transitions. Word has length 140 [2019-10-06 22:49:34,244 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:34,244 INFO L462 AbstractCegarLoop]: Abstraction has 133 states and 137 transitions. [2019-10-06 22:49:34,244 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-10-06 22:49:34,245 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 137 transitions. [2019-10-06 22:49:34,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2019-10-06 22:49:34,247 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:34,247 INFO L385 BasicCegarLoop]: trace histogram [100, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:34,450 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:34,451 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:34,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:34,452 INFO L82 PathProgramCache]: Analyzing trace with hash -890327394, now seen corresponding path program 9 times [2019-10-06 22:49:34,452 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:34,452 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:34,453 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:34,453 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:34,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:34,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:34,709 INFO L134 CoverageAnalysis]: Checked inductivity of 5594 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 5295 trivial. 0 not checked. [2019-10-06 22:49:34,710 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:34,710 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:34,710 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:35,074 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:49:35,075 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:35,078 INFO L256 TraceCheckSpWp]: Trace formula consists of 823 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-06 22:49:35,082 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:35,108 INFO L134 CoverageAnalysis]: Checked inductivity of 5594 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 5295 trivial. 0 not checked. [2019-10-06 22:49:35,108 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:35,292 INFO L134 CoverageAnalysis]: Checked inductivity of 5594 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 5295 trivial. 0 not checked. [2019-10-06 22:49:35,292 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:35,293 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:35,293 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:35,294 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:35,294 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:35,294 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:35,305 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:36,365 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:36,383 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:36,387 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:36,387 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:36,387 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:36,387 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_213 Int) (v_bAnd_~res~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (< main_~i~2 99)) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_214 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_214 4294967296) main_~ret5~0)) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 99)) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_213 4294967296) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_213 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_213 Int) (v_bAnd_~res~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (< main_~i~2 99)) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_214 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_214 4294967296) main_~ret5~0)) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 99)) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_213 4294967296) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_213 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 22:49:36,388 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:49:36,388 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_bAnd_~res~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= main_~ret~0 (mod v_prenex_1553 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1553 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)) (<= main_~ret~0 2147483647)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_bAnd_~res~0_BEFORE_RETURN_209 Int)) (or (and (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= main_~ret~0 (mod v_prenex_1553 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1553 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) main_~ret~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647))))) [2019-10-06 22:49:36,388 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:36,388 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:36,388 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:36,388 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:49:36,389 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:36,389 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:36,389 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:36,389 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:36,389 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:49:36,389 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:49:36,390 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_1554 4294967296) 2147483647))))) (exists ((v_prenex_1553 Int) (v_bAnd_~res~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (= (mod v_prenex_1553 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1553 4294967296) 2147483647))))) [2019-10-06 22:49:36,390 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:36,390 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:36,390 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:36,390 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:36,803 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:36,803 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 11] total 35 [2019-10-06 22:49:36,804 INFO L442 AbstractCegarLoop]: Interpolant automaton has 36 states [2019-10-06 22:49:36,805 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2019-10-06 22:49:36,805 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=330, Invalid=930, Unknown=0, NotChecked=0, Total=1260 [2019-10-06 22:49:36,805 INFO L87 Difference]: Start difference. First operand 133 states and 137 transitions. Second operand 36 states. [2019-10-06 22:49:38,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:38,394 INFO L93 Difference]: Finished difference Result 171 states and 192 transitions. [2019-10-06 22:49:38,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-10-06 22:49:38,394 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 158 [2019-10-06 22:49:38,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:38,396 INFO L225 Difference]: With dead ends: 171 [2019-10-06 22:49:38,396 INFO L226 Difference]: Without dead ends: 145 [2019-10-06 22:49:38,397 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 516 GetRequests, 452 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1043 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1067, Invalid=3223, Unknown=0, NotChecked=0, Total=4290 [2019-10-06 22:49:38,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2019-10-06 22:49:38,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 145. [2019-10-06 22:49:38,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2019-10-06 22:49:38,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 149 transitions. [2019-10-06 22:49:38,413 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 149 transitions. Word has length 158 [2019-10-06 22:49:38,413 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:38,414 INFO L462 AbstractCegarLoop]: Abstraction has 145 states and 149 transitions. [2019-10-06 22:49:38,414 INFO L463 AbstractCegarLoop]: Interpolant automaton has 36 states. [2019-10-06 22:49:38,414 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 149 transitions. [2019-10-06 22:49:38,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2019-10-06 22:49:38,416 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:38,416 INFO L385 BasicCegarLoop]: trace histogram [100, 66, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:38,621 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:38,622 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:38,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:38,622 INFO L82 PathProgramCache]: Analyzing trace with hash -2083832674, now seen corresponding path program 10 times [2019-10-06 22:49:38,623 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:38,623 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:38,623 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:38,624 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:38,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:38,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:38,901 INFO L134 CoverageAnalysis]: Checked inductivity of 7412 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7402 trivial. 0 not checked. [2019-10-06 22:49:38,901 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:38,902 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:38,902 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:39,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:39,321 INFO L256 TraceCheckSpWp]: Trace formula consists of 931 conjuncts, 24 conjunts are in the unsatisfiable core [2019-10-06 22:49:39,325 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:39,708 INFO L134 CoverageAnalysis]: Checked inductivity of 7412 backedges. 1060 proven. 253 refuted. 0 times theorem prover too weak. 6099 trivial. 0 not checked. [2019-10-06 22:49:39,708 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:40,455 INFO L134 CoverageAnalysis]: Checked inductivity of 7412 backedges. 0 proven. 1313 refuted. 0 times theorem prover too weak. 6099 trivial. 0 not checked. [2019-10-06 22:49:40,455 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:40,456 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:40,456 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:40,457 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:40,457 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:40,457 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:40,473 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:41,651 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:41,694 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:41,697 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:41,697 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:41,698 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret5~0)) (exists ((v_prenex_1776 Int) (v_prenex_1775 Int) (v_bAnd_~res~0_BEFORE_RETURN_239 Int) (v_bAnd_~res~0_BEFORE_RETURN_240 Int)) (or (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_240 4294967296) 2147483647)) (not (< main_~i~2 99)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_240 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1776 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1776 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (<= (mod v_prenex_1775 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_239 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)))))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_1776 Int) (v_prenex_1775 Int) (v_bAnd_~res~0_BEFORE_RETURN_239 Int) (v_bAnd_~res~0_BEFORE_RETURN_240 Int)) (or (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_240 4294967296) 2147483647)) (not (< main_~i~2 99)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_240 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1776 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1776 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (<= (mod v_prenex_1775 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_239 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 22:49:41,698 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:41,698 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:49:41,698 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_235 Int) (v_bAnd_~res~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int) (v_prenex_1747 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_235 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_235 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_1748 4294967296) (- 4294967296)) main_~ret~0) (not (<= (mod v_prenex_1748 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1747 4294967296) 2147483647) (= main_~ret~0 (mod v_prenex_1747 4294967296)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_236 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_236 4294967296))))) [2019-10-06 22:49:41,698 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:41,699 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:41,699 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:41,699 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:41,699 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:41,699 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:41,699 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:41,699 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:41,700 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:49:41,700 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:49:41,700 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_235 Int) (v_prenex_1747 Int)) (or (and (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_235 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_235 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (<= (mod v_prenex_1747 4294967296) 2147483647) (= (mod v_prenex_1747 4294967296) |main_#t~ret5|)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_1748 4294967296) 2147483647)) (= (+ (mod v_prenex_1748 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_236 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_236 4294967296) 2147483647))))) [2019-10-06 22:49:41,700 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:41,700 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:41,700 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:41,701 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:42,160 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:42,160 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 25, 25, 11] total 63 [2019-10-06 22:49:42,161 INFO L442 AbstractCegarLoop]: Interpolant automaton has 64 states [2019-10-06 22:49:42,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2019-10-06 22:49:42,163 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1177, Invalid=2855, Unknown=0, NotChecked=0, Total=4032 [2019-10-06 22:49:42,163 INFO L87 Difference]: Start difference. First operand 145 states and 149 transitions. Second operand 64 states. [2019-10-06 22:49:46,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:46,286 INFO L93 Difference]: Finished difference Result 208 states and 242 transitions. [2019-10-06 22:49:46,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2019-10-06 22:49:46,287 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 194 [2019-10-06 22:49:46,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:46,289 INFO L225 Difference]: With dead ends: 208 [2019-10-06 22:49:46,290 INFO L226 Difference]: Without dead ends: 170 [2019-10-06 22:49:46,292 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 648 GetRequests, 527 SyntacticMatches, 0 SemanticMatches, 121 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3272 ImplicationChecksByTransitivity, 5.1s TimeCoverageRelationStatistics Valid=3811, Invalid=11195, Unknown=0, NotChecked=0, Total=15006 [2019-10-06 22:49:46,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2019-10-06 22:49:46,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 170. [2019-10-06 22:49:46,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2019-10-06 22:49:46,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 174 transitions. [2019-10-06 22:49:46,309 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 174 transitions. Word has length 194 [2019-10-06 22:49:46,310 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:46,310 INFO L462 AbstractCegarLoop]: Abstraction has 170 states and 174 transitions. [2019-10-06 22:49:46,310 INFO L463 AbstractCegarLoop]: Interpolant automaton has 64 states. [2019-10-06 22:49:46,310 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 174 transitions. [2019-10-06 22:49:46,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 268 [2019-10-06 22:49:46,313 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:46,314 INFO L385 BasicCegarLoop]: trace histogram [138, 100, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:46,520 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:46,521 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:46,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:46,522 INFO L82 PathProgramCache]: Analyzing trace with hash -201777425, now seen corresponding path program 11 times [2019-10-06 22:49:46,522 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:46,522 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:46,522 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:46,522 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:46,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:46,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:47,830 INFO L134 CoverageAnalysis]: Checked inductivity of 14941 backedges. 2210 proven. 3291 refuted. 0 times theorem prover too weak. 9440 trivial. 0 not checked. [2019-10-06 22:49:47,830 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:47,830 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:47,831 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:48,217 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-10-06 22:49:48,217 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:48,218 INFO L256 TraceCheckSpWp]: Trace formula consists of 201 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-06 22:49:48,222 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:48,405 INFO L134 CoverageAnalysis]: Checked inductivity of 14941 backedges. 4422 proven. 15 refuted. 0 times theorem prover too weak. 10504 trivial. 0 not checked. [2019-10-06 22:49:48,405 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:48,590 INFO L134 CoverageAnalysis]: Checked inductivity of 14941 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 14926 trivial. 0 not checked. [2019-10-06 22:49:48,590 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:48,591 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:48,592 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:48,592 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:48,592 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:48,592 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:48,612 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:49,700 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:49,718 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:49,720 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:49,720 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:49,721 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_265 Int) (v_bAnd_~res~0_BEFORE_RETURN_266 Int) (v_prenex_1970 Int) (v_prenex_1969 Int)) (or (and (= main_~ret5~0 (mod v_bAnd_~res~0_BEFORE_RETURN_266 4294967296)) (not (< main_~i~2 99)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_266 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_265 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_265 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (<= (mod v_prenex_1969 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_265 Int) (v_bAnd_~res~0_BEFORE_RETURN_266 Int) (v_prenex_1970 Int) (v_prenex_1969 Int)) (or (and (= main_~ret5~0 (mod v_bAnd_~res~0_BEFORE_RETURN_266 4294967296)) (not (< main_~i~2 99)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_266 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_265 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_265 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (<= (mod v_prenex_1969 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 22:49:49,721 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:49,721 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:49:49,721 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_bAnd_~res~0_BEFORE_RETURN_261 Int) (v_bAnd_~res~0_BEFORE_RETURN_262 Int)) (or (and (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_262 4294967296)) (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_262 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_261 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_261 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_1942 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 100)) (= main_~ret~0 (mod v_prenex_1941 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1941 4294967296) 2147483647)))) [2019-10-06 22:49:49,721 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:49,721 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:49,721 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:49,721 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:49,722 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:49,722 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:49,722 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:49,722 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:49,722 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:49:49,722 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:49:49,722 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1942 Int) (v_bAnd_~res~0_BEFORE_RETURN_262 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_262 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_262 4294967296) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_prenex_1942 4294967296) (- 4294967296)))))) (exists ((v_prenex_1941 Int) (v_bAnd_~res~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_261 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_261 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (= (mod v_prenex_1941 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1941 4294967296) 2147483647))))) [2019-10-06 22:49:49,722 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:49,722 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:49,722 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:49,723 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:50,427 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:50,428 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 8, 8, 11] total 71 [2019-10-06 22:49:50,429 INFO L442 AbstractCegarLoop]: Interpolant automaton has 72 states [2019-10-06 22:49:50,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2019-10-06 22:49:50,430 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1296, Invalid=3816, Unknown=0, NotChecked=0, Total=5112 [2019-10-06 22:49:50,430 INFO L87 Difference]: Start difference. First operand 170 states and 174 transitions. Second operand 72 states. [2019-10-06 22:49:55,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:55,632 INFO L93 Difference]: Finished difference Result 241 states and 258 transitions. [2019-10-06 22:49:55,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2019-10-06 22:49:55,632 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 267 [2019-10-06 22:49:55,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:55,634 INFO L225 Difference]: With dead ends: 241 [2019-10-06 22:49:55,634 INFO L226 Difference]: Without dead ends: 178 [2019-10-06 22:49:55,636 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 917 GetRequests, 780 SyntacticMatches, 0 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3820 ImplicationChecksByTransitivity, 6.3s TimeCoverageRelationStatistics Valid=4186, Invalid=14996, Unknown=0, NotChecked=0, Total=19182 [2019-10-06 22:49:55,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2019-10-06 22:49:55,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2019-10-06 22:49:55,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2019-10-06 22:49:55,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 182 transitions. [2019-10-06 22:49:55,649 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 182 transitions. Word has length 267 [2019-10-06 22:49:55,649 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:55,649 INFO L462 AbstractCegarLoop]: Abstraction has 178 states and 182 transitions. [2019-10-06 22:49:55,650 INFO L463 AbstractCegarLoop]: Interpolant automaton has 72 states. [2019-10-06 22:49:55,650 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 182 transitions. [2019-10-06 22:49:55,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 278 [2019-10-06 22:49:55,653 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:55,653 INFO L385 BasicCegarLoop]: trace histogram [141, 100, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:55,858 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:55,858 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:55,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:55,859 INFO L82 PathProgramCache]: Analyzing trace with hash -998304102, now seen corresponding path program 12 times [2019-10-06 22:49:55,859 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:55,860 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:55,860 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:55,860 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:55,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:56,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:56,285 INFO L134 CoverageAnalysis]: Checked inductivity of 15430 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 15352 trivial. 0 not checked. [2019-10-06 22:49:56,285 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:56,286 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:56,286 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:56,815 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:49:56,816 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:56,822 INFO L256 TraceCheckSpWp]: Trace formula consists of 1188 conjuncts, 49 conjunts are in the unsatisfiable core [2019-10-06 22:49:56,829 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:58,096 INFO L134 CoverageAnalysis]: Checked inductivity of 15430 backedges. 4610 proven. 1128 refuted. 0 times theorem prover too weak. 9692 trivial. 0 not checked. [2019-10-06 22:49:58,096 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:00,923 INFO L134 CoverageAnalysis]: Checked inductivity of 15430 backedges. 0 proven. 5738 refuted. 0 times theorem prover too weak. 9692 trivial. 0 not checked. [2019-10-06 22:50:00,923 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:00,924 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:00,924 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:00,925 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:00,925 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:00,925 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:00,937 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:50:02,040 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:50:02,058 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:50:02,060 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:50:02,061 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:50:02,061 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_2163 Int) (v_bAnd_~res~0_BEFORE_RETURN_292 Int) (v_prenex_2164 Int) (v_bAnd_~res~0_BEFORE_RETURN_291 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_prenex_2163 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2163 4294967296) (- 4294967296)) main_~ret5~0)) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_291 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_291 4294967296) main_~ret5~0)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_292 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_292 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= (mod v_prenex_2164 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2164 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (exists ((v_prenex_2163 Int) (v_bAnd_~res~0_BEFORE_RETURN_292 Int) (v_prenex_2164 Int) (v_bAnd_~res~0_BEFORE_RETURN_291 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_prenex_2163 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2163 4294967296) (- 4294967296)) main_~ret5~0)) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_291 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_291 4294967296) main_~ret5~0)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_292 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_292 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= (mod v_prenex_2164 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2164 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret2~0)))) [2019-10-06 22:50:02,061 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:50:02,061 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:50:02,062 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_287 Int) (v_bAnd_~res~0_BEFORE_RETURN_288 Int) (v_prenex_2135 Int) (v_prenex_2136 Int)) (or (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_288 4294967296) (- 4294967296)) main_~ret~0) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_288 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= main_~ret~0 (mod v_prenex_2136 4294967296)) (<= (mod v_prenex_2136 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_prenex_2135 4294967296) (- 4294967296))) (not (<= (mod v_prenex_2135 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_287 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_287 4294967296)) (<= main_~ret~0 2147483647)))) [2019-10-06 22:50:02,062 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:50:02,062 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:50:02,063 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:02,063 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:02,063 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:02,063 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:50:02,063 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:50:02,063 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:50:02,063 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:50:02,064 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:50:02,064 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_288 Int) (v_prenex_2136 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_288 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_288 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (<= (mod v_prenex_2136 4294967296) 2147483647) (= (mod v_prenex_2136 4294967296) |main_#t~ret5|)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_287 Int) (v_prenex_2135 Int)) (or (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_2135 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_2135 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_287 4294967296) |main_#t~ret5|) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_287 4294967296) 2147483647))))) [2019-10-06 22:50:02,064 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:50:02,064 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:50:02,064 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:50:02,064 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:50:02,756 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:50:02,757 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 50, 50, 11] total 121 [2019-10-06 22:50:02,758 INFO L442 AbstractCegarLoop]: Interpolant automaton has 122 states [2019-10-06 22:50:02,760 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 122 interpolants. [2019-10-06 22:50:02,761 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4886, Invalid=9876, Unknown=0, NotChecked=0, Total=14762 [2019-10-06 22:50:02,761 INFO L87 Difference]: Start difference. First operand 178 states and 182 transitions. Second operand 122 states. [2019-10-06 22:50:14,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:14,982 INFO L93 Difference]: Finished difference Result 299 states and 358 transitions. [2019-10-06 22:50:14,983 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 122 states. [2019-10-06 22:50:14,983 INFO L78 Accepts]: Start accepts. Automaton has 122 states. Word has length 277 [2019-10-06 22:50:14,983 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:14,985 INFO L225 Difference]: With dead ends: 299 [2019-10-06 22:50:14,985 INFO L226 Difference]: Without dead ends: 228 [2019-10-06 22:50:14,988 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 963 GetRequests, 726 SyntacticMatches, 0 SemanticMatches, 237 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11837 ImplicationChecksByTransitivity, 16.1s TimeCoverageRelationStatistics Valid=15254, Invalid=41628, Unknown=0, NotChecked=0, Total=56882 [2019-10-06 22:50:14,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states. [2019-10-06 22:50:15,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 228. [2019-10-06 22:50:15,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2019-10-06 22:50:15,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 232 transitions. [2019-10-06 22:50:15,006 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 232 transitions. Word has length 277 [2019-10-06 22:50:15,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:15,006 INFO L462 AbstractCegarLoop]: Abstraction has 228 states and 232 transitions. [2019-10-06 22:50:15,006 INFO L463 AbstractCegarLoop]: Interpolant automaton has 122 states. [2019-10-06 22:50:15,006 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 232 transitions. [2019-10-06 22:50:15,009 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 426 [2019-10-06 22:50:15,009 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:15,010 INFO L385 BasicCegarLoop]: trace histogram [288, 100, 13, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:15,219 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:15,219 INFO L410 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:15,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:15,220 INFO L82 PathProgramCache]: Analyzing trace with hash -598150225, now seen corresponding path program 13 times [2019-10-06 22:50:15,220 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:15,220 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:15,220 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:15,221 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:15,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:15,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:19,238 INFO L134 CoverageAnalysis]: Checked inductivity of 47342 backedges. 18820 proven. 4656 refuted. 0 times theorem prover too weak. 23866 trivial. 0 not checked. [2019-10-06 22:50:19,239 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:19,239 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:50:19,239 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:19,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:19,907 INFO L256 TraceCheckSpWp]: Trace formula consists of 1633 conjuncts, 98 conjunts are in the unsatisfiable core [2019-10-06 22:50:19,915 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:50:20,031 INFO L134 CoverageAnalysis]: Checked inductivity of 47342 backedges. 18820 proven. 4656 refuted. 0 times theorem prover too weak. 23866 trivial. 0 not checked. [2019-10-06 22:50:20,032 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:24,037 INFO L134 CoverageAnalysis]: Checked inductivity of 47342 backedges. 0 proven. 23476 refuted. 0 times theorem prover too weak. 23866 trivial. 0 not checked. [2019-10-06 22:50:24,037 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:24,038 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:24,039 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:24,039 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:24,039 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:24,039 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:24,053 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:50:25,126 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:50:25,142 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:50:25,144 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:50:25,144 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:50:25,144 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:50:25,144 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_2358 Int) (v_prenex_2357 Int) (v_bAnd_~res~0_BEFORE_RETURN_317 Int) (v_bAnd_~res~0_BEFORE_RETURN_318 Int)) (or (and (<= (mod v_prenex_2357 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_prenex_2357 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= (mod v_prenex_2358 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_2358 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_317 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_317 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_318 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_318 4294967296) 2147483647))))) (not (= main_~ret~0 main_~ret2~0))) (and (exists ((v_prenex_2358 Int) (v_prenex_2357 Int) (v_bAnd_~res~0_BEFORE_RETURN_317 Int) (v_bAnd_~res~0_BEFORE_RETURN_318 Int)) (or (and (<= (mod v_prenex_2357 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_prenex_2357 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= (mod v_prenex_2358 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_2358 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_317 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_317 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_318 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_318 4294967296) 2147483647))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:50:25,144 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:50:25,145 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_313 Int) (v_bAnd_~res~0_BEFORE_RETURN_314 Int) (v_prenex_2330 Int) (v_prenex_2329 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_prenex_2329 4294967296) 2147483647) (= (mod v_prenex_2329 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2330 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_prenex_2330 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_bAnd_~res~0_BEFORE_RETURN_314 4294967296) main_~ret~0) (<= main_~ret~0 2147483647) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_314 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_313 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_313 4294967296) 2147483647))))) [2019-10-06 22:50:25,145 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:50:25,145 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:50:25,145 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:25,146 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:25,146 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:25,146 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:50:25,147 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:50:25,147 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:50:25,147 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:50:25,147 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:50:25,147 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_314 Int) (v_prenex_2330 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_2330 4294967296) 2147483647)) (= (+ (mod v_prenex_2330 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_314 4294967296) |main_#t~ret5|) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_314 4294967296) 2147483647)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_313 Int) (v_prenex_2329 Int)) (or (and (not (< main_~i~1 100)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_313 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_313 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (<= (mod v_prenex_2329 4294967296) 2147483647) (= |main_#t~ret5| (mod v_prenex_2329 4294967296)))))) [2019-10-06 22:50:25,147 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:50:25,148 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:50:25,148 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:50:25,148 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:50:26,054 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:50:26,055 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [99, 99, 99, 11] total 112 [2019-10-06 22:50:26,056 INFO L442 AbstractCegarLoop]: Interpolant automaton has 113 states [2019-10-06 22:50:26,057 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 113 interpolants. [2019-10-06 22:50:26,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5181, Invalid=7475, Unknown=0, NotChecked=0, Total=12656 [2019-10-06 22:50:26,058 INFO L87 Difference]: Start difference. First operand 228 states and 232 transitions. Second operand 113 states. [2019-10-06 22:50:37,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:37,787 INFO L93 Difference]: Finished difference Result 352 states and 364 transitions. [2019-10-06 22:50:37,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 112 states. [2019-10-06 22:50:37,787 INFO L78 Accepts]: Start accepts. Automaton has 113 states. Word has length 425 [2019-10-06 22:50:37,787 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:37,789 INFO L225 Difference]: With dead ends: 352 [2019-10-06 22:50:37,789 INFO L226 Difference]: Without dead ends: 231 [2019-10-06 22:50:37,792 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1480 GetRequests, 1167 SyntacticMatches, 95 SemanticMatches, 218 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12063 ImplicationChecksByTransitivity, 19.3s TimeCoverageRelationStatistics Valid=15928, Invalid=32252, Unknown=0, NotChecked=0, Total=48180 [2019-10-06 22:50:37,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states. [2019-10-06 22:50:37,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 231. [2019-10-06 22:50:37,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 231 states. [2019-10-06 22:50:37,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231 states to 231 states and 235 transitions. [2019-10-06 22:50:37,807 INFO L78 Accepts]: Start accepts. Automaton has 231 states and 235 transitions. Word has length 425 [2019-10-06 22:50:37,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:37,808 INFO L462 AbstractCegarLoop]: Abstraction has 231 states and 235 transitions. [2019-10-06 22:50:37,808 INFO L463 AbstractCegarLoop]: Interpolant automaton has 113 states. [2019-10-06 22:50:37,808 INFO L276 IsEmpty]: Start isEmpty. Operand 231 states and 235 transitions. [2019-10-06 22:50:37,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 435 [2019-10-06 22:50:37,811 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:37,811 INFO L385 BasicCegarLoop]: trace histogram [297, 100, 13, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:38,017 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:38,018 INFO L410 AbstractCegarLoop]: === Iteration 17 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:38,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:38,018 INFO L82 PathProgramCache]: Analyzing trace with hash 394499157, now seen corresponding path program 14 times [2019-10-06 22:50:38,019 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:38,019 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:38,019 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:38,020 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:38,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:38,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:38,786 INFO L134 CoverageAnalysis]: Checked inductivity of 49997 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 49906 trivial. 0 not checked. [2019-10-06 22:50:38,786 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:38,786 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:50:38,787 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:40,099 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2019-10-06 22:50:40,099 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:50:40,102 INFO L256 TraceCheckSpWp]: Trace formula consists of 329 conjuncts, 17 conjunts are in the unsatisfiable core [2019-10-06 22:50:40,109 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:50:40,213 INFO L134 CoverageAnalysis]: Checked inductivity of 49997 backedges. 20004 proven. 91 refuted. 0 times theorem prover too weak. 29902 trivial. 0 not checked. [2019-10-06 22:50:40,213 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:40,602 INFO L134 CoverageAnalysis]: Checked inductivity of 49997 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 49906 trivial. 0 not checked. [2019-10-06 22:50:40,603 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:40,604 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:40,604 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:40,604 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:40,605 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:40,605 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:40,619 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:50:41,692 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:50:41,712 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:50:41,719 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:50:41,719 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:50:41,719 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:50:41,720 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret5~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_344 Int) (v_bAnd_~res~0_BEFORE_RETURN_343 Int) (v_prenex_2552 Int) (v_prenex_2551 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= (mod v_prenex_2551 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2551 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_prenex_2552 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2552 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_bAnd_~res~0_BEFORE_RETURN_344 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_344 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_343 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_343 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)))))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_344 Int) (v_bAnd_~res~0_BEFORE_RETURN_343 Int) (v_prenex_2552 Int) (v_prenex_2551 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= (mod v_prenex_2551 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2551 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_prenex_2552 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2552 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_bAnd_~res~0_BEFORE_RETURN_344 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_344 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_343 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_343 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 22:50:41,720 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:50:41,720 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_2523 Int) (v_prenex_2524 Int) (v_bAnd_~res~0_BEFORE_RETURN_339 Int) (v_bAnd_~res~0_BEFORE_RETURN_340 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_2523 4294967296)) (<= main_~ret~0 2147483647) (<= (mod v_prenex_2523 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2524 4294967296) 2147483647)) (= (+ (mod v_prenex_2524 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_339 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_339 4294967296) (- 4294967296)))) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_340 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_340 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-06 22:50:41,720 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:50:41,720 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:50:41,721 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:41,721 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:41,721 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:41,721 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:50:41,721 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:50:41,721 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:50:41,721 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:50:41,722 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:50:41,722 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2523 Int) (v_bAnd_~res~0_BEFORE_RETURN_339 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_339 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_339 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (= |main_#t~ret5| (mod v_prenex_2523 4294967296)) (<= (mod v_prenex_2523 4294967296) 2147483647)))) (exists ((v_prenex_2524 Int) (v_bAnd_~res~0_BEFORE_RETURN_340 Int)) (or (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_2524 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_2524 4294967296) 2147483647))) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_340 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_340 4294967296) |main_#t~ret5|))))) [2019-10-06 22:50:41,722 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:50:41,722 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:50:41,722 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:50:41,723 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:50:42,229 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:50:42,229 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 11] total 41 [2019-10-06 22:50:42,231 INFO L442 AbstractCegarLoop]: Interpolant automaton has 42 states [2019-10-06 22:50:42,231 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2019-10-06 22:50:42,231 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=494, Invalid=1228, Unknown=0, NotChecked=0, Total=1722 [2019-10-06 22:50:42,232 INFO L87 Difference]: Start difference. First operand 231 states and 235 transitions. Second operand 42 states. [2019-10-06 22:50:43,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:43,935 INFO L93 Difference]: Finished difference Result 353 states and 372 transitions. [2019-10-06 22:50:43,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-10-06 22:50:43,935 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 434 [2019-10-06 22:50:43,935 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:43,937 INFO L225 Difference]: With dead ends: 353 [2019-10-06 22:50:43,937 INFO L226 Difference]: Without dead ends: 246 [2019-10-06 22:50:43,939 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1354 GetRequests, 1278 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1416 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1473, Invalid=4533, Unknown=0, NotChecked=0, Total=6006 [2019-10-06 22:50:43,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2019-10-06 22:50:43,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 246. [2019-10-06 22:50:43,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 246 states. [2019-10-06 22:50:43,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 246 states to 246 states and 250 transitions. [2019-10-06 22:50:43,956 INFO L78 Accepts]: Start accepts. Automaton has 246 states and 250 transitions. Word has length 434 [2019-10-06 22:50:43,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:43,957 INFO L462 AbstractCegarLoop]: Abstraction has 246 states and 250 transitions. [2019-10-06 22:50:43,957 INFO L463 AbstractCegarLoop]: Interpolant automaton has 42 states. [2019-10-06 22:50:43,957 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 250 transitions. [2019-10-06 22:50:43,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 450 [2019-10-06 22:50:43,960 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:43,960 INFO L385 BasicCegarLoop]: trace histogram [297, 100, 28, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:44,164 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:44,165 INFO L410 AbstractCegarLoop]: === Iteration 18 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:44,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:44,165 INFO L82 PathProgramCache]: Analyzing trace with hash -1918296678, now seen corresponding path program 15 times [2019-10-06 22:50:44,166 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:44,166 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:44,166 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:44,166 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:44,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:44,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:45,219 INFO L134 CoverageAnalysis]: Checked inductivity of 50312 backedges. 0 proven. 406 refuted. 0 times theorem prover too weak. 49906 trivial. 0 not checked. [2019-10-06 22:50:45,219 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:45,220 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:50:45,220 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:45,912 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:50:45,913 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:50:45,918 INFO L256 TraceCheckSpWp]: Trace formula consists of 1720 conjuncts, 30 conjunts are in the unsatisfiable core [2019-10-06 22:50:45,922 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:50:46,032 INFO L134 CoverageAnalysis]: Checked inductivity of 50312 backedges. 20004 proven. 406 refuted. 0 times theorem prover too weak. 29902 trivial. 0 not checked. [2019-10-06 22:50:46,032 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:47,322 INFO L134 CoverageAnalysis]: Checked inductivity of 50312 backedges. 0 proven. 406 refuted. 0 times theorem prover too weak. 49906 trivial. 0 not checked. [2019-10-06 22:50:47,322 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:47,323 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:47,324 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:47,324 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:47,324 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:47,324 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:47,336 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:50:48,355 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:50:48,370 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:50:48,373 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:50:48,373 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:50:48,373 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:50:48,374 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_2745 Int) (v_prenex_2746 Int) (v_bAnd_~res~0_BEFORE_RETURN_369 Int) (v_bAnd_~res~0_BEFORE_RETURN_370 Int)) (or (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_prenex_2745 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_prenex_2745 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_370 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 99)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_370 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= (mod v_prenex_2746 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2746 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_369 4294967296) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_369 4294967296) 2147483647))))) (and (exists ((v_prenex_2745 Int) (v_prenex_2746 Int) (v_bAnd_~res~0_BEFORE_RETURN_369 Int) (v_bAnd_~res~0_BEFORE_RETURN_370 Int)) (or (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_prenex_2745 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_prenex_2745 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_370 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 99)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_370 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= (mod v_prenex_2746 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2746 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_369 4294967296) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_369 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:50:48,374 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:50:48,374 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_366 Int) (v_bAnd_~res~0_BEFORE_RETURN_365 Int) (v_prenex_2718 Int) (v_prenex_2717 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_prenex_2717 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_2717 4294967296)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_366 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_366 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_2718 4294967296) 2147483647)) (= (+ (mod v_prenex_2718 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 100)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_365 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_365 4294967296) (- 4294967296)))))) [2019-10-06 22:50:48,375 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:50:48,375 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:50:48,375 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:48,375 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:48,375 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:48,375 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:50:48,376 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:50:48,376 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:50:48,376 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:50:48,376 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:50:48,376 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_366 Int) (v_prenex_2718 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_366 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_366 4294967296) |main_#t~ret5|)) (and (= (+ (mod v_prenex_2718 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 100)) (not (<= (mod v_prenex_2718 4294967296) 2147483647))))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_365 Int) (v_prenex_2717 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_365 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_365 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (<= (mod v_prenex_2717 4294967296) 2147483647) (= (mod v_prenex_2717 4294967296) |main_#t~ret5|))))) [2019-10-06 22:50:48,376 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:50:48,376 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:50:48,376 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:50:48,377 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:50:48,822 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:50:48,823 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31, 11] total 71 [2019-10-06 22:50:48,824 INFO L442 AbstractCegarLoop]: Interpolant automaton has 72 states [2019-10-06 22:50:48,825 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2019-10-06 22:50:48,825 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1859, Invalid=3253, Unknown=0, NotChecked=0, Total=5112 [2019-10-06 22:50:48,825 INFO L87 Difference]: Start difference. First operand 246 states and 250 transitions. Second operand 72 states. [2019-10-06 22:50:52,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:52,858 INFO L93 Difference]: Finished difference Result 383 states and 417 transitions. [2019-10-06 22:50:52,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2019-10-06 22:50:52,859 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 449 [2019-10-06 22:50:52,860 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:52,861 INFO L225 Difference]: With dead ends: 383 [2019-10-06 22:50:52,861 INFO L226 Difference]: Without dead ends: 276 [2019-10-06 22:50:52,863 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1444 GetRequests, 1308 SyntacticMatches, 0 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3966 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=5568, Invalid=13338, Unknown=0, NotChecked=0, Total=18906 [2019-10-06 22:50:52,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2019-10-06 22:50:52,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 276. [2019-10-06 22:50:52,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 276 states. [2019-10-06 22:50:52,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276 states to 276 states and 280 transitions. [2019-10-06 22:50:52,881 INFO L78 Accepts]: Start accepts. Automaton has 276 states and 280 transitions. Word has length 449 [2019-10-06 22:50:52,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:52,882 INFO L462 AbstractCegarLoop]: Abstraction has 276 states and 280 transitions. [2019-10-06 22:50:52,882 INFO L463 AbstractCegarLoop]: Interpolant automaton has 72 states. [2019-10-06 22:50:52,882 INFO L276 IsEmpty]: Start isEmpty. Operand 276 states and 280 transitions. [2019-10-06 22:50:52,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 480 [2019-10-06 22:50:52,886 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:52,886 INFO L385 BasicCegarLoop]: trace histogram [297, 100, 58, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:53,093 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:53,094 INFO L410 AbstractCegarLoop]: === Iteration 19 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:53,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:53,094 INFO L82 PathProgramCache]: Analyzing trace with hash 1648297018, now seen corresponding path program 16 times [2019-10-06 22:50:53,095 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:53,095 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:53,095 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:53,095 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:53,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:53,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:55,237 INFO L134 CoverageAnalysis]: Checked inductivity of 51617 backedges. 0 proven. 1711 refuted. 0 times theorem prover too weak. 49906 trivial. 0 not checked. [2019-10-06 22:50:55,238 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:55,238 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:50:55,238 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:55,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:55,992 INFO L256 TraceCheckSpWp]: Trace formula consists of 1840 conjuncts, 60 conjunts are in the unsatisfiable core [2019-10-06 22:50:55,999 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:50:56,157 INFO L134 CoverageAnalysis]: Checked inductivity of 51617 backedges. 20004 proven. 1711 refuted. 0 times theorem prover too weak. 29902 trivial. 0 not checked. [2019-10-06 22:50:56,157 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:59,164 INFO L134 CoverageAnalysis]: Checked inductivity of 51617 backedges. 0 proven. 1711 refuted. 0 times theorem prover too weak. 49906 trivial. 0 not checked. [2019-10-06 22:50:59,165 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:59,166 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:59,166 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:59,167 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:59,167 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:59,167 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:59,182 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:51:00,617 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:51:00,656 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:51:00,658 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:51:00,658 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:51:00,659 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:51:00,659 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_2940 Int) (v_prenex_2939 Int) (v_bAnd_~res~0_BEFORE_RETURN_395 Int) (v_bAnd_~res~0_BEFORE_RETURN_396 Int)) (or (and (not (< main_~i~2 99)) (not (<= (mod v_prenex_2939 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= main_~ret5~0 (+ (mod v_prenex_2939 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_2940 4294967296) main_~ret5~0) (<= (mod v_prenex_2940 4294967296) 2147483647)) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_395 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_bAnd_~res~0_BEFORE_RETURN_395 4294967296)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_396 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_396 4294967296) (- 4294967296)) main_~ret5~0))))) (and (exists ((v_prenex_2940 Int) (v_prenex_2939 Int) (v_bAnd_~res~0_BEFORE_RETURN_395 Int) (v_bAnd_~res~0_BEFORE_RETURN_396 Int)) (or (and (not (< main_~i~2 99)) (not (<= (mod v_prenex_2939 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= main_~ret5~0 (+ (mod v_prenex_2939 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_2940 4294967296) main_~ret5~0) (<= (mod v_prenex_2940 4294967296) 2147483647)) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_395 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_bAnd_~res~0_BEFORE_RETURN_395 4294967296)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_396 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_396 4294967296) (- 4294967296)) main_~ret5~0)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:51:00,659 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:51:00,659 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_2911 Int) (v_bAnd_~res~0_BEFORE_RETURN_391 Int) (v_bAnd_~res~0_BEFORE_RETURN_392 Int) (v_prenex_2912 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_391 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_391 4294967296)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= main_~ret~0 (+ (mod v_prenex_2911 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2911 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_392 4294967296) 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_392 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_2912 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2912 4294967296) 2147483647)) (<= main_~ret~0 2147483647)))) [2019-10-06 22:51:00,660 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:51:00,660 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:51:00,660 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:51:00,660 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:51:00,660 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:51:00,660 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:51:00,660 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:51:00,661 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:51:00,661 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:51:00,661 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 100)) (<= 1 bAnd_~i~0) (<= 100 bAnd_~i~0)) [2019-10-06 22:51:00,661 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2911 Int) (v_bAnd_~res~0_BEFORE_RETURN_391 Int)) (or (and (not (< main_~i~1 100)) (= |main_#t~ret5| (+ (mod v_prenex_2911 4294967296) (- 4294967296))) (not (<= (mod v_prenex_2911 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_391 4294967296) |main_#t~ret5|) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_391 4294967296) 2147483647)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_392 Int) (v_prenex_2912 Int)) (or (and (= (+ (mod v_prenex_2912 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 100)) (not (<= (mod v_prenex_2912 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_392 4294967296) 2147483647) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_392 4294967296)))))) [2019-10-06 22:51:00,661 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:51:00,661 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:51:00,662 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:51:00,662 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:51:01,518 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:51:01,519 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61, 61, 11] total 112 [2019-10-06 22:51:01,521 INFO L442 AbstractCegarLoop]: Interpolant automaton has 113 states [2019-10-06 22:51:01,522 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 113 interpolants. [2019-10-06 22:51:01,522 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5180, Invalid=7476, Unknown=0, NotChecked=0, Total=12656 [2019-10-06 22:51:01,523 INFO L87 Difference]: Start difference. First operand 276 states and 280 transitions. Second operand 113 states. [2019-10-06 22:51:10,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:51:10,687 INFO L93 Difference]: Finished difference Result 424 states and 469 transitions. [2019-10-06 22:51:10,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 112 states. [2019-10-06 22:51:10,687 INFO L78 Accepts]: Start accepts. Automaton has 113 states. Word has length 479 [2019-10-06 22:51:10,688 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:51:10,690 INFO L225 Difference]: With dead ends: 424 [2019-10-06 22:51:10,690 INFO L226 Difference]: Without dead ends: 317 [2019-10-06 22:51:10,692 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1605 GetRequests, 1368 SyntacticMatches, 19 SemanticMatches, 218 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9648 ImplicationChecksByTransitivity, 13.7s TimeCoverageRelationStatistics Valid=15531, Invalid=32649, Unknown=0, NotChecked=0, Total=48180 [2019-10-06 22:51:10,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states. [2019-10-06 22:51:10,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 317. [2019-10-06 22:51:10,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2019-10-06 22:51:10,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 321 transitions. [2019-10-06 22:51:10,712 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 321 transitions. Word has length 479 [2019-10-06 22:51:10,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:51:10,713 INFO L462 AbstractCegarLoop]: Abstraction has 317 states and 321 transitions. [2019-10-06 22:51:10,713 INFO L463 AbstractCegarLoop]: Interpolant automaton has 113 states. [2019-10-06 22:51:10,713 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 321 transitions. [2019-10-06 22:51:10,716 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 521 [2019-10-06 22:51:10,717 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:51:10,717 INFO L385 BasicCegarLoop]: trace histogram [297, 100, 99, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:51:10,923 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:10,923 INFO L410 AbstractCegarLoop]: === Iteration 20 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:51:10,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:51:10,924 INFO L82 PathProgramCache]: Analyzing trace with hash -722906315, now seen corresponding path program 17 times [2019-10-06 22:51:10,924 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:51:10,924 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:10,924 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:10,925 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:10,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:51:24,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-06 22:51:35,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-06 22:51:35,855 INFO L161 tionRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2019-10-06 22:51:35,855 INFO L451 BasicCegarLoop]: Counterexample might be feasible [2019-10-06 22:51:36,189 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 06.10 10:51:36 BoogieIcfgContainer [2019-10-06 22:51:36,190 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-10-06 22:51:36,191 INFO L168 Benchmark]: Toolchain (without parser) took 177805.09 ms. Allocated memory was 144.2 MB in the beginning and 1.4 GB in the end (delta: 1.3 GB). Free memory was 101.0 MB in the beginning and 244.6 MB in the end (delta: -143.6 MB). Peak memory consumption was 1.3 GB. Max. memory is 7.1 GB. [2019-10-06 22:51:36,191 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 144.2 MB. Free memory was 119.3 MB in the beginning and 119.1 MB in the end (delta: 210.0 kB). Peak memory consumption was 210.0 kB. Max. memory is 7.1 GB. [2019-10-06 22:51:36,191 INFO L168 Benchmark]: CACSL2BoogieTranslator took 403.92 ms. Allocated memory was 144.2 MB in the beginning and 199.8 MB in the end (delta: 55.6 MB). Free memory was 100.8 MB in the beginning and 179.1 MB in the end (delta: -78.3 MB). Peak memory consumption was 19.8 MB. Max. memory is 7.1 GB. [2019-10-06 22:51:36,192 INFO L168 Benchmark]: Boogie Preprocessor took 39.03 ms. Allocated memory is still 199.8 MB. Free memory was 179.1 MB in the beginning and 176.7 MB in the end (delta: 2.3 MB). Peak memory consumption was 2.3 MB. Max. memory is 7.1 GB. [2019-10-06 22:51:36,192 INFO L168 Benchmark]: RCFGBuilder took 469.97 ms. Allocated memory is still 199.8 MB. Free memory was 176.7 MB in the beginning and 156.3 MB in the end (delta: 20.5 MB). Peak memory consumption was 20.5 MB. Max. memory is 7.1 GB. [2019-10-06 22:51:36,192 INFO L168 Benchmark]: TraceAbstraction took 176887.94 ms. Allocated memory was 199.8 MB in the beginning and 1.4 GB in the end (delta: 1.2 GB). Free memory was 156.3 MB in the beginning and 244.6 MB in the end (delta: -88.3 MB). Peak memory consumption was 1.3 GB. Max. memory is 7.1 GB. [2019-10-06 22:51:36,193 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 144.2 MB. Free memory was 119.3 MB in the beginning and 119.1 MB in the end (delta: 210.0 kB). Peak memory consumption was 210.0 kB. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 403.92 ms. Allocated memory was 144.2 MB in the beginning and 199.8 MB in the end (delta: 55.6 MB). Free memory was 100.8 MB in the beginning and 179.1 MB in the end (delta: -78.3 MB). Peak memory consumption was 19.8 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 39.03 ms. Allocated memory is still 199.8 MB. Free memory was 179.1 MB in the beginning and 176.7 MB in the end (delta: 2.3 MB). Peak memory consumption was 2.3 MB. Max. memory is 7.1 GB. * RCFGBuilder took 469.97 ms. Allocated memory is still 199.8 MB. Free memory was 176.7 MB in the beginning and 156.3 MB in the end (delta: 20.5 MB). Peak memory consumption was 20.5 MB. Max. memory is 7.1 GB. * TraceAbstraction took 176887.94 ms. Allocated memory was 199.8 MB in the beginning and 1.4 GB in the end (delta: 1.2 GB). Free memory was 156.3 MB in the beginning and 244.6 MB in the end (delta: -88.3 MB). Peak memory consumption was 1.3 GB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 42]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of bitwiseAnd at line 13. Possible FailurePath: [L20] int x[100]; [L21] int temp; [L22] int ret; [L23] int ret2; [L24] int ret5; [L26] int i = 0; VAL [i=0, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=1, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=2, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=3, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=4, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=5, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=6, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=7, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=8, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=9, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=10, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=11, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=12, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=13, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=14, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=15, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=16, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=17, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=18, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=19, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=20, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=21, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=22, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=23, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=24, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=25, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=26, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=27, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=28, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=29, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=30, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=31, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=32, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=33, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=34, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=35, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=36, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=37, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=38, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=39, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=40, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=41, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=42, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=43, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=44, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=45, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=46, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=47, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=48, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=49, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=50, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=51, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=52, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=53, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=54, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=55, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=56, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=57, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=58, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=59, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=60, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=61, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=62, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=63, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=64, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=65, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=66, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=67, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=68, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=69, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=70, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=71, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=72, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=73, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=74, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=75, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=76, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=77, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=78, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=79, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=80, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=81, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=82, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=83, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=84, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=85, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=86, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=87, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=88, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=89, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=90, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=91, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=92, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=93, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=94, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=95, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=96, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=97, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=98, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=99, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=100, x={1:0}] [L26] COND FALSE !(i < 100) VAL [i=100, x={1:0}] [L30] CALL, EXPR bAnd(x) VAL [x={1:0}] [L9] int i; [L10] long long res; [L11] EXPR x[0] [L11] res = x[0] [L12] i = 1 VAL [i=1, res=1, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=2, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=3, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=4, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=5, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=6, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=7, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=8, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=9, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=10, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=11, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=12, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=13, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=14, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=15, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=16, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=17, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=18, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=19, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=20, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=21, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=22, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=23, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=24, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=25, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=26, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=27, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=28, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=29, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=30, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=31, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=32, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=33, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=34, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=35, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=36, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=37, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=38, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=39, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=40, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=41, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=42, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=43, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=44, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=45, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=46, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=47, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=48, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=49, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=50, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=51, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=52, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=53, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=54, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=55, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=56, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=57, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=58, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=59, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=60, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=61, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=62, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=63, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=64, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=65, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=66, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=67, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=68, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=69, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=70, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=71, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=72, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=73, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=74, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=75, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=76, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=77, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=78, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=79, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=80, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=81, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=82, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=83, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=84, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=85, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=86, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=87, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=88, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=89, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=90, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=91, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=92, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=93, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=94, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=95, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=96, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=97, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=98, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=99, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=100, x={1:0}, x={1:0}] [L12] COND FALSE !(i < 100) [L15] return res; [L30] RET, EXPR bAnd(x) VAL [bAnd(x)=6, i=100, x={1:0}] [L30] ret = bAnd(x) [L32] EXPR x[0] [L32] temp=x[0] [L32] EXPR x[1] [L32] x[0] = x[1] [L32] x[1] = temp VAL [i=100, ret=6, temp=1, x={1:0}] [L33] CALL, EXPR bAnd(x) VAL [x={1:0}] [L9] int i; [L10] long long res; [L11] EXPR x[0] [L11] res = x[0] [L12] i = 1 VAL [i=1, res=2, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=2, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=3, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=4, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=5, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=6, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=7, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=8, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=9, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=10, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=11, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=12, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=13, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=14, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=15, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=16, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=17, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=18, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=19, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=20, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=21, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=22, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=23, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=24, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=25, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=26, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=27, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=28, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=29, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=30, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=31, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=32, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=33, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=34, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=35, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=36, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=37, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=38, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=39, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=40, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=41, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=42, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=43, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=44, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=45, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=46, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=47, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=48, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=49, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=50, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=51, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=52, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=53, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=54, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=55, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=56, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=57, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=58, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=59, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=60, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=61, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=62, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=63, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=64, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=65, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=66, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=67, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=68, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=69, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=70, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=71, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=72, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=73, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=74, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=75, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=76, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=77, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=78, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=79, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=80, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=81, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=82, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=83, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=84, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=85, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=86, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=87, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=88, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=89, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=90, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=91, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=92, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=93, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=94, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=95, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=96, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=97, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=98, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=99, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=100, x={1:0}, x={1:0}] [L12] COND FALSE !(i < 100) [L15] return res; [L33] RET, EXPR bAnd(x) VAL [bAnd(x)=-1, i=100, ret=6, temp=1, x={1:0}] [L33] ret2 = bAnd(x) [L34] EXPR x[0] [L34] temp=x[0] [L35] int i =0 ; VAL [i=0, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=1, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=2, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=3, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=4, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=5, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=6, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=7, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=8, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=9, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=10, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=11, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=12, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=13, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=14, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=15, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=16, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=17, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=18, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=19, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=20, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=21, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=22, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=23, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=24, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=25, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=26, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=27, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=28, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=29, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=30, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=31, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=32, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=33, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=34, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=35, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=36, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=37, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=38, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=39, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=40, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=41, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=42, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=43, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=44, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=45, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=46, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=47, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=48, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=49, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=50, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=51, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=52, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=53, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=54, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=55, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=56, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=57, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=58, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=59, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=60, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=61, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=62, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=63, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=64, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=65, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=66, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=67, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=68, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=69, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=70, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=71, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=72, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=73, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=74, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=75, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=76, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=77, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=78, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=79, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=80, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=81, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=82, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=83, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=84, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=85, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=86, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=87, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=88, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=89, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=90, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=91, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=92, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=93, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=94, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=95, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=96, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=97, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=98, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=99, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L35] COND FALSE !(i<100 -1) [L38] x[100 -1] = temp VAL [i=99, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L39] CALL, EXPR bAnd(x) VAL [x={1:0}] [L9] int i; [L10] long long res; [L11] EXPR x[0] [L11] res = x[0] [L12] i = 1 VAL [i=1, res=1, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=2, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=3, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=4, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=5, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=6, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=7, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=8, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=9, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=10, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=11, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=12, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=13, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=14, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=15, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=16, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=17, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=18, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=19, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=20, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=21, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=22, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=23, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=24, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=25, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=26, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=27, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=28, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=29, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=30, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=31, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=32, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=33, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=34, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=35, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=36, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=37, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=38, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=39, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=40, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=41, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=42, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=43, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=44, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=45, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=46, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=47, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=48, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=49, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=50, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=51, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=52, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=53, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=54, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=55, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=56, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=57, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=58, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=59, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=60, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=61, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=62, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=63, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=64, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=65, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=66, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=67, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=68, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=69, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=70, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=71, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=72, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=73, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=74, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=75, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=76, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=77, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=78, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=79, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=80, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=81, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=82, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=83, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=84, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=85, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=86, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=87, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=88, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=89, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=90, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=91, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=92, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=93, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=94, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=95, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=96, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=97, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=98, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=99, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res & x[i] [L12] i++ VAL [i=100, x={1:0}, x={1:0}] [L12] COND FALSE !(i < 100) [L15] return res; [L39] RET, EXPR bAnd(x) VAL [bAnd(x)=7, i=99, i=100, ret=6, ret2=-1, temp=2, x={1:0}] [L39] ret5 = bAnd(x) [L41] COND TRUE ret != ret2 || ret !=ret5 VAL [i=100, i=99, ret=6, ret2=-1, ret5=7, temp=2, x={1:0}] [L42] __VERIFIER_error() VAL [i=99, i=100, ret=6, ret2=-1, ret5=7, temp=2, x={1:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 23 locations, 1 error locations. Result: UNSAFE, OverallTime: 176.8s, OverallIterations: 20, TraceHistogramMax: 297, AutomataDifference: 74.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 264 SDtfs, 352 SDslu, 2281 SDs, 0 SdLazy, 3564 SolverSat, 2359 SolverUnsat, 1 SolverUnknown, 0 SolverNotchecked, 7.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 11018 GetRequests, 9024 SyntacticMatches, 128 SemanticMatches, 1866 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65188 ImplicationChecksByTransitivity, 102.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=317occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 19 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.8s SsaConstructionTime, 18.4s SatisfiabilityAnalysisTime, 29.9s InterpolantComputationTime, 7024 NumberOfCodeBlocks, 6295 NumberOfCodeBlocksAsserted, 59 NumberOfCheckSat, 9677 ConstructedInterpolants, 0 QuantifiedInterpolants, 3855521 SizeOfPredicates, 18 NumberOfNonLiveVariables, 10560 ConjunctsInSsa, 422 ConjunctsInUnsatCore, 53 InterpolantComputations, 3 PerfectInterpolantSequences, 694393/752662 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: OVERALL_TIME[ms]: 21628, ICFG_INTERPRETER_ENTERED_PROCEDURES: 64, DAG_INTERPRETER_EARLY_EXIT_QUERIES: 1632, DAG_INTERPRETER_EARLY_EXITS: 0, TOOLS_POST_APPLICATIONS: 848, TOOLS_POST_TIME[ms]: 15414, TOOLS_POST_CALL_APPLICATIONS: 528, TOOLS_POST_CALL_TIME[ms]: 1419, TOOLS_POST_RETURN_APPLICATIONS: 448, TOOLS_POST_RETURN_TIME[ms]: 907, TOOLS_QUANTIFIERELIM_APPLICATIONS: 1824, TOOLS_QUANTIFIERELIM_TIME[ms]: 17353, TOOLS_QUANTIFIERELIM_MAX_TIME[ms]: 140, FLUID_QUERY_TIME[ms]: 30, FLUID_QUERIES: 1888, FLUID_YES_ANSWERS: 112, DOMAIN_JOIN_APPLICATIONS: 1856, DOMAIN_JOIN_TIME[ms]: 2276, DOMAIN_ALPHA_APPLICATIONS: 112, DOMAIN_ALPHA_TIME[ms]: 54, DOMAIN_WIDEN_APPLICATIONS: 96, DOMAIN_WIDEN_TIME[ms]: 367, DOMAIN_ISSUBSETEQ_APPLICATIONS: 256, DOMAIN_ISSUBSETEQ_TIME[ms]: 335, DOMAIN_ISBOTTOM_APPLICATIONS: 256, DOMAIN_ISBOTTOM_TIME[ms]: 387, LOOP_SUMMARIZER_APPLICATIONS: 160, LOOP_SUMMARIZER_CACHE_MISSES: 160, LOOP_SUMMARIZER_OVERALL_TIME[ms]: 3076, LOOP_SUMMARIZER_NEW_COMPUTATION_TIME[ms]: 3070, LOOP_SUMMARIZER_FIXPOINT_ITERATIONS: 256, CALL_SUMMARIZER_APPLICATIONS: 448, CALL_SUMMARIZER_CACHE_MISSES: 32, CALL_SUMMARIZER_OVERALL_TIME[ms]: 582, CALL_SUMMARIZER_NEW_COMPUTATION_TIME[ms]: 579, PROCEDURE_GRAPH_BUILDER_TIME[ms]: 11, PATH_EXPR_TIME[ms]: 15, REGEX_TO_DAG_TIME[ms]: 11, DAG_COMPRESSION_TIME[ms]: 71, DAG_COMPRESSION_PROCESSED_NODES: 3424, DAG_COMPRESSION_RETAINED_NODES: 1808, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request...