java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/array-crafted/bAnd2.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-06 22:48:37,025 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-06 22:48:37,029 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-06 22:48:37,048 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-06 22:48:37,048 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-06 22:48:37,050 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-06 22:48:37,052 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-06 22:48:37,062 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-06 22:48:37,067 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-06 22:48:37,070 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-06 22:48:37,071 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-06 22:48:37,073 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-06 22:48:37,073 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-06 22:48:37,075 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-06 22:48:37,077 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-06 22:48:37,078 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-06 22:48:37,080 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-06 22:48:37,080 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-06 22:48:37,082 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-06 22:48:37,086 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-06 22:48:37,092 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-06 22:48:37,095 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-06 22:48:37,096 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-06 22:48:37,099 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-06 22:48:37,101 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-06 22:48:37,110 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-06 22:48:37,111 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-06 22:48:37,112 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-06 22:48:37,113 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-06 22:48:37,127 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-06 22:48:37,128 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-06 22:48:37,129 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-06 22:48:37,129 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-06 22:48:37,129 INFO L138 SettingsManager]: * Use SBE=true [2019-10-06 22:48:37,130 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-06 22:48:37,130 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-06 22:48:37,130 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-06 22:48:37,130 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-06 22:48:37,130 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-06 22:48:37,131 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-06 22:48:37,131 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-06 22:48:37,131 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-06 22:48:37,131 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-06 22:48:37,132 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-06 22:48:37,132 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-06 22:48:37,132 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-06 22:48:37,132 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-06 22:48:37,132 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-06 22:48:37,133 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-06 22:48:37,133 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-06 22:48:37,133 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:37,133 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-06 22:48:37,133 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-06 22:48:37,134 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-06 22:48:37,134 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-06 22:48:37,134 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-06 22:48:37,134 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-06 22:48:37,134 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-06 22:48:37,444 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-06 22:48:37,461 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-06 22:48:37,465 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-06 22:48:37,466 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-06 22:48:37,467 INFO L275 PluginConnector]: CDTParser initialized [2019-10-06 22:48:37,468 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-crafted/bAnd2.i [2019-10-06 22:48:37,537 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0c1f1055e/ade7414adcf4418e9e713e06affa0e23/FLAGbaaaa04ab [2019-10-06 22:48:37,984 INFO L306 CDTParser]: Found 1 translation units. [2019-10-06 22:48:37,985 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-crafted/bAnd2.i [2019-10-06 22:48:37,992 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0c1f1055e/ade7414adcf4418e9e713e06affa0e23/FLAGbaaaa04ab [2019-10-06 22:48:38,380 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0c1f1055e/ade7414adcf4418e9e713e06affa0e23 [2019-10-06 22:48:38,390 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-06 22:48:38,391 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-06 22:48:38,392 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,393 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-06 22:48:38,398 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-06 22:48:38,398 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,401 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3ea19e4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38, skipping insertion in model container [2019-10-06 22:48:38,401 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,409 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-06 22:48:38,430 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-06 22:48:38,608 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,619 INFO L188 MainTranslator]: Completed pre-run [2019-10-06 22:48:38,644 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,747 INFO L192 MainTranslator]: Completed translation [2019-10-06 22:48:38,747 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38 WrapperNode [2019-10-06 22:48:38,747 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,748 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-06 22:48:38,748 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-06 22:48:38,748 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-06 22:48:38,759 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,759 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,766 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,767 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,776 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,781 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,783 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,785 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-06 22:48:38,786 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-06 22:48:38,786 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-06 22:48:38,786 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-06 22:48:38,787 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:38,848 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-06 22:48:38,848 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-06 22:48:38,848 INFO L138 BoogieDeclarations]: Found implementation of procedure bAnd [2019-10-06 22:48:38,848 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-06 22:48:38,848 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-06 22:48:38,849 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-06 22:48:38,849 INFO L130 BoogieDeclarations]: Found specification of procedure bAnd [2019-10-06 22:48:38,849 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-06 22:48:38,849 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-06 22:48:38,849 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-06 22:48:38,849 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-06 22:48:38,850 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-06 22:48:38,850 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-06 22:48:38,850 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-06 22:48:39,199 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-06 22:48:39,200 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-06 22:48:39,201 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39 BoogieIcfgContainer [2019-10-06 22:48:39,201 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-06 22:48:39,203 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-06 22:48:39,203 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-06 22:48:39,207 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-06 22:48:39,207 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.10 10:48:38" (1/3) ... [2019-10-06 22:48:39,208 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@78e42fdd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,208 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (2/3) ... [2019-10-06 22:48:39,209 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@78e42fdd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,209 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39" (3/3) ... [2019-10-06 22:48:39,211 INFO L109 eAbstractionObserver]: Analyzing ICFG bAnd2.i [2019-10-06 22:48:39,224 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-06 22:48:39,232 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-06 22:48:39,245 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-06 22:48:39,274 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-06 22:48:39,274 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-06 22:48:39,275 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-06 22:48:39,275 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-06 22:48:39,275 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-06 22:48:39,275 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-06 22:48:39,275 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-06 22:48:39,275 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-06 22:48:39,301 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-06 22:48:39,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-06 22:48:39,307 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,308 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,310 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,315 INFO L82 PathProgramCache]: Analyzing trace with hash -1674969442, now seen corresponding path program 1 times [2019-10-06 22:48:39,323 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,323 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,324 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,324 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,531 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-06 22:48:39,537 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,538 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:39,539 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:39,545 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:39,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:39,562 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,566 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-06 22:48:39,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:39,627 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-06 22:48:39,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:39,629 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-06 22:48:39,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:39,640 INFO L225 Difference]: With dead ends: 41 [2019-10-06 22:48:39,641 INFO L226 Difference]: Without dead ends: 20 [2019-10-06 22:48:39,654 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-06 22:48:39,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-06 22:48:39,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-06 22:48:39,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-06 22:48:39,714 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-06 22:48:39,714 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:39,715 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-06 22:48:39,716 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:39,717 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-06 22:48:39,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-06 22:48:39,722 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,723 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,723 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,724 INFO L82 PathProgramCache]: Analyzing trace with hash -2035795135, now seen corresponding path program 1 times [2019-10-06 22:48:39,724 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,725 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,725 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,725 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,838 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:39,838 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,839 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:39,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:39,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,930 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-06 22:48:39,941 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:39,978 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:39,978 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,023 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,024 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-06 22:48:40,024 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-06 22:48:40,026 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,026 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,027 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-06 22:48:40,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,037 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-06 22:48:40,038 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,038 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-06 22:48:40,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,039 INFO L225 Difference]: With dead ends: 33 [2019-10-06 22:48:40,040 INFO L226 Difference]: Without dead ends: 21 [2019-10-06 22:48:40,041 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-06 22:48:40,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-06 22:48:40,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-06 22:48:40,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-06 22:48:40,047 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-06 22:48:40,048 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,048 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-06 22:48:40,048 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,048 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-06 22:48:40,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-06 22:48:40,049 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,050 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,255 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,256 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,257 INFO L82 PathProgramCache]: Analyzing trace with hash -629127273, now seen corresponding path program 1 times [2019-10-06 22:48:40,257 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,258 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,258 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,258 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,379 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,380 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,380 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:40,380 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:40,381 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,381 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,382 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,382 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-06 22:48:40,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,403 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-06 22:48:40,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,405 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-06 22:48:40,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,406 INFO L225 Difference]: With dead ends: 31 [2019-10-06 22:48:40,407 INFO L226 Difference]: Without dead ends: 22 [2019-10-06 22:48:40,408 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-06 22:48:40,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-06 22:48:40,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-06 22:48:40,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-06 22:48:40,421 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-06 22:48:40,426 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,427 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-06 22:48:40,427 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,427 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-06 22:48:40,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-06 22:48:40,428 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,429 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,429 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,430 INFO L82 PathProgramCache]: Analyzing trace with hash -1942163656, now seen corresponding path program 1 times [2019-10-06 22:48:40,430 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,430 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,430 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,431 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,577 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,577 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,577 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:40,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,673 INFO L256 TraceCheckSpWp]: Trace formula consists of 136 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,679 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,700 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,701 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,736 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,737 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:40,767 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:40,767 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:40,774 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:40,781 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:40,782 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:40,934 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:43,296 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:43,335 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:43,341 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:43,341 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:43,342 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:43,342 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:48:43,342 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_2 Int) (v_bAnd_~res~0_BEFORE_RETURN_1 Int) (v_prenex_2 Int) (v_prenex_1 Int)) (or (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) main_~ret~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_2 Int) (v_bAnd_~res~0_BEFORE_RETURN_1 Int) (v_prenex_2 Int) (v_prenex_1 Int)) (or (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647))))) [2019-10-06 22:48:43,343 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:43,343 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:43,343 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_bAnd_~res~0_BEFORE_RETURN_6 Int) (v_bAnd_~res~0_BEFORE_RETURN_5 Int) (v_prenex_30 Int)) (or (and (<= (mod v_prenex_29 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= (mod v_prenex_29 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (<= (mod v_prenex_30 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0))))) (and (exists ((v_prenex_29 Int) (v_bAnd_~res~0_BEFORE_RETURN_6 Int) (v_bAnd_~res~0_BEFORE_RETURN_5 Int) (v_prenex_30 Int)) (or (and (<= (mod v_prenex_29 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= (mod v_prenex_29 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (<= (mod v_prenex_30 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:48:43,344 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:43,344 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:43,344 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:43,344 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:43,345 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:43,345 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:43,345 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:48:43,345 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 1000)) (<= 1 bAnd_~i~0) (<= 1000 bAnd_~i~0)) [2019-10-06 22:48:43,346 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_2 Int) (v_prenex_2 Int)) (or (and (not (< main_~i~1 1000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) |main_#t~ret5|)) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 1000))))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (= (+ (mod v_prenex_1 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 1000)) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) |main_#t~ret5|) (not (< main_~i~1 1000)))))) [2019-10-06 22:48:43,346 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:43,346 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:43,346 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:43,347 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:43,956 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:43,956 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-06 22:48:43,958 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-06 22:48:43,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-06 22:48:43,959 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-06 22:48:43,960 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-06 22:48:44,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:44,635 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-06 22:48:44,635 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-06 22:48:44,636 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-06 22:48:44,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:44,636 INFO L225 Difference]: With dead ends: 40 [2019-10-06 22:48:44,637 INFO L226 Difference]: Without dead ends: 25 [2019-10-06 22:48:44,638 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=133, Invalid=737, Unknown=0, NotChecked=0, Total=870 [2019-10-06 22:48:44,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-06 22:48:44,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-06 22:48:44,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-06 22:48:44,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-06 22:48:44,645 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-06 22:48:44,645 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:44,645 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-06 22:48:44,645 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-06 22:48:44,645 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-06 22:48:44,646 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-06 22:48:44,647 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:44,647 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:44,848 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:44,849 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:44,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:44,850 INFO L82 PathProgramCache]: Analyzing trace with hash 143191253, now seen corresponding path program 2 times [2019-10-06 22:48:44,850 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:44,850 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:44,851 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:44,851 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:44,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:44,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:44,959 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:44,959 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:44,960 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:44,960 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:45,055 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-06 22:48:45,055 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:48:45,059 INFO L256 TraceCheckSpWp]: Trace formula consists of 106 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:45,066 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:45,105 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:48:45,105 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:45,138 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:48:45,138 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:45,141 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:45,141 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:45,142 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:45,144 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:45,145 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:45,176 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:46,837 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:46,878 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:46,882 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:46,883 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:46,883 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:46,883 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:48:46,883 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_196 Int) (v_bAnd_~res~0_BEFORE_RETURN_27 Int) (v_bAnd_~res~0_BEFORE_RETURN_28 Int) (v_prenex_195 Int)) (or (and (not (<= (mod v_prenex_196 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296) 2147483647)) (and (not (<= (mod v_prenex_195 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_195 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296))))) [2019-10-06 22:48:46,888 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:46,889 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:46,890 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_prenex_223 Int) (v_bAnd_~res~0_BEFORE_RETURN_32 Int)) (or (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296))) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0))))) (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_prenex_223 Int) (v_bAnd_~res~0_BEFORE_RETURN_32 Int)) (or (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296))) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:48:46,890 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:46,891 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:46,891 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:46,891 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:46,891 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:46,892 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:46,892 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:48:46,892 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 1000)) (<= 1 bAnd_~i~0) (<= 1000 bAnd_~i~0)) [2019-10-06 22:48:46,892 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (not (< main_~i~1 1000)) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296) 2147483647)) (and (= (+ (mod v_prenex_195 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_195 4294967296) 2147483647)) (not (< main_~i~1 1000))))) (exists ((v_prenex_196 Int) (v_bAnd_~res~0_BEFORE_RETURN_28 Int)) (or (and (not (<= (mod v_prenex_196 4294967296) 2147483647)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 1000))) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296) |main_#t~ret5|))))) [2019-10-06 22:48:46,892 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:46,893 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:46,893 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:46,893 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:47,275 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:47,275 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-06 22:48:47,277 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-06 22:48:47,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-06 22:48:47,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-06 22:48:47,278 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-06 22:48:48,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:48,206 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-06 22:48:48,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-06 22:48:48,206 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-06 22:48:48,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:48,207 INFO L225 Difference]: With dead ends: 44 [2019-10-06 22:48:48,207 INFO L226 Difference]: Without dead ends: 29 [2019-10-06 22:48:48,208 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-06 22:48:48,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-06 22:48:48,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-06 22:48:48,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-06 22:48:48,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-06 22:48:48,215 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-06 22:48:48,215 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:48,215 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-06 22:48:48,215 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-06 22:48:48,215 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-06 22:48:48,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-06 22:48:48,217 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:48,217 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:48,420 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:48,421 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:48,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:48,422 INFO L82 PathProgramCache]: Analyzing trace with hash 766317228, now seen corresponding path program 3 times [2019-10-06 22:48:48,422 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:48,422 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:48,423 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:48,423 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:48,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:48,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:48,557 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:48,558 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:48,558 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:48,558 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:48,675 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:48:48,676 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:48:48,677 INFO L256 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-06 22:48:48,680 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:48,690 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:48,690 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:48,765 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:48,766 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:48,767 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:48,768 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:48,768 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:48,769 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:48,769 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:48,788 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:50,380 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:50,412 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:50,416 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:50,416 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:50,417 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:50,417 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:48:50,417 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int) (v_prenex_390 Int) (v_bAnd_~res~0_BEFORE_RETURN_54 Int)) (or (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647)) (and (= (mod v_prenex_389 4294967296) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) main_~ret~0) (<= main_~ret~0 2147483647) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) (- 4294967296)))))) [2019-10-06 22:48:50,418 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:50,418 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:50,419 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_58 Int) (v_prenex_417 Int) (v_bAnd_~res~0_BEFORE_RETURN_57 Int) (v_prenex_418 Int)) (or (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) 2147483647))) (and (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) (- 4294967296)))) (and (= main_~ret5~0 (mod v_prenex_418 4294967296)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_418 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret5~0))) (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_58 Int) (v_prenex_417 Int) (v_bAnd_~res~0_BEFORE_RETURN_57 Int) (v_prenex_418 Int)) (or (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) 2147483647))) (and (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) (- 4294967296)))) (and (= main_~ret5~0 (mod v_prenex_418 4294967296)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_418 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret2~0)))) [2019-10-06 22:48:50,419 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:50,419 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:50,420 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:50,420 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:50,420 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:50,421 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:50,421 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:48:50,421 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 1000)) (<= 1 bAnd_~i~0) (<= 1000 bAnd_~i~0)) [2019-10-06 22:48:50,422 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_390 Int) (v_bAnd_~res~0_BEFORE_RETURN_54 Int)) (or (and (not (< main_~i~1 1000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) |main_#t~ret5|) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_prenex_390 4294967296) (- 4294967296)))))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int)) (or (and (not (< main_~i~1 1000)) (<= (mod v_prenex_389 4294967296) 2147483647) (= (mod v_prenex_389 4294967296) |main_#t~ret5|)) (and (not (< main_~i~1 1000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) (- 4294967296))))))) [2019-10-06 22:48:50,422 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:50,422 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:50,423 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:50,423 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:50,955 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:50,955 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-06 22:48:50,957 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-06 22:48:50,959 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-06 22:48:50,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-06 22:48:50,960 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-06 22:48:52,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:52,055 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-06 22:48:52,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-06 22:48:52,055 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-06 22:48:52,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:52,056 INFO L225 Difference]: With dead ends: 54 [2019-10-06 22:48:52,056 INFO L226 Difference]: Without dead ends: 36 [2019-10-06 22:48:52,060 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-06 22:48:52,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-06 22:48:52,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-06 22:48:52,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-06 22:48:52,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-06 22:48:52,074 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-06 22:48:52,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:52,075 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-06 22:48:52,075 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-06 22:48:52,075 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-06 22:48:52,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-06 22:48:52,076 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:52,076 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:52,276 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:52,277 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:52,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:52,278 INFO L82 PathProgramCache]: Analyzing trace with hash 615727983, now seen corresponding path program 4 times [2019-10-06 22:48:52,278 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:52,278 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:52,279 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:52,279 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:52,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:52,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:52,429 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:52,430 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:52,430 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:52,430 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:52,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:52,561 INFO L256 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-06 22:48:52,564 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:52,578 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:52,578 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:52,854 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:52,855 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:52,857 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:52,857 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:52,857 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:52,858 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:52,858 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:52,900 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:54,180 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:54,204 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:54,208 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:54,209 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:54,209 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:54,209 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:48:54,210 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_583 Int) (v_bAnd_~res~0_BEFORE_RETURN_80 Int) (v_prenex_584 Int) (v_bAnd_~res~0_BEFORE_RETURN_79 Int)) (or (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) main_~ret~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_prenex_584 4294967296) main_~ret~0) (<= (mod v_prenex_584 4294967296) 2147483647)) (and (<= (mod v_prenex_583 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_583 4294967296)) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) 2147483647))))) [2019-10-06 22:48:54,210 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:54,210 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:54,210 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_bAnd_~res~0_BEFORE_RETURN_83 Int) (v_bAnd_~res~0_BEFORE_RETURN_84 Int)) (or (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_prenex_612 4294967296) 2147483647))) (and (<= (mod v_prenex_611 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) 2147483647)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_bAnd_~res~0_BEFORE_RETURN_83 Int) (v_bAnd_~res~0_BEFORE_RETURN_84 Int)) (or (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_prenex_612 4294967296) 2147483647))) (and (<= (mod v_prenex_611 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) 2147483647)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))))) [2019-10-06 22:48:54,211 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:54,235 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:54,235 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:54,235 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:54,236 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:54,236 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:54,236 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:48:54,236 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 1000)) (<= 1 bAnd_~i~0) (<= 1000 bAnd_~i~0)) [2019-10-06 22:48:54,237 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_584 Int) (v_bAnd_~res~0_BEFORE_RETURN_80 Int)) (or (and (= |main_#t~ret5| (mod v_prenex_584 4294967296)) (not (< main_~i~1 1000)) (<= (mod v_prenex_584 4294967296) 2147483647)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) |main_#t~ret5|)))) (exists ((v_prenex_583 Int) (v_bAnd_~res~0_BEFORE_RETURN_79 Int)) (or (and (not (< main_~i~1 1000)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) 2147483647))) (and (not (< main_~i~1 1000)) (<= (mod v_prenex_583 4294967296) 2147483647) (= |main_#t~ret5| (mod v_prenex_583 4294967296)))))) [2019-10-06 22:48:54,237 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:54,237 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:54,237 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:54,237 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:54,631 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:54,632 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-06 22:48:54,633 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-06 22:48:54,634 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-06 22:48:54,635 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-06 22:48:54,635 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 40 states. [2019-10-06 22:48:56,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:56,236 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-06 22:48:56,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-06 22:48:56,236 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 49 [2019-10-06 22:48:56,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:56,237 INFO L225 Difference]: With dead ends: 68 [2019-10-06 22:48:56,237 INFO L226 Difference]: Without dead ends: 50 [2019-10-06 22:48:56,239 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-06 22:48:56,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-06 22:48:56,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-06 22:48:56,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-06 22:48:56,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-06 22:48:56,248 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-06 22:48:56,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:56,248 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-06 22:48:56,248 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-06 22:48:56,249 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-06 22:48:56,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-06 22:48:56,250 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:56,250 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:56,453 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:56,454 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:56,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:56,455 INFO L82 PathProgramCache]: Analyzing trace with hash 2121294031, now seen corresponding path program 5 times [2019-10-06 22:48:56,455 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:56,455 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:56,455 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:56,456 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:56,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:56,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:56,920 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:56,920 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:56,920 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:56,920 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:57,079 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:48:57,079 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:48:57,081 INFO L256 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:57,084 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:57,135 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-06 22:48:57,136 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:57,183 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-06 22:48:57,184 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:57,185 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:57,185 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:57,185 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:57,186 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:57,186 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:57,202 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:58,451 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:58,474 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:58,477 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:58,477 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:58,477 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:58,477 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:48:58,478 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_777 Int) (v_bAnd_~res~0_BEFORE_RETURN_106 Int) (v_bAnd_~res~0_BEFORE_RETURN_105 Int) (v_prenex_778 Int)) (or (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) main_~ret~0)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) (- 4294967296)) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (<= (mod v_prenex_777 4294967296) 2147483647) (= main_~ret~0 (mod v_prenex_777 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-06 22:48:58,478 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:58,478 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:58,478 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret5~0)) (exists ((v_prenex_806 Int) (v_prenex_805 Int) (v_bAnd_~res~0_BEFORE_RETURN_109 Int) (v_bAnd_~res~0_BEFORE_RETURN_110 Int)) (or (and (= main_~ret5~0 (mod v_prenex_806 4294967296)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_806 4294967296) 2147483647)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (mod v_prenex_805 4294967296)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) 2147483647)))))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_806 Int) (v_prenex_805 Int) (v_bAnd_~res~0_BEFORE_RETURN_109 Int) (v_bAnd_~res~0_BEFORE_RETURN_110 Int)) (or (and (= main_~ret5~0 (mod v_prenex_806 4294967296)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_806 4294967296) 2147483647)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (mod v_prenex_805 4294967296)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) 2147483647))))))) [2019-10-06 22:48:58,479 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:58,479 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:48:58,479 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:58,479 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:58,479 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:58,480 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:58,480 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:48:58,480 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 1000)) (<= 1 bAnd_~i~0) (<= 1000 bAnd_~i~0)) [2019-10-06 22:48:58,480 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_777 Int) (v_bAnd_~res~0_BEFORE_RETURN_105 Int)) (or (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) 2147483647)) (not (< main_~i~1 1000))) (and (<= (mod v_prenex_777 4294967296) 2147483647) (= (mod v_prenex_777 4294967296) |main_#t~ret5|) (not (< main_~i~1 1000))))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (< main_~i~1 1000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296) 2147483647) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296))) (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 1000)))))) [2019-10-06 22:48:58,480 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:58,480 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:58,481 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:58,481 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:58,985 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:58,985 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-06 22:48:58,987 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-06 22:48:58,987 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-06 22:48:58,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-06 22:48:58,988 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 44 states. [2019-10-06 22:49:03,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:03,022 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-06 22:49:03,022 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-06 22:49:03,023 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 63 [2019-10-06 22:49:03,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:03,024 INFO L225 Difference]: With dead ends: 72 [2019-10-06 22:49:03,025 INFO L226 Difference]: Without dead ends: 54 [2019-10-06 22:49:03,027 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1350 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1349, Invalid=5457, Unknown=0, NotChecked=0, Total=6806 [2019-10-06 22:49:03,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-06 22:49:03,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-06 22:49:03,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-06 22:49:03,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-06 22:49:03,035 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-06 22:49:03,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:03,036 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-06 22:49:03,036 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-06 22:49:03,036 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-06 22:49:03,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-06 22:49:03,037 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:03,037 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:03,240 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:03,240 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:03,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:03,241 INFO L82 PathProgramCache]: Analyzing trace with hash -1728770399, now seen corresponding path program 6 times [2019-10-06 22:49:03,241 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:03,241 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:03,242 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:03,242 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:03,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:03,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:03,669 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:03,670 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:03,670 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:03,670 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:03,875 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:49:03,875 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:03,876 INFO L256 TraceCheckSpWp]: Trace formula consists of 331 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-06 22:49:03,879 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:03,895 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:03,895 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:04,905 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:04,905 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:04,907 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:04,907 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:04,908 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:04,908 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:04,908 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:04,936 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:06,267 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:06,322 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:06,325 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:06,326 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:06,326 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:06,326 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:49:06,326 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_bAnd_~res~0_BEFORE_RETURN_131 Int) (v_bAnd_~res~0_BEFORE_RETURN_132 Int)) (or (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296) 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) (exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_bAnd_~res~0_BEFORE_RETURN_131 Int) (v_bAnd_~res~0_BEFORE_RETURN_132 Int)) (or (and (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647))))) [2019-10-06 22:49:06,327 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:06,327 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:06,328 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_135 Int) (v_bAnd_~res~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_prenex_1000 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_135 Int) (v_bAnd_~res~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_prenex_1000 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))))) [2019-10-06 22:49:06,328 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:06,328 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:06,328 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:06,329 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:06,329 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:06,329 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:06,329 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:49:06,330 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 1000)) (<= 1 bAnd_~i~0) (<= 1000 bAnd_~i~0)) [2019-10-06 22:49:06,330 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_971 Int) (v_bAnd_~res~0_BEFORE_RETURN_131 Int)) (or (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (= (+ (mod v_prenex_971 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 1000))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) |main_#t~ret5|) (not (< main_~i~1 1000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) 2147483647)))) (exists ((v_prenex_972 Int) (v_bAnd_~res~0_BEFORE_RETURN_132 Int)) (or (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296) 2147483647) (not (< main_~i~1 1000)) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296))) (and (not (<= (mod v_prenex_972 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= (+ (mod v_prenex_972 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 22:49:06,330 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:06,330 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:06,331 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:06,331 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:06,838 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:06,839 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-06 22:49:06,840 INFO L442 AbstractCegarLoop]: Interpolant automaton has 70 states [2019-10-06 22:49:06,841 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2019-10-06 22:49:06,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1740, Invalid=3090, Unknown=0, NotChecked=0, Total=4830 [2019-10-06 22:49:06,843 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 70 states. [2019-10-06 22:49:10,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:10,226 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-06 22:49:10,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2019-10-06 22:49:10,226 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 67 [2019-10-06 22:49:10,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:10,228 INFO L225 Difference]: With dead ends: 104 [2019-10-06 22:49:10,228 INFO L226 Difference]: Without dead ends: 83 [2019-10-06 22:49:10,233 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3929 ImplicationChecksByTransitivity, 4.8s TimeCoverageRelationStatistics Valid=5099, Invalid=12723, Unknown=0, NotChecked=0, Total=17822 [2019-10-06 22:49:10,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-06 22:49:10,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-06 22:49:10,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-06 22:49:10,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-06 22:49:10,242 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-06 22:49:10,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:10,242 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-06 22:49:10,243 INFO L463 AbstractCegarLoop]: Interpolant automaton has 70 states. [2019-10-06 22:49:10,243 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-06 22:49:10,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-06 22:49:10,244 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:10,244 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:10,448 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:10,449 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:10,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:10,450 INFO L82 PathProgramCache]: Analyzing trace with hash 1695588190, now seen corresponding path program 7 times [2019-10-06 22:49:10,450 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:10,450 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:10,451 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:10,451 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:10,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:10,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:11,870 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:11,871 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:11,871 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:11,871 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:12,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:12,155 INFO L256 TraceCheckSpWp]: Trace formula consists of 505 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-06 22:49:12,159 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:12,183 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:12,183 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:15,777 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:15,777 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:15,779 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:15,779 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:15,779 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:15,780 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:15,780 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:15,799 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:17,036 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:17,058 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:17,061 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:17,061 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:17,061 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:17,061 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:49:17,062 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_157 Int) (v_bAnd_~res~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int) (v_prenex_1165 Int)) (or (and (<= (mod v_prenex_1166 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_prenex_1166 4294967296))) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_158 4294967296) 2147483647)) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_158 4294967296) (- 4294967296)))) (and (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1165 4294967296) 2147483647))) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_157 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_bAnd_~res~0_BEFORE_RETURN_157 4294967296) main_~ret~0) (<= main_~ret~0 2147483647)))) [2019-10-06 22:49:17,062 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:17,062 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:17,063 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_161 Int) (v_prenex_1194 Int) (v_prenex_1193 Int) (v_bAnd_~res~0_BEFORE_RETURN_162 Int)) (or (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_161 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_prenex_1193 4294967296) 2147483647) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_162 4294967296) 2147483647))) (and (<= (mod v_prenex_1194 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_161 Int) (v_prenex_1194 Int) (v_prenex_1193 Int) (v_bAnd_~res~0_BEFORE_RETURN_162 Int)) (or (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_161 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_prenex_1193 4294967296) 2147483647) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_162 4294967296) 2147483647))) (and (<= (mod v_prenex_1194 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))))) [2019-10-06 22:49:17,063 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:17,063 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:17,063 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:17,064 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:17,064 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:17,064 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:17,064 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:49:17,064 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 1000)) (<= 1 bAnd_~i~0) (<= 1000 bAnd_~i~0)) [2019-10-06 22:49:17,065 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int)) (or (and (= (mod v_prenex_1166 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1166 4294967296) 2147483647) (not (< main_~i~1 1000))) (and (not (< main_~i~1 1000)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_158 4294967296) 2147483647))))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_157 Int) (v_prenex_1165 Int)) (or (and (not (< main_~i~1 1000)) (not (<= (mod v_prenex_1165 4294967296) 2147483647)) (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_157 4294967296) |main_#t~ret5|) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_157 4294967296) 2147483647) (not (< main_~i~1 1000)))))) [2019-10-06 22:49:17,065 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:17,065 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:17,065 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:17,065 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:17,747 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:17,748 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 127 [2019-10-06 22:49:17,749 INFO L442 AbstractCegarLoop]: Interpolant automaton has 128 states [2019-10-06 22:49:17,751 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 128 interpolants. [2019-10-06 22:49:17,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6815, Invalid=9441, Unknown=0, NotChecked=0, Total=16256 [2019-10-06 22:49:17,755 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 128 states. [2019-10-06 22:49:27,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:27,497 INFO L93 Difference]: Finished difference Result 162 states and 227 transitions. [2019-10-06 22:49:27,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 127 states. [2019-10-06 22:49:27,498 INFO L78 Accepts]: Start accepts. Automaton has 128 states. Word has length 96 [2019-10-06 22:49:27,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:27,499 INFO L225 Difference]: With dead ends: 162 [2019-10-06 22:49:27,499 INFO L226 Difference]: Without dead ends: 141 [2019-10-06 22:49:27,504 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 471 GetRequests, 223 SyntacticMatches, 0 SemanticMatches, 248 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12078 ImplicationChecksByTransitivity, 14.5s TimeCoverageRelationStatistics Valid=20208, Invalid=42042, Unknown=0, NotChecked=0, Total=62250 [2019-10-06 22:49:27,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2019-10-06 22:49:27,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2019-10-06 22:49:27,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2019-10-06 22:49:27,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 145 transitions. [2019-10-06 22:49:27,520 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 145 transitions. Word has length 96 [2019-10-06 22:49:27,520 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:27,520 INFO L462 AbstractCegarLoop]: Abstraction has 141 states and 145 transitions. [2019-10-06 22:49:27,520 INFO L463 AbstractCegarLoop]: Interpolant automaton has 128 states. [2019-10-06 22:49:27,520 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 145 transitions. [2019-10-06 22:49:27,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2019-10-06 22:49:27,523 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:27,523 INFO L385 BasicCegarLoop]: trace histogram [114, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:27,730 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:27,730 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:27,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:27,731 INFO L82 PathProgramCache]: Analyzing trace with hash -795247042, now seen corresponding path program 8 times [2019-10-06 22:49:27,731 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:27,731 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:27,732 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:27,732 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:27,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:27,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:32,797 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 0 proven. 6555 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:32,800 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:32,800 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:32,800 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:33,071 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:49:33,071 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:33,072 INFO L256 TraceCheckSpWp]: Trace formula consists of 141 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 22:49:33,076 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:33,333 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 22:49:33,333 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:33,608 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 22:49:33,608 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:33,610 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:33,610 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:33,610 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:33,610 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:33,610 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:33,625 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:34,846 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:34,878 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:34,881 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:34,881 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:34,881 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:34,881 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:49:34,882 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_1359 Int) (v_bAnd_~res~0_BEFORE_RETURN_183 Int) (v_prenex_1360 Int) (v_bAnd_~res~0_BEFORE_RETURN_184 Int)) (or (and (= main_~ret~0 (mod v_prenex_1359 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1359 4294967296) 2147483647)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1360 4294967296) 2147483647))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) main_~ret~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-06 22:49:34,882 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:34,882 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:34,883 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_188 Int) (v_prenex_1388 Int) (v_prenex_1387 Int) (v_bAnd_~res~0_BEFORE_RETURN_187 Int)) (or (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_188 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_187 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_187 4294967296) 2147483647))) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_1388 4294967296) 2147483647)) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0))))) (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_188 Int) (v_prenex_1388 Int) (v_prenex_1387 Int) (v_bAnd_~res~0_BEFORE_RETURN_187 Int)) (or (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_188 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_187 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_187 4294967296) 2147483647))) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_1388 4294967296) 2147483647)) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:49:34,884 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:34,884 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:34,884 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:34,884 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:34,884 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:34,884 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:34,885 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:49:34,885 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 1000)) (<= 1 bAnd_~i~0) (<= 1000 bAnd_~i~0)) [2019-10-06 22:49:34,885 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1359 Int) (v_bAnd_~res~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 1000)) (= (mod v_prenex_1359 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1359 4294967296) 2147483647)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 1000))))) (exists ((v_prenex_1360 Int) (v_bAnd_~res~0_BEFORE_RETURN_184 Int)) (or (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) |main_#t~ret5|)) (and (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 1000)) (not (<= (mod v_prenex_1360 4294967296) 2147483647)))))) [2019-10-06 22:49:34,885 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:34,885 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:34,885 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:34,885 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:35,990 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:35,990 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [117, 7, 7, 11] total 137 [2019-10-06 22:49:35,991 INFO L442 AbstractCegarLoop]: Interpolant automaton has 138 states [2019-10-06 22:49:35,993 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 138 interpolants. [2019-10-06 22:49:35,994 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6880, Invalid=12026, Unknown=0, NotChecked=0, Total=18906 [2019-10-06 22:49:35,994 INFO L87 Difference]: Start difference. First operand 141 states and 145 transitions. Second operand 138 states. [2019-10-06 22:49:49,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:49,360 INFO L93 Difference]: Finished difference Result 169 states and 186 transitions. [2019-10-06 22:49:49,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 138 states. [2019-10-06 22:49:49,360 INFO L78 Accepts]: Start accepts. Automaton has 138 states. Word has length 154 [2019-10-06 22:49:49,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:49,362 INFO L225 Difference]: With dead ends: 169 [2019-10-06 22:49:49,362 INFO L226 Difference]: Without dead ends: 148 [2019-10-06 22:49:49,365 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 711 GetRequests, 442 SyntacticMatches, 0 SemanticMatches, 269 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12311 ImplicationChecksByTransitivity, 18.0s TimeCoverageRelationStatistics Valid=20694, Invalid=52476, Unknown=0, NotChecked=0, Total=73170 [2019-10-06 22:49:49,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2019-10-06 22:49:49,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 148. [2019-10-06 22:49:49,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2019-10-06 22:49:49,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 152 transitions. [2019-10-06 22:49:49,381 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 152 transitions. Word has length 154 [2019-10-06 22:49:49,382 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:49,382 INFO L462 AbstractCegarLoop]: Abstraction has 148 states and 152 transitions. [2019-10-06 22:49:49,382 INFO L463 AbstractCegarLoop]: Interpolant automaton has 138 states. [2019-10-06 22:49:49,382 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 152 transitions. [2019-10-06 22:49:49,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2019-10-06 22:49:49,384 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:49,384 INFO L385 BasicCegarLoop]: trace histogram [115, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:49,593 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:49,594 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:49,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:49,595 INFO L82 PathProgramCache]: Analyzing trace with hash 1403267681, now seen corresponding path program 9 times [2019-10-06 22:49:49,595 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:49,595 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:49,595 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:49,596 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:49,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:49,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:54,635 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:49:54,635 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:54,635 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:54,636 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:55,058 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:49:55,058 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:55,064 INFO L256 TraceCheckSpWp]: Trace formula consists of 913 conjuncts, 117 conjunts are in the unsatisfiable core [2019-10-06 22:49:55,068 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:55,120 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:49:55,121 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:09,517 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:50:09,517 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:09,518 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:09,519 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:09,519 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:09,519 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:09,519 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:09,535 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:50:10,763 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:50:10,793 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:50:10,796 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:50:10,796 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:50:10,796 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:50:10,797 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:50:10,797 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_bAnd_~res~0_BEFORE_RETURN_209 Int)) (or (and (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (mod v_prenex_1553 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1553 4294967296) 2147483647)) (and (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_bAnd_~res~0_BEFORE_RETURN_209 Int)) (or (and (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) main_~ret~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (mod v_prenex_1553 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1553 4294967296) 2147483647)) (and (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) 2147483647)) (<= main_~ret~0 2147483647))))) [2019-10-06 22:50:10,797 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:50:10,797 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:50:10,797 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_213 Int) (v_bAnd_~res~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_213 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_213 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_214 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (mod v_bAnd_~res~0_BEFORE_RETURN_214 4294967296) main_~ret5~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_213 Int) (v_bAnd_~res~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_213 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_213 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_214 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (mod v_bAnd_~res~0_BEFORE_RETURN_214 4294967296) main_~ret5~0)))))) [2019-10-06 22:50:10,798 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:10,798 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:50:10,798 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:10,798 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:50:10,798 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:50:10,799 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:50:10,799 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:50:10,799 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 1000)) (<= 1 bAnd_~i~0) (<= 1000 bAnd_~i~0)) [2019-10-06 22:50:10,799 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int)) (or (and (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 1000)) (not (<= (mod v_prenex_1554 4294967296) 2147483647))) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) |main_#t~ret5|)))) (exists ((v_prenex_1553 Int) (v_bAnd_~res~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 1000)) (= (mod v_prenex_1553 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1553 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 22:50:10,800 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:50:10,800 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:50:10,800 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:50:10,800 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:50:14,214 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:50:14,214 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [118, 118, 118, 11] total 245 [2019-10-06 22:50:14,216 INFO L442 AbstractCegarLoop]: Interpolant automaton has 246 states [2019-10-06 22:50:14,221 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 246 interpolants. [2019-10-06 22:50:14,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27524, Invalid=32745, Unknown=1, NotChecked=0, Total=60270 [2019-10-06 22:50:14,224 INFO L87 Difference]: Start difference. First operand 148 states and 152 transitions. Second operand 246 states. [2019-10-06 22:50:50,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:50,618 INFO L93 Difference]: Finished difference Result 292 states and 416 transitions. [2019-10-06 22:50:50,618 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 245 states. [2019-10-06 22:50:50,618 INFO L78 Accepts]: Start accepts. Automaton has 246 states. Word has length 173 [2019-10-06 22:50:50,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:50,622 INFO L225 Difference]: With dead ends: 292 [2019-10-06 22:50:50,622 INFO L226 Difference]: Without dead ends: 265 [2019-10-06 22:50:50,630 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 879 GetRequests, 395 SyntacticMatches, 0 SemanticMatches, 484 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41637 ImplicationChecksByTransitivity, 55.1s TimeCoverageRelationStatistics Valid=82099, Invalid=153610, Unknown=1, NotChecked=0, Total=235710 [2019-10-06 22:50:50,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2019-10-06 22:50:50,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 265. [2019-10-06 22:50:50,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2019-10-06 22:50:50,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 269 transitions. [2019-10-06 22:50:50,655 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 269 transitions. Word has length 173 [2019-10-06 22:50:50,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:50,656 INFO L462 AbstractCegarLoop]: Abstraction has 265 states and 269 transitions. [2019-10-06 22:50:50,656 INFO L463 AbstractCegarLoop]: Interpolant automaton has 246 states. [2019-10-06 22:50:50,656 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 269 transitions. [2019-10-06 22:50:50,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2019-10-06 22:50:50,660 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:50,661 INFO L385 BasicCegarLoop]: trace histogram [232, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:50,866 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:50,867 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:50,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:50,867 INFO L82 PathProgramCache]: Analyzing trace with hash 892913502, now seen corresponding path program 10 times [2019-10-06 22:50:50,868 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:50,868 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:50,868 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:50,868 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:50,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:51,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:10,809 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:51:10,809 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:10,809 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:51:10,809 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:11,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:11,407 INFO L256 TraceCheckSpWp]: Trace formula consists of 1615 conjuncts, 234 conjunts are in the unsatisfiable core [2019-10-06 22:51:11,415 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:51:11,547 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:51:11,547 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:52:11,060 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:52:11,060 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:52:11,062 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:52:11,062 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:52:11,062 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:52:11,063 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:52:11,063 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:52:11,079 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:52:12,810 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:52:12,845 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:52:12,847 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:52:12,847 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:52:12,848 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:52:12,848 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:52:12,848 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_235 Int) (v_bAnd_~res~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int) (v_prenex_1747 Int)) (or (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1747 4294967296) 2147483647) (= main_~ret~0 (mod v_prenex_1747 4294967296)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_235 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_235 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (= (+ (mod v_prenex_1748 4294967296) (- 4294967296)) main_~ret~0) (not (<= (mod v_prenex_1748 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_236 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_236 4294967296))))) [2019-10-06 22:52:12,848 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:52:12,848 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:52:12,849 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_1776 Int) (v_prenex_1775 Int) (v_bAnd_~res~0_BEFORE_RETURN_239 Int) (v_bAnd_~res~0_BEFORE_RETURN_240 Int)) (or (and (<= (mod v_prenex_1775 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1776 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1776 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_239 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_240 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_240 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_1776 Int) (v_prenex_1775 Int) (v_bAnd_~res~0_BEFORE_RETURN_239 Int) (v_bAnd_~res~0_BEFORE_RETURN_240 Int)) (or (and (<= (mod v_prenex_1775 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1776 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1776 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_239 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_240 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_240 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))))) [2019-10-06 22:52:12,849 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:12,849 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:12,849 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:12,849 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:52:12,850 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:52:12,850 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:52:12,850 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:52:12,850 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 1000)) (<= 1 bAnd_~i~0) (<= 1000 bAnd_~i~0)) [2019-10-06 22:52:12,850 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_235 Int) (v_prenex_1747 Int)) (or (and (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_235 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_235 4294967296) 2147483647))) (and (not (< main_~i~1 1000)) (<= (mod v_prenex_1747 4294967296) 2147483647) (= (mod v_prenex_1747 4294967296) |main_#t~ret5|)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int)) (or (and (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_236 4294967296)) (not (< main_~i~1 1000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_236 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (not (<= (mod v_prenex_1748 4294967296) 2147483647)) (= (+ (mod v_prenex_1748 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 22:52:12,850 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:52:12,850 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:52:12,851 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:52:12,851 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:52:14,835 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:52:14,836 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [235, 235, 235, 11] total 479 [2019-10-06 22:52:14,838 INFO L442 AbstractCegarLoop]: Interpolant automaton has 480 states [2019-10-06 22:52:14,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 480 interpolants. [2019-10-06 22:52:14,854 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=109775, Invalid=120145, Unknown=0, NotChecked=0, Total=229920 [2019-10-06 22:52:14,854 INFO L87 Difference]: Start difference. First operand 265 states and 269 transitions. Second operand 480 states. [2019-10-06 22:54:30,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:54:30,292 INFO L93 Difference]: Finished difference Result 526 states and 767 transitions. [2019-10-06 22:54:30,292 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 479 states. [2019-10-06 22:54:30,292 INFO L78 Accepts]: Start accepts. Automaton has 480 states. Word has length 290 [2019-10-06 22:54:30,293 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:54:30,295 INFO L225 Difference]: With dead ends: 526 [2019-10-06 22:54:30,295 INFO L226 Difference]: Without dead ends: 499 [2019-10-06 22:54:30,321 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1581 GetRequests, 629 SyntacticMatches, 0 SemanticMatches, 952 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151734 ImplicationChecksByTransitivity, 202.6s TimeCoverageRelationStatistics Valid=328384, Invalid=580778, Unknown=0, NotChecked=0, Total=909162 [2019-10-06 22:54:30,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 499 states. [2019-10-06 22:54:30,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 499 to 499. [2019-10-06 22:54:30,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 499 states. [2019-10-06 22:54:30,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 499 states to 499 states and 503 transitions. [2019-10-06 22:54:30,353 INFO L78 Accepts]: Start accepts. Automaton has 499 states and 503 transitions. Word has length 290 [2019-10-06 22:54:30,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:54:30,353 INFO L462 AbstractCegarLoop]: Abstraction has 499 states and 503 transitions. [2019-10-06 22:54:30,353 INFO L463 AbstractCegarLoop]: Interpolant automaton has 480 states. [2019-10-06 22:54:30,353 INFO L276 IsEmpty]: Start isEmpty. Operand 499 states and 503 transitions. [2019-10-06 22:54:30,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 525 [2019-10-06 22:54:30,365 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:54:30,365 INFO L385 BasicCegarLoop]: trace histogram [466, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:54:30,570 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:54:30,571 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:54:30,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:54:30,571 INFO L82 PathProgramCache]: Analyzing trace with hash -1526853826, now seen corresponding path program 11 times [2019-10-06 22:54:30,572 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:54:30,572 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:54:30,572 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:30,572 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:30,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:54:32,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:55:49,991 INFO L134 CoverageAnalysis]: Checked inductivity of 109355 backedges. 0 proven. 108811 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:55:49,992 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:55:49,992 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:55:49,992 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:55:50,528 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2019-10-06 22:55:50,528 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:55:50,530 INFO L256 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 22:55:50,539 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:55:51,529 INFO L134 CoverageAnalysis]: Checked inductivity of 109355 backedges. 246 proven. 10 refuted. 0 times theorem prover too weak. 109099 trivial. 0 not checked. [2019-10-06 22:55:51,529 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:55:52,672 INFO L134 CoverageAnalysis]: Checked inductivity of 109355 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 109345 trivial. 0 not checked. [2019-10-06 22:55:52,672 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:55:52,674 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:55:52,674 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:55:52,674 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:55:52,674 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:55:52,675 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:55:52,693 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:55:53,758 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:55:53,779 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:55:53,782 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:55:53,782 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:55:53,782 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:55:53,782 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:55:53,783 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_bAnd_~res~0_BEFORE_RETURN_261 Int) (v_bAnd_~res~0_BEFORE_RETURN_262 Int)) (or (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_1942 4294967296) (- 4294967296)) main_~ret~0)) (and (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_261 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_261 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_262 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_262 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (mod v_prenex_1941 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1941 4294967296) 2147483647)))) [2019-10-06 22:55:53,783 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:55:53,783 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:55:53,783 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_265 Int) (v_bAnd_~res~0_BEFORE_RETURN_266 Int) (v_prenex_1970 Int) (v_prenex_1969 Int)) (or (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_prenex_1969 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (mod v_bAnd_~res~0_BEFORE_RETURN_266 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_266 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_265 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_265 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_265 Int) (v_bAnd_~res~0_BEFORE_RETURN_266 Int) (v_prenex_1970 Int) (v_prenex_1969 Int)) (or (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_prenex_1969 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (mod v_bAnd_~res~0_BEFORE_RETURN_266 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_266 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_265 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_265 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))))) [2019-10-06 22:55:53,784 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:53,784 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:53,784 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:53,784 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:55:53,784 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:55:53,784 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:55:53,785 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:55:53,785 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (not (< bAnd_~i~0 1000)) (<= 1 bAnd_~i~0) (<= 1000 bAnd_~i~0)) [2019-10-06 22:55:53,785 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1941 Int) (v_bAnd_~res~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 1000)) (= (mod v_prenex_1941 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1941 4294967296) 2147483647)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_261 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_261 4294967296) (- 4294967296)))))) (exists ((v_prenex_1942 Int) (v_bAnd_~res~0_BEFORE_RETURN_262 Int)) (or (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_262 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_262 4294967296) |main_#t~ret5|)) (and (not (< main_~i~1 1000)) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_prenex_1942 4294967296) (- 4294967296))))))) [2019-10-06 22:55:53,785 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:55:53,785 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:55:53,785 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:55:53,786 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:55:57,446 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:55:57,447 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [469, 7, 7, 11] total 489 [2019-10-06 22:55:57,450 INFO L442 AbstractCegarLoop]: Interpolant automaton has 490 states [2019-10-06 22:55:57,461 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 490 interpolants. [2019-10-06 22:55:57,469 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=109840, Invalid=129770, Unknown=0, NotChecked=0, Total=239610 [2019-10-06 22:55:57,470 INFO L87 Difference]: Start difference. First operand 499 states and 503 transitions. Second operand 490 states. [2019-10-06 22:58:23,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:58:23,727 INFO L93 Difference]: Finished difference Result 533 states and 547 transitions. [2019-10-06 22:58:23,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 490 states. [2019-10-06 22:58:23,727 INFO L78 Accepts]: Start accepts. Automaton has 490 states. Word has length 524 [2019-10-06 22:58:23,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:58:23,730 INFO L225 Difference]: With dead ends: 533 [2019-10-06 22:58:23,730 INFO L226 Difference]: Without dead ends: 506 [2019-10-06 22:58:23,760 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 2526 GetRequests, 1553 SyntacticMatches, 0 SemanticMatches, 973 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 131111 ImplicationChecksByTransitivity, 218.2s TimeCoverageRelationStatistics Valid=329534, Invalid=620116, Unknown=0, NotChecked=0, Total=949650 [2019-10-06 22:58:23,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 506 states. [2019-10-06 22:58:23,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 506 to 506. [2019-10-06 22:58:23,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 506 states. [2019-10-06 22:58:23,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 506 states to 506 states and 510 transitions. [2019-10-06 22:58:23,787 INFO L78 Accepts]: Start accepts. Automaton has 506 states and 510 transitions. Word has length 524 [2019-10-06 22:58:23,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:58:23,788 INFO L462 AbstractCegarLoop]: Abstraction has 506 states and 510 transitions. [2019-10-06 22:58:23,788 INFO L463 AbstractCegarLoop]: Interpolant automaton has 490 states. [2019-10-06 22:58:23,788 INFO L276 IsEmpty]: Start isEmpty. Operand 506 states and 510 transitions. [2019-10-06 22:58:23,792 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 532 [2019-10-06 22:58:23,792 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:58:23,792 INFO L385 BasicCegarLoop]: trace histogram [467, 30, 10, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:58:23,994 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:58:23,995 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:58:23,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:58:23,995 INFO L82 PathProgramCache]: Analyzing trace with hash 147366017, now seen corresponding path program 12 times [2019-10-06 22:58:23,995 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:58:23,996 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:58:23,996 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:58:23,996 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:58:23,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:58:25,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:59:42,170 INFO L134 CoverageAnalysis]: Checked inductivity of 109867 backedges. 0 proven. 109278 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-10-06 22:59:42,170 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:59:42,170 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:59:42,170 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:59:43,131 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:59:43,131 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:59:43,147 INFO L256 TraceCheckSpWp]: Trace formula consists of 3049 conjuncts, 469 conjunts are in the unsatisfiable core [2019-10-06 22:59:43,162 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:59:43,658 INFO L134 CoverageAnalysis]: Checked inductivity of 109867 backedges. 0 proven. 109278 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-10-06 22:59:43,658 INFO L322 TraceCheckSpWp]: Computing backward predicates...