java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/array-crafted/bAnd3.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-06 22:48:37,234 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-06 22:48:37,240 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-06 22:48:37,260 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-06 22:48:37,260 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-06 22:48:37,262 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-06 22:48:37,264 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-06 22:48:37,274 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-06 22:48:37,277 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-06 22:48:37,278 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-06 22:48:37,280 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-06 22:48:37,281 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-06 22:48:37,281 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-06 22:48:37,284 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-06 22:48:37,287 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-06 22:48:37,288 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-06 22:48:37,290 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-06 22:48:37,292 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-06 22:48:37,294 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-06 22:48:37,299 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-06 22:48:37,304 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-06 22:48:37,307 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-06 22:48:37,309 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-06 22:48:37,310 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-06 22:48:37,313 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-06 22:48:37,324 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-06 22:48:37,325 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-06 22:48:37,326 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-06 22:48:37,327 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-06 22:48:37,361 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-06 22:48:37,361 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-06 22:48:37,367 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-06 22:48:37,367 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-06 22:48:37,367 INFO L138 SettingsManager]: * Use SBE=true [2019-10-06 22:48:37,367 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-06 22:48:37,368 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-06 22:48:37,368 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-06 22:48:37,368 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-06 22:48:37,369 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-06 22:48:37,369 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-06 22:48:37,369 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-06 22:48:37,369 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-06 22:48:37,370 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-06 22:48:37,370 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-06 22:48:37,370 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-06 22:48:37,371 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-06 22:48:37,371 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-06 22:48:37,372 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-06 22:48:37,372 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-06 22:48:37,372 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-06 22:48:37,372 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:37,372 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-06 22:48:37,373 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-06 22:48:37,373 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-06 22:48:37,373 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-06 22:48:37,373 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-06 22:48:37,374 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-06 22:48:37,374 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-06 22:48:37,682 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-06 22:48:37,695 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-06 22:48:37,698 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-06 22:48:37,700 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-06 22:48:37,700 INFO L275 PluginConnector]: CDTParser initialized [2019-10-06 22:48:37,701 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-crafted/bAnd3.i [2019-10-06 22:48:37,767 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7a99014e4/9098cfc8f17e4d4f8189ddef3d4676a5/FLAG7669e53c9 [2019-10-06 22:48:38,256 INFO L306 CDTParser]: Found 1 translation units. [2019-10-06 22:48:38,256 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-crafted/bAnd3.i [2019-10-06 22:48:38,262 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7a99014e4/9098cfc8f17e4d4f8189ddef3d4676a5/FLAG7669e53c9 [2019-10-06 22:48:38,618 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7a99014e4/9098cfc8f17e4d4f8189ddef3d4676a5 [2019-10-06 22:48:38,628 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-06 22:48:38,629 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-06 22:48:38,631 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,631 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-06 22:48:38,634 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-06 22:48:38,635 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,639 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@11574e77 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38, skipping insertion in model container [2019-10-06 22:48:38,639 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,647 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-06 22:48:38,668 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-06 22:48:38,892 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,900 INFO L188 MainTranslator]: Completed pre-run [2019-10-06 22:48:38,920 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,936 INFO L192 MainTranslator]: Completed translation [2019-10-06 22:48:38,936 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38 WrapperNode [2019-10-06 22:48:38,937 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,937 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-06 22:48:38,938 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-06 22:48:38,938 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-06 22:48:39,029 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,030 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,040 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,042 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,060 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,065 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,067 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,069 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-06 22:48:39,070 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-06 22:48:39,070 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-06 22:48:39,070 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-06 22:48:39,071 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:39,136 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-06 22:48:39,136 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-06 22:48:39,136 INFO L138 BoogieDeclarations]: Found implementation of procedure bAnd [2019-10-06 22:48:39,136 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-06 22:48:39,136 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-06 22:48:39,137 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-06 22:48:39,137 INFO L130 BoogieDeclarations]: Found specification of procedure bAnd [2019-10-06 22:48:39,137 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-06 22:48:39,137 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-06 22:48:39,137 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-06 22:48:39,137 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-06 22:48:39,138 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-06 22:48:39,138 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-06 22:48:39,138 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-06 22:48:39,500 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-06 22:48:39,500 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-06 22:48:39,501 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39 BoogieIcfgContainer [2019-10-06 22:48:39,502 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-06 22:48:39,503 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-06 22:48:39,503 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-06 22:48:39,506 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-06 22:48:39,506 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.10 10:48:38" (1/3) ... [2019-10-06 22:48:39,507 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@13b39aa3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,507 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (2/3) ... [2019-10-06 22:48:39,508 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@13b39aa3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,508 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39" (3/3) ... [2019-10-06 22:48:39,510 INFO L109 eAbstractionObserver]: Analyzing ICFG bAnd3.i [2019-10-06 22:48:39,521 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-06 22:48:39,528 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-06 22:48:39,540 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-06 22:48:39,563 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-06 22:48:39,563 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-06 22:48:39,563 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-06 22:48:39,563 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-06 22:48:39,564 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-06 22:48:39,564 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-06 22:48:39,564 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-06 22:48:39,564 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-06 22:48:39,579 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-06 22:48:39,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-06 22:48:39,584 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,585 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,587 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,591 INFO L82 PathProgramCache]: Analyzing trace with hash -1674969442, now seen corresponding path program 1 times [2019-10-06 22:48:39,598 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,598 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,599 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,599 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,782 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-06 22:48:39,782 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,783 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:39,785 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:39,789 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:39,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:39,804 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,807 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-06 22:48:39,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:39,844 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-06 22:48:39,845 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:39,847 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-06 22:48:39,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:39,856 INFO L225 Difference]: With dead ends: 41 [2019-10-06 22:48:39,857 INFO L226 Difference]: Without dead ends: 20 [2019-10-06 22:48:39,860 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-06 22:48:39,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-06 22:48:39,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-06 22:48:39,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-06 22:48:39,918 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-06 22:48:39,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:39,920 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-06 22:48:39,920 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:39,921 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-06 22:48:39,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-06 22:48:39,926 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,926 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,927 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,928 INFO L82 PathProgramCache]: Analyzing trace with hash -2035795135, now seen corresponding path program 1 times [2019-10-06 22:48:39,928 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,928 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,929 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,929 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,046 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,047 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,047 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:40,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,142 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,151 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,189 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,190 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,239 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,240 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-06 22:48:40,240 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-06 22:48:40,242 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,243 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,243 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,243 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-06 22:48:40,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,259 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-06 22:48:40,260 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,260 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-06 22:48:40,260 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,261 INFO L225 Difference]: With dead ends: 33 [2019-10-06 22:48:40,261 INFO L226 Difference]: Without dead ends: 21 [2019-10-06 22:48:40,263 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-06 22:48:40,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-06 22:48:40,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-06 22:48:40,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-06 22:48:40,270 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-06 22:48:40,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,271 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-06 22:48:40,271 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,271 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-06 22:48:40,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-06 22:48:40,272 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,272 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,478 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,478 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,479 INFO L82 PathProgramCache]: Analyzing trace with hash -629127273, now seen corresponding path program 1 times [2019-10-06 22:48:40,479 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,480 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,480 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,480 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,582 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,583 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,583 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:40,583 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:40,584 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,585 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-06 22:48:40,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,605 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-06 22:48:40,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,607 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-06 22:48:40,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,608 INFO L225 Difference]: With dead ends: 31 [2019-10-06 22:48:40,608 INFO L226 Difference]: Without dead ends: 22 [2019-10-06 22:48:40,610 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-06 22:48:40,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-06 22:48:40,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-06 22:48:40,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-06 22:48:40,622 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-06 22:48:40,627 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,627 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-06 22:48:40,628 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,628 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-06 22:48:40,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-06 22:48:40,631 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,631 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,632 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,632 INFO L82 PathProgramCache]: Analyzing trace with hash -1942163656, now seen corresponding path program 1 times [2019-10-06 22:48:40,632 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,633 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,633 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,633 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,784 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,784 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,785 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:40,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,868 INFO L256 TraceCheckSpWp]: Trace formula consists of 136 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,874 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,895 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,895 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,945 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,945 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:40,972 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:40,972 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:40,979 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:40,987 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:40,988 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:41,141 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:43,334 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:43,372 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:43,378 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:43,378 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:43,378 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:43,379 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:48:43,379 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_2 Int) (v_bAnd_~res~0_BEFORE_RETURN_1 Int) (v_prenex_2 Int) (v_prenex_1 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~0)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_2 Int) (v_bAnd_~res~0_BEFORE_RETURN_1 Int) (v_prenex_2 Int) (v_prenex_1 Int)) (or (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) main_~ret~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~0))))) [2019-10-06 22:48:43,380 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_bAnd_~res~0_BEFORE_RETURN_6 Int) (v_bAnd_~res~0_BEFORE_RETURN_5 Int) (v_prenex_30 Int)) (or (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (not (< main_~i~2 9999)) (<= (mod v_prenex_30 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_prenex_29 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= (mod v_prenex_29 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)))))) (and (exists ((v_prenex_29 Int) (v_bAnd_~res~0_BEFORE_RETURN_6 Int) (v_bAnd_~res~0_BEFORE_RETURN_5 Int) (v_prenex_30 Int)) (or (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (not (< main_~i~2 9999)) (<= (mod v_prenex_30 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_prenex_29 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= (mod v_prenex_29 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:48:43,380 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:43,380 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:43,381 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:43,381 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:43,381 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:43,381 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:43,400 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:43,401 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:43,401 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:48:43,401 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-06 22:48:43,401 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod v_prenex_1 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) |main_#t~ret5|)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_2 Int) (v_prenex_2 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) |main_#t~ret5|)) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 22:48:43,402 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:43,402 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:43,402 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:43,402 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:43,834 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:43,835 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-06 22:48:43,836 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-06 22:48:43,837 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-06 22:48:43,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-06 22:48:43,840 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-06 22:48:44,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:44,513 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-06 22:48:44,513 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-06 22:48:44,513 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-06 22:48:44,513 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:44,514 INFO L225 Difference]: With dead ends: 40 [2019-10-06 22:48:44,514 INFO L226 Difference]: Without dead ends: 25 [2019-10-06 22:48:44,515 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=133, Invalid=737, Unknown=0, NotChecked=0, Total=870 [2019-10-06 22:48:44,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-06 22:48:44,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-06 22:48:44,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-06 22:48:44,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-06 22:48:44,522 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-06 22:48:44,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:44,522 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-06 22:48:44,523 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-06 22:48:44,523 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-06 22:48:44,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-06 22:48:44,524 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:44,524 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:44,728 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:44,729 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:44,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:44,729 INFO L82 PathProgramCache]: Analyzing trace with hash 143191253, now seen corresponding path program 2 times [2019-10-06 22:48:44,730 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:44,730 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:44,730 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:44,730 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:44,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:44,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:44,857 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:44,857 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:44,858 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:44,858 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:44,966 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-06 22:48:44,968 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:48:44,975 INFO L256 TraceCheckSpWp]: Trace formula consists of 106 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:44,982 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:45,018 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:48:45,018 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:45,055 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:48:45,056 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:45,059 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:45,059 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:45,061 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:45,061 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:45,062 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:45,084 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:46,770 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:46,804 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:46,809 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:46,809 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:46,809 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:46,809 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:48:46,810 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_27 Int) (v_prenex_196 Int) (v_bAnd_~res~0_BEFORE_RETURN_28 Int) (v_prenex_195 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_195 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_195 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296))) (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~0)))) [2019-10-06 22:48:46,815 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_prenex_223 Int) (v_bAnd_~res~0_BEFORE_RETURN_32 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_prenex_223 Int) (v_bAnd_~res~0_BEFORE_RETURN_32 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296))))))) [2019-10-06 22:48:46,815 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:46,816 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:46,816 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:46,816 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:46,817 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:46,818 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:46,818 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:46,818 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:46,818 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:48:46,818 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-06 22:48:46,819 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296) 2147483647)) (and (= (+ (mod v_prenex_195 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 10000)) (not (<= (mod v_prenex_195 4294967296) 2147483647))))) (exists ((v_prenex_196 Int) (v_bAnd_~res~0_BEFORE_RETURN_28 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296) |main_#t~ret5|))))) [2019-10-06 22:48:46,819 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:46,819 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:46,819 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:46,819 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:47,202 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:47,203 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-06 22:48:47,204 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-06 22:48:47,205 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-06 22:48:47,205 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-06 22:48:47,205 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-06 22:48:48,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:48,253 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-06 22:48:48,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-06 22:48:48,254 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-06 22:48:48,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:48,255 INFO L225 Difference]: With dead ends: 44 [2019-10-06 22:48:48,255 INFO L226 Difference]: Without dead ends: 29 [2019-10-06 22:48:48,256 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-06 22:48:48,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-06 22:48:48,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-06 22:48:48,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-06 22:48:48,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-06 22:48:48,263 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-06 22:48:48,263 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:48,264 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-06 22:48:48,264 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-06 22:48:48,264 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-06 22:48:48,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-06 22:48:48,265 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:48,265 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:48,472 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:48,473 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:48,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:48,474 INFO L82 PathProgramCache]: Analyzing trace with hash 766317228, now seen corresponding path program 3 times [2019-10-06 22:48:48,474 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:48,474 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:48,474 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:48,474 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:48,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:48,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:48,555 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:48,555 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:48,555 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:48,555 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:48,668 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:48:48,668 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:48:48,670 INFO L256 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-06 22:48:48,672 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:48,687 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:48,687 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:48,798 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:48,798 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:48,800 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:48,801 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:48,801 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:48,801 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:48,802 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:48,822 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:50,295 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:50,317 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:50,320 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:50,321 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:50,321 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:50,321 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:48:50,322 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int) (v_prenex_390 Int) (v_bAnd_~res~0_BEFORE_RETURN_54 Int)) (or (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) main_~ret~0) (<= main_~ret~0 2147483647) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (= (mod v_prenex_389 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= main_~ret~0 2147483647)))) [2019-10-06 22:48:50,322 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_58 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_bAnd_~res~0_BEFORE_RETURN_57 Int)) (or (and (not (< main_~i~2 9999)) (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) (- 4294967296)))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_418 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_418 4294967296) 2147483647)) (and (not (< main_~i~2 9999)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) 2147483647))))) (not (= main_~ret~0 main_~ret2~0))) (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_58 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_bAnd_~res~0_BEFORE_RETURN_57 Int)) (or (and (not (< main_~i~2 9999)) (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) (- 4294967296)))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_418 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_418 4294967296) 2147483647)) (and (not (< main_~i~2 9999)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) 2147483647))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:48:50,322 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:50,322 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:50,323 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:50,323 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:50,323 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:50,323 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:50,323 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:50,324 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:50,324 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:48:50,324 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-06 22:48:50,324 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_390 Int) (v_bAnd_~res~0_BEFORE_RETURN_54 Int)) (or (and (not (< main_~i~1 10000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) |main_#t~ret5|) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_prenex_390 4294967296) (- 4294967296)))))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (<= (mod v_prenex_389 4294967296) 2147483647) (= (mod v_prenex_389 4294967296) |main_#t~ret5|))))) [2019-10-06 22:48:50,325 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:50,325 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:50,325 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:50,325 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:50,686 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:50,687 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-06 22:48:50,688 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-06 22:48:50,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-06 22:48:50,689 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-06 22:48:50,689 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-06 22:48:51,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:51,660 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-06 22:48:51,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-06 22:48:51,660 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-06 22:48:51,661 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:51,662 INFO L225 Difference]: With dead ends: 54 [2019-10-06 22:48:51,662 INFO L226 Difference]: Without dead ends: 36 [2019-10-06 22:48:51,664 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-06 22:48:51,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-06 22:48:51,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-06 22:48:51,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-06 22:48:51,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-06 22:48:51,678 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-06 22:48:51,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:51,679 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-06 22:48:51,679 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-06 22:48:51,679 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-06 22:48:51,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-06 22:48:51,684 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:51,684 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:51,887 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:51,888 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:51,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:51,889 INFO L82 PathProgramCache]: Analyzing trace with hash 615727983, now seen corresponding path program 4 times [2019-10-06 22:48:51,889 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:51,889 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:51,890 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:51,890 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:51,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:51,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:52,079 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:52,079 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:52,080 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:52,080 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:52,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:52,252 INFO L256 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-06 22:48:52,255 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:52,273 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:52,273 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:52,645 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:52,646 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:52,647 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:52,648 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:52,648 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:52,648 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:52,648 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:52,677 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:54,460 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:54,491 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:54,495 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:54,495 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:54,496 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:54,496 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:48:54,497 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_583 Int) (v_prenex_584 Int) (v_bAnd_~res~0_BEFORE_RETURN_80 Int) (v_bAnd_~res~0_BEFORE_RETURN_79 Int)) (or (and (not (< main_~i~1 10000)) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (<= (mod v_prenex_583 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_583 4294967296)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_prenex_584 4294967296) main_~ret~0) (<= (mod v_prenex_584 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) main_~ret~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-06 22:48:54,497 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_bAnd_~res~0_BEFORE_RETURN_83 Int) (v_bAnd_~res~0_BEFORE_RETURN_84 Int)) (or (and (not (< main_~i~2 9999)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_611 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) 2147483647)) (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647)))))) (and (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_bAnd_~res~0_BEFORE_RETURN_83 Int) (v_bAnd_~res~0_BEFORE_RETURN_84 Int)) (or (and (not (< main_~i~2 9999)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_611 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) 2147483647)) (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:48:54,498 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:54,498 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:54,498 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:54,499 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:54,499 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:54,499 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:54,499 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:54,500 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:54,500 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:48:54,500 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-06 22:48:54,501 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_584 Int) (v_bAnd_~res~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (mod v_prenex_584 4294967296)) (<= (mod v_prenex_584 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) |main_#t~ret5|)))) (exists ((v_prenex_583 Int) (v_bAnd_~res~0_BEFORE_RETURN_79 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_prenex_583 4294967296) 2147483647) (= |main_#t~ret5| (mod v_prenex_583 4294967296))) (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) 2147483647)))))) [2019-10-06 22:48:54,501 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:54,501 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:54,502 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:54,502 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:54,947 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:54,947 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-06 22:48:54,948 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-06 22:48:54,949 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-06 22:48:54,950 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-06 22:48:54,950 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 40 states. [2019-10-06 22:48:56,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:56,749 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-06 22:48:56,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-06 22:48:56,749 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 49 [2019-10-06 22:48:56,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:56,751 INFO L225 Difference]: With dead ends: 68 [2019-10-06 22:48:56,751 INFO L226 Difference]: Without dead ends: 50 [2019-10-06 22:48:56,754 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-06 22:48:56,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-06 22:48:56,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-06 22:48:56,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-06 22:48:56,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-06 22:48:56,763 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-06 22:48:56,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:56,763 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-06 22:48:56,763 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-06 22:48:56,763 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-06 22:48:56,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-06 22:48:56,765 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:56,765 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:56,969 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:56,969 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:56,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:56,970 INFO L82 PathProgramCache]: Analyzing trace with hash 2121294031, now seen corresponding path program 5 times [2019-10-06 22:48:56,970 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:56,971 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:56,971 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:56,971 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:56,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:57,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:57,576 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:57,576 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:57,576 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:57,576 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:57,779 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:48:57,779 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:48:57,781 INFO L256 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:57,793 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:57,835 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-06 22:48:57,836 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:57,886 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-06 22:48:57,886 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:57,888 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:57,888 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:57,888 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:57,889 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:57,889 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:57,905 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:59,156 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:48:59,179 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:59,182 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:59,182 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:59,182 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:48:59,182 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:48:59,182 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_777 Int) (v_bAnd_~res~0_BEFORE_RETURN_106 Int) (v_bAnd_~res~0_BEFORE_RETURN_105 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) main_~ret~0)) (and (<= (mod v_prenex_777 4294967296) 2147483647) (not (< main_~i~1 10000)) (= main_~ret~0 (mod v_prenex_777 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-06 22:48:59,183 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_806 Int) (v_prenex_805 Int) (v_bAnd_~res~0_BEFORE_RETURN_109 Int) (v_bAnd_~res~0_BEFORE_RETURN_110 Int)) (or (and (= main_~ret5~0 (mod v_prenex_805 4294967296)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (not (< main_~i~2 9999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) 2147483647))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_806 Int) (v_prenex_805 Int) (v_bAnd_~res~0_BEFORE_RETURN_109 Int) (v_bAnd_~res~0_BEFORE_RETURN_110 Int)) (or (and (= main_~ret5~0 (mod v_prenex_805 4294967296)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (not (< main_~i~2 9999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) 2147483647))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647)))))) [2019-10-06 22:48:59,183 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:59,183 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:59,183 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:59,184 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:48:59,184 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:59,184 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:59,184 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:48:59,184 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:59,184 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:48:59,185 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-06 22:48:59,185 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_777 Int) (v_bAnd_~res~0_BEFORE_RETURN_105 Int)) (or (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 10000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) 2147483647))) (and (<= (mod v_prenex_777 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_prenex_777 4294967296) |main_#t~ret5|)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_778 4294967296) 2147483647)) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296) 2147483647) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296)))))) [2019-10-06 22:48:59,185 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:59,185 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:59,185 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:59,185 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:59,738 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:59,738 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-06 22:48:59,739 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-06 22:48:59,740 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-06 22:48:59,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-06 22:48:59,741 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 44 states. [2019-10-06 22:49:04,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:04,156 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-06 22:49:04,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-06 22:49:04,156 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 63 [2019-10-06 22:49:04,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:04,158 INFO L225 Difference]: With dead ends: 72 [2019-10-06 22:49:04,158 INFO L226 Difference]: Without dead ends: 54 [2019-10-06 22:49:04,161 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1350 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=1349, Invalid=5457, Unknown=0, NotChecked=0, Total=6806 [2019-10-06 22:49:04,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-06 22:49:04,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-06 22:49:04,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-06 22:49:04,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-06 22:49:04,169 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-06 22:49:04,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:04,170 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-06 22:49:04,170 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-06 22:49:04,170 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-06 22:49:04,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-06 22:49:04,171 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:04,171 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:04,372 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:04,373 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:04,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:04,373 INFO L82 PathProgramCache]: Analyzing trace with hash -1728770399, now seen corresponding path program 6 times [2019-10-06 22:49:04,373 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:04,374 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:04,374 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:04,374 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:04,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:04,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:04,949 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:04,950 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:04,950 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:04,950 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:05,218 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:49:05,218 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:05,220 INFO L256 TraceCheckSpWp]: Trace formula consists of 331 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-06 22:49:05,223 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:05,244 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:05,245 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:06,721 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:06,722 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:06,723 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:06,724 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:06,724 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:06,724 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:06,725 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:06,764 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:08,005 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:08,029 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:08,032 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:08,032 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:08,032 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:08,032 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:49:08,033 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_bAnd_~res~0_BEFORE_RETURN_131 Int) (v_bAnd_~res~0_BEFORE_RETURN_132 Int)) (or (and (= main_~ret~0 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (not (< main_~i~1 10000)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) main_~ret~0) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296) 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) (exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_bAnd_~res~0_BEFORE_RETURN_131 Int) (v_bAnd_~res~0_BEFORE_RETURN_132 Int)) (or (and (= main_~ret~0 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (not (< main_~i~1 10000)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) main_~ret~0) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= main_~ret~0 2147483647))))) [2019-10-06 22:49:08,033 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_135 Int) (v_bAnd_~res~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 9999)) (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_1000 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0))))) (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_135 Int) (v_bAnd_~res~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 9999)) (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_1000 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:49:08,033 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:08,033 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:08,034 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:08,034 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:08,034 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:08,034 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:08,034 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:08,035 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:08,035 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:49:08,035 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-06 22:49:08,035 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_971 Int) (v_bAnd_~res~0_BEFORE_RETURN_131 Int)) (or (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) |main_#t~ret5|) (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (+ (mod v_prenex_971 4294967296) (- 4294967296)) |main_#t~ret5|)))) (exists ((v_prenex_972 Int) (v_bAnd_~res~0_BEFORE_RETURN_132 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296) 2147483647) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296))) (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (= (+ (mod v_prenex_972 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 22:49:08,035 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:08,035 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:08,036 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:08,036 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:08,517 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:08,517 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-06 22:49:08,518 INFO L442 AbstractCegarLoop]: Interpolant automaton has 70 states [2019-10-06 22:49:08,519 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2019-10-06 22:49:08,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1740, Invalid=3090, Unknown=0, NotChecked=0, Total=4830 [2019-10-06 22:49:08,521 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 70 states. [2019-10-06 22:49:12,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:12,450 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-06 22:49:12,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2019-10-06 22:49:12,450 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 67 [2019-10-06 22:49:12,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:12,452 INFO L225 Difference]: With dead ends: 104 [2019-10-06 22:49:12,452 INFO L226 Difference]: Without dead ends: 83 [2019-10-06 22:49:12,456 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3929 ImplicationChecksByTransitivity, 5.8s TimeCoverageRelationStatistics Valid=5099, Invalid=12723, Unknown=0, NotChecked=0, Total=17822 [2019-10-06 22:49:12,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-06 22:49:12,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-06 22:49:12,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-06 22:49:12,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-06 22:49:12,467 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-06 22:49:12,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:12,467 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-06 22:49:12,467 INFO L463 AbstractCegarLoop]: Interpolant automaton has 70 states. [2019-10-06 22:49:12,468 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-06 22:49:12,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-06 22:49:12,469 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:12,469 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:12,673 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:12,674 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:12,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:12,674 INFO L82 PathProgramCache]: Analyzing trace with hash 1695588190, now seen corresponding path program 7 times [2019-10-06 22:49:12,674 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:12,675 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:12,675 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:12,675 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:12,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:12,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:14,683 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:14,684 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:14,684 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:14,684 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:15,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:15,017 INFO L256 TraceCheckSpWp]: Trace formula consists of 505 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-06 22:49:15,021 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:15,042 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:15,042 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:20,790 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:20,790 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:20,792 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:20,792 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:20,792 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:20,793 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:20,793 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:20,807 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:22,228 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:22,254 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:22,257 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:22,257 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:22,258 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:22,258 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:49:22,258 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_157 Int) (v_bAnd_~res~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int) (v_prenex_1165 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_157 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_bAnd_~res~0_BEFORE_RETURN_157 4294967296) main_~ret~0) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_prenex_1166 4294967296))) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_158 4294967296) 2147483647)) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_158 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1165 4294967296) 2147483647))))) [2019-10-06 22:49:22,259 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_161 Int) (v_prenex_1194 Int) (v_prenex_1193 Int) (v_bAnd_~res~0_BEFORE_RETURN_162 Int)) (or (and (not (< main_~i~2 9999)) (<= (mod v_prenex_1193 4294967296) 2147483647) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_161 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_1194 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_162 4294967296) 2147483647)))))) (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_161 Int) (v_prenex_1194 Int) (v_prenex_1193 Int) (v_bAnd_~res~0_BEFORE_RETURN_162 Int)) (or (and (not (< main_~i~2 9999)) (<= (mod v_prenex_1193 4294967296) 2147483647) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_161 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_1194 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_162 4294967296) 2147483647))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:49:22,259 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:22,259 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:22,259 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:22,260 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:22,260 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:22,260 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:22,260 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:22,261 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:22,261 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:49:22,261 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-06 22:49:22,261 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_157 Int) (v_prenex_1165 Int)) (or (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_157 4294967296) |main_#t~ret5|) (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_157 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_1165 4294967296) 2147483647)) (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) |main_#t~ret5|)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_158 4294967296) 2147483647))) (and (= (mod v_prenex_1166 4294967296) |main_#t~ret5|) (not (< main_~i~1 10000)) (<= (mod v_prenex_1166 4294967296) 2147483647))))) [2019-10-06 22:49:22,261 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:22,261 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:22,261 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:22,262 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:24,966 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:24,967 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 127 [2019-10-06 22:49:24,968 INFO L442 AbstractCegarLoop]: Interpolant automaton has 128 states [2019-10-06 22:49:24,970 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 128 interpolants. [2019-10-06 22:49:24,974 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6815, Invalid=9440, Unknown=1, NotChecked=0, Total=16256 [2019-10-06 22:49:24,974 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 128 states. [2019-10-06 22:49:36,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:36,127 INFO L93 Difference]: Finished difference Result 162 states and 227 transitions. [2019-10-06 22:49:36,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 127 states. [2019-10-06 22:49:36,127 INFO L78 Accepts]: Start accepts. Automaton has 128 states. Word has length 96 [2019-10-06 22:49:36,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:36,129 INFO L225 Difference]: With dead ends: 162 [2019-10-06 22:49:36,129 INFO L226 Difference]: Without dead ends: 141 [2019-10-06 22:49:36,134 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 471 GetRequests, 223 SyntacticMatches, 0 SemanticMatches, 248 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12078 ImplicationChecksByTransitivity, 20.7s TimeCoverageRelationStatistics Valid=20208, Invalid=42041, Unknown=1, NotChecked=0, Total=62250 [2019-10-06 22:49:36,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2019-10-06 22:49:36,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2019-10-06 22:49:36,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2019-10-06 22:49:36,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 145 transitions. [2019-10-06 22:49:36,150 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 145 transitions. Word has length 96 [2019-10-06 22:49:36,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:36,151 INFO L462 AbstractCegarLoop]: Abstraction has 141 states and 145 transitions. [2019-10-06 22:49:36,151 INFO L463 AbstractCegarLoop]: Interpolant automaton has 128 states. [2019-10-06 22:49:36,151 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 145 transitions. [2019-10-06 22:49:36,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2019-10-06 22:49:36,154 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:36,154 INFO L385 BasicCegarLoop]: trace histogram [114, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:36,358 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:36,359 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:36,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:36,359 INFO L82 PathProgramCache]: Analyzing trace with hash -795247042, now seen corresponding path program 8 times [2019-10-06 22:49:36,360 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:36,360 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:36,360 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:36,360 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:36,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:36,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:44,105 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 0 proven. 6555 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:44,106 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:44,106 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:44,106 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:44,450 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:49:44,450 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:44,451 INFO L256 TraceCheckSpWp]: Trace formula consists of 141 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 22:49:44,455 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:44,821 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 22:49:44,822 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:45,137 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 22:49:45,137 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:45,139 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:45,139 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:45,139 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:45,140 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:45,140 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:45,160 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:46,384 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:49:46,409 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:46,414 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:46,414 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:46,414 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:49:46,415 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:49:46,415 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_1359 Int) (v_bAnd_~res~0_BEFORE_RETURN_183 Int) (v_prenex_1360 Int) (v_bAnd_~res~0_BEFORE_RETURN_184 Int)) (or (and (not (< main_~i~1 10000)) (= main_~ret~0 (mod v_prenex_1359 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1359 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) main_~ret~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1360 4294967296) 2147483647))))) [2019-10-06 22:49:46,416 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_188 Int) (v_prenex_1388 Int) (v_prenex_1387 Int) (v_bAnd_~res~0_BEFORE_RETURN_187 Int)) (or (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_188 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_187 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_187 4294967296) 2147483647))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1388 4294967296) 2147483647)) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)))))) (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_188 Int) (v_prenex_1388 Int) (v_prenex_1387 Int) (v_bAnd_~res~0_BEFORE_RETURN_187 Int)) (or (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_188 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_187 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_187 4294967296) 2147483647))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1388 4294967296) 2147483647)) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:49:46,417 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:46,417 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:46,417 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:46,417 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:46,417 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:46,418 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:46,418 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:49:46,418 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:46,418 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:49:46,418 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-06 22:49:46,418 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1359 Int) (v_bAnd_~res~0_BEFORE_RETURN_183 Int)) (or (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (= (mod v_prenex_1359 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1359 4294967296) 2147483647)))) (exists ((v_prenex_1360 Int) (v_bAnd_~res~0_BEFORE_RETURN_184 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_1360 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_184 4294967296) |main_#t~ret5|))))) [2019-10-06 22:49:46,419 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:46,419 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:46,419 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:46,419 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:47,631 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:47,632 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [117, 7, 7, 11] total 137 [2019-10-06 22:49:47,633 INFO L442 AbstractCegarLoop]: Interpolant automaton has 138 states [2019-10-06 22:49:47,635 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 138 interpolants. [2019-10-06 22:49:47,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6880, Invalid=12026, Unknown=0, NotChecked=0, Total=18906 [2019-10-06 22:49:47,637 INFO L87 Difference]: Start difference. First operand 141 states and 145 transitions. Second operand 138 states. [2019-10-06 22:50:02,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:02,626 INFO L93 Difference]: Finished difference Result 169 states and 186 transitions. [2019-10-06 22:50:02,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 138 states. [2019-10-06 22:50:02,626 INFO L78 Accepts]: Start accepts. Automaton has 138 states. Word has length 154 [2019-10-06 22:50:02,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:02,628 INFO L225 Difference]: With dead ends: 169 [2019-10-06 22:50:02,629 INFO L226 Difference]: Without dead ends: 148 [2019-10-06 22:50:02,631 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 711 GetRequests, 442 SyntacticMatches, 0 SemanticMatches, 269 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12311 ImplicationChecksByTransitivity, 22.5s TimeCoverageRelationStatistics Valid=20694, Invalid=52476, Unknown=0, NotChecked=0, Total=73170 [2019-10-06 22:50:02,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2019-10-06 22:50:02,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 148. [2019-10-06 22:50:02,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2019-10-06 22:50:02,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 152 transitions. [2019-10-06 22:50:02,648 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 152 transitions. Word has length 154 [2019-10-06 22:50:02,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:02,648 INFO L462 AbstractCegarLoop]: Abstraction has 148 states and 152 transitions. [2019-10-06 22:50:02,649 INFO L463 AbstractCegarLoop]: Interpolant automaton has 138 states. [2019-10-06 22:50:02,649 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 152 transitions. [2019-10-06 22:50:02,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2019-10-06 22:50:02,651 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:02,651 INFO L385 BasicCegarLoop]: trace histogram [115, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:02,856 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:02,856 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:02,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:02,857 INFO L82 PathProgramCache]: Analyzing trace with hash 1403267681, now seen corresponding path program 9 times [2019-10-06 22:50:02,857 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:02,858 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:02,858 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:02,858 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:02,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:03,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:10,945 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:50:10,945 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:10,946 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:50:10,946 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:11,430 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:50:11,430 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:50:11,435 INFO L256 TraceCheckSpWp]: Trace formula consists of 913 conjuncts, 117 conjunts are in the unsatisfiable core [2019-10-06 22:50:11,440 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:50:11,494 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:50:11,494 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:34,960 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:50:34,960 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:34,961 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:34,961 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:34,962 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:34,962 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:34,962 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:34,978 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:50:36,172 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:50:36,201 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:50:36,203 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:50:36,204 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:50:36,204 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:50:36,204 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:50:36,204 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_bAnd_~res~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= main_~ret~0 (mod v_prenex_1553 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1553 4294967296) 2147483647)) (and (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) (- 4294967296))) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) 2147483647)) (<= main_~ret~0 2147483647)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_bAnd_~res~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= main_~ret~0 (mod v_prenex_1553 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1553 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) main_~ret~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) (- 4294967296))) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) 2147483647)) (<= main_~ret~0 2147483647))))) [2019-10-06 22:50:36,205 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_213 Int) (v_bAnd_~res~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_213 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_213 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_214 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_214 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9999)) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_213 Int) (v_bAnd_~res~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_213 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_213 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_214 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_214 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9999)) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 22:50:36,205 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:50:36,205 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:50:36,205 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:36,205 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:50:36,205 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:36,206 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:50:36,206 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:50:36,206 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:50:36,206 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:50:36,206 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-06 22:50:36,206 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1553 Int) (v_bAnd_~res~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 10000)) (= (mod v_prenex_1553 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1553 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) |main_#t~ret5|)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_210 4294967296) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_1554 4294967296) 2147483647)))))) [2019-10-06 22:50:36,207 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:50:36,207 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:50:36,207 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:50:36,207 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:50:37,578 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:50:37,578 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [118, 118, 118, 11] total 245 [2019-10-06 22:50:37,580 INFO L442 AbstractCegarLoop]: Interpolant automaton has 246 states [2019-10-06 22:50:37,586 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 246 interpolants. [2019-10-06 22:50:37,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27524, Invalid=32746, Unknown=0, NotChecked=0, Total=60270 [2019-10-06 22:50:37,589 INFO L87 Difference]: Start difference. First operand 148 states and 152 transitions. Second operand 246 states. [2019-10-06 22:51:16,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:51:16,093 INFO L93 Difference]: Finished difference Result 292 states and 416 transitions. [2019-10-06 22:51:16,094 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 245 states. [2019-10-06 22:51:16,094 INFO L78 Accepts]: Start accepts. Automaton has 246 states. Word has length 173 [2019-10-06 22:51:16,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:51:16,099 INFO L225 Difference]: With dead ends: 292 [2019-10-06 22:51:16,099 INFO L226 Difference]: Without dead ends: 265 [2019-10-06 22:51:16,106 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 879 GetRequests, 395 SyntacticMatches, 0 SemanticMatches, 484 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41637 ImplicationChecksByTransitivity, 69.2s TimeCoverageRelationStatistics Valid=82099, Invalid=153611, Unknown=0, NotChecked=0, Total=235710 [2019-10-06 22:51:16,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2019-10-06 22:51:16,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 265. [2019-10-06 22:51:16,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2019-10-06 22:51:16,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 269 transitions. [2019-10-06 22:51:16,130 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 269 transitions. Word has length 173 [2019-10-06 22:51:16,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:51:16,131 INFO L462 AbstractCegarLoop]: Abstraction has 265 states and 269 transitions. [2019-10-06 22:51:16,131 INFO L463 AbstractCegarLoop]: Interpolant automaton has 246 states. [2019-10-06 22:51:16,131 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 269 transitions. [2019-10-06 22:51:16,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2019-10-06 22:51:16,135 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:51:16,135 INFO L385 BasicCegarLoop]: trace histogram [232, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:51:16,340 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:16,340 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:51:16,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:51:16,340 INFO L82 PathProgramCache]: Analyzing trace with hash 892913502, now seen corresponding path program 10 times [2019-10-06 22:51:16,341 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:51:16,341 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:16,341 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:16,341 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:16,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:51:16,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:47,693 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:51:47,693 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:47,693 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:51:47,693 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:48,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:48,402 INFO L256 TraceCheckSpWp]: Trace formula consists of 1615 conjuncts, 234 conjunts are in the unsatisfiable core [2019-10-06 22:51:48,408 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:51:48,499 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:51:48,499 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:53:22,094 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:53:22,095 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:53:22,096 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:53:22,096 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:53:22,097 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:53:22,097 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:53:22,097 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:53:22,128 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:53:23,314 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:53:23,334 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:53:23,336 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:53:23,336 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:53:23,336 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:53:23,337 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:53:23,337 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_235 Int) (v_bAnd_~res~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int) (v_prenex_1747 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod v_prenex_1748 4294967296) (- 4294967296)) main_~ret~0) (not (<= (mod v_prenex_1748 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1747 4294967296) 2147483647) (= main_~ret~0 (mod v_prenex_1747 4294967296)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_236 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_236 4294967296))) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_235 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_235 4294967296) 2147483647)) (<= main_~ret~0 2147483647)))) [2019-10-06 22:53:23,337 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret5~0)) (exists ((v_prenex_1776 Int) (v_prenex_1775 Int) (v_bAnd_~res~0_BEFORE_RETURN_239 Int) (v_bAnd_~res~0_BEFORE_RETURN_240 Int)) (or (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_239 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_prenex_1775 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_240 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_240 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1776 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1776 4294967296) 2147483647))))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_1776 Int) (v_prenex_1775 Int) (v_bAnd_~res~0_BEFORE_RETURN_239 Int) (v_bAnd_~res~0_BEFORE_RETURN_240 Int)) (or (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_239 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_prenex_1775 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_240 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_240 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1776 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1776 4294967296) 2147483647)))))) [2019-10-06 22:53:23,337 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:53:23,338 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:53:23,338 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:23,338 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:23,338 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:23,338 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:53:23,338 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:53:23,338 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:53:23,338 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:53:23,338 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-06 22:53:23,339 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_235 Int) (v_prenex_1747 Int)) (or (and (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_235 4294967296) (- 4294967296))) (not (< main_~i~1 10000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_235 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (<= (mod v_prenex_1747 4294967296) 2147483647) (= (mod v_prenex_1747 4294967296) |main_#t~ret5|)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_1748 4294967296) 2147483647)) (= (+ (mod v_prenex_1748 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_236 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_236 4294967296) 2147483647))))) [2019-10-06 22:53:23,339 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:53:23,339 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:53:23,339 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:53:23,339 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:53:25,370 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:53:25,371 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [235, 235, 235, 11] total 479 [2019-10-06 22:53:25,372 INFO L442 AbstractCegarLoop]: Interpolant automaton has 480 states [2019-10-06 22:53:25,381 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 480 interpolants. [2019-10-06 22:53:25,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=109775, Invalid=120145, Unknown=0, NotChecked=0, Total=229920 [2019-10-06 22:53:25,387 INFO L87 Difference]: Start difference. First operand 265 states and 269 transitions. Second operand 480 states. [2019-10-06 22:55:59,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:55:59,491 INFO L93 Difference]: Finished difference Result 526 states and 767 transitions. [2019-10-06 22:55:59,491 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 479 states. [2019-10-06 22:55:59,491 INFO L78 Accepts]: Start accepts. Automaton has 480 states. Word has length 290 [2019-10-06 22:55:59,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:55:59,494 INFO L225 Difference]: With dead ends: 526 [2019-10-06 22:55:59,494 INFO L226 Difference]: Without dead ends: 499 [2019-10-06 22:55:59,528 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1581 GetRequests, 629 SyntacticMatches, 0 SemanticMatches, 952 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151733 ImplicationChecksByTransitivity, 267.0s TimeCoverageRelationStatistics Valid=328384, Invalid=580777, Unknown=1, NotChecked=0, Total=909162 [2019-10-06 22:55:59,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 499 states. [2019-10-06 22:55:59,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 499 to 499. [2019-10-06 22:55:59,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 499 states. [2019-10-06 22:55:59,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 499 states to 499 states and 503 transitions. [2019-10-06 22:55:59,560 INFO L78 Accepts]: Start accepts. Automaton has 499 states and 503 transitions. Word has length 290 [2019-10-06 22:55:59,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:55:59,561 INFO L462 AbstractCegarLoop]: Abstraction has 499 states and 503 transitions. [2019-10-06 22:55:59,561 INFO L463 AbstractCegarLoop]: Interpolant automaton has 480 states. [2019-10-06 22:55:59,561 INFO L276 IsEmpty]: Start isEmpty. Operand 499 states and 503 transitions. [2019-10-06 22:55:59,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 525 [2019-10-06 22:55:59,572 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:55:59,572 INFO L385 BasicCegarLoop]: trace histogram [466, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:55:59,778 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:55:59,778 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:55:59,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:55:59,778 INFO L82 PathProgramCache]: Analyzing trace with hash -1526853826, now seen corresponding path program 11 times [2019-10-06 22:55:59,778 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:55:59,778 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:55:59,778 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:55:59,779 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:55:59,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:56:01,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:56:01,946 INFO L134 CoverageAnalysis]: Checked inductivity of 109355 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 109056 trivial. 0 not checked. [2019-10-06 22:56:01,947 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:56:01,947 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:56:01,947 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:56:02,610 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2019-10-06 22:56:02,610 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:56:02,612 INFO L256 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 22:56:02,622 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:56:02,771 INFO L134 CoverageAnalysis]: Checked inductivity of 109355 backedges. 246 proven. 10 refuted. 0 times theorem prover too weak. 109099 trivial. 0 not checked. [2019-10-06 22:56:02,772 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:56:02,970 INFO L134 CoverageAnalysis]: Checked inductivity of 109355 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 109345 trivial. 0 not checked. [2019-10-06 22:56:02,971 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:56:02,972 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:56:02,973 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:56:02,973 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:56:02,973 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:56:02,973 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:56:02,995 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:56:04,288 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-06 22:56:04,308 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:56:04,310 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:56:04,310 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:56:04,310 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-06 22:56:04,311 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:56:04,311 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_bAnd_~res~0_BEFORE_RETURN_261 Int) (v_bAnd_~res~0_BEFORE_RETURN_262 Int)) (or (and (not (< main_~i~1 10000)) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_262 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_262 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_261 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_261 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= main_~ret~0 (mod v_prenex_1941 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1941 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_1942 4294967296) (- 4294967296)) main_~ret~0)))) [2019-10-06 22:56:04,311 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret5~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_265 Int) (v_bAnd_~res~0_BEFORE_RETURN_266 Int) (v_prenex_1970 Int) (v_prenex_1969 Int)) (or (and (= main_~ret5~0 (mod v_bAnd_~res~0_BEFORE_RETURN_266 4294967296)) (not (< main_~i~2 9999)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_266 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_265 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_265 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_prenex_1969 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)))))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_265 Int) (v_bAnd_~res~0_BEFORE_RETURN_266 Int) (v_prenex_1970 Int) (v_prenex_1969 Int)) (or (and (= main_~ret5~0 (mod v_bAnd_~res~0_BEFORE_RETURN_266 4294967296)) (not (< main_~i~2 9999)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_266 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_265 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_265 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_prenex_1969 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 22:56:04,312 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:56:04,312 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:56:04,312 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:04,312 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:04,312 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:04,312 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:56:04,313 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-06 22:56:04,313 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:56:04,313 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:56:04,313 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-06 22:56:04,313 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1942 Int) (v_bAnd_~res~0_BEFORE_RETURN_262 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_262 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_262 4294967296) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_prenex_1942 4294967296) (- 4294967296)))))) (exists ((v_prenex_1941 Int) (v_bAnd_~res~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_261 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_261 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (= (mod v_prenex_1941 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1941 4294967296) 2147483647))))) [2019-10-06 22:56:04,313 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:56:04,313 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:56:04,313 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:56:04,313 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:56:04,711 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:56:04,711 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 7, 7, 11] total 33 [2019-10-06 22:56:04,713 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2019-10-06 22:56:04,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-10-06 22:56:04,714 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=173, Invalid=949, Unknown=0, NotChecked=0, Total=1122 [2019-10-06 22:56:04,714 INFO L87 Difference]: Start difference. First operand 499 states and 503 transitions. Second operand 34 states. [2019-10-06 22:56:06,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:56:06,329 INFO L93 Difference]: Finished difference Result 532 states and 548 transitions. [2019-10-06 22:56:06,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-10-06 22:56:06,329 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 524 [2019-10-06 22:56:06,330 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:56:06,334 INFO L225 Difference]: With dead ends: 532 [2019-10-06 22:56:06,334 INFO L226 Difference]: Without dead ends: 506 [2019-10-06 22:56:06,335 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1614 GetRequests, 1553 SyntacticMatches, 0 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 893 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=597, Invalid=3309, Unknown=0, NotChecked=0, Total=3906 [2019-10-06 22:56:06,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 506 states. [2019-10-06 22:56:06,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 506 to 506. [2019-10-06 22:56:06,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 506 states. [2019-10-06 22:56:06,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 506 states to 506 states and 510 transitions. [2019-10-06 22:56:06,365 INFO L78 Accepts]: Start accepts. Automaton has 506 states and 510 transitions. Word has length 524 [2019-10-06 22:56:06,365 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:56:06,365 INFO L462 AbstractCegarLoop]: Abstraction has 506 states and 510 transitions. [2019-10-06 22:56:06,365 INFO L463 AbstractCegarLoop]: Interpolant automaton has 34 states. [2019-10-06 22:56:06,366 INFO L276 IsEmpty]: Start isEmpty. Operand 506 states and 510 transitions. [2019-10-06 22:56:06,369 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 534 [2019-10-06 22:56:06,369 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:56:06,370 INFO L385 BasicCegarLoop]: trace histogram [466, 33, 10, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:56:06,574 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:56:06,575 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:56:06,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:56:06,575 INFO L82 PathProgramCache]: Analyzing trace with hash -216367462, now seen corresponding path program 12 times [2019-10-06 22:56:06,575 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:56:06,576 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:56:06,576 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:56:06,576 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:56:06,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:56:08,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:58:01,154 INFO L134 CoverageAnalysis]: Checked inductivity of 109502 backedges. 0 proven. 108811 refuted. 0 times theorem prover too weak. 691 trivial. 0 not checked. [2019-10-06 22:58:01,154 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:58:01,155 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:58:01,155 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:58:02,253 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:58:02,253 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:58:02,273 INFO L256 TraceCheckSpWp]: Trace formula consists of 3052 conjuncts, 468 conjunts are in the unsatisfiable core [2019-10-06 22:58:02,285 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:58:02,662 INFO L134 CoverageAnalysis]: Checked inductivity of 109502 backedges. 0 proven. 108811 refuted. 0 times theorem prover too weak. 691 trivial. 0 not checked. [2019-10-06 22:58:02,663 INFO L322 TraceCheckSpWp]: Computing backward predicates...