java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/array-crafted/bor3.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-06 22:48:37,252 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-06 22:48:37,254 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-06 22:48:37,272 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-06 22:48:37,273 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-06 22:48:37,275 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-06 22:48:37,277 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-06 22:48:37,286 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-06 22:48:37,291 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-06 22:48:37,294 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-06 22:48:37,296 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-06 22:48:37,297 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-06 22:48:37,297 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-06 22:48:37,299 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-06 22:48:37,302 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-06 22:48:37,303 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-06 22:48:37,304 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-06 22:48:37,305 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-06 22:48:37,307 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-06 22:48:37,311 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-06 22:48:37,316 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-06 22:48:37,317 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-06 22:48:37,318 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-06 22:48:37,318 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-06 22:48:37,320 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-10-06 22:48:37,321 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-10-06 22:48:37,321 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-10-06 22:48:37,322 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-10-06 22:48:37,322 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-10-06 22:48:37,323 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-10-06 22:48:37,323 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-06 22:48:37,324 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-06 22:48:37,325 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-06 22:48:37,325 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-06 22:48:37,326 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-06 22:48:37,327 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-06 22:48:37,327 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-06 22:48:37,327 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-06 22:48:37,328 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-06 22:48:37,328 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-06 22:48:37,329 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-06 22:48:37,330 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-06 22:48:37,344 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-06 22:48:37,344 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-06 22:48:37,345 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-06 22:48:37,345 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-06 22:48:37,346 INFO L138 SettingsManager]: * Use SBE=true [2019-10-06 22:48:37,346 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-06 22:48:37,346 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-06 22:48:37,346 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-06 22:48:37,347 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-06 22:48:37,347 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-06 22:48:37,347 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-06 22:48:37,347 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-06 22:48:37,347 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-06 22:48:37,348 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-06 22:48:37,348 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-06 22:48:37,348 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-06 22:48:37,348 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-06 22:48:37,348 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-06 22:48:37,349 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-06 22:48:37,349 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-06 22:48:37,349 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-06 22:48:37,349 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:37,349 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-06 22:48:37,350 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-06 22:48:37,350 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-06 22:48:37,350 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-06 22:48:37,350 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-06 22:48:37,350 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-06 22:48:37,351 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-06 22:48:37,662 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-06 22:48:37,675 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-06 22:48:37,679 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-06 22:48:37,681 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-06 22:48:37,681 INFO L275 PluginConnector]: CDTParser initialized [2019-10-06 22:48:37,682 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-crafted/bor3.i [2019-10-06 22:48:37,746 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/24eb3732a/579b4ccaf076484aade1f063f5e7518a/FLAGe4ac967e1 [2019-10-06 22:48:38,198 INFO L306 CDTParser]: Found 1 translation units. [2019-10-06 22:48:38,199 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-crafted/bor3.i [2019-10-06 22:48:38,205 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/24eb3732a/579b4ccaf076484aade1f063f5e7518a/FLAGe4ac967e1 [2019-10-06 22:48:38,617 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/24eb3732a/579b4ccaf076484aade1f063f5e7518a [2019-10-06 22:48:38,628 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-06 22:48:38,630 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-06 22:48:38,631 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,631 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-06 22:48:38,634 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-06 22:48:38,635 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,639 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@98dacbd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38, skipping insertion in model container [2019-10-06 22:48:38,639 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,647 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-06 22:48:38,665 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-06 22:48:38,844 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,855 INFO L188 MainTranslator]: Completed pre-run [2019-10-06 22:48:38,876 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,978 INFO L192 MainTranslator]: Completed translation [2019-10-06 22:48:38,979 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38 WrapperNode [2019-10-06 22:48:38,979 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,979 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-06 22:48:38,980 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-06 22:48:38,980 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-06 22:48:38,994 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,994 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,004 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,006 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,023 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,029 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,030 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,033 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-06 22:48:39,033 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-06 22:48:39,033 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-06 22:48:39,034 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-06 22:48:39,035 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:39,099 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-06 22:48:39,099 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-06 22:48:39,099 INFO L138 BoogieDeclarations]: Found implementation of procedure bor [2019-10-06 22:48:39,100 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-06 22:48:39,100 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-06 22:48:39,100 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-06 22:48:39,100 INFO L130 BoogieDeclarations]: Found specification of procedure bor [2019-10-06 22:48:39,100 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-06 22:48:39,100 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-06 22:48:39,101 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-06 22:48:39,101 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-06 22:48:39,101 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-06 22:48:39,101 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-06 22:48:39,101 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-06 22:48:39,480 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-06 22:48:39,480 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-06 22:48:39,482 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39 BoogieIcfgContainer [2019-10-06 22:48:39,483 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-06 22:48:39,484 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-06 22:48:39,484 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-06 22:48:39,487 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-06 22:48:39,487 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.10 10:48:38" (1/3) ... [2019-10-06 22:48:39,488 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5d50c3cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,488 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (2/3) ... [2019-10-06 22:48:39,489 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5d50c3cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,489 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39" (3/3) ... [2019-10-06 22:48:39,492 INFO L109 eAbstractionObserver]: Analyzing ICFG bor3.i [2019-10-06 22:48:39,505 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-06 22:48:39,513 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-06 22:48:39,523 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-06 22:48:39,546 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-06 22:48:39,546 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-06 22:48:39,547 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-06 22:48:39,547 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-06 22:48:39,547 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-06 22:48:39,547 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-06 22:48:39,547 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-06 22:48:39,548 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-06 22:48:39,565 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-06 22:48:39,571 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-06 22:48:39,571 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,572 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,574 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,579 INFO L82 PathProgramCache]: Analyzing trace with hash 2002379581, now seen corresponding path program 1 times [2019-10-06 22:48:39,586 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,587 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,587 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,587 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,764 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-06 22:48:39,765 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,766 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:39,766 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:39,770 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:39,785 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:39,786 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,789 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-06 22:48:39,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:39,828 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-06 22:48:39,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:39,830 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-06 22:48:39,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:39,840 INFO L225 Difference]: With dead ends: 41 [2019-10-06 22:48:39,840 INFO L226 Difference]: Without dead ends: 20 [2019-10-06 22:48:39,844 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-06 22:48:39,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-06 22:48:39,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-06 22:48:39,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-06 22:48:39,896 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-06 22:48:39,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:39,896 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-06 22:48:39,897 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:39,897 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-06 22:48:39,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-06 22:48:39,899 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,899 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,900 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,900 INFO L82 PathProgramCache]: Analyzing trace with hash 1232729663, now seen corresponding path program 1 times [2019-10-06 22:48:39,901 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,901 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,901 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,901 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,027 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,027 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,028 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:40,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,157 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,168 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,197 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,197 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,248 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,249 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-06 22:48:40,249 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-06 22:48:40,250 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,251 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,252 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,253 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-06 22:48:40,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,269 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-06 22:48:40,270 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,270 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-06 22:48:40,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,271 INFO L225 Difference]: With dead ends: 33 [2019-10-06 22:48:40,272 INFO L226 Difference]: Without dead ends: 21 [2019-10-06 22:48:40,273 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-06 22:48:40,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-06 22:48:40,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-06 22:48:40,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-06 22:48:40,283 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-06 22:48:40,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,283 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-06 22:48:40,283 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,283 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-06 22:48:40,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-06 22:48:40,287 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,287 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,500 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,501 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,501 INFO L82 PathProgramCache]: Analyzing trace with hash 638962104, now seen corresponding path program 1 times [2019-10-06 22:48:40,502 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,502 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,502 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,502 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,603 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,604 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,605 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:40,605 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:40,606 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,606 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,607 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,607 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-06 22:48:40,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,625 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-06 22:48:40,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,627 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-06 22:48:40,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,628 INFO L225 Difference]: With dead ends: 31 [2019-10-06 22:48:40,629 INFO L226 Difference]: Without dead ends: 22 [2019-10-06 22:48:40,629 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-06 22:48:40,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-06 22:48:40,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-06 22:48:40,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-06 22:48:40,641 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-06 22:48:40,646 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,647 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-06 22:48:40,647 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,652 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-06 22:48:40,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-06 22:48:40,654 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,654 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,655 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,656 INFO L82 PathProgramCache]: Analyzing trace with hash -454929733, now seen corresponding path program 1 times [2019-10-06 22:48:40,656 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,656 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,656 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,656 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,757 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,757 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,757 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:40,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,840 INFO L256 TraceCheckSpWp]: Trace formula consists of 136 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,845 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,882 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,882 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,937 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,938 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:40,972 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:40,972 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:40,978 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:40,988 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:40,988 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:41,125 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:43,282 INFO L199 IcfgInterpreter]: Interpreting procedure bor with input of size 1 for LOIs [2019-10-06 22:48:43,365 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:43,369 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:43,370 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:43,370 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:48:43,370 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bor_~res~0_BEFORE_RETURN_1 Int) (v_prenex_2 Int) (v_bor_~res~0_BEFORE_RETURN_2 Int) (v_prenex_1 Int)) (or (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_bor_~res~0_BEFORE_RETURN_1 4294967296)) (<= main_~ret~0 2147483647) (<= (mod v_bor_~res~0_BEFORE_RETURN_1 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (= (mod v_bor_~res~0_BEFORE_RETURN_2 4294967296) main_~ret~0) (<= (mod v_bor_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~0)))) [2019-10-06 22:48:43,370 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:43,371 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:43,371 INFO L193 IcfgInterpreter]: Reachable states at location borENTRY satisfy 601#true [2019-10-06 22:48:43,371 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bor_~i~0) [2019-10-06 22:48:43,372 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:43,372 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:43,372 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:43,373 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:43,373 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bor_~res~0_BEFORE_RETURN_5 Int) (v_bor_~res~0_BEFORE_RETURN_6 Int) (v_prenex_29 Int) (v_prenex_30 Int)) (or (and (not (< main_~i~2 9999)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_5 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_5 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647))) (and (<= (mod v_prenex_29 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= (mod v_prenex_29 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_6 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_6 4294967296)) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bor_~res~0_BEFORE_RETURN_5 Int) (v_bor_~res~0_BEFORE_RETURN_6 Int) (v_prenex_29 Int) (v_prenex_30 Int)) (or (and (not (< main_~i~2 9999)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_5 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_5 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647))) (and (<= (mod v_prenex_29 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= (mod v_prenex_29 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_6 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_6 4294967296)) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 22:48:43,373 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:43,374 INFO L193 IcfgInterpreter]: Reachable states at location borEXIT satisfy 644#(and (not (< bor_~i~0 10000)) (<= 10000 bor_~i~0) (<= 1 bor_~i~0) (= (ite (<= (mod bor_~res~0 4294967296) 2147483647) (mod bor_~res~0 4294967296) (+ (mod bor_~res~0 4294967296) (- 4294967296))) |bor_#res|)) [2019-10-06 22:48:43,374 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:48:43,374 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2 Int) (v_bor_~res~0_BEFORE_RETURN_2 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bor_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (= (mod v_bor_~res~0_BEFORE_RETURN_2 4294967296) |main_#t~ret5|)) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) |main_#t~ret5|)))) (exists ((v_bor_~res~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod v_prenex_1 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (mod v_bor_~res~0_BEFORE_RETURN_1 4294967296)) (<= (mod v_bor_~res~0_BEFORE_RETURN_1 4294967296) 2147483647))))) [2019-10-06 22:48:43,374 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:43,376 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:43,376 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:43,376 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:43,974 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:43,974 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-06 22:48:43,976 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-06 22:48:43,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-06 22:48:43,977 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-06 22:48:43,977 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-06 22:48:44,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:44,627 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-06 22:48:44,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-06 22:48:44,627 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-06 22:48:44,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:44,628 INFO L225 Difference]: With dead ends: 40 [2019-10-06 22:48:44,628 INFO L226 Difference]: Without dead ends: 25 [2019-10-06 22:48:44,630 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=133, Invalid=737, Unknown=0, NotChecked=0, Total=870 [2019-10-06 22:48:44,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-06 22:48:44,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-06 22:48:44,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-06 22:48:44,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-06 22:48:44,637 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-06 22:48:44,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:44,637 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-06 22:48:44,637 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-06 22:48:44,637 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-06 22:48:44,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-06 22:48:44,639 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:44,639 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:44,842 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:44,843 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:44,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:44,843 INFO L82 PathProgramCache]: Analyzing trace with hash 545849657, now seen corresponding path program 2 times [2019-10-06 22:48:44,843 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:44,843 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:44,844 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:44,844 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:44,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:44,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:44,945 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:44,945 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:44,945 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:44,946 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:45,024 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-06 22:48:45,025 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:48:45,030 INFO L256 TraceCheckSpWp]: Trace formula consists of 106 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:45,036 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:45,055 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:48:45,055 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:45,086 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:48:45,086 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:45,089 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:45,089 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:45,090 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:45,090 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:45,090 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:45,120 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:46,614 INFO L199 IcfgInterpreter]: Interpreting procedure bor with input of size 1 for LOIs [2019-10-06 22:48:46,649 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:46,654 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:46,654 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:46,655 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:48:46,655 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_196 Int) (v_prenex_195 Int) (v_bor_~res~0_BEFORE_RETURN_27 Int) (v_bor_~res~0_BEFORE_RETURN_28 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_28 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_28 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod v_bor_~res~0_BEFORE_RETURN_27 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_bor_~res~0_BEFORE_RETURN_27 4294967296)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_195 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_195 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod v_prenex_196 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_196 4294967296) main_~ret~0) (<= main_~ret~0 2147483647)))) [2019-10-06 22:48:46,655 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:46,656 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:46,656 INFO L193 IcfgInterpreter]: Reachable states at location borENTRY satisfy 601#true [2019-10-06 22:48:46,656 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bor_~i~0) [2019-10-06 22:48:46,656 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:46,656 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:46,657 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:46,657 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:46,657 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret5~0)) (exists ((v_prenex_224 Int) (v_bor_~res~0_BEFORE_RETURN_32 Int) (v_prenex_223 Int) (v_bor_~res~0_BEFORE_RETURN_31 Int)) (or (and (not (<= (mod v_prenex_223 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_223 4294967296) (- 4294967296)))) (and (not (< main_~i~2 9999)) (<= (mod v_bor_~res~0_BEFORE_RETURN_31 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_31 4294967296))) (and (not (< main_~i~2 9999)) (not (<= (mod v_prenex_224 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_224 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_32 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_32 4294967296)))))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_224 Int) (v_bor_~res~0_BEFORE_RETURN_32 Int) (v_prenex_223 Int) (v_bor_~res~0_BEFORE_RETURN_31 Int)) (or (and (not (<= (mod v_prenex_223 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_223 4294967296) (- 4294967296)))) (and (not (< main_~i~2 9999)) (<= (mod v_bor_~res~0_BEFORE_RETURN_31 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_31 4294967296))) (and (not (< main_~i~2 9999)) (not (<= (mod v_prenex_224 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_224 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_32 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_32 4294967296))))))) [2019-10-06 22:48:46,657 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:46,658 INFO L193 IcfgInterpreter]: Reachable states at location borEXIT satisfy 644#(and (not (< bor_~i~0 10000)) (<= 10000 bor_~i~0) (<= 1 bor_~i~0) (= (ite (<= (mod bor_~res~0 4294967296) 2147483647) (mod bor_~res~0 4294967296) (+ (mod bor_~res~0 4294967296) (- 4294967296))) |bor_#res|)) [2019-10-06 22:48:46,658 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:48:46,658 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_196 Int) (v_bor_~res~0_BEFORE_RETURN_28 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_prenex_196 4294967296) 2147483647) (= |main_#t~ret5| (mod v_prenex_196 4294967296))) (and (not (< main_~i~1 10000)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_28 4294967296) 2147483647)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_28 4294967296) (- 4294967296)) |main_#t~ret5|)))) (exists ((v_prenex_195 Int) (v_bor_~res~0_BEFORE_RETURN_27 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bor_~res~0_BEFORE_RETURN_27 4294967296) 2147483647) (= (mod v_bor_~res~0_BEFORE_RETURN_27 4294967296) |main_#t~ret5|)) (and (= (+ (mod v_prenex_195 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 10000)) (not (<= (mod v_prenex_195 4294967296) 2147483647)))))) [2019-10-06 22:48:46,658 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:46,658 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:46,658 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:46,659 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:47,110 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:47,111 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-06 22:48:47,112 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-06 22:48:47,112 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-06 22:48:47,112 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-06 22:48:47,113 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-06 22:48:47,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:47,987 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-06 22:48:47,987 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-06 22:48:47,987 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-06 22:48:47,988 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:47,989 INFO L225 Difference]: With dead ends: 44 [2019-10-06 22:48:47,989 INFO L226 Difference]: Without dead ends: 29 [2019-10-06 22:48:47,990 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-06 22:48:47,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-06 22:48:47,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-06 22:48:47,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-06 22:48:47,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-06 22:48:47,997 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-06 22:48:47,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:47,997 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-06 22:48:47,998 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-06 22:48:47,998 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-06 22:48:47,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-06 22:48:47,999 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:47,999 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:48,208 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:48,209 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:48,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:48,210 INFO L82 PathProgramCache]: Analyzing trace with hash -633329328, now seen corresponding path program 3 times [2019-10-06 22:48:48,210 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:48,211 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:48,211 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:48,211 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:48,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:48,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:48,343 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:48,343 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:48,344 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:48,344 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:48,464 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:48:48,464 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:48:48,466 INFO L256 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-06 22:48:48,478 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:48,487 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:48,488 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:48,565 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:48,566 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:48,568 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:48,568 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:48,568 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:48,569 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:48,569 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:48,594 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:50,249 INFO L199 IcfgInterpreter]: Interpreting procedure bor with input of size 1 for LOIs [2019-10-06 22:48:50,273 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:50,276 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:50,276 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:50,276 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:48:50,276 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_389 Int) (v_bor_~res~0_BEFORE_RETURN_54 Int) (v_bor_~res~0_BEFORE_RETURN_53 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod v_bor_~res~0_BEFORE_RETURN_53 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_bor_~res~0_BEFORE_RETURN_53 4294967296) main_~ret~0)) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_54 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_bor_~res~0_BEFORE_RETURN_54 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_389 4294967296) 2147483647)) (= main_~ret~0 (+ (mod v_prenex_389 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-06 22:48:50,277 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:50,277 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:50,277 INFO L193 IcfgInterpreter]: Reachable states at location borENTRY satisfy 601#true [2019-10-06 22:48:50,277 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bor_~i~0) [2019-10-06 22:48:50,277 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:50,277 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:50,278 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:50,278 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:50,278 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bor_~res~0_BEFORE_RETURN_58 Int) (v_bor_~res~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_58 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_58 4294967296) (- 4294967296)) main_~ret5~0)) (and (= main_~ret5~0 (+ (mod v_prenex_417 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_417 4294967296) 2147483647))) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_57 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_57 4294967296))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_418 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_418 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bor_~res~0_BEFORE_RETURN_58 Int) (v_bor_~res~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_58 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_58 4294967296) (- 4294967296)) main_~ret5~0)) (and (= main_~ret5~0 (+ (mod v_prenex_417 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_417 4294967296) 2147483647))) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_57 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_57 4294967296))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_418 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_418 4294967296) 2147483647)))))) [2019-10-06 22:48:50,278 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:50,278 INFO L193 IcfgInterpreter]: Reachable states at location borEXIT satisfy 644#(and (not (< bor_~i~0 10000)) (<= 10000 bor_~i~0) (<= 1 bor_~i~0) (= (ite (<= (mod bor_~res~0 4294967296) 2147483647) (mod bor_~res~0 4294967296) (+ (mod bor_~res~0 4294967296) (- 4294967296))) |bor_#res|)) [2019-10-06 22:48:50,279 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:48:50,279 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bor_~res~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_390 4294967296) 2147483647))) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_54 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_bor_~res~0_BEFORE_RETURN_54 4294967296) |main_#t~ret5|)))) (exists ((v_prenex_389 Int) (v_bor_~res~0_BEFORE_RETURN_53 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_389 4294967296) 2147483647)) (= (+ (mod v_prenex_389 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (<= (mod v_bor_~res~0_BEFORE_RETURN_53 4294967296) 2147483647) (= (mod v_bor_~res~0_BEFORE_RETURN_53 4294967296) |main_#t~ret5|))))) [2019-10-06 22:48:50,279 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:50,279 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:50,279 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:50,279 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:50,624 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:50,624 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-06 22:48:50,626 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-06 22:48:50,626 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-06 22:48:50,626 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-06 22:48:50,627 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-06 22:48:51,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:51,655 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-06 22:48:51,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-06 22:48:51,655 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-06 22:48:51,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:51,656 INFO L225 Difference]: With dead ends: 54 [2019-10-06 22:48:51,656 INFO L226 Difference]: Without dead ends: 36 [2019-10-06 22:48:51,658 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-06 22:48:51,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-06 22:48:51,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-06 22:48:51,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-06 22:48:51,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-06 22:48:51,676 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-06 22:48:51,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:51,677 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-06 22:48:51,677 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-06 22:48:51,677 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-06 22:48:51,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-06 22:48:51,681 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:51,681 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:51,884 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:51,885 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:51,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:51,886 INFO L82 PathProgramCache]: Analyzing trace with hash -1897195758, now seen corresponding path program 4 times [2019-10-06 22:48:51,886 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:51,886 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:51,886 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:51,887 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:51,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:51,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:52,074 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:52,074 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:52,075 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:52,075 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:52,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:52,226 INFO L256 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-06 22:48:52,228 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:52,243 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:52,244 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:52,527 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:52,528 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:52,529 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:52,529 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:52,530 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:52,530 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:52,530 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:52,545 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:53,778 INFO L199 IcfgInterpreter]: Interpreting procedure bor with input of size 1 for LOIs [2019-10-06 22:48:53,797 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:53,800 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:53,801 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:53,801 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:48:53,801 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_583 Int) (v_prenex_584 Int) (v_bor_~res~0_BEFORE_RETURN_79 Int) (v_bor_~res~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_prenex_584 4294967296) main_~ret~0) (<= (mod v_prenex_584 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_bor_~res~0_BEFORE_RETURN_79 4294967296) 2147483647) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bor_~res~0_BEFORE_RETURN_79 4294967296))) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) main_~ret~0) (not (<= (mod v_prenex_583 4294967296) 2147483647)) (<= main_~ret~0 2147483647)))) [2019-10-06 22:48:53,802 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:53,802 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:53,802 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bor_~i~0) [2019-10-06 22:48:53,802 INFO L193 IcfgInterpreter]: Reachable states at location borENTRY satisfy 601#true [2019-10-06 22:48:53,802 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:53,802 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:53,803 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:53,803 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:48:53,803 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_bor_~res~0_BEFORE_RETURN_83 Int) (v_bor_~res~0_BEFORE_RETURN_84 Int) (v_prenex_612 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_84 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_84 4294967296) 2147483647))) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_611 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (not (< main_~i~2 9999)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_83 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_83 4294967296) (- 4294967296)))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_612 4294967296) 2147483647) (= (mod v_prenex_612 4294967296) main_~ret5~0))))) (and (not (= main_~ret~0 main_~ret5~0)) (exists ((v_prenex_611 Int) (v_bor_~res~0_BEFORE_RETURN_83 Int) (v_bor_~res~0_BEFORE_RETURN_84 Int) (v_prenex_612 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_84 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_84 4294967296) 2147483647))) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_611 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (not (< main_~i~2 9999)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_83 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_83 4294967296) (- 4294967296)))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_612 4294967296) 2147483647) (= (mod v_prenex_612 4294967296) main_~ret5~0)))))) [2019-10-06 22:48:53,803 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:53,803 INFO L193 IcfgInterpreter]: Reachable states at location borEXIT satisfy 644#(and (not (< bor_~i~0 10000)) (<= 10000 bor_~i~0) (<= 1 bor_~i~0) (= (ite (<= (mod bor_~res~0 4294967296) 2147483647) (mod bor_~res~0 4294967296) (+ (mod bor_~res~0 4294967296) (- 4294967296))) |bor_#res|)) [2019-10-06 22:48:53,804 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:48:53,804 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_583 Int) (v_bor_~res~0_BEFORE_RETURN_79 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_583 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (mod v_bor_~res~0_BEFORE_RETURN_79 4294967296)) (<= (mod v_bor_~res~0_BEFORE_RETURN_79 4294967296) 2147483647)))) (exists ((v_prenex_584 Int) (v_bor_~res~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (mod v_prenex_584 4294967296)) (<= (mod v_prenex_584 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (+ (mod v_bor_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)))))) [2019-10-06 22:48:53,804 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:48:53,804 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:48:53,804 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:48:53,804 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:48:54,186 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:54,186 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-06 22:48:54,188 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-06 22:48:54,188 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-06 22:48:54,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-06 22:48:54,190 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 40 states. [2019-10-06 22:48:57,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:57,866 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-06 22:48:57,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-06 22:48:57,866 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 49 [2019-10-06 22:48:57,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:57,868 INFO L225 Difference]: With dead ends: 68 [2019-10-06 22:48:57,868 INFO L226 Difference]: Without dead ends: 50 [2019-10-06 22:48:57,870 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-06 22:48:57,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-06 22:48:57,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-06 22:48:57,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-06 22:48:57,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-06 22:48:57,879 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-06 22:48:57,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:57,879 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-06 22:48:57,879 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-06 22:48:57,879 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-06 22:48:57,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-06 22:48:57,880 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:57,881 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:58,084 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:58,085 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:58,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:58,085 INFO L82 PathProgramCache]: Analyzing trace with hash -755090094, now seen corresponding path program 5 times [2019-10-06 22:48:58,085 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:58,085 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:58,086 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:58,086 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:58,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:58,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:58,507 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:48:58,507 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:58,507 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:58,507 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:58,698 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:48:58,698 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:48:58,699 INFO L256 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:58,716 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:58,785 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-06 22:48:58,785 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:58,833 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-06 22:48:58,834 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:58,835 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:58,835 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:58,836 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:58,836 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:58,836 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:58,852 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:00,075 INFO L199 IcfgInterpreter]: Interpreting procedure bor with input of size 1 for LOIs [2019-10-06 22:49:00,098 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:00,101 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:00,101 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:00,101 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:49:00,102 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_bor_~res~0_BEFORE_RETURN_105 Int) (v_prenex_777 Int) (v_prenex_778 Int) (v_bor_~res~0_BEFORE_RETURN_106 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_777 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_prenex_777 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= main_~ret~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_106 4294967296) (- 4294967296))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_106 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod v_bor_~res~0_BEFORE_RETURN_105 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_bor_~res~0_BEFORE_RETURN_105 4294967296)) (<= main_~ret~0 2147483647)))) (exists ((v_bor_~res~0_BEFORE_RETURN_105 Int) (v_prenex_777 Int) (v_prenex_778 Int) (v_bor_~res~0_BEFORE_RETURN_106 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_777 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_prenex_777 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_106 4294967296) 2147483647)) (= main_~ret~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_106 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod v_bor_~res~0_BEFORE_RETURN_105 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_bor_~res~0_BEFORE_RETURN_105 4294967296)) (<= main_~ret~0 2147483647))))) [2019-10-06 22:49:00,102 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:00,102 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:00,102 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bor_~i~0) [2019-10-06 22:49:00,102 INFO L193 IcfgInterpreter]: Reachable states at location borENTRY satisfy 601#true [2019-10-06 22:49:00,102 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:00,103 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:49:00,103 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:00,103 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:00,103 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bor_~res~0_BEFORE_RETURN_110 Int) (v_prenex_806 Int) (v_prenex_805 Int) (v_bor_~res~0_BEFORE_RETURN_109 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= (mod v_bor_~res~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_bor_~res~0_BEFORE_RETURN_109 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_110 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647))))) (and (exists ((v_bor_~res~0_BEFORE_RETURN_110 Int) (v_prenex_806 Int) (v_prenex_805 Int) (v_bor_~res~0_BEFORE_RETURN_109 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= (mod v_bor_~res~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_bor_~res~0_BEFORE_RETURN_109 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_110 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:49:00,103 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:00,104 INFO L193 IcfgInterpreter]: Reachable states at location borEXIT satisfy 644#(and (not (< bor_~i~0 10000)) (<= 10000 bor_~i~0) (<= 1 bor_~i~0) (= (ite (<= (mod bor_~res~0 4294967296) 2147483647) (mod bor_~res~0 4294967296) (+ (mod bor_~res~0 4294967296) (- 4294967296))) |bor_#res|)) [2019-10-06 22:49:00,104 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:49:00,104 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_778 Int) (v_bor_~res~0_BEFORE_RETURN_106 Int)) (or (and (= (+ (mod v_bor_~res~0_BEFORE_RETURN_106 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 10000)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_106 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (= (mod v_prenex_778 4294967296) |main_#t~ret5|) (<= (mod v_prenex_778 4294967296) 2147483647)))) (exists ((v_bor_~res~0_BEFORE_RETURN_105 Int) (v_prenex_777 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bor_~res~0_BEFORE_RETURN_105 4294967296) 2147483647) (= (mod v_bor_~res~0_BEFORE_RETURN_105 4294967296) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_777 4294967296) 2147483647)) (= (+ (mod v_prenex_777 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 22:49:00,104 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:00,104 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:00,104 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:00,105 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:00,637 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:00,637 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-06 22:49:00,639 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-06 22:49:00,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-06 22:49:00,640 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-06 22:49:00,641 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 44 states. [2019-10-06 22:49:05,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:05,226 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-06 22:49:05,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-06 22:49:05,226 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 63 [2019-10-06 22:49:05,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:05,228 INFO L225 Difference]: With dead ends: 72 [2019-10-06 22:49:05,228 INFO L226 Difference]: Without dead ends: 54 [2019-10-06 22:49:05,230 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1350 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1349, Invalid=5457, Unknown=0, NotChecked=0, Total=6806 [2019-10-06 22:49:05,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-06 22:49:05,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-06 22:49:05,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-06 22:49:05,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-06 22:49:05,238 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-06 22:49:05,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:05,238 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-06 22:49:05,239 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-06 22:49:05,239 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-06 22:49:05,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-06 22:49:05,240 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:05,240 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:05,441 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:05,442 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:05,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:05,443 INFO L82 PathProgramCache]: Analyzing trace with hash 1616126463, now seen corresponding path program 6 times [2019-10-06 22:49:05,443 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:05,444 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:05,444 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:05,444 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:05,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:05,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:05,864 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:05,864 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:05,864 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:05,864 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:06,080 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:49:06,080 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:06,082 INFO L256 TraceCheckSpWp]: Trace formula consists of 331 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-06 22:49:06,085 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:06,102 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:06,102 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:07,090 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:07,090 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:07,092 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:07,092 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:07,092 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:07,093 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:07,093 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:07,111 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:08,397 INFO L199 IcfgInterpreter]: Interpreting procedure bor with input of size 1 for LOIs [2019-10-06 22:49:08,416 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:08,419 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:08,419 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:08,419 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:49:08,420 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_bor_~res~0_BEFORE_RETURN_132 Int) (v_bor_~res~0_BEFORE_RETURN_131 Int)) (or (and (= main_~ret~0 (mod v_prenex_972 4294967296)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_972 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_132 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= (mod v_bor_~res~0_BEFORE_RETURN_131 4294967296) main_~ret~0) (<= (mod v_bor_~res~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)))) (exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_bor_~res~0_BEFORE_RETURN_132 Int) (v_bor_~res~0_BEFORE_RETURN_131 Int)) (or (and (= main_~ret~0 (mod v_prenex_972 4294967296)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_972 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_132 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= (mod v_bor_~res~0_BEFORE_RETURN_131 4294967296) main_~ret~0) (<= (mod v_bor_~res~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647))))) [2019-10-06 22:49:08,420 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:08,420 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:08,420 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bor_~i~0) [2019-10-06 22:49:08,420 INFO L193 IcfgInterpreter]: Reachable states at location borENTRY satisfy 601#true [2019-10-06 22:49:08,420 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:08,421 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:08,421 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:08,421 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:08,421 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bor_~res~0_BEFORE_RETURN_136 Int) (v_bor_~res~0_BEFORE_RETURN_135 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (not (<= (mod v_bor_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296)))) (and (= (mod v_bor_~res~0_BEFORE_RETURN_135 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= (mod v_bor_~res~0_BEFORE_RETURN_135 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_1000 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0)) (and (not (<= (mod v_prenex_999 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_999 4294967296) (- 4294967296)) main_~ret5~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bor_~res~0_BEFORE_RETURN_136 Int) (v_bor_~res~0_BEFORE_RETURN_135 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (not (<= (mod v_bor_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296)))) (and (= (mod v_bor_~res~0_BEFORE_RETURN_135 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= (mod v_bor_~res~0_BEFORE_RETURN_135 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_1000 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0)) (and (not (<= (mod v_prenex_999 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_999 4294967296) (- 4294967296)) main_~ret5~0)))))) [2019-10-06 22:49:08,421 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:08,422 INFO L193 IcfgInterpreter]: Reachable states at location borEXIT satisfy 644#(and (not (< bor_~i~0 10000)) (<= 10000 bor_~i~0) (<= 1 bor_~i~0) (= (ite (<= (mod bor_~res~0 4294967296) 2147483647) (mod bor_~res~0 4294967296) (+ (mod bor_~res~0 4294967296) (- 4294967296))) |bor_#res|)) [2019-10-06 22:49:08,422 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:49:08,422 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_972 Int) (v_bor_~res~0_BEFORE_RETURN_132 Int)) (or (and (not (< main_~i~1 10000)) (= (mod v_prenex_972 4294967296) |main_#t~ret5|) (<= (mod v_prenex_972 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_132 4294967296) 2147483647))))) (exists ((v_prenex_971 Int) (v_bor_~res~0_BEFORE_RETURN_131 Int)) (or (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (+ (mod v_prenex_971 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (<= (mod v_bor_~res~0_BEFORE_RETURN_131 4294967296) 2147483647) (= (mod v_bor_~res~0_BEFORE_RETURN_131 4294967296) |main_#t~ret5|))))) [2019-10-06 22:49:08,422 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:08,422 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:08,423 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:08,423 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:08,958 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:08,958 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-06 22:49:08,959 INFO L442 AbstractCegarLoop]: Interpolant automaton has 70 states [2019-10-06 22:49:08,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2019-10-06 22:49:08,961 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1740, Invalid=3090, Unknown=0, NotChecked=0, Total=4830 [2019-10-06 22:49:08,961 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 70 states. [2019-10-06 22:49:12,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:12,227 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-06 22:49:12,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2019-10-06 22:49:12,227 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 67 [2019-10-06 22:49:12,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:12,229 INFO L225 Difference]: With dead ends: 104 [2019-10-06 22:49:12,229 INFO L226 Difference]: Without dead ends: 83 [2019-10-06 22:49:12,235 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3929 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=5099, Invalid=12723, Unknown=0, NotChecked=0, Total=17822 [2019-10-06 22:49:12,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-06 22:49:12,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-06 22:49:12,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-06 22:49:12,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-06 22:49:12,244 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-06 22:49:12,244 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:12,244 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-06 22:49:12,244 INFO L463 AbstractCegarLoop]: Interpolant automaton has 70 states. [2019-10-06 22:49:12,245 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-06 22:49:12,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-06 22:49:12,246 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:12,246 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:12,449 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:12,450 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:12,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:12,450 INFO L82 PathProgramCache]: Analyzing trace with hash 1754158397, now seen corresponding path program 7 times [2019-10-06 22:49:12,451 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:12,452 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:12,452 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:12,453 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:12,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:12,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:13,847 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:13,848 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:13,848 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:13,848 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:14,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:14,117 INFO L256 TraceCheckSpWp]: Trace formula consists of 505 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-06 22:49:14,120 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:14,163 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:14,163 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:17,737 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:17,738 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:17,739 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:17,739 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:17,740 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:17,740 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:17,740 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:17,761 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:19,002 INFO L199 IcfgInterpreter]: Interpreting procedure bor with input of size 1 for LOIs [2019-10-06 22:49:19,030 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:19,032 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:19,032 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:19,032 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:49:19,033 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bor_~res~0_BEFORE_RETURN_158 Int) (v_bor_~res~0_BEFORE_RETURN_157 Int) (v_prenex_1166 Int) (v_prenex_1165 Int)) (or (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_157 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_157 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (<= (mod v_prenex_1165 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_prenex_1165 4294967296))) (and (not (< main_~i~1 10000)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_prenex_1166 4294967296))) (and (not (<= (mod v_bor_~res~0_BEFORE_RETURN_158 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-06 22:49:19,033 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:19,033 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:19,033 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bor_~i~0) [2019-10-06 22:49:19,033 INFO L193 IcfgInterpreter]: Reachable states at location borENTRY satisfy 601#true [2019-10-06 22:49:19,033 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:19,034 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:19,034 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:19,034 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:19,034 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bor_~res~0_BEFORE_RETURN_162 Int) (v_bor_~res~0_BEFORE_RETURN_161 Int) (v_prenex_1194 Int) (v_prenex_1193 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1194 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1194 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 9999)) (<= (mod v_bor_~res~0_BEFORE_RETURN_161 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_161 4294967296))) (and (not (< main_~i~2 9999)) (<= (mod v_bor_~res~0_BEFORE_RETURN_162 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_bor_~res~0_BEFORE_RETURN_162 4294967296) main_~ret5~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bor_~res~0_BEFORE_RETURN_162 Int) (v_bor_~res~0_BEFORE_RETURN_161 Int) (v_prenex_1194 Int) (v_prenex_1193 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1194 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1194 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 9999)) (<= (mod v_bor_~res~0_BEFORE_RETURN_161 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_161 4294967296))) (and (not (< main_~i~2 9999)) (<= (mod v_bor_~res~0_BEFORE_RETURN_162 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_bor_~res~0_BEFORE_RETURN_162 4294967296) main_~ret5~0)))))) [2019-10-06 22:49:19,034 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:19,035 INFO L193 IcfgInterpreter]: Reachable states at location borEXIT satisfy 644#(and (not (< bor_~i~0 10000)) (<= 10000 bor_~i~0) (<= 1 bor_~i~0) (= (ite (<= (mod bor_~res~0 4294967296) 2147483647) (mod bor_~res~0 4294967296) (+ (mod bor_~res~0 4294967296) (- 4294967296))) |bor_#res|)) [2019-10-06 22:49:19,035 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:49:19,035 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bor_~res~0_BEFORE_RETURN_157 Int) (v_prenex_1165 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_157 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_157 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (<= (mod v_prenex_1165 4294967296) 2147483647) (= |main_#t~ret5| (mod v_prenex_1165 4294967296))))) (exists ((v_bor_~res~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int)) (or (and (= (mod v_prenex_1166 4294967296) |main_#t~ret5|) (not (< main_~i~1 10000)) (<= (mod v_prenex_1166 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_158 4294967296) 2147483647)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 22:49:19,035 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:19,035 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:19,035 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:19,035 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:19,663 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:19,663 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 127 [2019-10-06 22:49:19,665 INFO L442 AbstractCegarLoop]: Interpolant automaton has 128 states [2019-10-06 22:49:19,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 128 interpolants. [2019-10-06 22:49:19,670 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6815, Invalid=9441, Unknown=0, NotChecked=0, Total=16256 [2019-10-06 22:49:19,670 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 128 states. [2019-10-06 22:49:31,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:31,436 INFO L93 Difference]: Finished difference Result 162 states and 227 transitions. [2019-10-06 22:49:31,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 127 states. [2019-10-06 22:49:31,437 INFO L78 Accepts]: Start accepts. Automaton has 128 states. Word has length 96 [2019-10-06 22:49:31,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:31,438 INFO L225 Difference]: With dead ends: 162 [2019-10-06 22:49:31,438 INFO L226 Difference]: Without dead ends: 141 [2019-10-06 22:49:31,443 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 471 GetRequests, 223 SyntacticMatches, 0 SemanticMatches, 248 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12077 ImplicationChecksByTransitivity, 16.5s TimeCoverageRelationStatistics Valid=20208, Invalid=42041, Unknown=1, NotChecked=0, Total=62250 [2019-10-06 22:49:31,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2019-10-06 22:49:31,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2019-10-06 22:49:31,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2019-10-06 22:49:31,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 145 transitions. [2019-10-06 22:49:31,461 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 145 transitions. Word has length 96 [2019-10-06 22:49:31,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:31,462 INFO L462 AbstractCegarLoop]: Abstraction has 141 states and 145 transitions. [2019-10-06 22:49:31,462 INFO L463 AbstractCegarLoop]: Interpolant automaton has 128 states. [2019-10-06 22:49:31,462 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 145 transitions. [2019-10-06 22:49:31,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2019-10-06 22:49:31,465 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:31,465 INFO L385 BasicCegarLoop]: trace histogram [114, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:31,669 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:31,669 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:31,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:31,670 INFO L82 PathProgramCache]: Analyzing trace with hash -2111660931, now seen corresponding path program 8 times [2019-10-06 22:49:31,670 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:31,670 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:31,671 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:31,671 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:31,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:31,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:36,793 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 0 proven. 6555 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:49:36,794 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:36,794 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:36,794 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:37,075 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:49:37,075 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:37,076 INFO L256 TraceCheckSpWp]: Trace formula consists of 141 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 22:49:37,080 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:37,334 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 22:49:37,335 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:37,612 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 22:49:37,612 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:37,613 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:37,614 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:37,614 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:37,614 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:37,614 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:37,626 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:38,855 INFO L199 IcfgInterpreter]: Interpreting procedure bor with input of size 1 for LOIs [2019-10-06 22:49:38,878 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:38,881 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:38,881 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:38,882 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:49:38,882 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_1359 Int) (v_bor_~res~0_BEFORE_RETURN_184 Int) (v_bor_~res~0_BEFORE_RETURN_183 Int) (v_prenex_1360 Int)) (or (and (not (< main_~i~1 10000)) (= main_~ret~0 (mod v_prenex_1359 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1359 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_184 4294967296) 2147483647)) (= main_~ret~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_184 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_bor_~res~0_BEFORE_RETURN_183 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_1360 4294967296)) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1360 4294967296) 2147483647)))) [2019-10-06 22:49:38,882 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:38,882 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:38,882 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bor_~i~0) [2019-10-06 22:49:38,883 INFO L193 IcfgInterpreter]: Reachable states at location borENTRY satisfy 601#true [2019-10-06 22:49:38,883 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:38,883 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:38,883 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:38,883 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:49:38,884 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_1388 Int) (v_bor_~res~0_BEFORE_RETURN_188 Int) (v_bor_~res~0_BEFORE_RETURN_187 Int) (v_prenex_1387 Int)) (or (and (= (mod v_bor_~res~0_BEFORE_RETURN_187 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= (mod v_bor_~res~0_BEFORE_RETURN_187 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_prenex_1387 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1387 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296)))) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_188 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_188 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_1388 Int) (v_bor_~res~0_BEFORE_RETURN_188 Int) (v_bor_~res~0_BEFORE_RETURN_187 Int) (v_prenex_1387 Int)) (or (and (= (mod v_bor_~res~0_BEFORE_RETURN_187 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= (mod v_bor_~res~0_BEFORE_RETURN_187 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_prenex_1387 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1387 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296)))) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_188 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_188 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 22:49:38,884 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:38,884 INFO L193 IcfgInterpreter]: Reachable states at location borEXIT satisfy 644#(and (not (< bor_~i~0 10000)) (<= 10000 bor_~i~0) (<= 1 bor_~i~0) (= (ite (<= (mod bor_~res~0 4294967296) 2147483647) (mod bor_~res~0 4294967296) (+ (mod bor_~res~0 4294967296) (- 4294967296))) |bor_#res|)) [2019-10-06 22:49:38,884 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:49:38,884 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bor_~res~0_BEFORE_RETURN_184 Int) (v_prenex_1360 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_184 4294967296) 2147483647)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_184 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (= (mod v_prenex_1360 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1360 4294967296) 2147483647)))) (exists ((v_prenex_1359 Int) (v_bor_~res~0_BEFORE_RETURN_183 Int)) (or (and (not (<= (mod v_bor_~res~0_BEFORE_RETURN_183 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (= (mod v_prenex_1359 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1359 4294967296) 2147483647))))) [2019-10-06 22:49:38,884 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:49:38,884 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:49:38,885 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:49:38,885 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:49:39,974 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:39,975 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [117, 7, 7, 11] total 137 [2019-10-06 22:49:39,976 INFO L442 AbstractCegarLoop]: Interpolant automaton has 138 states [2019-10-06 22:49:39,978 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 138 interpolants. [2019-10-06 22:49:39,979 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6880, Invalid=12026, Unknown=0, NotChecked=0, Total=18906 [2019-10-06 22:49:39,979 INFO L87 Difference]: Start difference. First operand 141 states and 145 transitions. Second operand 138 states. [2019-10-06 22:49:55,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:55,249 INFO L93 Difference]: Finished difference Result 169 states and 186 transitions. [2019-10-06 22:49:55,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 138 states. [2019-10-06 22:49:55,250 INFO L78 Accepts]: Start accepts. Automaton has 138 states. Word has length 154 [2019-10-06 22:49:55,251 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:55,253 INFO L225 Difference]: With dead ends: 169 [2019-10-06 22:49:55,253 INFO L226 Difference]: Without dead ends: 148 [2019-10-06 22:49:55,256 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 711 GetRequests, 442 SyntacticMatches, 0 SemanticMatches, 269 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12310 ImplicationChecksByTransitivity, 20.0s TimeCoverageRelationStatistics Valid=20694, Invalid=52475, Unknown=1, NotChecked=0, Total=73170 [2019-10-06 22:49:55,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2019-10-06 22:49:55,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 148. [2019-10-06 22:49:55,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2019-10-06 22:49:55,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 152 transitions. [2019-10-06 22:49:55,272 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 152 transitions. Word has length 154 [2019-10-06 22:49:55,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:55,272 INFO L462 AbstractCegarLoop]: Abstraction has 148 states and 152 transitions. [2019-10-06 22:49:55,272 INFO L463 AbstractCegarLoop]: Interpolant automaton has 138 states. [2019-10-06 22:49:55,272 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 152 transitions. [2019-10-06 22:49:55,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2019-10-06 22:49:55,274 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:55,275 INFO L385 BasicCegarLoop]: trace histogram [115, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:55,478 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:55,483 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:55,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:55,484 INFO L82 PathProgramCache]: Analyzing trace with hash -1892637921, now seen corresponding path program 9 times [2019-10-06 22:49:55,484 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:55,484 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:55,484 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:55,484 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:55,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:55,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:00,471 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:50:00,471 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:00,471 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:50:00,471 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:00,880 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:50:00,880 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:50:00,885 INFO L256 TraceCheckSpWp]: Trace formula consists of 913 conjuncts, 117 conjunts are in the unsatisfiable core [2019-10-06 22:50:00,890 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:50:00,942 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:50:00,942 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:15,491 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:50:15,491 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:15,492 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:15,492 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:15,493 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:15,493 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:15,493 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:15,508 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:50:16,662 INFO L199 IcfgInterpreter]: Interpreting procedure bor with input of size 1 for LOIs [2019-10-06 22:50:16,689 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:50:16,692 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:50:16,692 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:50:16,692 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:50:16,693 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_1554 Int) (v_prenex_1553 Int) (v_bor_~res~0_BEFORE_RETURN_210 Int) (v_bor_~res~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_prenex_1554 4294967296)) (<= (mod v_prenex_1554 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= main_~ret~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_209 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_209 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (= main_~ret~0 (mod v_prenex_1553 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1553 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= main_~ret~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_210 4294967296) 2147483647)) (<= main_~ret~0 2147483647)))) [2019-10-06 22:50:16,693 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:50:16,693 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:50:16,693 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bor_~i~0) [2019-10-06 22:50:16,693 INFO L193 IcfgInterpreter]: Reachable states at location borENTRY satisfy 601#true [2019-10-06 22:50:16,693 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:16,694 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:50:16,694 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:16,694 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:50:16,694 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bor_~res~0_BEFORE_RETURN_214 Int) (v_bor_~res~0_BEFORE_RETURN_213 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (mod v_bor_~res~0_BEFORE_RETURN_213 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bor_~res~0_BEFORE_RETURN_213 4294967296) 2147483647)) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9999)) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_214 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_bor_~res~0_BEFORE_RETURN_214 4294967296) main_~ret5~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (exists ((v_bor_~res~0_BEFORE_RETURN_214 Int) (v_bor_~res~0_BEFORE_RETURN_213 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (mod v_bor_~res~0_BEFORE_RETURN_213 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bor_~res~0_BEFORE_RETURN_213 4294967296) 2147483647)) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9999)) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_214 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_bor_~res~0_BEFORE_RETURN_214 4294967296) main_~ret5~0)))) (not (= main_~ret~0 main_~ret2~0)))) [2019-10-06 22:50:16,694 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:50:16,695 INFO L193 IcfgInterpreter]: Reachable states at location borEXIT satisfy 644#(and (not (< bor_~i~0 10000)) (<= 10000 bor_~i~0) (<= 1 bor_~i~0) (= (ite (<= (mod bor_~res~0 4294967296) 2147483647) (mod bor_~res~0 4294967296) (+ (mod bor_~res~0 4294967296) (- 4294967296))) |bor_#res|)) [2019-10-06 22:50:16,695 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:50:16,695 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1553 Int) (v_bor_~res~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_209 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (= (mod v_prenex_1553 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1553 4294967296) 2147483647)))) (exists ((v_prenex_1554 Int) (v_bor_~res~0_BEFORE_RETURN_210 Int)) (or (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (mod v_prenex_1554 4294967296)) (<= (mod v_prenex_1554 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (+ (mod v_bor_~res~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_210 4294967296) 2147483647)))))) [2019-10-06 22:50:16,695 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:50:16,695 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:50:16,695 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:50:16,696 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:50:17,884 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:50:17,885 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [118, 118, 118, 11] total 245 [2019-10-06 22:50:17,887 INFO L442 AbstractCegarLoop]: Interpolant automaton has 246 states [2019-10-06 22:50:17,893 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 246 interpolants. [2019-10-06 22:50:17,896 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27524, Invalid=32746, Unknown=0, NotChecked=0, Total=60270 [2019-10-06 22:50:17,896 INFO L87 Difference]: Start difference. First operand 148 states and 152 transitions. Second operand 246 states. [2019-10-06 22:50:52,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:52,416 INFO L93 Difference]: Finished difference Result 292 states and 416 transitions. [2019-10-06 22:50:52,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 245 states. [2019-10-06 22:50:52,416 INFO L78 Accepts]: Start accepts. Automaton has 246 states. Word has length 173 [2019-10-06 22:50:52,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:52,419 INFO L225 Difference]: With dead ends: 292 [2019-10-06 22:50:52,419 INFO L226 Difference]: Without dead ends: 265 [2019-10-06 22:50:52,427 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 879 GetRequests, 395 SyntacticMatches, 0 SemanticMatches, 484 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41637 ImplicationChecksByTransitivity, 53.0s TimeCoverageRelationStatistics Valid=82099, Invalid=153611, Unknown=0, NotChecked=0, Total=235710 [2019-10-06 22:50:52,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2019-10-06 22:50:52,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 265. [2019-10-06 22:50:52,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2019-10-06 22:50:52,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 269 transitions. [2019-10-06 22:50:52,448 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 269 transitions. Word has length 173 [2019-10-06 22:50:52,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:52,449 INFO L462 AbstractCegarLoop]: Abstraction has 265 states and 269 transitions. [2019-10-06 22:50:52,449 INFO L463 AbstractCegarLoop]: Interpolant automaton has 246 states. [2019-10-06 22:50:52,449 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 269 transitions. [2019-10-06 22:50:52,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2019-10-06 22:50:52,453 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:52,453 INFO L385 BasicCegarLoop]: trace histogram [232, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:52,662 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:52,663 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:52,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:52,663 INFO L82 PathProgramCache]: Analyzing trace with hash -1905941539, now seen corresponding path program 10 times [2019-10-06 22:50:52,663 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:52,664 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:52,664 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:52,664 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:52,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:53,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:12,311 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:51:12,311 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:12,311 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:51:12,311 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:12,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:12,932 INFO L256 TraceCheckSpWp]: Trace formula consists of 1615 conjuncts, 234 conjunts are in the unsatisfiable core [2019-10-06 22:51:12,939 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:51:13,046 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:51:13,047 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:52:11,721 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:52:11,722 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:52:11,723 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:52:11,724 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:52:11,724 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:52:11,724 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:52:11,724 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:52:11,744 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:52:12,879 INFO L199 IcfgInterpreter]: Interpreting procedure bor with input of size 1 for LOIs [2019-10-06 22:52:12,899 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:52:12,901 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:52:12,902 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:52:12,902 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:52:12,902 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bor_~res~0_BEFORE_RETURN_236 Int) (v_bor_~res~0_BEFORE_RETURN_235 Int) (v_prenex_1748 Int) (v_prenex_1747 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_1747 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_prenex_1747 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_bor_~res~0_BEFORE_RETURN_235 4294967296) 2147483647) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bor_~res~0_BEFORE_RETURN_235 4294967296))) (and (not (< main_~i~1 10000)) (= main_~ret~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_236 4294967296) (- 4294967296))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_236 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1748 4294967296) 2147483647) (<= main_~ret~0 2147483647) (= (mod v_prenex_1748 4294967296) main_~ret~0)))) [2019-10-06 22:52:12,902 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:52:12,902 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:52:12,903 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bor_~i~0) [2019-10-06 22:52:12,903 INFO L193 IcfgInterpreter]: Reachable states at location borENTRY satisfy 601#true [2019-10-06 22:52:12,903 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:12,903 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:12,904 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:12,904 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:52:12,904 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_1776 Int) (v_prenex_1775 Int) (v_bor_~res~0_BEFORE_RETURN_240 Int) (v_bor_~res~0_BEFORE_RETURN_239 Int)) (or (and (not (< main_~i~2 9999)) (<= (mod v_bor_~res~0_BEFORE_RETURN_239 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_239 4294967296))) (and (not (<= (mod v_bor_~res~0_BEFORE_RETURN_240 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_240 4294967296) (- 4294967296)))) (and (not (< main_~i~2 9999)) (not (<= (mod v_prenex_1775 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1775 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1776 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1776 4294967296) 2147483647))))) (and (not (= main_~ret~0 main_~ret5~0)) (exists ((v_prenex_1776 Int) (v_prenex_1775 Int) (v_bor_~res~0_BEFORE_RETURN_240 Int) (v_bor_~res~0_BEFORE_RETURN_239 Int)) (or (and (not (< main_~i~2 9999)) (<= (mod v_bor_~res~0_BEFORE_RETURN_239 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_239 4294967296))) (and (not (<= (mod v_bor_~res~0_BEFORE_RETURN_240 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_bor_~res~0_BEFORE_RETURN_240 4294967296) (- 4294967296)))) (and (not (< main_~i~2 9999)) (not (<= (mod v_prenex_1775 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1775 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1776 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1776 4294967296) 2147483647)))))) [2019-10-06 22:52:12,904 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:52:12,905 INFO L193 IcfgInterpreter]: Reachable states at location borEXIT satisfy 644#(and (not (< bor_~i~0 10000)) (<= 10000 bor_~i~0) (<= 1 bor_~i~0) (= (ite (<= (mod bor_~res~0 4294967296) 2147483647) (mod bor_~res~0 4294967296) (+ (mod bor_~res~0 4294967296) (- 4294967296))) |bor_#res|)) [2019-10-06 22:52:12,905 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:52:12,905 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bor_~res~0_BEFORE_RETURN_235 Int) (v_prenex_1747 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_1747 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_prenex_1747 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (= (mod v_bor_~res~0_BEFORE_RETURN_235 4294967296) |main_#t~ret5|) (<= (mod v_bor_~res~0_BEFORE_RETURN_235 4294967296) 2147483647)))) (exists ((v_bor_~res~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_236 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_bor_~res~0_BEFORE_RETURN_236 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (mod v_prenex_1748 4294967296)) (<= (mod v_prenex_1748 4294967296) 2147483647))))) [2019-10-06 22:52:12,905 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:52:12,905 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:52:12,905 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:52:12,906 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:52:14,779 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:52:14,779 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [235, 235, 235, 11] total 479 [2019-10-06 22:52:14,781 INFO L442 AbstractCegarLoop]: Interpolant automaton has 480 states [2019-10-06 22:52:14,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 480 interpolants. [2019-10-06 22:52:14,795 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=109775, Invalid=120145, Unknown=0, NotChecked=0, Total=229920 [2019-10-06 22:52:14,795 INFO L87 Difference]: Start difference. First operand 265 states and 269 transitions. Second operand 480 states. [2019-10-06 22:54:29,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:54:29,504 INFO L93 Difference]: Finished difference Result 526 states and 767 transitions. [2019-10-06 22:54:29,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 479 states. [2019-10-06 22:54:29,504 INFO L78 Accepts]: Start accepts. Automaton has 480 states. Word has length 290 [2019-10-06 22:54:29,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:54:29,507 INFO L225 Difference]: With dead ends: 526 [2019-10-06 22:54:29,508 INFO L226 Difference]: Without dead ends: 499 [2019-10-06 22:54:29,535 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1581 GetRequests, 629 SyntacticMatches, 0 SemanticMatches, 952 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151734 ImplicationChecksByTransitivity, 201.3s TimeCoverageRelationStatistics Valid=328384, Invalid=580778, Unknown=0, NotChecked=0, Total=909162 [2019-10-06 22:54:29,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 499 states. [2019-10-06 22:54:29,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 499 to 499. [2019-10-06 22:54:29,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 499 states. [2019-10-06 22:54:29,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 499 states to 499 states and 503 transitions. [2019-10-06 22:54:29,558 INFO L78 Accepts]: Start accepts. Automaton has 499 states and 503 transitions. Word has length 290 [2019-10-06 22:54:29,558 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:54:29,559 INFO L462 AbstractCegarLoop]: Abstraction has 499 states and 503 transitions. [2019-10-06 22:54:29,559 INFO L463 AbstractCegarLoop]: Interpolant automaton has 480 states. [2019-10-06 22:54:29,559 INFO L276 IsEmpty]: Start isEmpty. Operand 499 states and 503 transitions. [2019-10-06 22:54:29,569 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 525 [2019-10-06 22:54:29,570 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:54:29,570 INFO L385 BasicCegarLoop]: trace histogram [466, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:54:29,775 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:54:29,776 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:54:29,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:54:29,777 INFO L82 PathProgramCache]: Analyzing trace with hash -1824394979, now seen corresponding path program 11 times [2019-10-06 22:54:29,777 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:54:29,777 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:54:29,777 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:29,777 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:29,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:54:31,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:54:32,219 INFO L134 CoverageAnalysis]: Checked inductivity of 109355 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 109056 trivial. 0 not checked. [2019-10-06 22:54:32,220 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:54:32,220 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:54:32,220 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:54:32,746 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2019-10-06 22:54:32,747 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:54:32,748 INFO L256 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 22:54:32,757 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:54:33,064 INFO L134 CoverageAnalysis]: Checked inductivity of 109355 backedges. 246 proven. 10 refuted. 0 times theorem prover too weak. 109099 trivial. 0 not checked. [2019-10-06 22:54:33,065 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:54:33,440 INFO L134 CoverageAnalysis]: Checked inductivity of 109355 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 109345 trivial. 0 not checked. [2019-10-06 22:54:33,440 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:54:33,444 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:54:33,444 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:54:33,445 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:54:33,446 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:54:33,446 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:54:33,467 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:54:34,640 INFO L199 IcfgInterpreter]: Interpreting procedure bor with input of size 1 for LOIs [2019-10-06 22:54:34,656 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:54:34,658 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:54:34,658 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:54:34,658 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:54:34,658 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_bor_~res~0_BEFORE_RETURN_262 Int) (v_bor_~res~0_BEFORE_RETURN_261 Int)) (or (and (<= (mod v_bor_~res~0_BEFORE_RETURN_261 4294967296) 2147483647) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bor_~res~0_BEFORE_RETURN_261 4294967296))) (and (not (< main_~i~1 10000)) (= (mod v_prenex_1942 4294967296) main_~ret~0) (<= (mod v_prenex_1942 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_262 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_262 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_prenex_1941 4294967296) (- 4294967296))) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (<= main_~ret~0 2147483647)))) (exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_bor_~res~0_BEFORE_RETURN_262 Int) (v_bor_~res~0_BEFORE_RETURN_261 Int)) (or (and (<= (mod v_bor_~res~0_BEFORE_RETURN_261 4294967296) 2147483647) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bor_~res~0_BEFORE_RETURN_261 4294967296))) (and (not (< main_~i~1 10000)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_262 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_262 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod v_prenex_1942 4294967296) 2147483647) (= (mod v_prenex_1942 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_prenex_1941 4294967296) (- 4294967296))) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (<= main_~ret~0 2147483647))))) [2019-10-06 22:54:34,659 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:54:34,659 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:54:34,659 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bor_~i~0) [2019-10-06 22:54:34,659 INFO L193 IcfgInterpreter]: Reachable states at location borENTRY satisfy 601#true [2019-10-06 22:54:34,659 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:34,659 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:34,659 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:34,659 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 22:54:34,659 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bor_~res~0_BEFORE_RETURN_266 Int) (v_bor_~res~0_BEFORE_RETURN_265 Int) (v_prenex_1970 Int) (v_prenex_1969 Int)) (or (and (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_265 4294967296)) (not (< main_~i~2 9999)) (<= (mod v_bor_~res~0_BEFORE_RETURN_265 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (+ (mod v_prenex_1969 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1969 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= (mod v_bor_~res~0_BEFORE_RETURN_266 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bor_~res~0_BEFORE_RETURN_266 4294967296) 2147483647))))) (and (exists ((v_bor_~res~0_BEFORE_RETURN_266 Int) (v_bor_~res~0_BEFORE_RETURN_265 Int) (v_prenex_1970 Int) (v_prenex_1969 Int)) (or (and (= main_~ret5~0 (mod v_bor_~res~0_BEFORE_RETURN_265 4294967296)) (not (< main_~i~2 9999)) (<= (mod v_bor_~res~0_BEFORE_RETURN_265 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (+ (mod v_prenex_1969 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1969 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= (mod v_bor_~res~0_BEFORE_RETURN_266 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bor_~res~0_BEFORE_RETURN_266 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 22:54:34,660 INFO L193 IcfgInterpreter]: Reachable states at location borEXIT satisfy 644#(and (not (< bor_~i~0 10000)) (<= 10000 bor_~i~0) (<= 1 bor_~i~0) (= (ite (<= (mod bor_~res~0 4294967296) 2147483647) (mod bor_~res~0 4294967296) (+ (mod bor_~res~0 4294967296) (- 4294967296))) |bor_#res|)) [2019-10-06 22:54:34,660 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:54:34,660 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:54:34,660 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1941 Int) (v_bor_~res~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (= (+ (mod v_prenex_1941 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (<= (mod v_bor_~res~0_BEFORE_RETURN_261 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_bor_~res~0_BEFORE_RETURN_261 4294967296) |main_#t~ret5|)))) (exists ((v_prenex_1942 Int) (v_bor_~res~0_BEFORE_RETURN_262 Int)) (or (and (= (+ (mod v_bor_~res~0_BEFORE_RETURN_262 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 10000)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_262 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (mod v_prenex_1942 4294967296)) (<= (mod v_prenex_1942 4294967296) 2147483647))))) [2019-10-06 22:54:34,660 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 22:54:34,660 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 22:54:34,660 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 22:54:34,661 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 22:54:35,034 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:54:35,035 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 7, 7, 11] total 33 [2019-10-06 22:54:35,037 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2019-10-06 22:54:35,037 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-10-06 22:54:35,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=173, Invalid=949, Unknown=0, NotChecked=0, Total=1122 [2019-10-06 22:54:35,038 INFO L87 Difference]: Start difference. First operand 499 states and 503 transitions. Second operand 34 states. [2019-10-06 22:54:38,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:54:38,522 INFO L93 Difference]: Finished difference Result 532 states and 548 transitions. [2019-10-06 22:54:38,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-10-06 22:54:38,522 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 524 [2019-10-06 22:54:38,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:54:38,526 INFO L225 Difference]: With dead ends: 532 [2019-10-06 22:54:38,526 INFO L226 Difference]: Without dead ends: 506 [2019-10-06 22:54:38,527 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1614 GetRequests, 1553 SyntacticMatches, 0 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 892 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=597, Invalid=3308, Unknown=1, NotChecked=0, Total=3906 [2019-10-06 22:54:38,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 506 states. [2019-10-06 22:54:38,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 506 to 506. [2019-10-06 22:54:38,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 506 states. [2019-10-06 22:54:38,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 506 states to 506 states and 510 transitions. [2019-10-06 22:54:38,556 INFO L78 Accepts]: Start accepts. Automaton has 506 states and 510 transitions. Word has length 524 [2019-10-06 22:54:38,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:54:38,557 INFO L462 AbstractCegarLoop]: Abstraction has 506 states and 510 transitions. [2019-10-06 22:54:38,557 INFO L463 AbstractCegarLoop]: Interpolant automaton has 34 states. [2019-10-06 22:54:38,557 INFO L276 IsEmpty]: Start isEmpty. Operand 506 states and 510 transitions. [2019-10-06 22:54:38,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 534 [2019-10-06 22:54:38,561 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:54:38,562 INFO L385 BasicCegarLoop]: trace histogram [466, 33, 10, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:54:38,766 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:54:38,766 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:54:38,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:54:38,767 INFO L82 PathProgramCache]: Analyzing trace with hash 1952640954, now seen corresponding path program 12 times [2019-10-06 22:54:38,767 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:54:38,767 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:54:38,768 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:38,768 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:38,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:54:40,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:55:58,482 INFO L134 CoverageAnalysis]: Checked inductivity of 109502 backedges. 0 proven. 108811 refuted. 0 times theorem prover too weak. 691 trivial. 0 not checked. [2019-10-06 22:55:58,483 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:55:58,483 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:55:58,483 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:55:59,514 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:55:59,515 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:55:59,530 INFO L256 TraceCheckSpWp]: Trace formula consists of 3052 conjuncts, 468 conjunts are in the unsatisfiable core [2019-10-06 22:55:59,542 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:55:59,802 INFO L134 CoverageAnalysis]: Checked inductivity of 109502 backedges. 0 proven. 108811 refuted. 0 times theorem prover too weak. 691 trivial. 0 not checked. [2019-10-06 22:55:59,802 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:59:59,396 INFO L134 CoverageAnalysis]: Checked inductivity of 109502 backedges. 0 proven. 108811 refuted. 0 times theorem prover too weak. 691 trivial. 0 not checked. [2019-10-06 22:59:59,397 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:59:59,398 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:59:59,398 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:59:59,398 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:59:59,399 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:59:59,399 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:59:59,417 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:00:00,560 INFO L199 IcfgInterpreter]: Interpreting procedure bor with input of size 1 for LOIs [2019-10-06 23:00:00,594 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:00:00,596 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:00:00,596 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:00:00,596 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 23:00:00,597 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bor_~res~0_BEFORE_RETURN_288 Int) (v_prenex_2135 Int) (v_bor_~res~0_BEFORE_RETURN_287 Int) (v_prenex_2136 Int)) (or (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_prenex_2135 4294967296) (- 4294967296))) (not (<= (mod v_prenex_2135 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_288 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_288 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_bor_~res~0_BEFORE_RETURN_287 4294967296)) (<= (mod v_bor_~res~0_BEFORE_RETURN_287 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= main_~ret~0 (mod v_prenex_2136 4294967296)) (<= (mod v_prenex_2136 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-06 23:00:00,597 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:00:00,597 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:00:00,598 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bor_~i~0) [2019-10-06 23:00:00,598 INFO L193 IcfgInterpreter]: Reachable states at location borENTRY satisfy 601#true [2019-10-06 23:00:00,598 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:00:00,598 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:00:00,598 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:00:00,598 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:00:00,599 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_2163 Int) (v_prenex_2164 Int) (v_bor_~res~0_BEFORE_RETURN_292 Int) (v_bor_~res~0_BEFORE_RETURN_291 Int)) (or (and (not (< main_~i~2 9999)) (not (<= (mod v_prenex_2163 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2163 4294967296) (- 4294967296)) main_~ret5~0)) (and (= (+ (mod v_bor_~res~0_BEFORE_RETURN_292 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9999)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_292 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bor_~res~0_BEFORE_RETURN_291 4294967296) 2147483647) (= (mod v_bor_~res~0_BEFORE_RETURN_291 4294967296) main_~ret5~0)) (and (= (mod v_prenex_2164 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_2164 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_2163 Int) (v_prenex_2164 Int) (v_bor_~res~0_BEFORE_RETURN_292 Int) (v_bor_~res~0_BEFORE_RETURN_291 Int)) (or (and (not (< main_~i~2 9999)) (not (<= (mod v_prenex_2163 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2163 4294967296) (- 4294967296)) main_~ret5~0)) (and (= (+ (mod v_bor_~res~0_BEFORE_RETURN_292 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9999)) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_292 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bor_~res~0_BEFORE_RETURN_291 4294967296) 2147483647) (= (mod v_bor_~res~0_BEFORE_RETURN_291 4294967296) main_~ret5~0)) (and (= (mod v_prenex_2164 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_2164 4294967296) 2147483647)))))) [2019-10-06 23:00:00,599 INFO L193 IcfgInterpreter]: Reachable states at location borEXIT satisfy 644#(and (not (< bor_~i~0 10000)) (<= 10000 bor_~i~0) (<= 1 bor_~i~0) (= (ite (<= (mod bor_~res~0 4294967296) 2147483647) (mod bor_~res~0 4294967296) (+ (mod bor_~res~0 4294967296) (- 4294967296))) |bor_#res|)) [2019-10-06 23:00:00,599 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:00:00,599 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 23:00:00,602 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bor_~res~0_BEFORE_RETURN_288 Int) (v_prenex_2136 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_prenex_2136 4294967296) 2147483647) (= (mod v_prenex_2136 4294967296) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (= (+ (mod v_bor_~res~0_BEFORE_RETURN_288 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_bor_~res~0_BEFORE_RETURN_288 4294967296) 2147483647))))) (exists ((v_bor_~res~0_BEFORE_RETURN_287 Int) (v_prenex_2135 Int)) (or (and (not (< main_~i~1 10000)) (= (mod v_bor_~res~0_BEFORE_RETURN_287 4294967296) |main_#t~ret5|) (<= (mod v_bor_~res~0_BEFORE_RETURN_287 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= (+ (mod v_prenex_2135 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_2135 4294967296) 2147483647)))))) [2019-10-06 23:00:00,604 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:00:00,604 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:00:00,604 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:00:00,604 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:00:04,275 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:00:04,276 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [469, 469, 469, 11] total 947 [2019-10-06 23:00:04,278 INFO L442 AbstractCegarLoop]: Interpolant automaton has 948 states [2019-10-06 23:00:04,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 948 interpolants. [2019-10-06 23:00:04,338 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=438545, Invalid=459211, Unknown=0, NotChecked=0, Total=897756 [2019-10-06 23:00:04,339 INFO L87 Difference]: Start difference. First operand 506 states and 510 transitions. Second operand 948 states.