java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/loops/linear_search.c -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 13:44:32,565 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 13:44:32,567 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 13:44:32,579 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 13:44:32,580 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 13:44:32,581 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 13:44:32,582 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 13:44:32,584 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 13:44:32,586 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 13:44:32,586 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 13:44:32,587 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 13:44:32,588 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 13:44:32,589 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 13:44:32,590 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 13:44:32,590 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 13:44:32,592 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 13:44:32,592 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 13:44:32,593 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 13:44:32,595 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 13:44:32,597 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 13:44:32,598 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 13:44:32,599 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 13:44:32,600 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 13:44:32,601 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 13:44:32,603 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 13:44:32,606 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-07 13:44:32,606 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-07 13:44:32,607 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-07 13:44:32,608 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-07 13:44:32,609 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-07 13:44:32,609 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-07 13:44:32,610 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-07 13:44:32,610 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-07 13:44:32,610 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 13:44:32,611 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 13:44:32,612 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 13:44:32,612 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 13:44:32,631 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 13:44:32,631 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 13:44:32,632 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 13:44:32,632 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 13:44:32,632 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 13:44:32,633 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 13:44:32,633 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 13:44:32,633 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 13:44:32,633 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 13:44:32,633 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 13:44:32,633 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 13:44:32,634 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 13:44:32,634 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 13:44:32,634 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 13:44:32,634 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 13:44:32,634 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 13:44:32,635 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 13:44:32,635 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 13:44:32,635 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 13:44:32,635 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 13:44:32,635 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 13:44:32,636 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 13:44:32,636 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 13:44:32,636 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 13:44:32,636 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 13:44:32,636 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 13:44:32,637 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 13:44:32,637 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 13:44:32,637 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 13:44:32,971 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 13:44:32,991 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 13:44:32,994 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 13:44:32,996 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 13:44:32,996 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 13:44:32,997 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops/linear_search.c [2019-10-07 13:44:33,067 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/33395970b/dac7dc1e782547f2bfaaec16b443e29d/FLAG97fd69424 [2019-10-07 13:44:33,482 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 13:44:33,482 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops/linear_search.c [2019-10-07 13:44:33,487 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/33395970b/dac7dc1e782547f2bfaaec16b443e29d/FLAG97fd69424 [2019-10-07 13:44:33,883 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/33395970b/dac7dc1e782547f2bfaaec16b443e29d [2019-10-07 13:44:33,892 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 13:44:33,893 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 13:44:33,894 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 13:44:33,895 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 13:44:33,898 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 13:44:33,899 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 01:44:33" (1/1) ... [2019-10-07 13:44:33,902 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7c8bf277 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 01:44:33, skipping insertion in model container [2019-10-07 13:44:33,902 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 01:44:33" (1/1) ... [2019-10-07 13:44:33,909 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 13:44:33,929 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 13:44:34,119 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 13:44:34,131 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 13:44:34,163 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 13:44:34,182 INFO L192 MainTranslator]: Completed translation [2019-10-07 13:44:34,183 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 01:44:34 WrapperNode [2019-10-07 13:44:34,183 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 13:44:34,184 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 13:44:34,184 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 13:44:34,185 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 13:44:34,300 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 01:44:34" (1/1) ... [2019-10-07 13:44:34,300 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 01:44:34" (1/1) ... [2019-10-07 13:44:34,309 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 01:44:34" (1/1) ... [2019-10-07 13:44:34,311 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 01:44:34" (1/1) ... [2019-10-07 13:44:34,328 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 01:44:34" (1/1) ... [2019-10-07 13:44:34,332 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 01:44:34" (1/1) ... [2019-10-07 13:44:34,334 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 01:44:34" (1/1) ... [2019-10-07 13:44:34,336 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 13:44:34,336 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 13:44:34,336 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 13:44:34,336 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 13:44:34,337 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 01:44:34" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 13:44:34,409 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 13:44:34,410 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 13:44:34,410 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2019-10-07 13:44:34,410 INFO L138 BoogieDeclarations]: Found implementation of procedure linear_search [2019-10-07 13:44:34,410 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 13:44:34,411 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 13:44:34,411 INFO L130 BoogieDeclarations]: Found specification of procedure malloc [2019-10-07 13:44:34,411 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2019-10-07 13:44:34,411 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2019-10-07 13:44:34,411 INFO L130 BoogieDeclarations]: Found specification of procedure linear_search [2019-10-07 13:44:34,412 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 13:44:34,412 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 13:44:34,413 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2019-10-07 13:44:34,413 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 13:44:34,413 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 13:44:34,413 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 13:44:34,414 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 13:44:34,875 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 13:44:34,875 INFO L284 CfgBuilder]: Removed 1 assume(true) statements. [2019-10-07 13:44:34,876 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 01:44:34 BoogieIcfgContainer [2019-10-07 13:44:34,876 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 13:44:34,877 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 13:44:34,877 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 13:44:34,880 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 13:44:34,880 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 01:44:33" (1/3) ... [2019-10-07 13:44:34,881 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2ca7abfb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 01:44:34, skipping insertion in model container [2019-10-07 13:44:34,881 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 01:44:34" (2/3) ... [2019-10-07 13:44:34,881 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2ca7abfb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 01:44:34, skipping insertion in model container [2019-10-07 13:44:34,881 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 01:44:34" (3/3) ... [2019-10-07 13:44:34,883 INFO L109 eAbstractionObserver]: Analyzing ICFG linear_search.c [2019-10-07 13:44:34,892 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 13:44:34,899 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 13:44:34,909 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 13:44:34,932 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 13:44:34,933 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 13:44:34,933 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 13:44:34,933 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 13:44:34,933 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 13:44:34,933 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 13:44:34,933 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 13:44:34,934 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 13:44:34,951 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states. [2019-10-07 13:44:34,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-10-07 13:44:34,957 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 13:44:34,958 INFO L385 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 13:44:34,960 INFO L410 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 13:44:34,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 13:44:34,965 INFO L82 PathProgramCache]: Analyzing trace with hash -1155056295, now seen corresponding path program 1 times [2019-10-07 13:44:34,971 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 13:44:34,971 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:44:34,971 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:44:34,971 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:44:34,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 13:44:35,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 13:44:35,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:44:35,145 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:44:35,146 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 13:44:35,146 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-10-07 13:44:35,149 INFO L442 AbstractCegarLoop]: Interpolant automaton has 2 states [2019-10-07 13:44:35,160 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2019-10-07 13:44:35,161 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2019-10-07 13:44:35,162 INFO L87 Difference]: Start difference. First operand 25 states. Second operand 2 states. [2019-10-07 13:44:35,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 13:44:35,181 INFO L93 Difference]: Finished difference Result 40 states and 44 transitions. [2019-10-07 13:44:35,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2019-10-07 13:44:35,182 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 16 [2019-10-07 13:44:35,183 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 13:44:35,189 INFO L225 Difference]: With dead ends: 40 [2019-10-07 13:44:35,190 INFO L226 Difference]: Without dead ends: 18 [2019-10-07 13:44:35,193 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2019-10-07 13:44:35,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2019-10-07 13:44:35,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2019-10-07 13:44:35,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2019-10-07 13:44:35,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2019-10-07 13:44:35,226 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 16 [2019-10-07 13:44:35,226 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 13:44:35,226 INFO L462 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2019-10-07 13:44:35,226 INFO L463 AbstractCegarLoop]: Interpolant automaton has 2 states. [2019-10-07 13:44:35,227 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2019-10-07 13:44:35,227 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2019-10-07 13:44:35,227 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 13:44:35,228 INFO L385 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 13:44:35,228 INFO L410 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 13:44:35,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 13:44:35,228 INFO L82 PathProgramCache]: Analyzing trace with hash -890265588, now seen corresponding path program 1 times [2019-10-07 13:44:35,229 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 13:44:35,229 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:44:35,229 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:44:35,229 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:44:35,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 13:44:35,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 13:44:35,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:44:35,507 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:44:35,508 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 13:44:35,508 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-10-07 13:44:35,511 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-10-07 13:44:35,511 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-10-07 13:44:35,512 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2019-10-07 13:44:35,512 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand 8 states. [2019-10-07 13:44:35,698 WARN L191 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 16 DAG size of output: 14 [2019-10-07 13:44:35,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 13:44:35,780 INFO L93 Difference]: Finished difference Result 28 states and 28 transitions. [2019-10-07 13:44:35,781 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-10-07 13:44:35,781 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 17 [2019-10-07 13:44:35,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 13:44:35,782 INFO L225 Difference]: With dead ends: 28 [2019-10-07 13:44:35,782 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 13:44:35,783 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=37, Invalid=119, Unknown=0, NotChecked=0, Total=156 [2019-10-07 13:44:35,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 13:44:35,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 13:44:35,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 13:44:35,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 20 transitions. [2019-10-07 13:44:35,789 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 20 transitions. Word has length 17 [2019-10-07 13:44:35,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 13:44:35,789 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 20 transitions. [2019-10-07 13:44:35,789 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-10-07 13:44:35,790 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 20 transitions. [2019-10-07 13:44:35,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-10-07 13:44:35,790 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 13:44:35,791 INFO L385 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 13:44:35,791 INFO L410 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 13:44:35,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 13:44:35,791 INFO L82 PathProgramCache]: Analyzing trace with hash 831240490, now seen corresponding path program 1 times [2019-10-07 13:44:35,792 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 13:44:35,792 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:44:35,792 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:44:35,792 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:44:35,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 13:44:35,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 13:44:36,008 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:44:36,009 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:44:36,009 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 13:44:36,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 13:44:36,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 13:44:36,128 INFO L256 TraceCheckSpWp]: Trace formula consists of 100 conjuncts, 13 conjunts are in the unsatisfiable core [2019-10-07 13:44:36,140 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 13:44:36,279 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:44:36,280 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 13:44:36,543 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-07 13:44:36,620 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:44:36,620 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 13:44:36,648 INFO L162 IcfgInterpreter]: Started Sifa with 18 locations of interest [2019-10-07 13:44:36,649 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 13:44:36,655 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 13:44:36,664 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 13:44:36,664 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 13:44:36,837 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 30 for LOIs [2019-10-07 13:44:37,214 INFO L199 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 14 for LOIs [2019-10-07 13:44:37,263 INFO L199 IcfgInterpreter]: Interpreting procedure linear_search with input of size 18 for LOIs [2019-10-07 13:44:37,457 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 16 for LOIs [2019-10-07 13:44:37,464 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 13:44:37,464 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 13:44:37,465 INFO L193 IcfgInterpreter]: Reachable states at location __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 177#(and (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond))) (<= __VERIFIER_assert_~cond 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) [2019-10-07 13:44:37,465 INFO L193 IcfgInterpreter]: Reachable states at location L17-2 satisfy 301#(and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3)) [2019-10-07 13:44:37,465 INFO L193 IcfgInterpreter]: Reachable states at location linear_searchENTRY satisfy 181#(and (or (and (= (+ (mod ~SIZE~0 4294967296) (- 4294967296)) |linear_search_#in~n|) (= 3 |linear_search_#in~q|) (not (<= (mod ~SIZE~0 4294967296) 2147483647))) (and (= (mod ~SIZE~0 4294967296) |linear_search_#in~n|) (= 3 |linear_search_#in~q|) (<= (mod ~SIZE~0 4294967296) 2147483647))) (<= 3 |linear_search_#in~q|) (<= |linear_search_#in~q| 3)) [2019-10-07 13:44:37,466 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 305#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= ~MAX~0 |old(~MAX~0)|) (= |#NULL.offset| |old(#NULL.offset)|) (= |old(~SIZE~0)| ~SIZE~0)) [2019-10-07 13:44:37,466 INFO L193 IcfgInterpreter]: Reachable states at location L25 satisfy 38#(exists ((v_prenex_1 Int) (|v_main_#t~nondet3_3| Int)) (or (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_3| 4294967296) 2) 1)) (= |#valid| |old(#valid)|) (not (< (mod |v_main_#t~nondet3_3| 4294967296) 0)) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod v_prenex_1 4294967296) 0) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (not (= (mod v_prenex_1 2) 0)) (= |#valid| |old(#valid)|) (= |#memory_int| |old(#memory_int)|) (= ~SIZE~0 (+ (div (mod v_prenex_1 4294967296) 2) 2)) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_3| 4294967296) 2) 1)) (= |#valid| |old(#valid)|) (= |#memory_int| |old(#memory_int)|) (= (mod |v_main_#t~nondet3_3| 2) 0) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)))) [2019-10-07 13:44:37,466 INFO L193 IcfgInterpreter]: Reachable states at location L15-3 satisfy 277#(and (<= 0 (+ linear_search_~j~0 1)) (and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3))) [2019-10-07 13:44:37,467 INFO L193 IcfgInterpreter]: Reachable states at location L15-5 satisfy 282#(or (and (<= 0 linear_search_~j~0) (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3)) (and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3))) [2019-10-07 13:44:37,467 INFO L193 IcfgInterpreter]: Reachable states at location linear_searchEXIT satisfy 291#(and (<= 3 |linear_search_#in~q|) (<= |linear_search_#res| 1) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3) (<= 0 |linear_search_#res|)) [2019-10-07 13:44:37,467 INFO L193 IcfgInterpreter]: Reachable states at location L28-2 satisfy 154#(or (and (<= |main_#t~ret5| 2147483647) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (<= 0 (+ |main_#t~ret5| 2147483648)) (= 1 |main_#t~ret5|)) (and (<= |main_#t~ret5| 2147483647) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (<= 0 (+ |main_#t~ret5| 2147483648)) (= 0 |main_#t~ret5|))) [2019-10-07 13:44:37,468 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (<= ~MAX~0 100000) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= ~SIZE~0 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |#valid| 0)) (<= 0 ~SIZE~0) (= |#NULL.offset| 0) (<= ~SIZE~0 0) (<= 100000 ~MAX~0)) [2019-10-07 13:44:37,468 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= |#valid| |old(#valid)|) (<= |old(~SIZE~0)| 0) (<= 0 ~SIZE~0) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= ~SIZE~0 0) (= |old(~SIZE~0)| ~SIZE~0) (<= 100000 ~MAX~0)) [2019-10-07 13:44:37,468 INFO L193 IcfgInterpreter]: Reachable states at location L28-1 satisfy 135#(and (or (= 0 |main_#t~ret5|) (= 1 |main_#t~ret5|)) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1)) [2019-10-07 13:44:37,468 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 310#(and (<= ~MAX~0 100000) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= ~SIZE~0 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| 0 0)) (<= 0 ~SIZE~0) (= |#NULL.offset| 0) (<= ~SIZE~0 0) (<= 100000 ~MAX~0)) [2019-10-07 13:44:37,469 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 13:44:37,470 INFO L193 IcfgInterpreter]: Reachable states at location L28 satisfy 43#(exists ((v_prenex_2 Int) (v_prenex_1 Int) (|v_main_#t~nondet3_3| Int)) (or (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_2 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (= (mod v_prenex_2 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_2 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod v_prenex_2 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (= |main_#t~malloc4.base| main_~a~0.base) (< (mod v_prenex_1 4294967296) 0) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (not (= (mod v_prenex_1 2) 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= ~SIZE~0 (+ (div (mod v_prenex_1 4294967296) 2) 2)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_3| 4294967296) 2) 1)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (< (mod |v_main_#t~nondet3_3| 4294967296) 0)) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_2 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (= (mod v_prenex_2 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_3| 4294967296) 2) 1)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (< (mod |v_main_#t~nondet3_3| 4294967296) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (< (mod v_prenex_1 4294967296) 0) (not (< (mod ~SIZE~0 4294967296) 0)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (not (= (mod v_prenex_1 2) 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= ~SIZE~0 (+ (div (mod v_prenex_1 4294967296) 2) 2)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_2 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod v_prenex_2 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (< (mod v_prenex_1 4294967296) 0) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (not (= (mod v_prenex_1 2) 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (= ~SIZE~0 (+ (div (mod v_prenex_1 4294967296) 2) 2)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (= ~SIZE~0 (+ (div (mod v_prenex_2 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod v_prenex_2 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (< (mod v_prenex_1 4294967296) 0) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (not (= (mod v_prenex_1 2) 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= ~SIZE~0 (+ (div (mod v_prenex_1 4294967296) 2) 2)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (< (mod v_prenex_1 4294967296) 0) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (not (= (mod v_prenex_1 2) 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= ~SIZE~0 (+ (div (mod v_prenex_1 4294967296) 2) 2)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (< (mod v_prenex_1 4294967296) 0) (not (< (mod ~SIZE~0 4294967296) 0)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (not (= (mod v_prenex_1 2) 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= ~SIZE~0 (+ (div (mod v_prenex_1 4294967296) 2) 2)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (= ~SIZE~0 (+ (div (mod v_prenex_2 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod v_prenex_2 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_3| 4294967296) 2) 1)) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= |main_#t~malloc4.base| main_~a~0.base) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (< (mod |v_main_#t~nondet3_3| 4294967296) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_3| 4294967296) 2) 1)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= |main_#t~malloc4.base| main_~a~0.base) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (< (mod |v_main_#t~nondet3_3| 4294967296) 0)) (= (mod ~SIZE~0 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_3| 4294967296) 2) 1)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (= |main_#t~malloc4.base| main_~a~0.base) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (< (mod |v_main_#t~nondet3_3| 4294967296) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_3| 4294967296) 2) 1)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= |main_#t~malloc4.base| main_~a~0.base) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (< (mod |v_main_#t~nondet3_3| 4294967296) 0)) (= (mod ~SIZE~0 2) 0) (= |#NULL.offset| 0)))) [2019-10-07 13:44:37,471 INFO L193 IcfgInterpreter]: Reachable states at location L6 satisfy 172#(and (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond))) (<= __VERIFIER_assert_~cond 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) [2019-10-07 13:44:37,471 INFO L193 IcfgInterpreter]: Reachable states at location L5 satisfy 167#(and (or (and (<= __VERIFIER_assert_~cond 0) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) (and (<= 1 __VERIFIER_assert_~cond) (<= 1 |__VERIFIER_assert_#in~cond|) (<= __VERIFIER_assert_~cond 1))) (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)))) [2019-10-07 13:44:37,471 INFO L193 IcfgInterpreter]: Reachable states at location __VERIFIER_assertENTRY satisfy 162#(and (or (<= 1 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0)) (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1)))) [2019-10-07 13:44:40,610 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 13:44:40,611 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 13] total 31 [2019-10-07 13:44:40,612 INFO L442 AbstractCegarLoop]: Interpolant automaton has 31 states [2019-10-07 13:44:40,612 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2019-10-07 13:44:40,614 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=829, Unknown=1, NotChecked=0, Total=930 [2019-10-07 13:44:40,614 INFO L87 Difference]: Start difference. First operand 20 states and 20 transitions. Second operand 31 states. [2019-10-07 13:44:42,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 13:44:42,665 INFO L93 Difference]: Finished difference Result 30 states and 30 transitions. [2019-10-07 13:44:42,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-10-07 13:44:42,666 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 19 [2019-10-07 13:44:42,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 13:44:42,667 INFO L225 Difference]: With dead ends: 30 [2019-10-07 13:44:42,667 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 13:44:42,668 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 31 SyntacticMatches, 6 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 438 ImplicationChecksByTransitivity, 4.8s TimeCoverageRelationStatistics Valid=227, Invalid=1752, Unknown=1, NotChecked=0, Total=1980 [2019-10-07 13:44:42,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 13:44:42,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 13:44:42,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 13:44:42,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 22 transitions. [2019-10-07 13:44:42,676 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 22 transitions. Word has length 19 [2019-10-07 13:44:42,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 13:44:42,677 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 22 transitions. [2019-10-07 13:44:42,677 INFO L463 AbstractCegarLoop]: Interpolant automaton has 31 states. [2019-10-07 13:44:42,677 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 22 transitions. [2019-10-07 13:44:42,678 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-10-07 13:44:42,678 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 13:44:42,678 INFO L385 BasicCegarLoop]: trace histogram [3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 13:44:42,886 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 13:44:42,887 INFO L410 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 13:44:42,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 13:44:42,888 INFO L82 PathProgramCache]: Analyzing trace with hash 1636172488, now seen corresponding path program 2 times [2019-10-07 13:44:42,888 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 13:44:42,889 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:44:42,889 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:44:42,890 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:44:42,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 13:44:42,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 13:44:43,385 WARN L191 SmtUtils]: Spent 190.00 ms on a formula simplification. DAG size of input: 151 DAG size of output: 27 [2019-10-07 13:44:45,856 WARN L191 SmtUtils]: Spent 2.12 s on a formula simplification. DAG size of input: 89 DAG size of output: 40 [2019-10-07 13:44:45,928 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:44:45,928 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:44:45,928 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 13:44:45,928 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 13:44:46,081 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 13:44:46,082 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 13:44:46,083 INFO L256 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 48 conjunts are in the unsatisfiable core [2019-10-07 13:44:46,087 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 13:44:46,202 WARN L225 Elim1Store]: Array PQE input equivalent to false [2019-10-07 13:44:50,476 WARN L191 SmtUtils]: Spent 4.27 s on a formula simplification. DAG size of input: 61 DAG size of output: 30 [2019-10-07 13:44:50,879 WARN L191 SmtUtils]: Spent 190.00 ms on a formula simplification that was a NOOP. DAG size: 41 [2019-10-07 13:44:52,292 WARN L191 SmtUtils]: Spent 1.30 s on a formula simplification. DAG size of input: 66 DAG size of output: 56 [2019-10-07 13:44:52,919 WARN L191 SmtUtils]: Spent 563.00 ms on a formula simplification that was a NOOP. DAG size: 47 [2019-10-07 13:44:54,785 WARN L191 SmtUtils]: Spent 1.78 s on a formula simplification. DAG size of input: 62 DAG size of output: 52 [2019-10-07 13:44:56,197 WARN L191 SmtUtils]: Spent 1.25 s on a formula simplification. DAG size of input: 48 DAG size of output: 48 [2019-10-07 13:44:56,228 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:44:56,229 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 13:44:56,629 WARN L191 SmtUtils]: Spent 305.00 ms on a formula simplification. DAG size of input: 115 DAG size of output: 70 [2019-10-07 13:44:56,838 WARN L191 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 63 [2019-10-07 13:44:57,752 WARN L191 SmtUtils]: Spent 186.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 70 [2019-10-07 13:44:58,793 WARN L191 SmtUtils]: Spent 475.00 ms on a formula simplification that was a NOOP. DAG size: 82 [2019-10-07 13:44:58,877 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:44:58,877 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 13:44:58,879 INFO L162 IcfgInterpreter]: Started Sifa with 18 locations of interest [2019-10-07 13:44:58,879 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 13:44:58,879 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 13:44:58,880 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 13:44:58,880 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 13:44:58,920 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 30 for LOIs [2019-10-07 13:44:59,052 INFO L199 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 16 for LOIs [2019-10-07 13:44:59,077 INFO L199 IcfgInterpreter]: Interpreting procedure linear_search with input of size 18 for LOIs [2019-10-07 13:44:59,233 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 16 for LOIs [2019-10-07 13:44:59,238 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 13:44:59,239 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 13:44:59,239 INFO L193 IcfgInterpreter]: Reachable states at location __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 177#(and (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond))) (<= __VERIFIER_assert_~cond 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) [2019-10-07 13:44:59,239 INFO L193 IcfgInterpreter]: Reachable states at location L17-2 satisfy 301#(and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3)) [2019-10-07 13:44:59,240 INFO L193 IcfgInterpreter]: Reachable states at location linear_searchENTRY satisfy 181#(and (or (and (= (+ (mod ~SIZE~0 4294967296) (- 4294967296)) |linear_search_#in~n|) (= 3 |linear_search_#in~q|) (not (<= (mod ~SIZE~0 4294967296) 2147483647))) (and (= (mod ~SIZE~0 4294967296) |linear_search_#in~n|) (= 3 |linear_search_#in~q|) (<= (mod ~SIZE~0 4294967296) 2147483647))) (<= 3 |linear_search_#in~q|) (<= |linear_search_#in~q| 3)) [2019-10-07 13:44:59,240 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 305#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= ~MAX~0 |old(~MAX~0)|) (= |#NULL.offset| |old(#NULL.offset)|) (= |old(~SIZE~0)| ~SIZE~0)) [2019-10-07 13:44:59,242 INFO L193 IcfgInterpreter]: Reachable states at location L25 satisfy 38#(exists ((v_prenex_13 Int) (|v_main_#t~nondet3_5| Int)) (or (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (< (mod |v_main_#t~nondet3_5| 4294967296) 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_5| 4294967296) 2) 2)) (= |#valid| |old(#valid)|) (not (= (mod |v_main_#t~nondet3_5| 2) 0)) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= ~SIZE~0 (+ (div (mod v_prenex_13 4294967296) 2) 1)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (= (mod v_prenex_13 2) 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| |old(#valid)|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= ~SIZE~0 (+ (div (mod v_prenex_13 4294967296) 2) 1)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (not (< (mod v_prenex_13 4294967296) 0)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| |old(#valid)|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)))) [2019-10-07 13:44:59,243 INFO L193 IcfgInterpreter]: Reachable states at location L15-3 satisfy 277#(and (<= 0 (+ linear_search_~j~0 1)) (and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3))) [2019-10-07 13:44:59,243 INFO L193 IcfgInterpreter]: Reachable states at location L15-5 satisfy 282#(or (and (<= 0 linear_search_~j~0) (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3)) (and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3))) [2019-10-07 13:44:59,244 INFO L193 IcfgInterpreter]: Reachable states at location linear_searchEXIT satisfy 291#(and (<= 3 |linear_search_#in~q|) (<= |linear_search_#res| 1) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3) (<= 0 |linear_search_#res|)) [2019-10-07 13:44:59,244 INFO L193 IcfgInterpreter]: Reachable states at location L28-2 satisfy 154#(or (and (<= |main_#t~ret5| 2147483647) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (<= 0 (+ |main_#t~ret5| 2147483648)) (= 1 |main_#t~ret5|)) (and (<= |main_#t~ret5| 2147483647) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (<= 0 (+ |main_#t~ret5| 2147483648)) (= 0 |main_#t~ret5|))) [2019-10-07 13:44:59,245 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (<= ~MAX~0 100000) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= ~SIZE~0 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |#valid| 0)) (<= 0 ~SIZE~0) (= |#NULL.offset| 0) (<= ~SIZE~0 0) (<= 100000 ~MAX~0)) [2019-10-07 13:44:59,246 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (<= 0 |old(~SIZE~0)|) (= |#valid| |old(#valid)|) (<= |old(~SIZE~0)| 0) (<= 0 ~SIZE~0) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= ~SIZE~0 0) (= |old(~SIZE~0)| ~SIZE~0) (<= 100000 ~MAX~0)) [2019-10-07 13:44:59,246 INFO L193 IcfgInterpreter]: Reachable states at location L28-1 satisfy 135#(or (and (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (= 1 |main_#t~ret5|)) (and (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (= 0 |main_#t~ret5|))) [2019-10-07 13:44:59,247 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 310#(and (<= ~MAX~0 100000) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= ~SIZE~0 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| 0 0)) (<= 0 ~SIZE~0) (= |#NULL.offset| 0) (<= ~SIZE~0 0) (<= 100000 ~MAX~0)) [2019-10-07 13:44:59,248 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 13:44:59,253 INFO L193 IcfgInterpreter]: Reachable states at location L28 satisfy 43#(exists ((v_prenex_14 Int) (v_prenex_13 Int) (|v_main_#t~nondet3_5| Int)) (or (and (= ~SIZE~0 (+ (div (mod v_prenex_13 4294967296) 2) 1)) (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (< (mod v_prenex_13 4294967296) 0)) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_5| 4294967296) 2) 2)) (not (= (mod |v_main_#t~nondet3_5| 2) 0)) (not (= |main_#t~malloc4.base| 0)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (< (mod |v_main_#t~nondet3_5| 4294967296) 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_5| 4294967296) 2) 2)) (not (= (mod |v_main_#t~nondet3_5| 2) 0)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (< (mod |v_main_#t~nondet3_5| 4294967296) 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_5| 4294967296) 2) 2)) (not (= (mod |v_main_#t~nondet3_5| 2) 0)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (< (mod |v_main_#t~nondet3_5| 4294967296) 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_5| 4294967296) 2) 2)) (not (= (mod |v_main_#t~nondet3_5| 2) 0)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (< (mod |v_main_#t~nondet3_5| 4294967296) 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= (mod v_prenex_14 2) 0) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_14 4294967296) 2) 1)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (= ~SIZE~0 (+ (div (mod v_prenex_13 4294967296) 2) 1)) (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (< (mod v_prenex_13 4294967296) 0)) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_5| 4294967296) 2) 2)) (not (= (mod |v_main_#t~nondet3_5| 2) 0)) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (< (mod |v_main_#t~nondet3_5| 4294967296) 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= (mod v_prenex_14 2) 0) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_14 4294967296) 2) 1)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= (mod v_prenex_14 2) 0) (not (= |main_#t~malloc4.base| 0)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_14 4294967296) 2) 1)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= (mod v_prenex_14 2) 0) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_14 4294967296) 2) 1)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= (mod v_prenex_14 2) 0) (not (= |main_#t~malloc4.base| 0)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_14 4294967296) 2) 1)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (= ~SIZE~0 (+ (div (mod v_prenex_13 4294967296) 2) 1)) (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (< (mod v_prenex_13 4294967296) 0)) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (= ~SIZE~0 (+ (div (mod v_prenex_13 4294967296) 2) 1)) (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (< (mod v_prenex_13 4294967296) 0)) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (= ~SIZE~0 (+ (div (mod v_prenex_13 4294967296) 2) 1)) (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (< (mod v_prenex_13 4294967296) 0)) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_5| 4294967296) 2) 2)) (not (= (mod |v_main_#t~nondet3_5| 2) 0)) (not (= |main_#t~malloc4.base| 0)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (< (mod |v_main_#t~nondet3_5| 4294967296) 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= (mod v_prenex_14 2) 0) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_14 4294967296) 2) 1)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (= ~SIZE~0 (+ (div (mod v_prenex_13 4294967296) 2) 1)) (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (< (mod v_prenex_13 4294967296) 0)) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)))) [2019-10-07 13:44:59,254 INFO L193 IcfgInterpreter]: Reachable states at location L6 satisfy 172#(and (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond))) (<= __VERIFIER_assert_~cond 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) [2019-10-07 13:44:59,254 INFO L193 IcfgInterpreter]: Reachable states at location L5 satisfy 167#(and (or (and (<= __VERIFIER_assert_~cond 0) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) (and (<= 1 __VERIFIER_assert_~cond) (<= 1 |__VERIFIER_assert_#in~cond|) (<= __VERIFIER_assert_~cond 1))) (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)))) [2019-10-07 13:44:59,255 INFO L193 IcfgInterpreter]: Reachable states at location __VERIFIER_assertENTRY satisfy 162#(and (or (<= 1 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0)) (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1)) (and (= |__VERIFIER_assert_#in~cond| 0) (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1)))) [2019-10-07 13:45:01,586 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 13:45:01,586 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 15, 12, 13] total 45 [2019-10-07 13:45:01,589 INFO L442 AbstractCegarLoop]: Interpolant automaton has 45 states [2019-10-07 13:45:01,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2019-10-07 13:45:01,590 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=1820, Unknown=0, NotChecked=0, Total=1980 [2019-10-07 13:45:01,590 INFO L87 Difference]: Start difference. First operand 22 states and 22 transitions. Second operand 45 states. [2019-10-07 13:45:03,850 WARN L191 SmtUtils]: Spent 593.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 58 [2019-10-07 13:45:05,705 WARN L191 SmtUtils]: Spent 1.70 s on a formula simplification. DAG size of input: 90 DAG size of output: 70 [2019-10-07 13:45:06,059 WARN L191 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 61 [2019-10-07 13:45:06,517 WARN L191 SmtUtils]: Spent 304.00 ms on a formula simplification. DAG size of input: 115 DAG size of output: 77 [2019-10-07 13:45:06,929 WARN L191 SmtUtils]: Spent 261.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 77 [2019-10-07 13:45:07,269 WARN L191 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 52 [2019-10-07 13:45:07,739 WARN L191 SmtUtils]: Spent 298.00 ms on a formula simplification. DAG size of input: 109 DAG size of output: 87 [2019-10-07 13:45:08,416 WARN L191 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 55 [2019-10-07 13:45:10,695 WARN L191 SmtUtils]: Spent 1.08 s on a formula simplification. DAG size of input: 47 DAG size of output: 43 [2019-10-07 13:45:11,515 WARN L191 SmtUtils]: Spent 669.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 45 [2019-10-07 13:45:12,120 WARN L191 SmtUtils]: Spent 531.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 45 [2019-10-07 13:45:12,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 13:45:12,484 INFO L93 Difference]: Finished difference Result 32 states and 32 transitions. [2019-10-07 13:45:12,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-10-07 13:45:12,484 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 21 [2019-10-07 13:45:12,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 13:45:12,485 INFO L225 Difference]: With dead ends: 32 [2019-10-07 13:45:12,485 INFO L226 Difference]: Without dead ends: 24 [2019-10-07 13:45:12,487 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 28 SyntacticMatches, 3 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 905 ImplicationChecksByTransitivity, 22.1s TimeCoverageRelationStatistics Valid=380, Invalid=3402, Unknown=0, NotChecked=0, Total=3782 [2019-10-07 13:45:12,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2019-10-07 13:45:12,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2019-10-07 13:45:12,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2019-10-07 13:45:12,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2019-10-07 13:45:12,496 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 21 [2019-10-07 13:45:12,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 13:45:12,497 INFO L462 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2019-10-07 13:45:12,497 INFO L463 AbstractCegarLoop]: Interpolant automaton has 45 states. [2019-10-07 13:45:12,497 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2019-10-07 13:45:12,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2019-10-07 13:45:12,498 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 13:45:12,498 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 13:45:12,707 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 13:45:12,708 INFO L410 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 13:45:12,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 13:45:12,709 INFO L82 PathProgramCache]: Analyzing trace with hash 2081709286, now seen corresponding path program 3 times [2019-10-07 13:45:12,709 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 13:45:12,709 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:45:12,709 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:45:12,710 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:45:12,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 13:45:12,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 13:45:19,503 WARN L191 SmtUtils]: Spent 6.46 s on a formula simplification. DAG size of input: 302 DAG size of output: 39 [2019-10-07 13:45:19,665 WARN L191 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 30 [2019-10-07 13:45:19,891 WARN L191 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 102 DAG size of output: 54 [2019-10-07 13:45:20,056 WARN L191 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 49 [2019-10-07 13:45:20,273 WARN L191 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 54 [2019-10-07 13:45:20,480 WARN L191 SmtUtils]: Spent 178.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 57 [2019-10-07 13:45:20,624 WARN L191 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 42 [2019-10-07 13:45:20,980 WARN L191 SmtUtils]: Spent 280.00 ms on a formula simplification. DAG size of input: 188 DAG size of output: 46 [2019-10-07 13:45:21,037 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:45:21,037 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:45:21,037 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 13:45:21,037 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 13:45:21,183 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 13:45:21,183 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 13:45:21,185 INFO L256 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 43 conjunts are in the unsatisfiable core [2019-10-07 13:45:21,187 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 13:45:27,173 WARN L191 SmtUtils]: Spent 2.01 s on a formula simplification. DAG size of input: 29 DAG size of output: 13 [2019-10-07 13:45:27,182 WARN L225 Elim1Store]: Array PQE input equivalent to false [2019-10-07 13:45:28,732 WARN L191 SmtUtils]: Spent 1.22 s on a formula simplification. DAG size of input: 62 DAG size of output: 52 [2019-10-07 13:45:29,318 WARN L191 SmtUtils]: Spent 536.00 ms on a formula simplification that was a NOOP. DAG size: 43 [2019-10-07 13:45:31,262 WARN L191 SmtUtils]: Spent 1.84 s on a formula simplification. DAG size of input: 66 DAG size of output: 56 [2019-10-07 13:45:31,838 WARN L191 SmtUtils]: Spent 508.00 ms on a formula simplification that was a NOOP. DAG size: 46 [2019-10-07 13:45:34,729 WARN L191 SmtUtils]: Spent 2.80 s on a formula simplification. DAG size of input: 68 DAG size of output: 56 [2019-10-07 13:45:36,241 WARN L191 SmtUtils]: Spent 1.29 s on a formula simplification. DAG size of input: 72 DAG size of output: 52 [2019-10-07 13:45:38,507 WARN L191 SmtUtils]: Spent 2.17 s on a formula simplification. DAG size of input: 61 DAG size of output: 42 [2019-10-07 13:45:40,197 WARN L191 SmtUtils]: Spent 1.59 s on a formula simplification. DAG size of input: 48 DAG size of output: 48 [2019-10-07 13:45:40,353 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:45:40,353 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 13:45:43,596 WARN L191 SmtUtils]: Spent 3.10 s on a formula simplification. DAG size of input: 175 DAG size of output: 108 [2019-10-07 13:45:43,722 WARN L191 SmtUtils]: Spent 124.00 ms on a formula simplification that was a NOOP. DAG size: 88 [2019-10-07 13:45:44,009 WARN L191 SmtUtils]: Spent 284.00 ms on a formula simplification. DAG size of input: 96 DAG size of output: 93 [2019-10-07 13:45:44,130 WARN L191 SmtUtils]: Spent 119.00 ms on a formula simplification that was a NOOP. DAG size: 87 [2019-10-07 13:45:44,775 WARN L191 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 61 [2019-10-07 13:45:45,562 WARN L191 SmtUtils]: Spent 307.00 ms on a formula simplification that was a NOOP. DAG size: 94 [2019-10-07 13:45:50,381 WARN L191 SmtUtils]: Spent 4.11 s on a formula simplification. DAG size of input: 106 DAG size of output: 103 [2019-10-07 13:45:51,544 WARN L191 SmtUtils]: Spent 882.00 ms on a formula simplification. DAG size of input: 121 DAG size of output: 107 [2019-10-07 13:47:09,681 WARN L191 SmtUtils]: Spent 1.21 m on a formula simplification. DAG size of input: 249 DAG size of output: 121 [2019-10-07 13:47:09,697 WARN L225 Elim1Store]: Array PQE input equivalent to true [2019-10-07 13:47:09,701 WARN L225 Elim1Store]: Array PQE input equivalent to true [2019-10-07 13:47:11,725 WARN L191 SmtUtils]: Spent 2.02 s on a formula simplification. DAG size of input: 65 DAG size of output: 1 [2019-10-07 13:47:11,735 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:47:11,736 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 13:47:11,737 INFO L162 IcfgInterpreter]: Started Sifa with 18 locations of interest [2019-10-07 13:47:11,737 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 13:47:11,738 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 13:47:11,738 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 13:47:11,738 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 13:47:11,786 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 30 for LOIs [2019-10-07 13:47:11,888 INFO L199 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 14 for LOIs [2019-10-07 13:47:11,905 INFO L199 IcfgInterpreter]: Interpreting procedure linear_search with input of size 18 for LOIs [2019-10-07 13:47:12,000 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 16 for LOIs [2019-10-07 13:47:12,004 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 13:47:12,004 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 13:47:12,006 INFO L193 IcfgInterpreter]: Reachable states at location __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 177#(and (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond))) (<= __VERIFIER_assert_~cond 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) [2019-10-07 13:47:12,006 INFO L193 IcfgInterpreter]: Reachable states at location L17-2 satisfy 301#(and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3)) [2019-10-07 13:47:12,006 INFO L193 IcfgInterpreter]: Reachable states at location linear_searchENTRY satisfy 181#(and (or (and (= (+ (mod ~SIZE~0 4294967296) (- 4294967296)) |linear_search_#in~n|) (= 3 |linear_search_#in~q|) (not (<= (mod ~SIZE~0 4294967296) 2147483647))) (and (= (mod ~SIZE~0 4294967296) |linear_search_#in~n|) (= 3 |linear_search_#in~q|) (<= (mod ~SIZE~0 4294967296) 2147483647))) (<= 3 |linear_search_#in~q|) (<= |linear_search_#in~q| 3)) [2019-10-07 13:47:12,007 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 305#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= ~MAX~0 |old(~MAX~0)|) (= |#NULL.offset| |old(#NULL.offset)|) (= |old(~SIZE~0)| ~SIZE~0)) [2019-10-07 13:47:12,007 INFO L193 IcfgInterpreter]: Reachable states at location L25 satisfy 38#(exists ((v_prenex_29 Int) (|v_main_#t~nondet3_7| Int)) (or (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_7| 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= |#valid| |old(#valid)|) (not (< (mod |v_main_#t~nondet3_7| 4294967296) 0)) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= (mod |v_main_#t~nondet3_7| 2) 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_7| 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= |#valid| |old(#valid)|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~SIZE~0 (+ (div (mod v_prenex_29 4294967296) 2) 2)) (= ~MAX~0 100000) (< (mod v_prenex_29 4294967296) 0) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= |#valid| |old(#valid)|) (not (= (mod v_prenex_29 2) 0)) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)))) [2019-10-07 13:47:12,007 INFO L193 IcfgInterpreter]: Reachable states at location L15-3 satisfy 277#(and (<= 0 (+ linear_search_~j~0 1)) (and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3))) [2019-10-07 13:47:12,008 INFO L193 IcfgInterpreter]: Reachable states at location L15-5 satisfy 282#(or (and (<= 0 linear_search_~j~0) (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3)) (and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3))) [2019-10-07 13:47:12,011 INFO L193 IcfgInterpreter]: Reachable states at location linear_searchEXIT satisfy 291#(and (<= 3 |linear_search_#in~q|) (<= |linear_search_#res| 1) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3) (<= 0 |linear_search_#res|)) [2019-10-07 13:47:12,012 INFO L193 IcfgInterpreter]: Reachable states at location L28-2 satisfy 154#(or (and (<= |main_#t~ret5| 2147483647) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (<= 0 (+ |main_#t~ret5| 2147483648)) (= 1 |main_#t~ret5|)) (and (<= |main_#t~ret5| 2147483647) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (<= 0 (+ |main_#t~ret5| 2147483648)) (= 0 |main_#t~ret5|))) [2019-10-07 13:47:12,012 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (<= ~MAX~0 100000) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= ~SIZE~0 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |#valid| 0)) (<= 0 ~SIZE~0) (= |#NULL.offset| 0) (<= ~SIZE~0 0) (<= 100000 ~MAX~0)) [2019-10-07 13:47:12,012 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= |#valid| |old(#valid)|) (<= |old(~SIZE~0)| 0) (<= 0 ~SIZE~0) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= ~SIZE~0 0) (= |old(~SIZE~0)| ~SIZE~0) (<= 100000 ~MAX~0)) [2019-10-07 13:47:12,013 INFO L193 IcfgInterpreter]: Reachable states at location L28-1 satisfy 135#(and (or (= 0 |main_#t~ret5|) (= 1 |main_#t~ret5|)) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1)) [2019-10-07 13:47:12,013 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 310#(and (<= ~MAX~0 100000) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= ~SIZE~0 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| 0 0)) (<= 0 ~SIZE~0) (= |#NULL.offset| 0) (<= ~SIZE~0 0) (<= 100000 ~MAX~0)) [2019-10-07 13:47:12,013 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 13:47:12,014 INFO L193 IcfgInterpreter]: Reachable states at location L28 satisfy 43#(exists ((v_prenex_29 Int) (v_prenex_30 Int) (|v_main_#t~nondet3_7| Int)) (or (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_29 4294967296) 2) 2)) (not (< (mod ~SIZE~0 4294967296) 0)) (< (mod v_prenex_29 4294967296) 0) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (= (mod v_prenex_29 2) 0)) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_29 4294967296) 2) 2)) (not (< (mod ~SIZE~0 4294967296) 0)) (< (mod v_prenex_29 4294967296) 0) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (= (mod v_prenex_29 2) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= (mod |v_main_#t~nondet3_7| 2) 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_7| 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= (mod |v_main_#t~nondet3_7| 2) 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_7| 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= (mod |v_main_#t~nondet3_7| 2) 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_7| 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= (mod |v_main_#t~nondet3_7| 2) 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_7| 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_29 4294967296) 2) 2)) (< (mod v_prenex_29 4294967296) 0) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (= (mod v_prenex_29 2) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_29 4294967296) 2) 2)) (< (mod v_prenex_29 4294967296) 0) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (= (mod v_prenex_29 2) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (= 0 |main_#t~malloc4.offset|) (<= 0 |#NULL.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (not (< (mod v_prenex_30 4294967296) 0)) (= ~SIZE~0 (+ (div (mod v_prenex_30 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_29 4294967296) 2) 2)) (< (mod v_prenex_29 4294967296) 0) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (not (= (mod v_prenex_29 2) 0)) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (= 0 |main_#t~malloc4.offset|) (<= 0 |#NULL.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod v_prenex_30 4294967296) 0)) (= ~SIZE~0 (+ (div (mod v_prenex_30 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (= 0 |main_#t~malloc4.offset|) (<= 0 |#NULL.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod v_prenex_30 4294967296) 0)) (= ~SIZE~0 (+ (div (mod v_prenex_30 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (= 0 |main_#t~malloc4.offset|) (<= 0 |#NULL.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (not (< (mod v_prenex_30 4294967296) 0)) (= ~SIZE~0 (+ (div (mod v_prenex_30 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_29 4294967296) 2) 2)) (< (mod v_prenex_29 4294967296) 0) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (not (= (mod v_prenex_29 2) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (= 0 |main_#t~malloc4.offset|) (<= 0 |#NULL.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod v_prenex_30 4294967296) 0)) (= ~SIZE~0 (+ (div (mod v_prenex_30 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= (mod |v_main_#t~nondet3_7| 2) 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_7| 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (<= |#NULL.base| 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (= (mod |v_main_#t~nondet3_7| 2) 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_7| 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (= 0 |main_#t~malloc4.offset|) (<= 0 |#NULL.offset|) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod v_prenex_30 4294967296) 0)) (= ~SIZE~0 (+ (div (mod v_prenex_30 4294967296) 2) 1)) (= 0 (select |old(#valid)| 0)) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)))) [2019-10-07 13:47:12,014 INFO L193 IcfgInterpreter]: Reachable states at location L6 satisfy 172#(and (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond))) (<= __VERIFIER_assert_~cond 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) [2019-10-07 13:47:12,014 INFO L193 IcfgInterpreter]: Reachable states at location L5 satisfy 167#(and (or (and (<= __VERIFIER_assert_~cond 0) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) (and (<= 1 __VERIFIER_assert_~cond) (<= 1 |__VERIFIER_assert_#in~cond|) (<= __VERIFIER_assert_~cond 1))) (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)))) [2019-10-07 13:47:12,015 INFO L193 IcfgInterpreter]: Reachable states at location __VERIFIER_assertENTRY satisfy 162#(and (or (<= 1 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0)) (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1)))) [2019-10-07 13:47:24,763 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 13:47:24,763 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 18, 16, 13] total 54 [2019-10-07 13:47:24,765 INFO L442 AbstractCegarLoop]: Interpolant automaton has 54 states [2019-10-07 13:47:24,766 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2019-10-07 13:47:24,767 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=191, Invalid=2665, Unknown=6, NotChecked=0, Total=2862 [2019-10-07 13:47:24,768 INFO L87 Difference]: Start difference. First operand 24 states and 24 transitions. Second operand 54 states. [2019-10-07 13:47:27,595 WARN L191 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 63 [2019-10-07 13:47:28,130 WARN L191 SmtUtils]: Spent 311.00 ms on a formula simplification. DAG size of input: 92 DAG size of output: 75 [2019-10-07 13:47:28,502 WARN L191 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 66 [2019-10-07 13:47:29,794 WARN L191 SmtUtils]: Spent 966.00 ms on a formula simplification. DAG size of input: 124 DAG size of output: 77 [2019-10-07 13:47:30,252 WARN L191 SmtUtils]: Spent 214.00 ms on a formula simplification. DAG size of input: 104 DAG size of output: 71 [2019-10-07 13:47:35,011 WARN L191 SmtUtils]: Spent 4.45 s on a formula simplification. DAG size of input: 127 DAG size of output: 93 [2019-10-07 13:47:35,756 WARN L191 SmtUtils]: Spent 537.00 ms on a formula simplification. DAG size of input: 120 DAG size of output: 84 [2019-10-07 13:47:38,350 WARN L191 SmtUtils]: Spent 383.00 ms on a formula simplification. DAG size of input: 143 DAG size of output: 95 [2019-10-07 13:47:38,797 WARN L191 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 57 [2019-10-07 13:47:39,552 WARN L191 SmtUtils]: Spent 386.00 ms on a formula simplification. DAG size of input: 183 DAG size of output: 92 [2019-10-07 13:47:43,715 WARN L191 SmtUtils]: Spent 202.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 60 [2019-10-07 13:47:52,747 WARN L191 SmtUtils]: Spent 364.00 ms on a formula simplification that was a NOOP. DAG size: 32 [2019-10-07 13:47:53,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 13:47:53,024 INFO L93 Difference]: Finished difference Result 34 states and 34 transitions. [2019-10-07 13:47:53,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-10-07 13:47:53,025 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 23 [2019-10-07 13:47:53,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 13:47:53,026 INFO L225 Difference]: With dead ends: 34 [2019-10-07 13:47:53,026 INFO L226 Difference]: Without dead ends: 26 [2019-10-07 13:47:53,028 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 24 SyntacticMatches, 7 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1196 ImplicationChecksByTransitivity, 144.0s TimeCoverageRelationStatistics Valid=441, Invalid=4953, Unknown=8, NotChecked=0, Total=5402 [2019-10-07 13:47:53,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2019-10-07 13:47:53,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2019-10-07 13:47:53,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2019-10-07 13:47:53,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 26 transitions. [2019-10-07 13:47:53,037 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 26 transitions. Word has length 23 [2019-10-07 13:47:53,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 13:47:53,038 INFO L462 AbstractCegarLoop]: Abstraction has 26 states and 26 transitions. [2019-10-07 13:47:53,038 INFO L463 AbstractCegarLoop]: Interpolant automaton has 54 states. [2019-10-07 13:47:53,038 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 26 transitions. [2019-10-07 13:47:53,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 13:47:53,039 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 13:47:53,039 INFO L385 BasicCegarLoop]: trace histogram [5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 13:47:53,242 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 13:47:53,243 INFO L410 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 13:47:53,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 13:47:53,244 INFO L82 PathProgramCache]: Analyzing trace with hash 745842564, now seen corresponding path program 4 times [2019-10-07 13:47:53,244 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 13:47:53,244 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:47:53,244 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:47:53,245 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:47:53,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 13:47:53,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 13:47:53,668 WARN L191 SmtUtils]: Spent 188.00 ms on a formula simplification. DAG size of input: 168 DAG size of output: 28 [2019-10-07 13:47:54,179 WARN L191 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 104 DAG size of output: 53 [2019-10-07 13:47:54,353 WARN L191 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 88 DAG size of output: 48 [2019-10-07 13:47:54,557 WARN L191 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 65 [2019-10-07 13:47:54,780 WARN L191 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 58 [2019-10-07 13:47:54,989 WARN L191 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 55 [2019-10-07 13:47:55,390 WARN L191 SmtUtils]: Spent 267.00 ms on a formula simplification. DAG size of input: 164 DAG size of output: 64 [2019-10-07 13:47:55,484 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:47:55,484 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:47:55,484 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 13:47:55,484 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 13:47:55,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 13:47:55,719 WARN L254 TraceCheckSpWp]: Trace formula consists of 112 conjuncts, 56 conjunts are in the unsatisfiable core [2019-10-07 13:47:55,724 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 13:48:01,630 WARN L191 SmtUtils]: Spent 5.79 s on a formula simplification. DAG size of input: 35 DAG size of output: 17 [2019-10-07 13:48:01,644 WARN L225 Elim1Store]: Array PQE input equivalent to false [2019-10-07 13:48:03,741 WARN L191 SmtUtils]: Spent 2.10 s on a formula simplification. DAG size of input: 61 DAG size of output: 30 [2019-10-07 13:48:05,972 WARN L191 SmtUtils]: Spent 1.88 s on a formula simplification. DAG size of input: 66 DAG size of output: 56 [2019-10-07 13:48:06,534 WARN L191 SmtUtils]: Spent 501.00 ms on a formula simplification that was a NOOP. DAG size: 47 [2019-10-07 13:48:07,042 WARN L191 SmtUtils]: Spent 374.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 60 [2019-10-07 13:48:09,237 WARN L191 SmtUtils]: Spent 1.93 s on a formula simplification. DAG size of input: 73 DAG size of output: 63 [2019-10-07 13:48:15,231 WARN L191 SmtUtils]: Spent 5.71 s on a formula simplification. DAG size of input: 70 DAG size of output: 60 [2019-10-07 13:48:18,932 WARN L191 SmtUtils]: Spent 3.49 s on a formula simplification. DAG size of input: 58 DAG size of output: 58 [2019-10-07 13:48:18,948 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:48:18,948 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 13:48:20,293 WARN L191 SmtUtils]: Spent 1.20 s on a formula simplification. DAG size of input: 193 DAG size of output: 104 [2019-10-07 13:48:20,619 WARN L191 SmtUtils]: Spent 235.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 92 [2019-10-07 13:48:20,729 WARN L191 SmtUtils]: Spent 108.00 ms on a formula simplification that was a NOOP. DAG size: 84 [2019-10-07 13:48:21,798 WARN L191 SmtUtils]: Spent 225.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 80 [2019-10-07 13:48:26,663 WARN L191 SmtUtils]: Spent 2.46 s on a formula simplification that was a NOOP. DAG size: 92 [2019-10-07 13:48:33,784 WARN L191 SmtUtils]: Spent 6.75 s on a formula simplification. DAG size of input: 109 DAG size of output: 94 [2019-10-07 13:48:45,277 WARN L191 SmtUtils]: Spent 8.60 s on a formula simplification that was a NOOP. DAG size: 106 [2019-10-07 13:49:31,315 WARN L191 SmtUtils]: Spent 43.23 s on a formula simplification. DAG size of input: 128 DAG size of output: 108 [2019-10-07 13:50:24,432 WARN L191 SmtUtils]: Spent 42.67 s on a formula simplification that was a NOOP. DAG size: 120 [2019-10-07 13:50:24,452 WARN L225 Elim1Store]: Array PQE input equivalent to true [2019-10-07 13:50:24,505 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:50:24,505 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 13:50:24,507 INFO L162 IcfgInterpreter]: Started Sifa with 18 locations of interest [2019-10-07 13:50:24,507 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 13:50:24,508 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 13:50:24,508 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 13:50:24,508 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 13:50:24,541 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 32 for LOIs [2019-10-07 13:50:24,631 INFO L199 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 14 for LOIs [2019-10-07 13:50:24,647 INFO L199 IcfgInterpreter]: Interpreting procedure linear_search with input of size 18 for LOIs [2019-10-07 13:50:24,728 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 16 for LOIs [2019-10-07 13:50:24,732 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 13:50:24,732 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 13:50:24,733 INFO L193 IcfgInterpreter]: Reachable states at location __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 177#(and (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond))) (<= __VERIFIER_assert_~cond 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) [2019-10-07 13:50:24,733 INFO L193 IcfgInterpreter]: Reachable states at location L17-2 satisfy 301#(and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3)) [2019-10-07 13:50:24,733 INFO L193 IcfgInterpreter]: Reachable states at location linear_searchENTRY satisfy 181#(and (or (and (= (+ (mod ~SIZE~0 4294967296) (- 4294967296)) |linear_search_#in~n|) (= 3 |linear_search_#in~q|) (not (<= (mod ~SIZE~0 4294967296) 2147483647))) (and (= (mod ~SIZE~0 4294967296) |linear_search_#in~n|) (= 3 |linear_search_#in~q|) (<= (mod ~SIZE~0 4294967296) 2147483647))) (<= 3 |linear_search_#in~q|) (<= |linear_search_#in~q| 3)) [2019-10-07 13:50:24,733 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 305#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= ~MAX~0 |old(~MAX~0)|) (= |#NULL.offset| |old(#NULL.offset)|) (= |old(~SIZE~0)| ~SIZE~0)) [2019-10-07 13:50:24,733 INFO L193 IcfgInterpreter]: Reachable states at location L25 satisfy 38#(exists ((v_prenex_41 Int) (|v_main_#t~nondet3_9| Int)) (or (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (= (mod |v_main_#t~nondet3_9| 2) 0)) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| |old(#valid)|) (<= |old(~SIZE~0)| 0) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_9| 4294967296) 2) 2)) (= |old(#length)| |#length|) (< (mod |v_main_#t~nondet3_9| 4294967296) 0) (<= 100000 ~MAX~0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (< (mod v_prenex_41 4294967296) 0)) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_41 4294967296) 2) 1)) (= |#valid| |old(#valid)|) (<= |old(~SIZE~0)| 0) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= (mod v_prenex_41 2) 0) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_41 4294967296) 2) 1)) (= |#valid| |old(#valid)|) (<= |old(~SIZE~0)| 0) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)))) [2019-10-07 13:50:24,734 INFO L193 IcfgInterpreter]: Reachable states at location L15-3 satisfy 277#(and (<= 0 (+ linear_search_~j~0 1)) (and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3))) [2019-10-07 13:50:24,734 INFO L193 IcfgInterpreter]: Reachable states at location L15-5 satisfy 282#(or (and (<= 0 linear_search_~j~0) (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3)) (and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3))) [2019-10-07 13:50:24,734 INFO L193 IcfgInterpreter]: Reachable states at location linear_searchEXIT satisfy 291#(and (<= 3 |linear_search_#in~q|) (<= |linear_search_#res| 1) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3) (<= 0 |linear_search_#res|)) [2019-10-07 13:50:24,734 INFO L193 IcfgInterpreter]: Reachable states at location L28-2 satisfy 154#(or (and (<= |main_#t~ret5| 2147483647) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (<= 0 (+ |main_#t~ret5| 2147483648)) (= 1 |main_#t~ret5|)) (and (<= |main_#t~ret5| 2147483647) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (<= 0 (+ |main_#t~ret5| 2147483648)) (= 0 |main_#t~ret5|))) [2019-10-07 13:50:24,734 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (<= ~MAX~0 100000) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= ~SIZE~0 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |#valid| 0)) (<= 0 ~SIZE~0) (= |#NULL.offset| 0) (<= ~SIZE~0 0) (<= 100000 ~MAX~0)) [2019-10-07 13:50:24,734 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| |old(#valid)|) (<= |old(~SIZE~0)| 0) (<= 0 ~SIZE~0) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= ~SIZE~0 0) (= |old(~SIZE~0)| ~SIZE~0) (<= 100000 ~MAX~0)) [2019-10-07 13:50:24,735 INFO L193 IcfgInterpreter]: Reachable states at location L28-1 satisfy 135#(and (or (= 0 |main_#t~ret5|) (= 1 |main_#t~ret5|)) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1)) [2019-10-07 13:50:24,735 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 310#(and (<= ~MAX~0 100000) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= ~SIZE~0 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| 0 0)) (<= 0 ~SIZE~0) (= |#NULL.offset| 0) (<= ~SIZE~0 0) (<= 100000 ~MAX~0)) [2019-10-07 13:50:24,735 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 13:50:24,736 INFO L193 IcfgInterpreter]: Reachable states at location L28 satisfy 43#(exists ((v_prenex_41 Int) (|v_main_#t~nondet3_9| Int) (v_prenex_42 Int)) (or (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (not (< (mod v_prenex_42 4294967296) 0)) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (= ~SIZE~0 (+ (div (mod v_prenex_42 4294967296) 2) 1)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (<= |old(~SIZE~0)| 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (= (mod |v_main_#t~nondet3_9| 2) 0)) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (< (mod |v_main_#t~nondet3_9| 4294967296) 0) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (<= |old(~SIZE~0)| 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_9| 4294967296) 2) 2))) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (= (mod |v_main_#t~nondet3_9| 2) 0)) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (< (mod |v_main_#t~nondet3_9| 4294967296) 0) (<= 100000 ~MAX~0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (<= |old(~SIZE~0)| 0) (= |#NULL.offset| 0) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_9| 4294967296) 2) 2))) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (not (< (mod v_prenex_42 4294967296) 0)) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod v_prenex_42 4294967296) 2) 1)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (<= |old(~SIZE~0)| 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= (mod v_prenex_41 2) 0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_41 4294967296) 2) 1)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (<= |old(~SIZE~0)| 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (not (< (mod v_prenex_42 4294967296) 0)) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod v_prenex_42 4294967296) 2) 1)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (<= |old(~SIZE~0)| 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= (mod v_prenex_41 2) 0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_41 4294967296) 2) 1)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (<= |old(~SIZE~0)| 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (= (mod |v_main_#t~nondet3_9| 2) 0)) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (< (mod |v_main_#t~nondet3_9| 4294967296) 0) (<= 100000 ~MAX~0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (<= |old(~SIZE~0)| 0) (= |#NULL.offset| 0) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_9| 4294967296) 2) 2))) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= (mod v_prenex_41 2) 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_41 4294967296) 2) 1)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (<= |old(~SIZE~0)| 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (= (mod |v_main_#t~nondet3_9| 2) 0)) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (< (mod |v_main_#t~nondet3_9| 4294967296) 0) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (<= |old(~SIZE~0)| 0) (= |#NULL.offset| 0) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_9| 4294967296) 2) 2))) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (= (mod v_prenex_41 2) 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_41 4294967296) 2) 1)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (<= |old(~SIZE~0)| 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= (mod v_prenex_41 2) 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_41 4294967296) 2) 1)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (<= |old(~SIZE~0)| 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (mod v_prenex_41 2) 0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= ~SIZE~0 (+ (div (mod v_prenex_41 4294967296) 2) 1)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (<= |old(~SIZE~0)| 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (= (mod |v_main_#t~nondet3_9| 2) 0)) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (< (mod |v_main_#t~nondet3_9| 4294967296) 0) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (<= |old(~SIZE~0)| 0) (= |#NULL.offset| 0) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_9| 4294967296) 2) 2))) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (not (< (mod v_prenex_42 4294967296) 0)) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod v_prenex_42 4294967296) 2) 1)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (<= |old(~SIZE~0)| 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (not (< (mod v_prenex_42 4294967296) 0)) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod v_prenex_42 4294967296) 2) 1)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (<= |old(~SIZE~0)| 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (not (= (mod |v_main_#t~nondet3_9| 2) 0)) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (< (mod |v_main_#t~nondet3_9| 4294967296) 0) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (<= |old(~SIZE~0)| 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_9| 4294967296) 2) 2))) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (not (< (mod v_prenex_42 4294967296) 0)) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (= ~SIZE~0 (+ (div (mod v_prenex_42 4294967296) 2) 1)) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (<= 0 |old(~SIZE~0)|) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (<= |old(~SIZE~0)| 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)))) [2019-10-07 13:50:24,736 INFO L193 IcfgInterpreter]: Reachable states at location L6 satisfy 172#(and (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond))) (<= __VERIFIER_assert_~cond 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) [2019-10-07 13:50:24,736 INFO L193 IcfgInterpreter]: Reachable states at location L5 satisfy 167#(and (or (and (<= __VERIFIER_assert_~cond 0) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) (and (<= 1 __VERIFIER_assert_~cond) (<= 1 |__VERIFIER_assert_#in~cond|) (<= __VERIFIER_assert_~cond 1))) (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)))) [2019-10-07 13:50:24,736 INFO L193 IcfgInterpreter]: Reachable states at location __VERIFIER_assertENTRY satisfy 162#(and (or (<= 1 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0)) (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1)))) [2019-10-07 13:50:36,461 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 13:50:36,462 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 19, 16, 13] total 57 [2019-10-07 13:50:36,463 INFO L442 AbstractCegarLoop]: Interpolant automaton has 57 states [2019-10-07 13:50:36,464 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2019-10-07 13:50:36,465 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=2984, Unknown=5, NotChecked=0, Total=3192 [2019-10-07 13:50:36,465 INFO L87 Difference]: Start difference. First operand 26 states and 26 transitions. Second operand 57 states. [2019-10-07 13:50:42,701 WARN L191 SmtUtils]: Spent 671.00 ms on a formula simplification. DAG size of input: 127 DAG size of output: 60 [2019-10-07 13:50:43,321 WARN L191 SmtUtils]: Spent 335.00 ms on a formula simplification. DAG size of input: 128 DAG size of output: 72 [2019-10-07 13:50:43,667 WARN L191 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 64 [2019-10-07 13:50:44,452 WARN L191 SmtUtils]: Spent 486.00 ms on a formula simplification. DAG size of input: 94 DAG size of output: 76 [2019-10-07 13:50:45,540 WARN L191 SmtUtils]: Spent 856.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 69 [2019-10-07 13:50:46,532 WARN L191 SmtUtils]: Spent 741.00 ms on a formula simplification. DAG size of input: 98 DAG size of output: 84 [2019-10-07 13:50:47,047 WARN L191 SmtUtils]: Spent 187.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 74 [2019-10-07 13:50:48,100 WARN L191 SmtUtils]: Spent 784.00 ms on a formula simplification. DAG size of input: 158 DAG size of output: 85 [2019-10-07 13:50:50,946 WARN L191 SmtUtils]: Spent 2.52 s on a formula simplification. DAG size of input: 131 DAG size of output: 104 [2019-10-07 13:50:51,529 WARN L191 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 54 [2019-10-07 13:50:52,960 WARN L191 SmtUtils]: Spent 1.17 s on a formula simplification. DAG size of input: 141 DAG size of output: 112 [2019-10-07 13:51:01,482 WARN L191 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 57 [2019-10-07 13:51:05,919 WARN L191 SmtUtils]: Spent 100.00 ms on a formula simplification that was a NOOP. DAG size: 134 [2019-10-07 13:51:13,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 13:51:13,533 INFO L93 Difference]: Finished difference Result 36 states and 36 transitions. [2019-10-07 13:51:13,533 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-10-07 13:51:13,534 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 25 [2019-10-07 13:51:13,534 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 13:51:13,535 INFO L225 Difference]: With dead ends: 36 [2019-10-07 13:51:13,535 INFO L226 Difference]: Without dead ends: 28 [2019-10-07 13:51:13,538 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 32 SyntacticMatches, 3 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1424 ImplicationChecksByTransitivity, 182.5s TimeCoverageRelationStatistics Valid=486, Invalid=5512, Unknown=8, NotChecked=0, Total=6006 [2019-10-07 13:51:13,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2019-10-07 13:51:13,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2019-10-07 13:51:13,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2019-10-07 13:51:13,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 28 transitions. [2019-10-07 13:51:13,548 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 28 transitions. Word has length 25 [2019-10-07 13:51:13,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 13:51:13,548 INFO L462 AbstractCegarLoop]: Abstraction has 28 states and 28 transitions. [2019-10-07 13:51:13,549 INFO L463 AbstractCegarLoop]: Interpolant automaton has 57 states. [2019-10-07 13:51:13,549 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 28 transitions. [2019-10-07 13:51:13,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-10-07 13:51:13,549 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 13:51:13,550 INFO L385 BasicCegarLoop]: trace histogram [6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 13:51:13,753 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 13:51:13,754 INFO L410 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 13:51:13,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 13:51:13,754 INFO L82 PathProgramCache]: Analyzing trace with hash 1173144226, now seen corresponding path program 5 times [2019-10-07 13:51:13,754 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 13:51:13,755 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:51:13,755 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:51:13,755 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:51:13,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 13:51:13,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 13:51:14,283 WARN L191 SmtUtils]: Spent 199.00 ms on a formula simplification. DAG size of input: 182 DAG size of output: 31 [2019-10-07 13:51:14,697 WARN L191 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 113 DAG size of output: 53 [2019-10-07 13:51:14,953 WARN L191 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 53 [2019-10-07 13:51:15,183 WARN L191 SmtUtils]: Spent 180.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 76 [2019-10-07 13:51:15,417 WARN L191 SmtUtils]: Spent 191.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 66 [2019-10-07 13:51:15,834 WARN L191 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 142 DAG size of output: 44 [2019-10-07 13:51:15,990 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:51:15,991 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:51:15,991 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 13:51:15,991 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 13:51:17,197 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2019-10-07 13:51:17,197 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 13:51:17,199 INFO L256 TraceCheckSpWp]: Trace formula consists of 116 conjuncts, 52 conjunts are in the unsatisfiable core [2019-10-07 13:51:17,203 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 13:51:22,199 WARN L191 SmtUtils]: Spent 832.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 14 [2019-10-07 13:51:22,212 WARN L225 Elim1Store]: Array PQE input equivalent to false [2019-10-07 13:51:26,349 WARN L191 SmtUtils]: Spent 4.14 s on a formula simplification. DAG size of input: 60 DAG size of output: 30 [2019-10-07 13:51:28,387 WARN L191 SmtUtils]: Spent 2.02 s on a formula simplification that was a NOOP. DAG size: 28 [2019-10-07 13:51:29,097 WARN L191 SmtUtils]: Spent 336.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 57 [2019-10-07 13:51:29,857 WARN L191 SmtUtils]: Spent 327.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 58 [2019-10-07 13:51:32,439 WARN L191 SmtUtils]: Spent 2.32 s on a formula simplification. DAG size of input: 67 DAG size of output: 57 [2019-10-07 13:51:33,140 WARN L191 SmtUtils]: Spent 192.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 55 [2019-10-07 13:51:33,155 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:51:33,155 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 13:51:33,999 WARN L191 SmtUtils]: Spent 670.00 ms on a formula simplification. DAG size of input: 169 DAG size of output: 93 [2019-10-07 13:51:34,288 WARN L191 SmtUtils]: Spent 204.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 85 [2019-10-07 13:51:35,524 WARN L191 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 57 [2019-10-07 13:51:35,863 WARN L191 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 65 [2019-10-07 13:51:38,423 WARN L191 SmtUtils]: Spent 435.00 ms on a formula simplification that was a NOOP. DAG size: 84 [2019-10-07 13:51:46,533 WARN L191 SmtUtils]: Spent 6.60 s on a formula simplification. DAG size of input: 99 DAG size of output: 89 [2019-10-07 13:51:51,327 WARN L191 SmtUtils]: Spent 584.00 ms on a formula simplification that was a NOOP. DAG size: 99 [2019-10-07 13:51:57,979 WARN L191 SmtUtils]: Spent 6.12 s on a formula simplification. DAG size of input: 121 DAG size of output: 115 [2019-10-07 13:52:30,505 WARN L191 SmtUtils]: Spent 26.74 s on a formula simplification. DAG size of input: 125 DAG size of output: 124 [2019-10-07 13:52:30,525 WARN L225 Elim1Store]: Array PQE input equivalent to true [2019-10-07 13:52:30,531 WARN L225 Elim1Store]: Array PQE input equivalent to true [2019-10-07 13:52:30,562 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:52:30,562 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 13:52:30,564 INFO L162 IcfgInterpreter]: Started Sifa with 18 locations of interest [2019-10-07 13:52:30,564 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 13:52:30,564 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 13:52:30,564 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 13:52:30,565 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 13:52:30,591 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 30 for LOIs [2019-10-07 13:52:30,671 INFO L199 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 16 for LOIs [2019-10-07 13:52:30,693 INFO L199 IcfgInterpreter]: Interpreting procedure linear_search with input of size 18 for LOIs [2019-10-07 13:52:30,772 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 16 for LOIs [2019-10-07 13:52:30,776 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 13:52:30,776 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 13:52:30,777 INFO L193 IcfgInterpreter]: Reachable states at location __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 177#(and (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond))) (<= __VERIFIER_assert_~cond 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) [2019-10-07 13:52:30,777 INFO L193 IcfgInterpreter]: Reachable states at location L17-2 satisfy 301#(and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3)) [2019-10-07 13:52:30,777 INFO L193 IcfgInterpreter]: Reachable states at location linear_searchENTRY satisfy 181#(and (or (and (= (+ (mod ~SIZE~0 4294967296) (- 4294967296)) |linear_search_#in~n|) (= 3 |linear_search_#in~q|) (not (<= (mod ~SIZE~0 4294967296) 2147483647))) (and (= (mod ~SIZE~0 4294967296) |linear_search_#in~n|) (= 3 |linear_search_#in~q|) (<= (mod ~SIZE~0 4294967296) 2147483647))) (<= 3 |linear_search_#in~q|) (<= |linear_search_#in~q| 3)) [2019-10-07 13:52:30,777 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 305#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= ~MAX~0 |old(~MAX~0)|) (= |#NULL.offset| |old(#NULL.offset)|) (= |old(~SIZE~0)| ~SIZE~0)) [2019-10-07 13:52:30,777 INFO L193 IcfgInterpreter]: Reachable states at location L25 satisfy 38#(exists ((|v_main_#t~nondet3_11| Int) (v_prenex_53 Int)) (or (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= ~SIZE~0 (+ (div (mod v_prenex_53 4294967296) 2) 1)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| |old(#valid)|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (not (< (mod v_prenex_53 4294967296) 0)) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_11| 4294967296) 2) 2)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| |old(#valid)|) (< (mod |v_main_#t~nondet3_11| 4294967296) 0) (= |#memory_int| |old(#memory_int)|) (not (= (mod |v_main_#t~nondet3_11| 2) 0)) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= ~SIZE~0 (+ (div (mod v_prenex_53 4294967296) 2) 1)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= (mod v_prenex_53 2) 0) (= |#valid| |old(#valid)|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 100000 ~MAX~0)))) [2019-10-07 13:52:30,778 INFO L193 IcfgInterpreter]: Reachable states at location L15-3 satisfy 277#(and (<= 0 (+ linear_search_~j~0 1)) (and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3))) [2019-10-07 13:52:30,778 INFO L193 IcfgInterpreter]: Reachable states at location L15-5 satisfy 282#(or (and (<= 0 linear_search_~j~0) (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3)) (and (<= 3 |linear_search_#in~q|) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3))) [2019-10-07 13:52:30,778 INFO L193 IcfgInterpreter]: Reachable states at location linear_searchEXIT satisfy 291#(and (<= 3 |linear_search_#in~q|) (<= |linear_search_#res| 1) (<= 3 linear_search_~q) (<= 0 (+ linear_search_~j~0 1)) (= |linear_search_#in~q| 3) (<= linear_search_~q 3) (<= |linear_search_#in~q| 3) (<= 0 |linear_search_#res|)) [2019-10-07 13:52:30,778 INFO L193 IcfgInterpreter]: Reachable states at location L28-2 satisfy 154#(or (and (<= |main_#t~ret5| 2147483647) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (<= 0 (+ |main_#t~ret5| 2147483648)) (= 1 |main_#t~ret5|)) (and (<= |main_#t~ret5| 2147483647) (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (<= 0 (+ |main_#t~ret5| 2147483648)) (= 0 |main_#t~ret5|))) [2019-10-07 13:52:30,778 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (<= ~MAX~0 100000) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= ~SIZE~0 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |#valid| 0)) (<= 0 ~SIZE~0) (= |#NULL.offset| 0) (<= ~SIZE~0 0) (<= 100000 ~MAX~0)) [2019-10-07 13:52:30,779 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (<= 0 |old(~SIZE~0)|) (= |#valid| |old(#valid)|) (<= |old(~SIZE~0)| 0) (<= 0 ~SIZE~0) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= ~SIZE~0 0) (= |old(~SIZE~0)| ~SIZE~0) (<= 100000 ~MAX~0)) [2019-10-07 13:52:30,779 INFO L193 IcfgInterpreter]: Reachable states at location L28-1 satisfy 135#(or (and (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (= 1 |main_#t~ret5|)) (and (<= 0 |main_#t~ret5|) (<= |main_#t~ret5| 1) (= 0 |main_#t~ret5|))) [2019-10-07 13:52:30,779 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 310#(and (<= ~MAX~0 100000) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= ~SIZE~0 0) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= |#valid| (store |old(#valid)| 0 0)) (<= 0 ~SIZE~0) (= |#NULL.offset| 0) (<= ~SIZE~0 0) (<= 100000 ~MAX~0)) [2019-10-07 13:52:30,779 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 13:52:30,780 INFO L193 IcfgInterpreter]: Reachable states at location L28 satisfy 43#(exists ((|v_main_#t~nondet3_11| Int) (v_prenex_54 Int) (v_prenex_53 Int)) (or (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= ~SIZE~0 (+ (div (mod v_prenex_54 4294967296) 2) 1)) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod v_prenex_54 2) 0) (= (mod ~SIZE~0 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (not (< (mod v_prenex_53 4294967296) 0)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_53 4294967296) 2) 1)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (not (< (mod v_prenex_53 4294967296) 0)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_53 4294967296) 2) 1)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (not (< (mod v_prenex_53 4294967296) 0)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_53 4294967296) 2) 1)) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= ~SIZE~0 (+ (div (mod v_prenex_54 4294967296) 2) 1)) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod v_prenex_54 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (not (< (mod v_prenex_53 4294967296) 0)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_53 4294967296) 2) 1)) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= ~SIZE~0 (+ (div (mod v_prenex_54 4294967296) 2) 1)) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod v_prenex_54 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= ~SIZE~0 (+ (div (mod v_prenex_54 4294967296) 2) 1)) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod v_prenex_54 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_11| 4294967296) 2) 2)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (< (mod |v_main_#t~nondet3_11| 4294967296) 0) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (= (mod |v_main_#t~nondet3_11| 2) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= ~SIZE~0 (+ (div (mod v_prenex_54 4294967296) 2) 1)) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod v_prenex_54 2) 0) (= (mod ~SIZE~0 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= ~SIZE~0 (+ (div (mod v_prenex_54 4294967296) 2) 1)) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod v_prenex_54 2) 0) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (not (= |main_#t~malloc4.base| 0)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (not (< (mod v_prenex_53 4294967296) 0)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_53 4294967296) 2) 1)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (< (mod ~SIZE~0 4294967296) 0) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_11| 4294967296) 2) 2)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (< (mod |v_main_#t~nondet3_11| 4294967296) 0) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (not (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296)) (- 17179869184)) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (= (mod |v_main_#t~nondet3_11| 2) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_11| 4294967296) 2) 2)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (< (mod |v_main_#t~nondet3_11| 4294967296) 0) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (= (mod |v_main_#t~nondet3_11| 2) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_11| 4294967296) 2) 2)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (< (mod |v_main_#t~nondet3_11| 4294967296) 0) (not (= |main_#t~malloc4.base| 0)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (not (= (mod |v_main_#t~nondet3_11| 2) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_11| 4294967296) 2) 2)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (< (mod |v_main_#t~nondet3_11| 4294967296) 0) (not (= |main_#t~malloc4.base| 0)) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset (- 17179869184)) 3)) |#memory_int|) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (not (< (mod ~SIZE~0 4294967296) 0)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (not (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647)) (not (= (mod |v_main_#t~nondet3_11| 2) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< 1 (mod ~SIZE~0 4294967296)) (= ~SIZE~0 (+ (div (mod |v_main_#t~nondet3_11| 4294967296) 2) 2)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (< (mod |v_main_#t~nondet3_11| 4294967296) 0) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (<= (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296) 2147483647) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ (* 4 (mod (div (mod ~SIZE~0 4294967296) 2) 4294967296)) main_~a~0.offset) 3)) |#memory_int|) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= (mod ~SIZE~0 2) 0) (not (= (mod |v_main_#t~nondet3_11| 2) 0)) (= |#NULL.offset| 0)) (and (<= ~MAX~0 100000) (= |old(~SIZE~0)| 0) (= 0 |#NULL.base|) (= 0 (select |old(#valid)| |main_#t~malloc4.base|)) (<= 0 |#NULL.base|) (= ~MAX~0 100000) (< (mod ~SIZE~0 4294967296) 0) (< 1 (mod ~SIZE~0 4294967296)) (= |#length| (store |old(#length)| |main_#t~malloc4.base| (* 4 ~SIZE~0))) (= (store |old(#memory_int)| main_~a~0.base (store (select |old(#memory_int)| main_~a~0.base) (+ main_~a~0.offset (* 4 (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296))) 3)) |#memory_int|) (<= 0 |#NULL.offset|) (= 0 |main_#t~malloc4.offset|) (<= (mod (+ (div (mod ~SIZE~0 4294967296) 2) 1) 4294967296) 2147483647) (not (= |main_#t~malloc4.base| 0)) (< (mod ~SIZE~0 4294967296) (mod ~MAX~0 4294967296)) (not (< (mod v_prenex_53 4294967296) 0)) (< |#StackHeapBarrier| |main_#t~malloc4.base|) (<= 100000 ~MAX~0) (not (= (mod ~SIZE~0 2) 0)) (= main_~a~0.offset |main_#t~malloc4.offset|) (<= |#NULL.base| 0) (= |main_#t~malloc4.base| main_~a~0.base) (= ~SIZE~0 (+ (div (mod v_prenex_53 4294967296) 2) 1)) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0)) (= |#valid| (store |old(#valid)| |main_#t~malloc4.base| 1)) (= |#NULL.offset| 0)))) [2019-10-07 13:52:30,780 INFO L193 IcfgInterpreter]: Reachable states at location L6 satisfy 172#(and (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= 0 __VERIFIER_assert_~cond) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond))) (<= __VERIFIER_assert_~cond 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) [2019-10-07 13:52:30,780 INFO L193 IcfgInterpreter]: Reachable states at location L5 satisfy 167#(and (or (and (<= __VERIFIER_assert_~cond 0) (<= |__VERIFIER_assert_#in~cond| 0) (<= 0 __VERIFIER_assert_~cond)) (and (<= 1 __VERIFIER_assert_~cond) (<= 1 |__VERIFIER_assert_#in~cond|) (<= __VERIFIER_assert_~cond 1))) (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 0) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)) (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond)))) [2019-10-07 13:52:30,781 INFO L193 IcfgInterpreter]: Reachable states at location __VERIFIER_assertENTRY satisfy 162#(and (or (<= 1 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 0)) (or (and (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (= |__VERIFIER_assert_#in~cond| 1) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1)) (and (= |__VERIFIER_assert_#in~cond| 0) (<= 0 (+ |__VERIFIER_assert_#in~cond| 2147483648)) (<= 0 |__VERIFIER_assert_#in~cond|) (<= |__VERIFIER_assert_#in~cond| 2147483647) (<= |__VERIFIER_assert_#in~cond| 1)))) [2019-10-07 13:53:03,324 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 13:53:03,325 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 16, 13] total 57 [2019-10-07 13:53:03,327 INFO L442 AbstractCegarLoop]: Interpolant automaton has 57 states [2019-10-07 13:53:03,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2019-10-07 13:53:03,328 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=2986, Unknown=16, NotChecked=0, Total=3192 [2019-10-07 13:53:03,329 INFO L87 Difference]: Start difference. First operand 28 states and 28 transitions. Second operand 57 states. [2019-10-07 13:53:22,502 WARN L191 SmtUtils]: Spent 4.12 s on a formula simplification. DAG size of input: 142 DAG size of output: 138 [2019-10-07 13:53:23,892 WARN L191 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 116 DAG size of output: 71 [2019-10-07 13:53:25,112 WARN L191 SmtUtils]: Spent 825.00 ms on a formula simplification. DAG size of input: 132 DAG size of output: 83 [2019-10-07 13:53:25,518 WARN L191 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 75 [2019-10-07 13:53:26,204 WARN L191 SmtUtils]: Spent 368.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 86 [2019-10-07 13:53:26,628 WARN L191 SmtUtils]: Spent 181.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 79 [2019-10-07 13:53:27,686 WARN L191 SmtUtils]: Spent 787.00 ms on a formula simplification. DAG size of input: 139 DAG size of output: 94 [2019-10-07 13:53:28,368 WARN L191 SmtUtils]: Spent 350.00 ms on a formula simplification. DAG size of input: 122 DAG size of output: 100 [2019-10-07 13:53:29,130 WARN L191 SmtUtils]: Spent 313.00 ms on a formula simplification. DAG size of input: 123 DAG size of output: 101 [2019-10-07 13:53:30,215 WARN L191 SmtUtils]: Spent 440.00 ms on a formula simplification. DAG size of input: 155 DAG size of output: 126 [2019-10-07 13:53:31,604 WARN L191 SmtUtils]: Spent 872.00 ms on a formula simplification. DAG size of input: 137 DAG size of output: 128 [2019-10-07 13:53:32,633 WARN L191 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 65 [2019-10-07 13:53:33,994 WARN L191 SmtUtils]: Spent 798.00 ms on a formula simplification. DAG size of input: 175 DAG size of output: 136 [2019-10-07 13:53:41,882 WARN L191 SmtUtils]: Spent 4.25 s on a formula simplification. DAG size of input: 144 DAG size of output: 140 [2019-10-07 13:53:44,270 WARN L191 SmtUtils]: Spent 2.17 s on a formula simplification. DAG size of input: 69 DAG size of output: 68 [2019-10-07 13:53:49,830 WARN L191 SmtUtils]: Spent 4.16 s on a formula simplification. DAG size of input: 146 DAG size of output: 142 [2019-10-07 13:53:55,690 WARN L191 SmtUtils]: Spent 2.08 s on a formula simplification. DAG size of input: 54 DAG size of output: 51 [2019-10-07 13:54:00,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 13:54:00,704 INFO L93 Difference]: Finished difference Result 38 states and 38 transitions. [2019-10-07 13:54:00,706 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-10-07 13:54:00,707 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 27 [2019-10-07 13:54:00,707 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 13:54:00,708 INFO L225 Difference]: With dead ends: 38 [2019-10-07 13:54:00,708 INFO L226 Difference]: Without dead ends: 30 [2019-10-07 13:54:00,710 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 39 SyntacticMatches, 5 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1318 ImplicationChecksByTransitivity, 138.1s TimeCoverageRelationStatistics Valid=494, Invalid=5968, Unknown=18, NotChecked=0, Total=6480 [2019-10-07 13:54:00,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2019-10-07 13:54:00,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 30. [2019-10-07 13:54:00,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2019-10-07 13:54:00,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 30 transitions. [2019-10-07 13:54:00,722 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 30 transitions. Word has length 27 [2019-10-07 13:54:00,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 13:54:00,723 INFO L462 AbstractCegarLoop]: Abstraction has 30 states and 30 transitions. [2019-10-07 13:54:00,723 INFO L463 AbstractCegarLoop]: Interpolant automaton has 57 states. [2019-10-07 13:54:00,723 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 30 transitions. [2019-10-07 13:54:00,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 13:54:00,724 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 13:54:00,724 INFO L385 BasicCegarLoop]: trace histogram [7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 13:54:00,927 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 13:54:00,927 INFO L410 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 13:54:00,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 13:54:00,928 INFO L82 PathProgramCache]: Analyzing trace with hash -506819008, now seen corresponding path program 6 times [2019-10-07 13:54:00,928 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 13:54:00,928 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:54:00,929 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:54:00,929 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 13:54:00,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 13:54:00,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 13:54:01,408 WARN L191 SmtUtils]: Spent 274.00 ms on a formula simplification. DAG size of input: 168 DAG size of output: 34 [2019-10-07 13:54:01,933 WARN L191 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 108 DAG size of output: 48 [2019-10-07 13:54:02,104 WARN L191 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 53 [2019-10-07 13:54:02,278 WARN L191 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 49 [2019-10-07 13:54:02,484 WARN L191 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 88 DAG size of output: 56 [2019-10-07 13:54:02,660 WARN L191 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 60 [2019-10-07 13:54:02,826 WARN L191 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 58 [2019-10-07 13:54:03,056 WARN L191 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 150 DAG size of output: 54 [2019-10-07 13:54:03,153 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:54:03,153 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 13:54:03,153 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 13:54:03,153 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 13:54:03,688 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 13:54:03,688 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 13:54:03,690 INFO L256 TraceCheckSpWp]: Trace formula consists of 120 conjuncts, 57 conjunts are in the unsatisfiable core [2019-10-07 13:54:03,695 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 13:54:17,844 WARN L225 Elim1Store]: Array PQE input equivalent to false [2019-10-07 13:54:20,161 WARN L191 SmtUtils]: Spent 1.91 s on a formula simplification. DAG size of input: 64 DAG size of output: 54 [2019-10-07 13:54:21,139 WARN L191 SmtUtils]: Spent 786.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 55 [2019-10-07 13:54:21,776 WARN L191 SmtUtils]: Spent 568.00 ms on a formula simplification that was a NOOP. DAG size: 49 [2019-10-07 13:54:24,456 WARN L191 SmtUtils]: Spent 2.55 s on a formula simplification. DAG size of input: 72 DAG size of output: 62 [2019-10-07 13:54:26,569 WARN L191 SmtUtils]: Spent 2.04 s on a formula simplification that was a NOOP. DAG size: 53 [2019-10-07 13:54:29,939 WARN L191 SmtUtils]: Spent 3.23 s on a formula simplification. DAG size of input: 75 DAG size of output: 63 [2019-10-07 13:54:30,703 WARN L191 SmtUtils]: Spent 691.00 ms on a formula simplification that was a NOOP. DAG size: 58 [2019-10-07 13:54:32,552 WARN L191 SmtUtils]: Spent 1.70 s on a formula simplification. DAG size of input: 80 DAG size of output: 68 [2019-10-07 13:54:33,332 WARN L191 SmtUtils]: Spent 655.00 ms on a formula simplification that was a NOOP. DAG size: 64 [2019-10-07 13:54:38,723 WARN L191 SmtUtils]: Spent 5.23 s on a formula simplification. DAG size of input: 87 DAG size of output: 77 [2019-10-07 13:54:41,885 WARN L191 SmtUtils]: Spent 2.81 s on a formula simplification. DAG size of input: 85 DAG size of output: 75 [2019-10-07 13:54:42,215 WARN L191 SmtUtils]: Spent 161.00 ms on a formula simplification that was a NOOP. DAG size: 82 [2019-10-07 13:54:44,159 WARN L191 SmtUtils]: Spent 1.74 s on a formula simplification. DAG size of input: 109 DAG size of output: 109 [2019-10-07 13:54:44,400 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-07 13:54:44,401 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 13:55:08,598 WARN L191 SmtUtils]: Spent 23.99 s on a formula simplification. DAG size of input: 284 DAG size of output: 161 [2019-10-07 13:55:08,797 WARN L191 SmtUtils]: Spent 196.00 ms on a formula simplification that was a NOOP. DAG size: 117 [2019-10-07 13:55:09,536 WARN L191 SmtUtils]: Spent 731.00 ms on a formula simplification. DAG size of input: 130 DAG size of output: 127 [2019-10-07 13:55:09,807 WARN L191 SmtUtils]: Spent 269.00 ms on a formula simplification that was a NOOP. DAG size: 115 [2019-10-07 13:55:12,797 WARN L191 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 83 [2019-10-07 13:55:13,152 WARN L191 SmtUtils]: Spent 174.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 89 [2019-10-07 13:55:13,603 WARN L191 SmtUtils]: Spent 147.00 ms on a formula simplification that was a NOOP. DAG size: 101 [2019-10-07 13:55:14,390 WARN L191 SmtUtils]: Spent 505.00 ms on a formula simplification. DAG size of input: 123 DAG size of output: 106 [2019-10-07 13:55:20,273 WARN L191 SmtUtils]: Spent 3.02 s on a formula simplification that was a NOOP. DAG size: 117 [2019-10-07 13:55:27,103 WARN L191 SmtUtils]: Spent 6.39 s on a formula simplification. DAG size of input: 141 DAG size of output: 139 [2019-10-07 13:55:50,755 WARN L191 SmtUtils]: Spent 17.47 s on a formula simplification that was a NOOP. DAG size: 150 [2019-10-07 13:56:04,438 WARN L191 SmtUtils]: Spent 9.85 s on a formula simplification. DAG size of input: 166 DAG size of output: 166 [2019-10-07 13:56:06,675 WARN L860 $PredicateComparison]: unable to prove that (let ((.cse2 (mod c_linear_search_~j~0 4294967296)) (.cse5 (mod c_linear_search_~n 4294967296)) (.cse3 (select |c_#memory_int| c_linear_search_~a.base)) (.cse1 (mod c_~SIZE~0 4294967296))) (or (let ((.cse0 (select |c_#memory_int| |c_linear_search_#in~a.base|))) (and (not (= (select .cse0 (+ |c_linear_search_#in~a.offset| 20)) 3)) (not (= (select .cse0 (+ |c_linear_search_#in~a.offset| 8)) 3)) (not (= (select .cse0 |c_linear_search_#in~a.offset|) 3)) (<= .cse1 6) (not (= (select .cse0 (+ |c_linear_search_#in~a.offset| 12)) 3)) (< 5 .cse1) (not (= 3 (select .cse0 (+ |c_linear_search_#in~a.offset| 4)))) (not (= (select .cse0 (+ |c_linear_search_#in~a.offset| 16)) 3)))) (let ((.cse4 (* 4 .cse2))) (and (or (< 2147483647 .cse2) (= (select .cse3 (+ c_linear_search_~a.offset .cse4)) c_linear_search_~q)) (or (<= .cse2 2147483647) (= (select .cse3 (+ c_linear_search_~a.offset .cse4 (- 17179869184))) c_linear_search_~q)))) (<= .cse5 .cse2) (not (= 3 |c_linear_search_#in~q|)) (let ((.cse7 (mod (+ c_linear_search_~j~0 1) 4294967296)) (.cse13 (= (select .cse3 (+ c_linear_search_~a.offset 4)) c_linear_search_~q)) (.cse10 (= (select .cse3 (+ c_linear_search_~a.offset (- 4))) c_linear_search_~q)) (.cse12 (= (select .cse3 c_linear_search_~a.offset) c_linear_search_~q))) (let ((.cse8 (let ((.cse35 (mod (+ c_linear_search_~j~0 2) 4294967296)) (.cse34 (mod (+ c_linear_search_~j~0 4) 4294967296)) (.cse36 (mod (+ c_linear_search_~j~0 3) 4294967296))) (let ((.cse39 (* 4 .cse36)) (.cse38 (* 4 .cse34)) (.cse37 (* 4 .cse35)) (.cse32 (= 20 .cse35))) (let ((.cse27 (<= .cse5 0)) (.cse28 (< 1 .cse1)) (.cse29 (not .cse32)) (.cse18 (= (select .cse3 (+ .cse37 c_linear_search_~a.offset (- 17179869184))) c_linear_search_~q)) (.cse21 (<= .cse35 2147483647)) (.cse23 (not (= (select .cse3 (+ c_linear_search_~a.offset .cse38 (- 17179869184))) c_linear_search_~q))) (.cse31 (< 2147483647 .cse36)) (.cse22 (= (select .cse3 (+ .cse39 c_linear_search_~a.offset (- 17179869184))) c_linear_search_~q)) (.cse30 (< .cse34 .cse5)) (.cse26 (<= .cse36 2147483647)) (.cse15 (<= .cse5 .cse36)) (.cse16 (= (select .cse3 (+ .cse39 c_linear_search_~a.offset)) c_linear_search_~q)) (.cse17 (not (= (select .cse3 (+ c_linear_search_~a.offset .cse38)) c_linear_search_~q))) (.cse19 (< .cse34 .cse1)) (.cse24 (= (select .cse3 (+ .cse37 c_linear_search_~a.offset)) c_linear_search_~q)) (.cse20 (< 2147483647 .cse34)) (.cse33 (= .cse36 20)) (.cse25 (< 2147483647 .cse35))) (and (or .cse15 .cse16 .cse17 .cse18 .cse19 .cse20 .cse21) (or .cse22 .cse23 .cse15 .cse19 .cse24 .cse25 .cse26) (or .cse10 (not .cse13) .cse27 .cse12 .cse28 .cse29) (or .cse10 .cse27 .cse12 (< 1 .cse5) .cse28 .cse29) (or .cse22 .cse15 .cse18 .cse19 .cse21 .cse30 .cse26) (or .cse15 .cse16 .cse18 .cse19 .cse21 .cse30 .cse31) (or .cse22 .cse23 .cse15 .cse18 .cse19 .cse21 .cse26) (or .cse32 .cse15 .cse16 .cse19 .cse24 .cse30 .cse31 .cse33 .cse25) (or .cse15 .cse16 .cse24 (not (= .cse34 20))) (or .cse23 .cse15 .cse16 (<= .cse34 2147483647) .cse19 .cse24 .cse31) (or .cse22 .cse15 .cse19 .cse24 .cse30 .cse25 .cse26) (or .cse32 .cse15 .cse16 .cse17 .cse19 .cse24 .cse20 .cse33 .cse25)))))) (.cse6 (* 4 .cse7)) (.cse9 (= .cse7 20))) (and (or (= (select .cse3 (+ .cse6 c_linear_search_~a.offset (- 17179869184))) c_linear_search_~q) (<= .cse7 2147483647) .cse8) (or (< 2147483647 .cse7) .cse9 .cse8 (= (select .cse3 (+ .cse6 c_linear_search_~a.offset)) c_linear_search_~q)) (or .cse10 (not .cse9) (let ((.cse11 (<= .cse5 1)) (.cse14 (< 2 .cse1))) (and (or .cse11 .cse12 .cse13 .cse14 (< 2 .cse5)) (or .cse11 .cse12 .cse13 .cse14 (not (= (select .cse3 (+ c_linear_search_~a.offset 8)) c_linear_search_~q))))))))) (and (or (not (= .cse1 (+ |c_linear_search_#in~n| 4294967296))) (<= .cse1 2147483647)) (or (not (= .cse1 |c_linear_search_#in~n|)) (< 2147483647 .cse1))))) is different from true [2019-10-07 13:57:27,121 WARN L191 SmtUtils]: Spent 1.22 m on a formula simplification. DAG size of input: 198 DAG size of output: 174