java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/array-crafted/mapavg1.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-06 22:48:37,250 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-06 22:48:37,253 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-06 22:48:37,273 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-06 22:48:37,274 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-06 22:48:37,276 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-06 22:48:37,278 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-06 22:48:37,290 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-06 22:48:37,293 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-06 22:48:37,294 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-06 22:48:37,295 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-06 22:48:37,296 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-06 22:48:37,297 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-06 22:48:37,299 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-06 22:48:37,302 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-06 22:48:37,303 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-06 22:48:37,304 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-06 22:48:37,308 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-06 22:48:37,310 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-06 22:48:37,315 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-06 22:48:37,318 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-06 22:48:37,320 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-06 22:48:37,321 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-06 22:48:37,323 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-06 22:48:37,325 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-06 22:48:37,337 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-06 22:48:37,338 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-06 22:48:37,339 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-06 22:48:37,341 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-06 22:48:37,358 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-06 22:48:37,359 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-06 22:48:37,360 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-06 22:48:37,361 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-06 22:48:37,361 INFO L138 SettingsManager]: * Use SBE=true [2019-10-06 22:48:37,361 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-06 22:48:37,361 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-06 22:48:37,362 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-06 22:48:37,362 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-06 22:48:37,362 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-06 22:48:37,363 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-06 22:48:37,363 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-06 22:48:37,363 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-06 22:48:37,364 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-06 22:48:37,364 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-06 22:48:37,364 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-06 22:48:37,364 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-06 22:48:37,364 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-06 22:48:37,365 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-06 22:48:37,365 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-06 22:48:37,365 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-06 22:48:37,365 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:37,365 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-06 22:48:37,366 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-06 22:48:37,366 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-06 22:48:37,366 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-06 22:48:37,366 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-06 22:48:37,366 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-06 22:48:37,367 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-06 22:48:37,639 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-06 22:48:37,654 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-06 22:48:37,658 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-06 22:48:37,659 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-06 22:48:37,659 INFO L275 PluginConnector]: CDTParser initialized [2019-10-06 22:48:37,660 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-crafted/mapavg1.i [2019-10-06 22:48:37,724 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4753029eb/811ef2a0d1264dc3aa32af4005f80c9e/FLAG33a130f21 [2019-10-06 22:48:38,144 INFO L306 CDTParser]: Found 1 translation units. [2019-10-06 22:48:38,146 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-crafted/mapavg1.i [2019-10-06 22:48:38,152 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4753029eb/811ef2a0d1264dc3aa32af4005f80c9e/FLAG33a130f21 [2019-10-06 22:48:38,561 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4753029eb/811ef2a0d1264dc3aa32af4005f80c9e [2019-10-06 22:48:38,570 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-06 22:48:38,572 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-06 22:48:38,573 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,573 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-06 22:48:38,577 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-06 22:48:38,577 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,580 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3ea19e4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38, skipping insertion in model container [2019-10-06 22:48:38,580 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,588 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-06 22:48:38,609 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-06 22:48:38,796 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,804 INFO L188 MainTranslator]: Completed pre-run [2019-10-06 22:48:38,825 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,837 INFO L192 MainTranslator]: Completed translation [2019-10-06 22:48:38,837 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38 WrapperNode [2019-10-06 22:48:38,837 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,838 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-06 22:48:38,838 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-06 22:48:38,838 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-06 22:48:38,927 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,928 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,936 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,936 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,944 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,950 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,951 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,953 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-06 22:48:38,954 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-06 22:48:38,954 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-06 22:48:38,954 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-06 22:48:38,955 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:39,018 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-06 22:48:39,018 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-06 22:48:39,018 INFO L138 BoogieDeclarations]: Found implementation of procedure mapavg [2019-10-06 22:48:39,019 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-06 22:48:39,019 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-06 22:48:39,019 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-06 22:48:39,019 INFO L130 BoogieDeclarations]: Found specification of procedure mapavg [2019-10-06 22:48:39,019 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-06 22:48:39,019 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-06 22:48:39,020 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-06 22:48:39,020 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-06 22:48:39,020 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-06 22:48:39,020 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-06 22:48:39,020 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-06 22:48:39,393 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-06 22:48:39,393 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-06 22:48:39,394 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39 BoogieIcfgContainer [2019-10-06 22:48:39,394 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-06 22:48:39,396 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-06 22:48:39,396 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-06 22:48:39,399 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-06 22:48:39,399 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.10 10:48:38" (1/3) ... [2019-10-06 22:48:39,400 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@126dbd96 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,400 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (2/3) ... [2019-10-06 22:48:39,401 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@126dbd96 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,401 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39" (3/3) ... [2019-10-06 22:48:39,403 INFO L109 eAbstractionObserver]: Analyzing ICFG mapavg1.i [2019-10-06 22:48:39,416 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-06 22:48:39,424 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-06 22:48:39,436 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-06 22:48:39,460 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-06 22:48:39,461 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-06 22:48:39,461 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-06 22:48:39,461 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-06 22:48:39,461 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-06 22:48:39,462 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-06 22:48:39,462 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-06 22:48:39,462 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-06 22:48:39,478 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-06 22:48:39,484 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-06 22:48:39,484 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,485 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,487 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,491 INFO L82 PathProgramCache]: Analyzing trace with hash -1953355565, now seen corresponding path program 1 times [2019-10-06 22:48:39,498 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,498 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,499 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,499 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,677 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-06 22:48:39,678 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,684 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:39,685 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:39,690 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:39,705 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:39,706 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,709 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-06 22:48:39,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:39,760 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-06 22:48:39,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:39,763 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-06 22:48:39,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:39,773 INFO L225 Difference]: With dead ends: 41 [2019-10-06 22:48:39,773 INFO L226 Difference]: Without dead ends: 20 [2019-10-06 22:48:39,780 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-06 22:48:39,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-06 22:48:39,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-06 22:48:39,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-06 22:48:39,825 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-06 22:48:39,826 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:39,826 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-06 22:48:39,826 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:39,826 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-06 22:48:39,828 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-06 22:48:39,828 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,828 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,829 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,830 INFO L82 PathProgramCache]: Analyzing trace with hash -1072677037, now seen corresponding path program 1 times [2019-10-06 22:48:39,830 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,830 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,830 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,831 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,969 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:39,970 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,970 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:39,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,048 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,055 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,088 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,089 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,143 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,144 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-06 22:48:40,144 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-06 22:48:40,146 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,146 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,146 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,146 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-06 22:48:40,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,158 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-06 22:48:40,159 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,159 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-06 22:48:40,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,160 INFO L225 Difference]: With dead ends: 33 [2019-10-06 22:48:40,160 INFO L226 Difference]: Without dead ends: 21 [2019-10-06 22:48:40,162 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-06 22:48:40,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-06 22:48:40,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-06 22:48:40,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-06 22:48:40,167 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-06 22:48:40,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,168 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-06 22:48:40,168 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,168 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-06 22:48:40,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-06 22:48:40,169 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,170 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,374 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,381 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,381 INFO L82 PathProgramCache]: Analyzing trace with hash 608739335, now seen corresponding path program 1 times [2019-10-06 22:48:40,381 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,382 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,382 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,382 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,467 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,467 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,468 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:40,469 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:40,469 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,469 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,470 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,470 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-06 22:48:40,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,487 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-06 22:48:40,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,489 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-06 22:48:40,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,490 INFO L225 Difference]: With dead ends: 31 [2019-10-06 22:48:40,490 INFO L226 Difference]: Without dead ends: 22 [2019-10-06 22:48:40,491 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-06 22:48:40,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-06 22:48:40,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-06 22:48:40,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-06 22:48:40,497 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-06 22:48:40,499 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,499 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-06 22:48:40,499 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,499 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-06 22:48:40,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-06 22:48:40,500 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,501 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,501 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,501 INFO L82 PathProgramCache]: Analyzing trace with hash -824983385, now seen corresponding path program 1 times [2019-10-06 22:48:40,502 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,502 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,502 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,503 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,622 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,623 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,623 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:40,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,705 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,711 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,753 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,754 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,791 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,791 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:40,817 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:40,817 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:40,823 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:40,830 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:40,831 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:40,956 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:00,376 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:49:00,448 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:00,452 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:00,452 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:00,452 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:49:00,453 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:49:00,453 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:00,453 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:00,453 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 22:49:00,453 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:49:00,454 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:00,454 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:00,454 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:00,454 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:49:00,454 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:00,455 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:00,455 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:49:00,455 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:49:00,455 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (<= (mod (+ (div v_prenex_1 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (< v_prenex_1 0) (not (= (mod v_prenex_1 100) 0)) (= (mod (+ (div v_prenex_1 100) 1) 4294967296) |main_#t~ret4|)) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_1 0))) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_1 100) 1) 4294967296) 2147483647)) (< v_prenex_1 0) (= (+ (mod (+ (div v_prenex_1 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_prenex_1 100) 0))) (and (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100) 4294967296)) (not (< main_~i~1 100)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_1 100) 0) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100) 4294967296) 2147483647)) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100) 4294967296) 2147483647)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_1 100) 0)) (and (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100) 4294967296)) (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_1 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100) 4294967296) 2147483647)))) (exists ((v_prenex_2 Int) (v_mapavg_~ret~0_BEFORE_RETURN_2 Int)) (or (and (<= (mod (+ (div v_prenex_2 100) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_2 100) 4294967296) 2147483647) (not (< v_prenex_2 0)) (not (< main_~i~1 100)) (= (mod (div v_prenex_2 100) 4294967296) |main_#t~ret4|)) (and (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_2 100))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (and (<= (mod (+ (div v_prenex_2 100) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_2 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod (div v_prenex_2 100) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_2 100))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 4294967296) (- 4294967296)))) (and (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 1) 4294967296) 2147483647)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_2 0))) (and (<= (mod (+ (div v_prenex_2 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (not (<= (mod (div v_prenex_2 100) 4294967296) 2147483647)) (= 0 (mod v_prenex_2 100)) (= |main_#t~ret4| (+ (mod (div v_prenex_2 100) 4294967296) (- 4294967296)))) (and (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_2 100))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 1) 4294967296) 2147483647)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (and (<= (mod (+ (div v_prenex_2 100) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_2 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod (+ (div v_prenex_2 100) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_prenex_2 100))) (< v_prenex_2 0)) (and (<= (mod (+ (div v_prenex_2 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (not (<= (mod (div v_prenex_2 100) 4294967296) 2147483647)) (= (mod (+ (div v_prenex_2 100) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_prenex_2 100))) (< v_prenex_2 0)) (and (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 1) 4294967296) 2147483647)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_2 100))) (and (<= (mod (+ (div v_prenex_2 100) 1) 4294967296) 2147483647) (not (< v_prenex_2 0)) (not (< main_~i~1 100)) (not (<= (mod (div v_prenex_2 100) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_2 100) 4294967296) (- 4294967296)))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_2 100)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100) 4294967296) (- 4294967296))))))) [2019-10-06 22:49:00,456 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:49:00,457 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:00,458 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:49:00,458 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:49:02,813 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:02,813 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 12] total 17 [2019-10-06 22:49:02,815 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-10-06 22:49:02,816 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-10-06 22:49:02,816 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=225, Unknown=1, NotChecked=0, Total=272 [2019-10-06 22:49:02,817 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 17 states. [2019-10-06 22:49:31,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:31,332 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-06 22:49:31,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-10-06 22:49:31,334 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 29 [2019-10-06 22:49:31,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:31,335 INFO L225 Difference]: With dead ends: 40 [2019-10-06 22:49:31,335 INFO L226 Difference]: Without dead ends: 25 [2019-10-06 22:49:31,336 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 14.6s TimeCoverageRelationStatistics Valid=123, Invalid=626, Unknown=7, NotChecked=0, Total=756 [2019-10-06 22:49:31,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-06 22:49:31,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-06 22:49:31,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-06 22:49:31,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-06 22:49:31,341 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-06 22:49:31,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:31,342 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-06 22:49:31,342 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-10-06 22:49:31,342 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-06 22:49:31,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-06 22:49:31,343 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:31,343 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:31,544 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:31,545 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:31,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:31,546 INFO L82 PathProgramCache]: Analyzing trace with hash 1686538791, now seen corresponding path program 2 times [2019-10-06 22:49:31,546 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:31,546 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:31,547 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:31,547 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:31,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:31,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:31,632 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:49:31,633 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:31,633 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:31,633 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:31,727 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-06 22:49:31,728 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:31,733 INFO L256 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:49:31,737 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:31,755 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:49:31,755 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:31,785 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:49:31,785 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:31,788 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:31,788 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:31,788 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:31,789 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:31,789 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:31,811 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:49,967 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:49:49,990 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:49,993 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:49,993 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:49,993 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:49:49,993 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:49:49,994 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:49,994 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:49,994 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 22:49:49,994 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:49:49,994 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:49,995 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:49,995 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:49,995 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:49:49,995 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:49,995 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:49,996 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:49:49,996 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:49:49,996 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_301 Int) (v_mapavg_~ret~0_BEFORE_RETURN_27 Int)) (or (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_27 0)) (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 100) 4294967296)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 100) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_301 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (< v_prenex_301 0) (= (+ (mod (+ (div v_prenex_301 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_prenex_301 100)))) (and (not (< main_~i~1 100)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_27 100)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 100) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 100) 4294967296) (- 4294967296)))) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_27 0)) (not (< main_~i~1 100)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 100) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 100) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (= (mod (+ (div v_prenex_301 100) 1) 4294967296) |main_#t~ret4|) (< v_prenex_301 0) (<= (mod (+ (div v_prenex_301 100) 1) 4294967296) 2147483647) (not (= 0 (mod v_prenex_301 100)))) (and (not (< main_~i~1 100)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_27 100)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 100) 4294967296)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 100) 4294967296) 2147483647)))) (exists ((v_prenex_302 Int) (v_mapavg_~ret~0_BEFORE_RETURN_28 Int)) (or (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_28 0))) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 1) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_28 0))) (and (not (<= (mod (+ (div v_prenex_302 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (div v_prenex_302 100) 4294967296)) (not (< v_prenex_302 0)) (<= (mod (div v_prenex_302 100) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_302 100) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_302 100) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (not (= (mod v_prenex_302 100) 0)) (< v_prenex_302 0) (<= (mod (div v_prenex_302 100) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_302 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (div v_prenex_302 100) 4294967296)) (= (mod v_prenex_302 100) 0) (<= (mod (div v_prenex_302 100) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (div v_prenex_302 100) 4294967296)) (= (mod v_prenex_302 100) 0) (<= (mod (+ (div v_prenex_302 100) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_302 100) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 4294967296) 2147483647)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_28 100) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_28 0) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 1) 4294967296) (- 4294967296)))) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_28 100) 0) (not (< main_~i~1 100)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 1) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 4294967296) 2147483647))) (and (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 4294967296) 2147483647)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_28 100) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_28 0)) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_28 100) 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100) 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (div v_prenex_302 100) 4294967296)) (not (< v_prenex_302 0)) (<= (mod (div v_prenex_302 100) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_302 100) 1) 4294967296) 2147483647)) (and (= (mod (+ (div v_prenex_302 100) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100)) (not (= (mod v_prenex_302 100) 0)) (< v_prenex_302 0) (<= (mod (div v_prenex_302 100) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_302 100) 1) 4294967296) 2147483647))))) [2019-10-06 22:49:49,996 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:49:49,996 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:49,997 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:49:49,997 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:49:50,284 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:50,285 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-06 22:49:50,286 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-10-06 22:49:50,286 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-10-06 22:49:50,287 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=360, Unknown=0, NotChecked=0, Total=420 [2019-10-06 22:49:50,287 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 21 states. [2019-10-06 22:50:13,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:13,164 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-06 22:50:13,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-10-06 22:50:13,165 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 32 [2019-10-06 22:50:13,166 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:13,166 INFO L225 Difference]: With dead ends: 44 [2019-10-06 22:50:13,166 INFO L226 Difference]: Without dead ends: 29 [2019-10-06 22:50:13,167 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 10.8s TimeCoverageRelationStatistics Valid=200, Invalid=1127, Unknown=5, NotChecked=0, Total=1332 [2019-10-06 22:50:13,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-06 22:50:13,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-06 22:50:13,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-06 22:50:13,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-06 22:50:13,173 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-06 22:50:13,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:13,174 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-06 22:50:13,174 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-10-06 22:50:13,174 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-06 22:50:13,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-06 22:50:13,175 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:13,175 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:13,376 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:13,377 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:13,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:13,377 INFO L82 PathProgramCache]: Analyzing trace with hash -682053593, now seen corresponding path program 3 times [2019-10-06 22:50:13,378 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:13,378 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:13,378 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:13,379 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:13,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:13,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:13,496 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:13,497 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:13,497 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:50:13,497 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:13,611 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:50:13,611 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:50:13,612 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-06 22:50:13,614 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:50:13,627 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:13,627 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:13,702 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:13,703 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:13,704 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:13,704 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:13,705 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:13,705 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:13,705 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:13,718 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:50:20,521 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:50:20,540 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:50:20,542 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:50:20,542 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:50:20,542 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:50:20,543 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:50:20,543 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:50:20,543 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:50:20,543 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 22:50:20,543 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:50:20,543 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:20,544 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:20,544 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:20,544 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:50:20,544 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:50:20,544 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:50:20,544 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:50:20,545 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:50:20,545 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_613 Int)) (or (and (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (div v_prenex_613 100) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_613 100) 4294967296) 2147483647)) (= 0 (mod v_prenex_613 100))) (and (not (< v_prenex_613 0)) (not (< main_~i~1 100)) (<= (mod (div v_prenex_613 100) 4294967296) 2147483647) (= (mod (div v_prenex_613 100) 4294967296) |main_#t~ret4|)) (and (< v_mapavg_~ret~0_BEFORE_RETURN_53 0) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 100) 1) 4294967296)) (not (< main_~i~1 100)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_53 100))) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 100) 1) 4294967296) 2147483647)) (and (not (< v_prenex_613 0)) (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (div v_prenex_613 100) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_613 100) 4294967296) 2147483647))) (and (< v_mapavg_~ret~0_BEFORE_RETURN_53 0) (not (< main_~i~1 100)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_53 100))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 100) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 100) 1) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (<= (mod (div v_prenex_613 100) 4294967296) 2147483647) (= (mod (div v_prenex_613 100) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_613 100))))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_614 Int)) (or (and (<= (mod (div v_prenex_614 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod (div v_prenex_614 100) 4294967296) |main_#t~ret4|) (not (< v_prenex_614 0))) (and (not (< main_~i~1 100)) (not (<= (mod (div v_prenex_614 100) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_614 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_prenex_614 100))) (and (<= (mod (div v_prenex_614 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod (div v_prenex_614 100) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_614 100))) (and (< v_mapavg_~ret~0_BEFORE_RETURN_54 0) (not (< main_~i~1 100)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_54 100) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_54 100))) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_54 100) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod (div v_prenex_614 100) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_614 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_614 0))) (and (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_54 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_54 0) (not (< main_~i~1 100)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_54 100) 1) 4294967296) 2147483647)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_54 100))))))) [2019-10-06 22:50:20,545 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:50:20,545 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:50:20,545 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:50:20,546 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:50:22,828 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:50:22,829 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-06 22:50:22,832 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-10-06 22:50:22,832 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-10-06 22:50:22,833 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=469, Unknown=1, NotChecked=0, Total=600 [2019-10-06 22:50:22,833 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 25 states. [2019-10-06 22:50:47,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:47,634 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-06 22:50:47,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-10-06 22:50:47,636 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 42 [2019-10-06 22:50:47,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:47,639 INFO L225 Difference]: With dead ends: 54 [2019-10-06 22:50:47,639 INFO L226 Difference]: Without dead ends: 36 [2019-10-06 22:50:47,641 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 487 ImplicationChecksByTransitivity, 12.9s TimeCoverageRelationStatistics Valid=359, Invalid=1527, Unknown=6, NotChecked=0, Total=1892 [2019-10-06 22:50:47,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-06 22:50:47,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-06 22:50:47,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-06 22:50:47,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-06 22:50:47,652 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-06 22:50:47,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:47,652 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-06 22:50:47,653 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-10-06 22:50:47,653 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-06 22:50:47,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-06 22:50:47,654 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:47,654 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:47,857 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:47,857 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:47,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:47,858 INFO L82 PathProgramCache]: Analyzing trace with hash -1538541913, now seen corresponding path program 4 times [2019-10-06 22:50:47,858 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:47,858 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:47,859 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:47,859 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:47,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:47,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:48,087 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:48,088 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:48,088 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:50:48,088 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:48,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:48,237 INFO L256 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-06 22:50:48,239 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:50:48,262 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:48,263 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:48,631 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:48,632 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:48,634 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:48,634 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:48,635 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:48,636 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:48,636 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:48,657 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:51:00,708 WARN L176 IndexEqualityManager]: solver failed to check if following not equals relation is implied: (= (select (select |v_#memory_int_141| |main_~#x~0.base|) |main_~#x~0.offset|) main_~temp~0) [2019-10-06 22:51:30,338 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:51:30,362 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:51:30,390 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:51:30,390 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:51:30,390 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:51:30,390 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:51:30,390 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:51:30,391 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:51:30,391 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 22:51:30,391 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:51:30,391 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:51:30,391 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:51:30,391 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:51:30,391 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:51:30,391 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:51:30,392 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:51:30,392 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:51:30,392 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:51:30,392 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_860 Int) (v_mapavg_~ret~0_BEFORE_RETURN_80 Int)) (or (and (<= (mod (div v_prenex_860 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (div v_prenex_860 100) 4294967296)) (= (mod v_prenex_860 100) 0) (not (<= (mod (+ (div v_prenex_860 100) 1) 4294967296) 2147483647))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 4294967296) (- 4294967296))) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_80 100) 0)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 1) 4294967296) 2147483647)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_80 100) 0)) (and (< v_mapavg_~ret~0_BEFORE_RETURN_80 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_80 100) 0)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 1) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_860 100) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_860 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (div v_prenex_860 100) 4294967296)) (not (< v_prenex_860 0))) (and (= (mod (+ (div v_prenex_860 100) 1) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_860 100) 4294967296) 2147483647) (< v_prenex_860 0) (<= (mod (+ (div v_prenex_860 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (not (= (mod v_prenex_860 100) 0))) (and (<= (mod (div v_prenex_860 100) 4294967296) 2147483647) (< v_prenex_860 0) (not (< main_~i~1 100)) (not (= (mod v_prenex_860 100) 0)) (= (+ (mod (+ (div v_prenex_860 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_860 100) 1) 4294967296) 2147483647))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 1) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_80 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 4294967296) (- 4294967296)))) (and (<= (mod (div v_prenex_860 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (div v_prenex_860 100) 4294967296)) (not (< v_prenex_860 0)) (not (<= (mod (+ (div v_prenex_860 100) 1) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_860 100) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_860 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (div v_prenex_860 100) 4294967296)) (= (mod v_prenex_860 100) 0)) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_80 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 1) 4294967296) 2147483647))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 1) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_80 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_80 100) 0)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100) 1) 4294967296) |main_#t~ret4|)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_859 Int)) (or (and (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_859 100) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_859 100) 4294967296) 2147483647) (< v_prenex_859 0) (= (mod (+ (div v_prenex_859 100) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_prenex_859 100)))) (and (not (< v_prenex_859 0)) (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_859 100) 1) 4294967296) 2147483647) (not (<= (mod (div v_prenex_859 100) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_859 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_79 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_79 100)))) (and (not (< v_prenex_859 0)) (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_859 100) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_859 100) 4294967296) 2147483647) (= (mod (div v_prenex_859 100) 4294967296) |main_#t~ret4|)) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 4294967296) |main_#t~ret4|) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_79 100)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_859 100) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_859 100) 4294967296) 2147483647) (= 0 (mod v_prenex_859 100)) (= (mod (div v_prenex_859 100) 4294967296) |main_#t~ret4|)) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_79 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 4294967296) 2147483647))) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 4294967296) |main_#t~ret4|) (not (< v_mapavg_~ret~0_BEFORE_RETURN_79 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_859 100) 1) 4294967296) 2147483647) (not (<= (mod (div v_prenex_859 100) 4294967296) 2147483647)) (< v_prenex_859 0) (= (mod (+ (div v_prenex_859 100) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_prenex_859 100)))) (and (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_859 100) 1) 4294967296) 2147483647) (not (<= (mod (div v_prenex_859 100) 4294967296) 2147483647)) (= 0 (mod v_prenex_859 100)) (= (+ (mod (div v_prenex_859 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_79 100)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_79 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_79 100))) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100) 4294967296) 2147483647)))))) [2019-10-06 22:51:30,393 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:51:30,393 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:51:30,393 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:51:30,393 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:51:30,766 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:51:30,767 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-06 22:51:30,768 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2019-10-06 22:51:30,769 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-10-06 22:51:30,769 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=431, Invalid=1051, Unknown=0, NotChecked=0, Total=1482 [2019-10-06 22:51:30,770 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 39 states. [2019-10-06 22:51:41,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:51:41,533 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-06 22:51:41,533 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-10-06 22:51:41,533 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 49 [2019-10-06 22:51:41,534 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:51:41,534 INFO L225 Difference]: With dead ends: 68 [2019-10-06 22:51:41,535 INFO L226 Difference]: Without dead ends: 50 [2019-10-06 22:51:41,540 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1245 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=1234, Invalid=3877, Unknown=1, NotChecked=0, Total=5112 [2019-10-06 22:51:41,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-06 22:51:41,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-06 22:51:41,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-06 22:51:41,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-06 22:51:41,557 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-06 22:51:41,558 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:51:41,558 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-06 22:51:41,558 INFO L463 AbstractCegarLoop]: Interpolant automaton has 39 states. [2019-10-06 22:51:41,558 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-06 22:51:41,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-06 22:51:41,559 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:51:41,559 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:51:41,771 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:41,772 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:51:41,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:51:41,773 INFO L82 PathProgramCache]: Analyzing trace with hash -511572313, now seen corresponding path program 5 times [2019-10-06 22:51:41,773 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:51:41,773 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:41,774 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:41,774 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:41,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:51:41,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:42,215 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:51:42,216 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:42,216 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:51:42,216 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:42,383 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:51:42,384 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:51:42,384 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:51:42,387 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:51:42,435 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-06 22:51:42,436 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:51:42,476 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-06 22:51:42,476 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:51:42,478 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:51:42,478 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:51:42,478 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:51:42,479 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:51:42,479 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:51:42,497 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:52:00,226 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:52:00,247 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:52:00,250 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:52:00,250 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:52:00,250 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:52:00,250 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:52:00,250 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:52:00,250 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:52:00,251 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 22:52:00,251 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:52:00,251 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:00,251 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:52:00,251 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:00,251 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:52:00,251 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:52:00,252 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:52:00,252 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:52:00,252 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:52:00,252 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1226 Int) (v_mapavg_~ret~0_BEFORE_RETURN_106 Int)) (or (and (not (< main_~i~1 100)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 4294967296) 2147483647)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 1) 4294967296) 2147483647) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 100) 0)) (and (= (+ (mod (+ (div v_prenex_1226 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_1226 100) 1) 4294967296) 2147483647)) (< v_prenex_1226 0) (not (= (mod v_prenex_1226 100) 0)) (not (<= (mod (div v_prenex_1226 100) 4294967296) 2147483647))) (and (= (+ (mod (div v_prenex_1226 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_1226 0)) (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_1226 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_1226 100) 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_1226 100) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (mod (div v_prenex_1226 100) 4294967296)) (<= (mod (div v_prenex_1226 100) 4294967296) 2147483647) (= (mod v_prenex_1226 100) 0)) (and (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_106 0)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 4294967296) 2147483647)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 1) 4294967296) 2147483647)) (and (not (< v_prenex_1226 0)) (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_1226 100) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (mod (div v_prenex_1226 100) 4294967296)) (<= (mod (div v_prenex_1226 100) 4294967296) 2147483647)) (and (= (+ (mod (div v_prenex_1226 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_1226 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_1226 100) 4294967296) 2147483647)) (= (mod v_prenex_1226 100) 0)) (and (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 100) 0)) (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_106 0) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 4294967296) 2147483647) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_106 0)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 4294967296)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 4294967296) 2147483647) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 4294967296)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 4294967296) 2147483647) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 100) 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 1) 4294967296) 2147483647)) (and (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 100) 0)) (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_106 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 4294967296) 2147483647)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100) 1) 4294967296) 2147483647)) (and (= (+ (mod (+ (div v_prenex_1226 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_1226 100) 1) 4294967296) 2147483647)) (< v_prenex_1226 0) (<= (mod (div v_prenex_1226 100) 4294967296) 2147483647) (not (= (mod v_prenex_1226 100) 0))))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_1225 Int)) (or (and (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (div v_prenex_1225 100) 4294967296) (- 4294967296))) (= 0 (mod v_prenex_1225 100)) (not (<= (mod (div v_prenex_1225 100) 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (<= (mod (div v_prenex_1225 100) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_1225 100) 4294967296)) (not (< v_prenex_1225 0))) (and (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_105 100))) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 100) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_105 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 100) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (div v_prenex_1225 100) 4294967296) (- 4294967296))) (not (< v_prenex_1225 0)) (not (<= (mod (div v_prenex_1225 100) 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (<= (mod (div v_prenex_1225 100) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_1225 100) 4294967296)) (= 0 (mod v_prenex_1225 100))) (and (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_105 100))) (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 100) 1) 4294967296)) (< v_mapavg_~ret~0_BEFORE_RETURN_105 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 100) 1) 4294967296) 2147483647))))) [2019-10-06 22:52:00,252 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:52:00,252 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:52:00,252 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:52:00,252 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:52:02,681 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:52:02,681 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-06 22:52:02,683 INFO L442 AbstractCegarLoop]: Interpolant automaton has 43 states [2019-10-06 22:52:02,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2019-10-06 22:52:02,684 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=445, Invalid=1360, Unknown=1, NotChecked=0, Total=1806 [2019-10-06 22:52:02,684 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 43 states. [2019-10-06 22:52:51,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:52:51,367 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-06 22:52:51,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2019-10-06 22:52:51,368 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 63 [2019-10-06 22:52:51,368 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:52:51,369 INFO L225 Difference]: With dead ends: 72 [2019-10-06 22:52:51,369 INFO L226 Difference]: Without dead ends: 54 [2019-10-06 22:52:51,371 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 177 SyntacticMatches, 0 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1240 ImplicationChecksByTransitivity, 30.5s TimeCoverageRelationStatistics Valid=1339, Invalid=5127, Unknown=14, NotChecked=0, Total=6480 [2019-10-06 22:52:51,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-06 22:52:51,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-06 22:52:51,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-06 22:52:51,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-06 22:52:51,379 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-06 22:52:51,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:52:51,379 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-06 22:52:51,379 INFO L463 AbstractCegarLoop]: Interpolant automaton has 43 states. [2019-10-06 22:52:51,380 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-06 22:52:51,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-06 22:52:51,381 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:52:51,381 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:52:51,581 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:52:51,582 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:52:51,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:52:51,583 INFO L82 PathProgramCache]: Analyzing trace with hash -637611949, now seen corresponding path program 6 times [2019-10-06 22:52:51,583 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:52:51,583 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:52:51,584 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:52:51,584 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:52:51,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:52:51,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:52:52,042 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:52:52,043 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:52:52,043 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:52:52,043 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:52:52,256 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:52:52,256 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:52:52,258 INFO L256 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-06 22:52:52,261 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:52:52,279 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:52:52,281 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:52:53,201 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:52:53,202 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:52:53,203 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:52:53,203 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:52:53,204 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:52:53,204 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:52:53,204 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:52:53,220 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:53:13,455 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:53:13,481 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:53:13,483 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:53:13,483 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:53:13,483 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:53:13,484 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:53:13,484 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:53:13,484 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:53:13,484 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 22:53:13,484 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:53:13,485 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:13,485 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:13,485 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:13,485 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:53:13,485 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:53:13,485 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:53:13,486 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:53:13,486 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:53:13,486 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1502 Int) (v_mapavg_~ret~0_BEFORE_RETURN_132 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod (div v_prenex_1502 100) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_1502 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_1502 0))) (and (= |main_#t~ret4| (mod (div v_prenex_1502 100) 4294967296)) (not (< main_~i~1 100)) (<= (mod (div v_prenex_1502 100) 4294967296) 2147483647) (not (< v_prenex_1502 0))) (and (= |main_#t~ret4| (mod (div v_prenex_1502 100) 4294967296)) (not (< main_~i~1 100)) (<= (mod (div v_prenex_1502 100) 4294967296) 2147483647) (= 0 (mod v_prenex_1502 100))) (and (not (< main_~i~1 100)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_132 100))) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 100) 1) 4294967296) 2147483647) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 100) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_132 0)) (and (not (< main_~i~1 100)) (not (<= (mod (div v_prenex_1502 100) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_1502 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_prenex_1502 100))) (and (not (< main_~i~1 100)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_132 100))) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 100) 1) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_132 0)))) (exists ((v_prenex_1501 Int) (v_mapavg_~ret~0_BEFORE_RETURN_131 Int)) (or (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_131 100) 0)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_mapavg_~ret~0_BEFORE_RETURN_131 0))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_131 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 4294967296))) (and (< v_mapavg_~ret~0_BEFORE_RETURN_131 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_131 100) 0)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (< v_prenex_1501 0) (= (mod (+ (div v_prenex_1501 100) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_1501 100) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1501 100) 4294967296) 2147483647) (not (= (mod v_prenex_1501 100) 0))) (and (not (< main_~i~1 100)) (not (< v_prenex_1501 0)) (<= (mod (+ (div v_prenex_1501 100) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1501 100) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_1501 100) 4294967296))) (and (not (<= (mod (div v_prenex_1501 100) 4294967296) 2147483647)) (< v_prenex_1501 0) (= (mod (+ (div v_prenex_1501 100) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_1501 100) 1) 4294967296) 2147483647) (not (= (mod v_prenex_1501 100) 0))) (and (= (+ (mod (div v_prenex_1501 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_1501 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (< v_prenex_1501 0)) (<= (mod (+ (div v_prenex_1501 100) 1) 4294967296) 2147483647)) (and (= (+ (mod (div v_prenex_1501 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_1501 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_1501 100) 1) 4294967296) 2147483647) (= (mod v_prenex_1501 100) 0)) (and (< v_mapavg_~ret~0_BEFORE_RETURN_131 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 4294967296) 2147483647) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_131 100) 0)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_1501 100) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1501 100) 4294967296) 2147483647) (= (mod v_prenex_1501 100) 0) (= |main_#t~ret4| (mod (div v_prenex_1501 100) 4294967296))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 4294967296) 2147483647) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_131 100) 0) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100) 4294967296)))))) [2019-10-06 22:53:13,486 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:53:13,487 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:53:13,487 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:53:13,487 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:53:13,940 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:53:13,940 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-06 22:53:13,941 INFO L442 AbstractCegarLoop]: Interpolant automaton has 69 states [2019-10-06 22:53:13,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2019-10-06 22:53:13,944 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1736, Invalid=2956, Unknown=0, NotChecked=0, Total=4692 [2019-10-06 22:53:13,944 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 69 states. [2019-10-06 22:53:38,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:53:38,271 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-06 22:53:38,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2019-10-06 22:53:38,271 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 67 [2019-10-06 22:53:38,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:53:38,273 INFO L225 Difference]: With dead ends: 104 [2019-10-06 22:53:38,273 INFO L226 Difference]: Without dead ends: 83 [2019-10-06 22:53:38,278 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 295 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3689 ImplicationChecksByTransitivity, 13.0s TimeCoverageRelationStatistics Valid=5089, Invalid=12199, Unknown=4, NotChecked=0, Total=17292 [2019-10-06 22:53:38,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-06 22:53:38,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-06 22:53:38,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-06 22:53:38,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-06 22:53:38,287 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-06 22:53:38,287 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:53:38,287 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-06 22:53:38,287 INFO L463 AbstractCegarLoop]: Interpolant automaton has 69 states. [2019-10-06 22:53:38,287 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-06 22:53:38,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-06 22:53:38,289 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:53:38,289 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:53:38,489 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:53:38,490 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:53:38,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:53:38,491 INFO L82 PathProgramCache]: Analyzing trace with hash -421590573, now seen corresponding path program 7 times [2019-10-06 22:53:38,491 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:53:38,491 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:53:38,492 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:53:38,492 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:53:38,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:53:38,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:53:39,911 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:39,912 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:53:39,912 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:53:39,912 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:53:40,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:53:40,193 INFO L256 TraceCheckSpWp]: Trace formula consists of 529 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-06 22:53:40,195 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:53:40,218 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:40,219 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:53:43,292 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:43,293 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:53:43,294 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:53:43,294 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:53:43,295 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:53:43,295 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:53:43,295 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:53:43,317 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:54:01,591 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:54:01,621 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:54:01,622 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:54:01,623 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:54:01,623 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:54:01,623 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:54:01,623 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:54:01,623 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:54:01,624 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 22:54:01,624 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:54:01,624 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:01,624 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:01,624 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:01,624 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:54:01,624 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:54:01,625 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:54:01,625 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:54:01,625 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:54:01,625 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_157 Int) (v_prenex_1819 Int)) (or (and (not (< main_~i~1 100)) (= (mod (div v_prenex_1819 100) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_1819 100) 4294967296) 2147483647) (not (< v_prenex_1819 0))) (and (not (< main_~i~1 100)) (= (+ (mod (div v_prenex_1819 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_1819 100) 4294967296) 2147483647)) (= 0 (mod v_prenex_1819 100))) (and (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_157 0) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 100) 1) 4294967296) 2147483647)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_157 100)))) (and (not (< main_~i~1 100)) (= (+ (mod (div v_prenex_1819 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_1819 100) 4294967296) 2147483647)) (not (< v_prenex_1819 0))) (and (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_157 0) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 100) 1) 4294967296)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 100) 1) 4294967296) 2147483647) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_157 100)))) (and (not (< main_~i~1 100)) (= (mod (div v_prenex_1819 100) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_1819 100) 4294967296) 2147483647) (= 0 (mod v_prenex_1819 100))))) (exists ((v_prenex_1820 Int) (v_mapavg_~ret~0_BEFORE_RETURN_158 Int)) (or (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_158 100))) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 1) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_158 0)) (and (<= (mod (+ (div v_prenex_1820 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (<= (mod (div v_prenex_1820 100) 4294967296) 2147483647) (= (mod (div v_prenex_1820 100) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_1820 100))) (and (not (< main_~i~1 100)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_158 100))) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 4294967296) 2147483647)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 1) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_158 0)) (and (<= (mod (+ (div v_prenex_1820 100) 1) 4294967296) 2147483647) (< v_prenex_1820 0) (not (< main_~i~1 100)) (not (= 0 (mod v_prenex_1820 100))) (<= (mod (div v_prenex_1820 100) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_prenex_1820 100) 1) 4294967296))) (and (<= (mod (+ (div v_prenex_1820 100) 1) 4294967296) 2147483647) (< v_prenex_1820 0) (not (<= (mod (div v_prenex_1820 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (= 0 (mod v_prenex_1820 100))) (= |main_#t~ret4| (mod (+ (div v_prenex_1820 100) 1) 4294967296))) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 1) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_158 0)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_prenex_1820 100) 1) 4294967296) 2147483647) (not (<= (mod (div v_prenex_1820 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (< v_prenex_1820 0)) (= (+ (mod (div v_prenex_1820 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 1) 4294967296) 2147483647)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_158 100)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 1) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_158 0)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 1) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_158 100))) (and (<= (mod (+ (div v_prenex_1820 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (<= (mod (div v_prenex_1820 100) 4294967296) 2147483647) (not (< v_prenex_1820 0)) (= (mod (div v_prenex_1820 100) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_prenex_1820 100) 1) 4294967296) 2147483647) (not (<= (mod (div v_prenex_1820 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= 0 (mod v_prenex_1820 100)) (= (+ (mod (div v_prenex_1820 100) 4294967296) (- 4294967296)) |main_#t~ret4|))))) [2019-10-06 22:54:01,625 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:54:01,625 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:54:01,626 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:54:01,626 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:54:04,287 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:54:04,288 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 113 [2019-10-06 22:54:04,289 INFO L442 AbstractCegarLoop]: Interpolant automaton has 113 states [2019-10-06 22:54:04,291 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 113 interpolants. [2019-10-06 22:54:04,294 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5278, Invalid=7377, Unknown=1, NotChecked=0, Total=12656 [2019-10-06 22:54:04,294 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 113 states. [2019-10-06 22:54:23,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:54:23,642 INFO L93 Difference]: Finished difference Result 148 states and 199 transitions. [2019-10-06 22:54:23,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 112 states. [2019-10-06 22:54:23,643 INFO L78 Accepts]: Start accepts. Automaton has 113 states. Word has length 96 [2019-10-06 22:54:23,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:54:23,645 INFO L225 Difference]: With dead ends: 148 [2019-10-06 22:54:23,645 INFO L226 Difference]: Without dead ends: 127 [2019-10-06 22:54:23,649 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 455 GetRequests, 223 SyntacticMatches, 14 SemanticMatches, 218 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9597 ImplicationChecksByTransitivity, 18.7s TimeCoverageRelationStatistics Valid=15627, Invalid=32550, Unknown=3, NotChecked=0, Total=48180 [2019-10-06 22:54:23,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2019-10-06 22:54:23,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 127. [2019-10-06 22:54:23,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127 states. [2019-10-06 22:54:23,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 131 transitions. [2019-10-06 22:54:23,664 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 131 transitions. Word has length 96 [2019-10-06 22:54:23,664 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:54:23,664 INFO L462 AbstractCegarLoop]: Abstraction has 127 states and 131 transitions. [2019-10-06 22:54:23,664 INFO L463 AbstractCegarLoop]: Interpolant automaton has 113 states. [2019-10-06 22:54:23,665 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 131 transitions. [2019-10-06 22:54:23,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-10-06 22:54:23,667 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:54:23,667 INFO L385 BasicCegarLoop]: trace histogram [100, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:54:23,871 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:54:23,872 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:54:23,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:54:23,873 INFO L82 PathProgramCache]: Analyzing trace with hash 1796270547, now seen corresponding path program 8 times [2019-10-06 22:54:23,873 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:54:23,873 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:54:23,874 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:23,874 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:23,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:54:24,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:54:24,152 INFO L134 CoverageAnalysis]: Checked inductivity of 5171 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 5161 trivial. 0 not checked. [2019-10-06 22:54:24,153 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:54:24,153 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:54:24,153 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:54:24,408 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:54:24,408 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:54:24,409 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 22:54:24,415 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:54:24,474 INFO L134 CoverageAnalysis]: Checked inductivity of 5171 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 5109 trivial. 0 not checked. [2019-10-06 22:54:24,475 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:54:24,591 INFO L134 CoverageAnalysis]: Checked inductivity of 5171 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 5109 trivial. 0 not checked. [2019-10-06 22:54:24,591 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:54:24,593 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:54:24,593 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:54:24,593 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:54:24,593 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:54:24,594 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:54:24,607 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:55:02,221 WARN L160 IndexEqualityManager]: solver failed to check if following equality is implied: (= main_~temp~0 (select (select |v_#memory_int_361| |main_~#x~0.base|) |main_~#x~0.offset|)) [2019-10-06 22:55:04,017 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:55:04,037 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:55:04,039 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:55:04,039 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:55:04,039 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:55:04,039 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:55:04,039 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:55:04,039 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:55:04,039 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 22:55:04,039 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:55:04,040 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:04,040 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:04,040 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:04,040 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:55:04,040 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:55:04,040 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:55:04,040 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:55:04,040 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:55:04,041 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2119 Int) (v_mapavg_~ret~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 100)) (= (+ (mod (div v_prenex_2119 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_2119 0)) (not (<= (mod (+ (div v_prenex_2119 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2119 100) 4294967296) 2147483647))) (and (not (= (mod v_prenex_2119 100) 0)) (not (< main_~i~1 100)) (= (+ (mod (+ (div v_prenex_2119 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_prenex_2119 0) (not (<= (mod (+ (div v_prenex_2119 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2119 100) 4294967296) 2147483647))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_183 0)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (= (mod v_prenex_2119 100) 0) (= (mod (div v_prenex_2119 100) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_2119 100) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2119 100) 4294967296) 2147483647)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 4294967296) 2147483647) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_183 100) 0)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_183 0)) (and (not (< main_~i~1 100)) (= (+ (mod (div v_prenex_2119 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_prenex_2119 100) 0) (not (<= (mod (+ (div v_prenex_2119 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2119 100) 4294967296) 2147483647))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_183 0)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (not (< v_prenex_2119 0)) (= (mod (div v_prenex_2119 100) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_2119 100) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2119 100) 4294967296) 2147483647)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_183 100) 0)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_183 0)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 4294967296) 2147483647) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_183 100) 0) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_183 100) 0) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (= (mod v_prenex_2119 100) 0)) (not (< main_~i~1 100)) (= (+ (mod (+ (div v_prenex_2119 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_prenex_2119 0) (not (<= (mod (+ (div v_prenex_2119 100) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2119 100) 4294967296) 2147483647)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_184 Int) (v_prenex_2120 Int)) (or (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_184 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_184 100) 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 1) 4294967296) 2147483647) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 4294967296))) (and (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_184 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 1) 4294967296) 2147483647) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 4294967296))) (and (not (<= (mod (+ (div v_prenex_2120 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (< v_prenex_2120 0)) (= (+ (mod (div v_prenex_2120 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2120 100) 4294967296) 2147483647))) (and (not (<= (mod (+ (div v_prenex_2120 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (mod v_prenex_2120 100) 0) (= (+ (mod (div v_prenex_2120 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2120 100) 4294967296) 2147483647))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_184 100) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_184 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 1) 4294967296) 2147483647)) (and (<= (mod (div v_prenex_2120 100) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2120 100) 1) 4294967296) 2147483647)) (< v_prenex_2120 0) (not (< main_~i~1 100)) (= (+ (mod (+ (div v_prenex_2120 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_prenex_2120 100) 0))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_184 100) 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_184 100) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_184 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 1) 4294967296) 2147483647) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_2120 100) 1) 4294967296) 2147483647)) (< v_prenex_2120 0) (not (< main_~i~1 100)) (= (+ (mod (+ (div v_prenex_2120 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_prenex_2120 100) 0)) (not (<= (mod (div v_prenex_2120 100) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_2120 100) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2120 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (mod v_prenex_2120 100) 0) (= |main_#t~ret4| (mod (div v_prenex_2120 100) 4294967296))) (and (<= (mod (div v_prenex_2120 100) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2120 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (< v_prenex_2120 0)) (= |main_#t~ret4| (mod (div v_prenex_2120 100) 4294967296)))))) [2019-10-06 22:55:04,041 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:55:04,041 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:55:04,041 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:55:04,041 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:55:04,390 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:55:04,391 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 27 [2019-10-06 22:55:04,392 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2019-10-06 22:55:04,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-10-06 22:55:04,393 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=591, Unknown=0, NotChecked=0, Total=702 [2019-10-06 22:55:04,393 INFO L87 Difference]: Start difference. First operand 127 states and 131 transitions. Second operand 27 states. [2019-10-06 22:55:27,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:55:27,148 INFO L93 Difference]: Finished difference Result 154 states and 170 transitions. [2019-10-06 22:55:27,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-10-06 22:55:27,148 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 140 [2019-10-06 22:55:27,149 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:55:27,151 INFO L225 Difference]: With dead ends: 154 [2019-10-06 22:55:27,151 INFO L226 Difference]: Without dead ends: 134 [2019-10-06 22:55:27,152 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 401 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 517 ImplicationChecksByTransitivity, 14.7s TimeCoverageRelationStatistics Valid=399, Invalid=1947, Unknown=6, NotChecked=0, Total=2352 [2019-10-06 22:55:27,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2019-10-06 22:55:27,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2019-10-06 22:55:27,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2019-10-06 22:55:27,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 138 transitions. [2019-10-06 22:55:27,166 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 138 transitions. Word has length 140 [2019-10-06 22:55:27,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:55:27,166 INFO L462 AbstractCegarLoop]: Abstraction has 134 states and 138 transitions. [2019-10-06 22:55:27,166 INFO L463 AbstractCegarLoop]: Interpolant automaton has 27 states. [2019-10-06 22:55:27,166 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 138 transitions. [2019-10-06 22:55:27,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2019-10-06 22:55:27,168 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:55:27,169 INFO L385 BasicCegarLoop]: trace histogram [100, 30, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:55:27,373 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:55:27,373 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:55:27,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:55:27,374 INFO L82 PathProgramCache]: Analyzing trace with hash 1187611431, now seen corresponding path program 9 times [2019-10-06 22:55:27,374 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:55:27,374 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:55:27,375 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:55:27,375 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:55:27,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:55:27,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:55:27,743 INFO L134 CoverageAnalysis]: Checked inductivity of 5599 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 5300 trivial. 0 not checked. [2019-10-06 22:55:27,744 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:55:27,745 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:55:27,745 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:55:28,139 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:55:28,139 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:55:28,143 INFO L256 TraceCheckSpWp]: Trace formula consists of 887 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-06 22:55:28,146 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:55:28,219 INFO L134 CoverageAnalysis]: Checked inductivity of 5599 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 5300 trivial. 0 not checked. [2019-10-06 22:55:28,219 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:55:28,448 INFO L134 CoverageAnalysis]: Checked inductivity of 5599 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 5300 trivial. 0 not checked. [2019-10-06 22:55:28,449 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:55:28,454 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:55:28,454 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:55:28,455 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:55:28,455 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:55:28,456 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:55:28,469 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:55:45,529 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:55:45,547 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:55:45,549 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:55:45,549 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:55:45,549 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:55:45,549 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:55:45,550 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:55:45,550 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:55:45,550 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 22:55:45,550 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:55:45,550 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:45,550 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:55:45,550 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:45,551 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:55:45,551 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:55:45,551 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:55:45,551 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:55:45,551 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:55:45,551 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2485 Int) (v_mapavg_~ret~0_BEFORE_RETURN_209 Int)) (or (and (= (mod v_prenex_2485 100) 0) (not (< main_~i~1 100)) (= (+ (mod (div v_prenex_2485 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2485 100) 4294967296) 2147483647))) (and (not (< v_prenex_2485 0)) (not (< main_~i~1 100)) (= (mod (div v_prenex_2485 100) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2485 100) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 100) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 100) 1) 4294967296)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_209 100) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_209 0)) (and (not (< v_prenex_2485 0)) (not (< main_~i~1 100)) (= (+ (mod (div v_prenex_2485 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2485 100) 4294967296) 2147483647))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 100) 1) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 100) 1) 4294967296) (- 4294967296))) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_209 100) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_209 0)) (and (= (mod v_prenex_2485 100) 0) (not (< main_~i~1 100)) (= (mod (div v_prenex_2485 100) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2485 100) 4294967296) 2147483647)))) (exists ((v_prenex_2486 Int) (v_mapavg_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_2486 100) 1) 4294967296) 2147483647) (= 0 (mod v_prenex_2486 100)) (= |main_#t~ret4| (mod (div v_prenex_2486 100) 4294967296)) (<= (mod (div v_prenex_2486 100) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_2486 100) 1) 4294967296) 2147483647)) (= 0 (mod v_prenex_2486 100)) (= |main_#t~ret4| (mod (div v_prenex_2486 100) 4294967296)) (<= (mod (div v_prenex_2486 100) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_2486 100) 1) 4294967296) 2147483647)) (not (< v_prenex_2486 0)) (= |main_#t~ret4| (mod (div v_prenex_2486 100) 4294967296)) (<= (mod (div v_prenex_2486 100) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_2486 100) 1) 4294967296) 2147483647) (not (< v_prenex_2486 0)) (= |main_#t~ret4| (mod (div v_prenex_2486 100) 4294967296)) (<= (mod (div v_prenex_2486 100) 4294967296) 2147483647)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_210 0) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_210 100))) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 1) 4294967296) 2147483647) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 1) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_210 100)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 1) 4294967296) 2147483647) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (= 0 (mod v_prenex_2486 100))) (not (< main_~i~1 100)) (<= (mod (+ (div v_prenex_2486 100) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_2486 100) 1) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2486 100) 4294967296) 2147483647) (< v_prenex_2486 0)) (and (not (= 0 (mod v_prenex_2486 100))) (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_2486 100) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2486 100) 1) 4294967296) (- 4294967296))) (<= (mod (div v_prenex_2486 100) 4294967296) 2147483647) (< v_prenex_2486 0)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_210 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 1) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_210 0) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_210 100))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 1) 4294967296) (- 4294967296)))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_210 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 1) 4294967296) 2147483647) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_210 100)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 1) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100) 4294967296) (- 4294967296)) |main_#t~ret4|))))) [2019-10-06 22:55:45,551 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:55:45,551 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:55:45,552 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:55:45,552 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:55:47,841 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:55:47,841 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 11] total 35 [2019-10-06 22:55:47,842 INFO L442 AbstractCegarLoop]: Interpolant automaton has 35 states [2019-10-06 22:55:47,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2019-10-06 22:55:47,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=326, Invalid=863, Unknown=1, NotChecked=0, Total=1190 [2019-10-06 22:55:47,843 INFO L87 Difference]: Start difference. First operand 134 states and 138 transitions. Second operand 35 states. [2019-10-06 22:56:13,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:56:13,445 INFO L93 Difference]: Finished difference Result 173 states and 194 transitions. [2019-10-06 22:56:13,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-10-06 22:56:13,446 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 159 [2019-10-06 22:56:13,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:56:13,447 INFO L225 Difference]: With dead ends: 173 [2019-10-06 22:56:13,447 INFO L226 Difference]: Without dead ends: 146 [2019-10-06 22:56:13,451 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 518 GetRequests, 456 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 937 ImplicationChecksByTransitivity, 15.8s TimeCoverageRelationStatistics Valid=1057, Invalid=2968, Unknown=7, NotChecked=0, Total=4032 [2019-10-06 22:56:13,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2019-10-06 22:56:13,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2019-10-06 22:56:13,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2019-10-06 22:56:13,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 150 transitions. [2019-10-06 22:56:13,480 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 150 transitions. Word has length 159 [2019-10-06 22:56:13,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:56:13,480 INFO L462 AbstractCegarLoop]: Abstraction has 146 states and 150 transitions. [2019-10-06 22:56:13,480 INFO L463 AbstractCegarLoop]: Interpolant automaton has 35 states. [2019-10-06 22:56:13,480 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 150 transitions. [2019-10-06 22:56:13,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2019-10-06 22:56:13,482 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:56:13,482 INFO L385 BasicCegarLoop]: trace histogram [100, 66, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:56:13,688 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:56:13,688 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:56:13,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:56:13,689 INFO L82 PathProgramCache]: Analyzing trace with hash -1497381337, now seen corresponding path program 10 times [2019-10-06 22:56:13,689 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:56:13,689 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:56:13,690 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:56:13,690 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:56:13,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:56:13,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:56:14,012 INFO L134 CoverageAnalysis]: Checked inductivity of 7417 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 7402 trivial. 0 not checked. [2019-10-06 22:56:14,012 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:56:14,012 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:56:14,012 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:56:14,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:56:14,412 INFO L256 TraceCheckSpWp]: Trace formula consists of 1067 conjuncts, 24 conjunts are in the unsatisfiable core [2019-10-06 22:56:14,415 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:56:14,727 INFO L134 CoverageAnalysis]: Checked inductivity of 7417 backedges. 1060 proven. 253 refuted. 0 times theorem prover too weak. 6104 trivial. 0 not checked. [2019-10-06 22:56:14,728 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:56:15,450 INFO L134 CoverageAnalysis]: Checked inductivity of 7417 backedges. 0 proven. 1313 refuted. 0 times theorem prover too weak. 6104 trivial. 0 not checked. [2019-10-06 22:56:15,450 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:56:15,451 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:56:15,451 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:56:15,452 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:56:15,452 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:56:15,452 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:56:15,481 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:56:21,654 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:56:21,673 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:56:21,676 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:56:21,676 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:56:21,676 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:56:21,676 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:56:21,676 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:56:21,677 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:56:21,677 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 22:56:21,677 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:56:21,677 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:21,677 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:21,678 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:21,678 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:56:21,678 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:56:21,678 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:56:21,678 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:56:21,678 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:56:21,679 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_2768 Int)) (or (and (not (< main_~i~1 100)) (= (mod (div v_prenex_2768 100) 4294967296) |main_#t~ret4|) (= (mod v_prenex_2768 100) 0) (<= (mod (div v_prenex_2768 100) 4294967296) 2147483647)) (and (not (<= (mod (div v_prenex_2768 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (mod v_prenex_2768 100) 0) (= (+ (mod (div v_prenex_2768 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 100) 1) 4294967296) 2147483647) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_236 100) 0)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 100) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_236 0)) (and (not (< main_~i~1 100)) (= (mod (div v_prenex_2768 100) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2768 100) 4294967296) 2147483647) (not (< v_prenex_2768 0))) (and (not (<= (mod (div v_prenex_2768 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (< v_prenex_2768 0)) (= (+ (mod (div v_prenex_2768 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_236 100) 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 100) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 100) 1) 4294967296) (- 4294967296))) (< v_mapavg_~ret~0_BEFORE_RETURN_236 0)))) (exists ((v_prenex_2767 Int) (v_mapavg_~ret~0_BEFORE_RETURN_235 Int)) (or (and (not (< main_~i~1 100)) (= (mod (div v_prenex_2767 100) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2767 100) 4294967296) 2147483647) (not (< v_prenex_2767 0))) (and (= (+ (mod (div v_prenex_2767 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (not (<= (mod (div v_prenex_2767 100) 4294967296) 2147483647)) (= 0 (mod v_prenex_2767 100))) (and (not (< main_~i~1 100)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_235 100))) (< v_mapavg_~ret~0_BEFORE_RETURN_235 0) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 100) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 100) 1) 4294967296) 2147483647)) (and (= (+ (mod (div v_prenex_2767 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (not (<= (mod (div v_prenex_2767 100) 4294967296) 2147483647)) (not (< v_prenex_2767 0))) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 100) 1) 4294967296) 2147483647)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_235 100))) (< v_mapavg_~ret~0_BEFORE_RETURN_235 0) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (= (mod (div v_prenex_2767 100) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2767 100) 4294967296) 2147483647) (= 0 (mod v_prenex_2767 100)))))) [2019-10-06 22:56:21,679 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:56:21,679 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:56:21,679 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:56:21,679 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:56:24,073 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:56:24,074 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 25, 25, 11] total 64 [2019-10-06 22:56:24,075 INFO L442 AbstractCegarLoop]: Interpolant automaton has 64 states [2019-10-06 22:56:24,076 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2019-10-06 22:56:24,076 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1180, Invalid=2851, Unknown=1, NotChecked=0, Total=4032 [2019-10-06 22:56:24,076 INFO L87 Difference]: Start difference. First operand 146 states and 150 transitions. Second operand 64 states. [2019-10-06 22:57:18,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:57:18,247 INFO L93 Difference]: Finished difference Result 210 states and 244 transitions. [2019-10-06 22:57:18,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2019-10-06 22:57:18,249 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 195 [2019-10-06 22:57:18,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:57:18,251 INFO L225 Difference]: With dead ends: 210 [2019-10-06 22:57:18,251 INFO L226 Difference]: Without dead ends: 171 [2019-10-06 22:57:18,253 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 652 GetRequests, 531 SyntacticMatches, 0 SemanticMatches, 121 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3196 ImplicationChecksByTransitivity, 41.0s TimeCoverageRelationStatistics Valid=3824, Invalid=11164, Unknown=18, NotChecked=0, Total=15006 [2019-10-06 22:57:18,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2019-10-06 22:57:18,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 171. [2019-10-06 22:57:18,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2019-10-06 22:57:18,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 175 transitions. [2019-10-06 22:57:18,269 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 175 transitions. Word has length 195 [2019-10-06 22:57:18,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:57:18,269 INFO L462 AbstractCegarLoop]: Abstraction has 171 states and 175 transitions. [2019-10-06 22:57:18,269 INFO L463 AbstractCegarLoop]: Interpolant automaton has 64 states. [2019-10-06 22:57:18,270 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 175 transitions. [2019-10-06 22:57:18,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 269 [2019-10-06 22:57:18,273 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:57:18,273 INFO L385 BasicCegarLoop]: trace histogram [138, 100, 6, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:57:18,478 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:57:18,479 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:57:18,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:57:18,480 INFO L82 PathProgramCache]: Analyzing trace with hash 1575477843, now seen corresponding path program 11 times [2019-10-06 22:57:18,480 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:57:18,480 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:57:18,480 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:57:18,481 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:57:18,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:57:18,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:57:20,004 INFO L134 CoverageAnalysis]: Checked inductivity of 14947 backedges. 2210 proven. 3291 refuted. 0 times theorem prover too weak. 9446 trivial. 0 not checked. [2019-10-06 22:57:20,004 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:57:20,004 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:57:20,004 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:57:20,476 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-10-06 22:57:20,477 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:57:20,479 INFO L256 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-06 22:57:20,483 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:57:20,673 INFO L134 CoverageAnalysis]: Checked inductivity of 14947 backedges. 4422 proven. 21 refuted. 0 times theorem prover too weak. 10504 trivial. 0 not checked. [2019-10-06 22:57:20,673 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:57:20,924 INFO L134 CoverageAnalysis]: Checked inductivity of 14947 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 14926 trivial. 0 not checked. [2019-10-06 22:57:20,925 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:57:20,926 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:57:20,926 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:57:20,926 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:57:20,927 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:57:20,927 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:57:20,943 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:57:26,988 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:57:27,007 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:57:27,010 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:57:27,010 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:57:27,010 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:57:27,011 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:57:27,011 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:57:27,011 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:57:27,011 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 22:57:27,011 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:57:27,011 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:57:27,012 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:57:27,012 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:57:27,012 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:57:27,012 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:57:27,012 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:57:27,012 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:57:27,013 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:57:27,013 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2995 Int) (v_mapavg_~ret~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod (div v_prenex_2995 100) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_2995 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_2995 0))) (and (<= (mod (div v_prenex_2995 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod (div v_prenex_2995 100) 4294967296) |main_#t~ret4|) (not (< v_prenex_2995 0))) (and (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_261 100) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_261 100))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_261 100) 1) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_261 0)) (and (not (< main_~i~1 100)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_261 100) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_261 100))) (< v_mapavg_~ret~0_BEFORE_RETURN_261 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_261 100) 1) 4294967296) 2147483647)) (and (<= (mod (div v_prenex_2995 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod (div v_prenex_2995 100) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_2995 100))) (and (not (< main_~i~1 100)) (not (<= (mod (div v_prenex_2995 100) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_2995 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_prenex_2995 100))))) (exists ((v_prenex_2996 Int) (v_mapavg_~ret~0_BEFORE_RETURN_262 Int)) (or (and (= (mod (div v_prenex_2996 100) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100)) (<= (mod (div v_prenex_2996 100) 4294967296) 2147483647) (not (< v_prenex_2996 0))) (and (not (<= (mod (div v_prenex_2996 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (< v_prenex_2996 0)) (= (+ (mod (div v_prenex_2996 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (div v_prenex_2996 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (mod v_prenex_2996 100) 0) (= (+ (mod (div v_prenex_2996 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_262 0) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_262 100) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_262 100) 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_262 100) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_262 0) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_262 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_262 100) 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_262 100) 1) 4294967296) 2147483647))) (and (= (mod (div v_prenex_2996 100) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100)) (<= (mod (div v_prenex_2996 100) 4294967296) 2147483647) (= (mod v_prenex_2996 100) 0))))) [2019-10-06 22:57:27,013 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:57:27,013 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:57:27,013 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:57:27,014 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:57:29,556 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:57:29,557 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 9, 9, 11] total 73 [2019-10-06 22:57:29,558 INFO L442 AbstractCegarLoop]: Interpolant automaton has 73 states [2019-10-06 22:57:29,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2019-10-06 22:57:29,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1321, Invalid=3934, Unknown=1, NotChecked=0, Total=5256 [2019-10-06 22:57:29,560 INFO L87 Difference]: Start difference. First operand 171 states and 175 transitions. Second operand 73 states. [2019-10-06 22:59:09,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:59:09,554 INFO L93 Difference]: Finished difference Result 244 states and 262 transitions. [2019-10-06 22:59:09,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2019-10-06 22:59:09,556 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 268 [2019-10-06 22:59:09,556 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:59:09,557 INFO L225 Difference]: With dead ends: 244 [2019-10-06 22:59:09,558 INFO L226 Difference]: Without dead ends: 180 [2019-10-06 22:59:09,562 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 921 GetRequests, 782 SyntacticMatches, 0 SemanticMatches, 139 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3931 ImplicationChecksByTransitivity, 75.0s TimeCoverageRelationStatistics Valid=4267, Invalid=15439, Unknown=34, NotChecked=0, Total=19740 [2019-10-06 22:59:09,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2019-10-06 22:59:09,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 180. [2019-10-06 22:59:09,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2019-10-06 22:59:09,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 184 transitions. [2019-10-06 22:59:09,576 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 184 transitions. Word has length 268 [2019-10-06 22:59:09,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:59:09,577 INFO L462 AbstractCegarLoop]: Abstraction has 180 states and 184 transitions. [2019-10-06 22:59:09,577 INFO L463 AbstractCegarLoop]: Interpolant automaton has 73 states. [2019-10-06 22:59:09,577 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 184 transitions. [2019-10-06 22:59:09,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 280 [2019-10-06 22:59:09,579 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:59:09,579 INFO L385 BasicCegarLoop]: trace histogram [141, 100, 14, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:59:09,790 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:59:09,790 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:59:09,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:59:09,791 INFO L82 PathProgramCache]: Analyzing trace with hash -2035539065, now seen corresponding path program 12 times [2019-10-06 22:59:09,791 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:59:09,791 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:59:09,792 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:59:09,792 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:59:09,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:59:10,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:59:11,272 INFO L134 CoverageAnalysis]: Checked inductivity of 15457 backedges. 4610 proven. 1128 refuted. 0 times theorem prover too weak. 9719 trivial. 0 not checked. [2019-10-06 22:59:11,272 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:59:11,272 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:59:11,273 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:59:11,855 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:59:11,855 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:59:11,858 INFO L256 TraceCheckSpWp]: Trace formula consists of 1478 conjuncts, 49 conjunts are in the unsatisfiable core [2019-10-06 22:59:11,866 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:59:11,944 INFO L134 CoverageAnalysis]: Checked inductivity of 15457 backedges. 4610 proven. 1128 refuted. 0 times theorem prover too weak. 9719 trivial. 0 not checked. [2019-10-06 22:59:11,944 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:59:14,624 INFO L134 CoverageAnalysis]: Checked inductivity of 15457 backedges. 0 proven. 5738 refuted. 0 times theorem prover too weak. 9719 trivial. 0 not checked. [2019-10-06 22:59:14,625 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:59:14,626 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:59:14,626 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:59:14,626 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:59:14,627 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:59:14,627 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:59:14,654 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:59:33,811 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:59:33,828 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:59:33,831 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:59:33,831 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:59:33,831 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 22:59:33,832 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:59:33,832 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:59:33,832 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:59:33,832 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 22:59:33,832 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:59:33,832 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:59:33,832 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:59:33,833 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:59:33,833 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:59:33,833 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:59:33,833 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:59:33,833 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 22:59:33,833 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:59:33,834 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_288 Int) (v_prenex_3230 Int)) (or (and (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 1) 4294967296) 2147483647) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_288 100) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_288 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 4294967296) 2147483647))) (and (= (+ (mod (div v_prenex_3230 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (not (< v_prenex_3230 0)) (not (<= (mod (+ (div v_prenex_3230 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_3230 100) 4294967296) 2147483647))) (and (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 1) 4294967296) |main_#t~ret4|) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 1) 4294967296) 2147483647) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_288 100) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_288 0)) (and (<= (mod (div v_prenex_3230 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod (div v_prenex_3230 100) 4294967296) |main_#t~ret4|) (not (< v_prenex_3230 0)) (not (<= (mod (+ (div v_prenex_3230 100) 1) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_3230 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_3230 100) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_3230 100) 1) 4294967296) 2147483647)) (not (= (mod v_prenex_3230 100) 0)) (< v_prenex_3230 0)) (and (= (+ (mod (div v_prenex_3230 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_3230 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_3230 100) 4294967296) 2147483647)) (= (mod v_prenex_3230 100) 0)) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 1) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 4294967296) |main_#t~ret4|) (not (< v_mapavg_~ret~0_BEFORE_RETURN_288 0))) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 1) 4294967296) 2147483647) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_288 100) 0) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 1) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_288 0)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_3230 100) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod (div v_prenex_3230 100) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_3230 100) 1) 4294967296) 2147483647)) (= (mod v_prenex_3230 100) 0)) (and (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_3230 100) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_3230 100) 1) 4294967296) 2147483647)) (not (= (mod v_prenex_3230 100) 0)) (not (<= (mod (div v_prenex_3230 100) 4294967296) 2147483647)) (< v_prenex_3230 0)) (and (not (< main_~i~1 100)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_288 100) 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 1) 4294967296) 2147483647) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_288 100) 4294967296) 2147483647))))) (exists ((v_prenex_3229 Int) (v_mapavg_~ret~0_BEFORE_RETURN_287 Int)) (or (and (<= (mod (+ (div v_prenex_3229 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod (+ (div v_prenex_3229 100) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_prenex_3229 100))) (< v_prenex_3229 0)) (and (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_287 100) 4294967296)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_287 100)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_287 100) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_287 100)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_287 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_287 100) 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_3229 100) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_3229 100))) (= (+ (mod (+ (div v_prenex_3229 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_prenex_3229 0)) (and (not (< main_~i~1 100)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_287 0)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_287 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_287 100) 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_287 100) 4294967296)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_287 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_287 100) 4294967296) 2147483647))))) [2019-10-06 22:59:33,834 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:59:33,834 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:59:33,834 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:59:33,834 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:59:36,427 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:59:36,427 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50, 11] total 109 [2019-10-06 22:59:36,429 INFO L442 AbstractCegarLoop]: Interpolant automaton has 109 states [2019-10-06 22:59:36,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2019-10-06 22:59:36,431 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4877, Invalid=6894, Unknown=1, NotChecked=0, Total=11772 [2019-10-06 22:59:36,431 INFO L87 Difference]: Start difference. First operand 180 states and 184 transitions. Second operand 109 states. [2019-10-06 23:00:03,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:00:03,727 INFO L93 Difference]: Finished difference Result 302 states and 360 transitions. [2019-10-06 23:00:03,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 108 states. [2019-10-06 23:00:03,727 INFO L78 Accepts]: Start accepts. Automaton has 109 states. Word has length 279 [2019-10-06 23:00:03,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:00:03,730 INFO L225 Difference]: With dead ends: 302 [2019-10-06 23:00:03,730 INFO L226 Difference]: Without dead ends: 229 [2019-10-06 23:00:03,733 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 989 GetRequests, 779 SyntacticMatches, 0 SemanticMatches, 210 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8412 ImplicationChecksByTransitivity, 22.1s TimeCoverageRelationStatistics Valid=15006, Invalid=29722, Unknown=4, NotChecked=0, Total=44732 [2019-10-06 23:00:03,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229 states. [2019-10-06 23:00:03,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229 to 229. [2019-10-06 23:00:03,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 229 states. [2019-10-06 23:00:03,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229 states to 229 states and 233 transitions. [2019-10-06 23:00:03,747 INFO L78 Accepts]: Start accepts. Automaton has 229 states and 233 transitions. Word has length 279 [2019-10-06 23:00:03,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:00:03,748 INFO L462 AbstractCegarLoop]: Abstraction has 229 states and 233 transitions. [2019-10-06 23:00:03,748 INFO L463 AbstractCegarLoop]: Interpolant automaton has 109 states. [2019-10-06 23:00:03,748 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states and 233 transitions. [2019-10-06 23:00:03,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 427 [2019-10-06 23:00:03,751 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:00:03,751 INFO L385 BasicCegarLoop]: trace histogram [288, 100, 14, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:00:03,952 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:00:03,952 INFO L410 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:00:03,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:00:03,953 INFO L82 PathProgramCache]: Analyzing trace with hash 1381696083, now seen corresponding path program 13 times [2019-10-06 23:00:03,953 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:00:03,954 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:00:03,954 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:00:03,954 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:00:03,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:00:04,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:00:08,468 INFO L134 CoverageAnalysis]: Checked inductivity of 47356 backedges. 18820 proven. 4656 refuted. 0 times theorem prover too weak. 23880 trivial. 0 not checked. [2019-10-06 23:00:08,468 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:00:08,468 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:00:08,468 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:00:09,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:00:09,231 INFO L256 TraceCheckSpWp]: Trace formula consists of 2213 conjuncts, 98 conjunts are in the unsatisfiable core [2019-10-06 23:00:09,240 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:00:09,435 INFO L134 CoverageAnalysis]: Checked inductivity of 47356 backedges. 18820 proven. 4656 refuted. 0 times theorem prover too weak. 23880 trivial. 0 not checked. [2019-10-06 23:00:09,435 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:00:13,577 INFO L134 CoverageAnalysis]: Checked inductivity of 47356 backedges. 0 proven. 23476 refuted. 0 times theorem prover too weak. 23880 trivial. 0 not checked. [2019-10-06 23:00:13,577 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:00:13,579 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:00:13,579 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:00:13,579 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:00:13,579 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:00:13,580 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:00:13,596 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:00:31,390 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 23:00:31,406 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:00:31,408 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:00:31,408 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:00:31,408 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:00:31,409 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 23:00:31,409 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:00:31,409 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:00:31,409 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 23:00:31,409 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 23:00:31,410 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:00:31,410 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:00:31,410 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:00:31,410 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 23:00:31,410 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:00:31,411 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 23:00:31,411 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:00:31,411 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 23:00:31,411 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_313 Int) (v_prenex_3523 Int)) (or (and (not (< v_prenex_3523 0)) (not (< main_~i~1 100)) (= (mod (div v_prenex_3523 100) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_3523 100) 4294967296) 2147483647)) (and (= (mod v_prenex_3523 100) 0) (not (< main_~i~1 100)) (= (mod (div v_prenex_3523 100) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_3523 100) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_313 100) 1) 4294967296) 2147483647) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_313 100) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_313 0) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_313 100) 1) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (div v_prenex_3523 100) 4294967296) 2147483647)) (= (mod v_prenex_3523 100) 0) (not (< main_~i~1 100)) (= (+ (mod (div v_prenex_3523 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_313 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_313 100) 1) 4294967296) 2147483647)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_313 100) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_313 0)) (and (not (<= (mod (div v_prenex_3523 100) 4294967296) 2147483647)) (not (< v_prenex_3523 0)) (not (< main_~i~1 100)) (= (+ (mod (div v_prenex_3523 100) 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_prenex_3524 Int) (v_mapavg_~ret~0_BEFORE_RETURN_314 Int)) (or (and (not (< main_~i~1 100)) (= (mod (div v_prenex_3524 100) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_3524 100) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_3524 100) 4294967296) 2147483647) (= 0 (mod v_prenex_3524 100))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_314 100)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 4294967296) (- 4294967296))) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 1) 4294967296) 2147483647)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_314 100)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= (mod (div v_prenex_3524 100) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_3524 100) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_3524 100) 4294967296) 2147483647) (not (< v_prenex_3524 0))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_314 0) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_314 100))) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 1) 4294967296) 2147483647))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 4294967296) (- 4294967296))) (not (< v_mapavg_~ret~0_BEFORE_RETURN_314 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (= 0 (mod v_prenex_3524 100))) (not (<= (mod (+ (div v_prenex_3524 100) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_3524 100) 4294967296) 2147483647) (< v_prenex_3524 0) (= (+ (mod (+ (div v_prenex_3524 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 4294967296) (- 4294967296))) (not (< v_mapavg_~ret~0_BEFORE_RETURN_314 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 1) 4294967296) 2147483647))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 1) 4294967296)) (< v_mapavg_~ret~0_BEFORE_RETURN_314 0) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_314 100))) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_314 100) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (= 0 (mod v_prenex_3524 100))) (<= (mod (+ (div v_prenex_3524 100) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_prenex_3524 100) 1) 4294967296)) (<= (mod (div v_prenex_3524 100) 4294967296) 2147483647) (< v_prenex_3524 0)) (and (not (< main_~i~1 100)) (= (mod (div v_prenex_3524 100) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_3524 100) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_3524 100) 4294967296) 2147483647) (not (< v_prenex_3524 0))) (and (not (< main_~i~1 100)) (= (mod (div v_prenex_3524 100) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_3524 100) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_3524 100) 4294967296) 2147483647) (= 0 (mod v_prenex_3524 100)))))) [2019-10-06 23:00:31,411 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 23:00:31,411 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 23:00:31,411 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 23:00:31,412 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 23:00:32,343 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:00:32,343 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [99, 99, 99, 11] total 113 [2019-10-06 23:00:32,345 INFO L442 AbstractCegarLoop]: Interpolant automaton has 113 states [2019-10-06 23:00:32,346 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 113 interpolants. [2019-10-06 23:00:32,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5279, Invalid=7377, Unknown=0, NotChecked=0, Total=12656 [2019-10-06 23:00:32,347 INFO L87 Difference]: Start difference. First operand 229 states and 233 transitions. Second operand 113 states. [2019-10-06 23:01:11,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:11,477 INFO L93 Difference]: Finished difference Result 355 states and 368 transitions. [2019-10-06 23:01:11,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 112 states. [2019-10-06 23:01:11,479 INFO L78 Accepts]: Start accepts. Automaton has 113 states. Word has length 426 [2019-10-06 23:01:11,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:11,481 INFO L225 Difference]: With dead ends: 355 [2019-10-06 23:01:11,481 INFO L226 Difference]: Without dead ends: 233 [2019-10-06 23:01:11,485 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1483 GetRequests, 1171 SyntacticMatches, 94 SemanticMatches, 218 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11877 ImplicationChecksByTransitivity, 32.0s TimeCoverageRelationStatistics Valid=16228, Invalid=31946, Unknown=6, NotChecked=0, Total=48180 [2019-10-06 23:01:11,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2019-10-06 23:01:11,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 233. [2019-10-06 23:01:11,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 233 states. [2019-10-06 23:01:11,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 237 transitions. [2019-10-06 23:01:11,503 INFO L78 Accepts]: Start accepts. Automaton has 233 states and 237 transitions. Word has length 426 [2019-10-06 23:01:11,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:11,503 INFO L462 AbstractCegarLoop]: Abstraction has 233 states and 237 transitions. [2019-10-06 23:01:11,503 INFO L463 AbstractCegarLoop]: Interpolant automaton has 113 states. [2019-10-06 23:01:11,503 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 237 transitions. [2019-10-06 23:01:11,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 439 [2019-10-06 23:01:11,506 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:11,507 INFO L385 BasicCegarLoop]: trace histogram [300, 100, 14, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:11,707 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:11,708 INFO L410 AbstractCegarLoop]: === Iteration 17 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:11,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:11,709 INFO L82 PathProgramCache]: Analyzing trace with hash 1065332307, now seen corresponding path program 14 times [2019-10-06 23:01:11,709 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:11,709 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:11,709 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:11,710 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:11,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:12,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:12,720 INFO L134 CoverageAnalysis]: Checked inductivity of 50914 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 50809 trivial. 0 not checked. [2019-10-06 23:01:12,720 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:12,720 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:12,720 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:14,123 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2019-10-06 23:01:14,124 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:01:14,127 INFO L256 TraceCheckSpWp]: Trace formula consists of 393 conjuncts, 16 conjunts are in the unsatisfiable core [2019-10-06 23:01:14,133 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:14,255 INFO L134 CoverageAnalysis]: Checked inductivity of 50914 backedges. 20406 proven. 105 refuted. 0 times theorem prover too weak. 30403 trivial. 0 not checked. [2019-10-06 23:01:14,255 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:14,631 INFO L134 CoverageAnalysis]: Checked inductivity of 50914 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 50809 trivial. 0 not checked. [2019-10-06 23:01:14,631 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:14,632 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:14,632 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:14,633 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:14,633 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:14,633 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:14,650 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:33,622 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 23:01:33,645 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:33,648 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:33,648 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:33,648 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:01:33,648 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 23:01:33,648 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:33,649 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:33,649 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 100 mapavg_~i~0) (not (< mapavg_~i~0 100)) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 100) 0))) (+ (div mapavg_~ret~0 100) 1) (div mapavg_~ret~0 100)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 0 mapavg_~i~0)) [2019-10-06 23:01:33,649 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 23:01:33,649 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:33,649 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:33,649 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:33,650 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 23:01:33,650 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:33,650 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 23:01:33,650 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:01:33,650 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 23:01:33,651 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_3829 Int) (v_mapavg_~ret~0_BEFORE_RETURN_339 Int)) (or (and (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_339 100) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_339 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_339 100) 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_339 100) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (<= (mod (div v_prenex_3829 100) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_3829 100) 4294967296)) (= (mod v_prenex_3829 100) 0)) (and (not (<= (mod (div v_prenex_3829 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (not (< v_prenex_3829 0)) (= (+ (mod (div v_prenex_3829 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (div v_prenex_3829 100) 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (mod v_prenex_3829 100) 0) (= (+ (mod (div v_prenex_3829 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_339 100) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_339 100) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_339 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_339 100) 0))) (and (not (< main_~i~1 100)) (<= (mod (div v_prenex_3829 100) 4294967296) 2147483647) (not (< v_prenex_3829 0)) (= |main_#t~ret4| (mod (div v_prenex_3829 100) 4294967296))))) (exists ((v_prenex_3830 Int) (v_mapavg_~ret~0_BEFORE_RETURN_340 Int)) (or (and (not (= 0 (mod v_prenex_3830 100))) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_3830 100) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (< v_prenex_3830 0) (not (<= (mod (+ (div v_prenex_3830 100) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_3830 100) 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_3830 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_3830 100) 4294967296) 2147483647)) (= 0 (mod v_prenex_3830 100)) (= (+ (mod (div v_prenex_3830 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_340 100))) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_340 0) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 1) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_3830 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_3830 100) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_3830 100) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_3830 0))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_340 0)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_3830 100) 1) 4294967296) 2147483647)) (not (< v_prenex_3830 0)) (<= (mod (div v_prenex_3830 100) 4294967296) 2147483647) (= (mod (div v_prenex_3830 100) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_340 0)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_340 100)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 4294967296) |main_#t~ret4|)) (and (not (= 0 (mod v_prenex_3830 100))) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_3830 100) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (< v_prenex_3830 0) (not (<= (mod (+ (div v_prenex_3830 100) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_3830 100) 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (not (<= (mod (+ (div v_prenex_3830 100) 1) 4294967296) 2147483647)) (= 0 (mod v_prenex_3830 100)) (<= (mod (div v_prenex_3830 100) 4294967296) 2147483647) (= (mod (div v_prenex_3830 100) 4294967296) |main_#t~ret4|)) (and (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_340 100))) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (< v_mapavg_~ret~0_BEFORE_RETURN_340 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 4294967296) 2147483647)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 1) 4294967296) |main_#t~ret4|)) (and (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_340 100)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 1) 4294967296) 2147483647) (not (< main_~i~1 100)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_340 100) 4294967296) (- 4294967296)) |main_#t~ret4|))))) [2019-10-06 23:01:33,651 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 23:01:33,651 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 23:01:33,651 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 23:01:33,651 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 23:01:34,038 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:34,039 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 11] total 43 [2019-10-06 23:01:34,040 INFO L442 AbstractCegarLoop]: Interpolant automaton has 43 states [2019-10-06 23:01:34,041 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2019-10-06 23:01:34,041 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=553, Invalid=1253, Unknown=0, NotChecked=0, Total=1806 [2019-10-06 23:01:34,041 INFO L87 Difference]: Start difference. First operand 233 states and 237 transitions. Second operand 43 states.