java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/array-crafted/mapavg2.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-06 22:48:37,115 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-06 22:48:37,118 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-06 22:48:37,132 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-06 22:48:37,132 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-06 22:48:37,133 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-06 22:48:37,135 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-06 22:48:37,137 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-06 22:48:37,148 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-06 22:48:37,149 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-06 22:48:37,152 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-06 22:48:37,153 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-06 22:48:37,154 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-06 22:48:37,155 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-06 22:48:37,156 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-06 22:48:37,159 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-06 22:48:37,160 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-06 22:48:37,161 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-06 22:48:37,165 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-06 22:48:37,167 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-06 22:48:37,171 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-06 22:48:37,174 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-06 22:48:37,175 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-06 22:48:37,176 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-06 22:48:37,180 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-06 22:48:37,190 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-06 22:48:37,192 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-06 22:48:37,196 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-06 22:48:37,196 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-06 22:48:37,212 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-06 22:48:37,212 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-06 22:48:37,214 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-06 22:48:37,214 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-06 22:48:37,214 INFO L138 SettingsManager]: * Use SBE=true [2019-10-06 22:48:37,214 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-06 22:48:37,214 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-06 22:48:37,215 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-06 22:48:37,215 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-06 22:48:37,215 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-06 22:48:37,215 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-06 22:48:37,215 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-06 22:48:37,216 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-06 22:48:37,216 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-06 22:48:37,216 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-06 22:48:37,216 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-06 22:48:37,216 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-06 22:48:37,217 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-06 22:48:37,217 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-06 22:48:37,217 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-06 22:48:37,217 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-06 22:48:37,217 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:37,218 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-06 22:48:37,218 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-06 22:48:37,218 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-06 22:48:37,218 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-06 22:48:37,218 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-06 22:48:37,218 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-06 22:48:37,219 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-06 22:48:37,549 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-06 22:48:37,561 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-06 22:48:37,564 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-06 22:48:37,565 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-06 22:48:37,566 INFO L275 PluginConnector]: CDTParser initialized [2019-10-06 22:48:37,566 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-crafted/mapavg2.i [2019-10-06 22:48:37,619 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/df9e13e36/a7b31828700a40b7a2839371cc148bf1/FLAGe14a63d4b [2019-10-06 22:48:38,046 INFO L306 CDTParser]: Found 1 translation units. [2019-10-06 22:48:38,047 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-crafted/mapavg2.i [2019-10-06 22:48:38,053 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/df9e13e36/a7b31828700a40b7a2839371cc148bf1/FLAGe14a63d4b [2019-10-06 22:48:38,434 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/df9e13e36/a7b31828700a40b7a2839371cc148bf1 [2019-10-06 22:48:38,447 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-06 22:48:38,449 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-06 22:48:38,450 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,450 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-06 22:48:38,455 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-06 22:48:38,456 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,459 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@39f7fc14 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38, skipping insertion in model container [2019-10-06 22:48:38,459 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,467 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-06 22:48:38,487 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-06 22:48:38,662 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,670 INFO L188 MainTranslator]: Completed pre-run [2019-10-06 22:48:38,691 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,705 INFO L192 MainTranslator]: Completed translation [2019-10-06 22:48:38,705 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38 WrapperNode [2019-10-06 22:48:38,705 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,706 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-06 22:48:38,706 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-06 22:48:38,706 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-06 22:48:38,799 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,800 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,806 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,807 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,815 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,820 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,821 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,823 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-06 22:48:38,824 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-06 22:48:38,824 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-06 22:48:38,824 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-06 22:48:38,825 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:38,880 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-06 22:48:38,880 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-06 22:48:38,880 INFO L138 BoogieDeclarations]: Found implementation of procedure mapavg [2019-10-06 22:48:38,880 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-06 22:48:38,880 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-06 22:48:38,880 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-06 22:48:38,881 INFO L130 BoogieDeclarations]: Found specification of procedure mapavg [2019-10-06 22:48:38,881 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-06 22:48:38,881 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-06 22:48:38,881 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-06 22:48:38,881 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-06 22:48:38,881 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-06 22:48:38,881 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-06 22:48:38,882 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-06 22:48:39,270 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-06 22:48:39,270 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-06 22:48:39,271 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39 BoogieIcfgContainer [2019-10-06 22:48:39,271 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-06 22:48:39,272 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-06 22:48:39,273 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-06 22:48:39,275 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-06 22:48:39,276 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.10 10:48:38" (1/3) ... [2019-10-06 22:48:39,276 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3f643174 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,277 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (2/3) ... [2019-10-06 22:48:39,277 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3f643174 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,277 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39" (3/3) ... [2019-10-06 22:48:39,279 INFO L109 eAbstractionObserver]: Analyzing ICFG mapavg2.i [2019-10-06 22:48:39,286 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-06 22:48:39,293 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-06 22:48:39,302 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-06 22:48:39,323 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-06 22:48:39,323 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-06 22:48:39,323 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-06 22:48:39,324 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-06 22:48:39,324 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-06 22:48:39,324 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-06 22:48:39,324 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-06 22:48:39,324 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-06 22:48:39,342 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-06 22:48:39,347 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-06 22:48:39,348 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,349 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,351 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,357 INFO L82 PathProgramCache]: Analyzing trace with hash -1953355565, now seen corresponding path program 1 times [2019-10-06 22:48:39,365 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,365 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,365 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,365 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,536 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-06 22:48:39,537 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,538 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:39,538 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:39,543 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:39,562 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:39,563 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,565 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-06 22:48:39,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:39,616 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-06 22:48:39,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:39,622 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-06 22:48:39,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:39,633 INFO L225 Difference]: With dead ends: 41 [2019-10-06 22:48:39,634 INFO L226 Difference]: Without dead ends: 20 [2019-10-06 22:48:39,640 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-06 22:48:39,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-06 22:48:39,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-06 22:48:39,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-06 22:48:39,693 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-06 22:48:39,694 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:39,695 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-06 22:48:39,695 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:39,695 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-06 22:48:39,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-06 22:48:39,699 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,699 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,700 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,701 INFO L82 PathProgramCache]: Analyzing trace with hash -1072677037, now seen corresponding path program 1 times [2019-10-06 22:48:39,702 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,702 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,702 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,702 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,837 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:39,837 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,837 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:39,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:39,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,930 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-06 22:48:39,939 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:39,975 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:39,975 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,016 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,016 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-06 22:48:40,016 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-06 22:48:40,018 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,018 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,019 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,019 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-06 22:48:40,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,033 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-06 22:48:40,034 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,034 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-06 22:48:40,034 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,035 INFO L225 Difference]: With dead ends: 33 [2019-10-06 22:48:40,035 INFO L226 Difference]: Without dead ends: 21 [2019-10-06 22:48:40,037 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-06 22:48:40,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-06 22:48:40,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-06 22:48:40,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-06 22:48:40,043 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-06 22:48:40,043 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,043 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-06 22:48:40,043 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,043 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-06 22:48:40,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-06 22:48:40,044 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,045 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,250 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,251 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,252 INFO L82 PathProgramCache]: Analyzing trace with hash 608739335, now seen corresponding path program 1 times [2019-10-06 22:48:40,252 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,253 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,253 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,253 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,350 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,350 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,351 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:40,351 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:40,351 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,352 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,352 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,352 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-06 22:48:40,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,370 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-06 22:48:40,373 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,373 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-06 22:48:40,374 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,375 INFO L225 Difference]: With dead ends: 31 [2019-10-06 22:48:40,375 INFO L226 Difference]: Without dead ends: 22 [2019-10-06 22:48:40,376 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-06 22:48:40,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-06 22:48:40,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-06 22:48:40,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-06 22:48:40,385 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-06 22:48:40,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,389 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-06 22:48:40,389 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,389 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-06 22:48:40,390 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-06 22:48:40,390 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,391 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,391 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,391 INFO L82 PathProgramCache]: Analyzing trace with hash -824983385, now seen corresponding path program 1 times [2019-10-06 22:48:40,391 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,392 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,392 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,392 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,502 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,502 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,503 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:40,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,588 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,590 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,607 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,607 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,646 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,647 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:40,673 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:40,674 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:40,680 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:40,690 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:40,691 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:40,833 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:58,878 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:48:58,906 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:48:58,909 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:48:58,910 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:48:58,910 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:48:58,910 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:48:58,911 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:48:58,911 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:48:58,911 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:48:58,911 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 1000 mapavg_~i~0) (<= 0 mapavg_~i~0) (= (ite (<= (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) 2147483647) (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (+ (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 1000))) [2019-10-06 22:48:58,911 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:48:58,912 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:58,912 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:58,912 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:48:58,912 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:48:58,912 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:48:58,913 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:48:58,913 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:48:58,913 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_2 Int) (v_prenex_2 Int)) (or (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 1) 4294967296) 2147483647)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 4294967296) |main_#t~ret4|)) (and (= (+ (mod (div v_prenex_2 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 1000)) (<= (mod (+ (div v_prenex_2 1000) 1) 4294967296) 2147483647) (not (<= (mod (div v_prenex_2 1000) 4294967296) 2147483647)) (= (mod v_prenex_2 1000) 0)) (and (not (= (mod v_prenex_2 1000) 0)) (not (< main_~i~1 1000)) (= (mod (+ (div v_prenex_2 1000) 1) 4294967296) |main_#t~ret4|) (< v_prenex_2 0) (<= (mod (+ (div v_prenex_2 1000) 1) 4294967296) 2147483647) (not (<= (mod (div v_prenex_2 1000) 4294967296) 2147483647))) (and (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 1) 4294967296) 2147483647)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 4294967296) 2147483647) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (and (= (+ (mod (div v_prenex_2 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_2 0)) (not (< main_~i~1 1000)) (<= (mod (+ (div v_prenex_2 1000) 1) 4294967296) 2147483647) (not (<= (mod (div v_prenex_2 1000) 4294967296) 2147483647))) (and (= (+ (mod (div v_prenex_2 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_2 0)) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_prenex_2 1000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2 1000) 4294967296) 2147483647))) (and (not (= (mod v_prenex_2 1000) 0)) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_prenex_2 1000) 1) 4294967296) 2147483647)) (< v_prenex_2 0) (not (<= (mod (div v_prenex_2 1000) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_2 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (+ (mod (div v_prenex_2 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_prenex_2 1000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2 1000) 4294967296) 2147483647)) (= (mod v_prenex_2 1000) 0)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 1) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 1) 4294967296) 2147483647) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 0) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 1) 4294967296) 2147483647) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 0) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 1) 4294967296) 2147483647)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 1000) 4294967296) |main_#t~ret4|)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (= (mod v_prenex_1 1000) 0) (not (< main_~i~1 1000)) (= (mod (div v_prenex_1 1000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_1 1000) 4294967296) 2147483647)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 1000) 1) 4294967296) 2147483647) (not (< main_~i~1 1000)) (< v_mapavg_~ret~0_BEFORE_RETURN_1 0) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 1000) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_1 1000) 0))) (and (not (< v_prenex_1 0)) (= |main_#t~ret4| (+ (mod (div v_prenex_1 1000) 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (not (<= (mod (div v_prenex_1 1000) 4294967296) 2147483647))) (and (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 1000) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 1000) 1) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_1 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_1 1000) 0))) (and (= (mod v_prenex_1 1000) 0) (= |main_#t~ret4| (+ (mod (div v_prenex_1 1000) 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (not (<= (mod (div v_prenex_1 1000) 4294967296) 2147483647))) (and (not (< v_prenex_1 0)) (not (< main_~i~1 1000)) (= (mod (div v_prenex_1 1000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_1 1000) 4294967296) 2147483647))))) [2019-10-06 22:48:58,914 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:48:58,914 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:48:58,914 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:48:58,914 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:48:59,151 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:48:59,152 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 12] total 17 [2019-10-06 22:48:59,153 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-10-06 22:48:59,153 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-10-06 22:48:59,154 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=226, Unknown=0, NotChecked=0, Total=272 [2019-10-06 22:48:59,154 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 17 states. [2019-10-06 22:49:25,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:25,701 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-06 22:49:25,702 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-10-06 22:49:25,702 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 29 [2019-10-06 22:49:25,702 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:25,703 INFO L225 Difference]: With dead ends: 40 [2019-10-06 22:49:25,703 INFO L226 Difference]: Without dead ends: 25 [2019-10-06 22:49:25,704 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 12.6s TimeCoverageRelationStatistics Valid=123, Invalid=627, Unknown=6, NotChecked=0, Total=756 [2019-10-06 22:49:25,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-06 22:49:25,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-06 22:49:25,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-06 22:49:25,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-06 22:49:25,713 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-06 22:49:25,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:25,719 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-06 22:49:25,719 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-10-06 22:49:25,720 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-06 22:49:25,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-06 22:49:25,721 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:25,721 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:25,922 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:25,922 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:25,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:25,923 INFO L82 PathProgramCache]: Analyzing trace with hash 1686538791, now seen corresponding path program 2 times [2019-10-06 22:49:25,923 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:25,924 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:25,924 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:25,924 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:25,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:25,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:26,026 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:49:26,027 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:26,027 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:26,027 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:26,097 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-06 22:49:26,099 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:26,105 INFO L256 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:49:26,108 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:26,128 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:49:26,129 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:26,170 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:49:26,171 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:26,173 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:26,173 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:26,173 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:26,174 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:26,174 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:26,194 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:32,983 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:49:33,024 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:33,027 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:33,028 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:33,028 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:49:33,028 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:49:33,028 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:33,028 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:33,029 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:33,029 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 1000 mapavg_~i~0) (<= 0 mapavg_~i~0) (= (ite (<= (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) 2147483647) (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (+ (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 1000))) [2019-10-06 22:49:33,029 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:49:33,029 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:33,029 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:33,029 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:33,030 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:49:33,030 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:33,030 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:49:33,034 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:49:33,034 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_301 Int) (v_mapavg_~ret~0_BEFORE_RETURN_27 Int)) (or (and (<= (mod (div v_prenex_301 1000) 4294967296) 2147483647) (not (< v_prenex_301 0)) (not (< main_~i~1 1000)) (= (mod (div v_prenex_301 1000) 4294967296) |main_#t~ret4|)) (and (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_27 1000) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_27 0)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 1000) 1) 4294967296) 2147483647) (not (< main_~i~1 1000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_27 1000) 0)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 1000) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_27 0)) (and (<= (mod (div v_prenex_301 1000) 4294967296) 2147483647) (= (mod v_prenex_301 1000) 0) (not (< main_~i~1 1000)) (= (mod (div v_prenex_301 1000) 4294967296) |main_#t~ret4|)) (and (= (+ (mod (div v_prenex_301 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_301 0)) (not (<= (mod (div v_prenex_301 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000))) (and (= (+ (mod (div v_prenex_301 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_prenex_301 1000) 0) (not (<= (mod (div v_prenex_301 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000))))) (exists ((v_prenex_302 Int) (v_mapavg_~ret~0_BEFORE_RETURN_28 Int)) (or (and (not (<= (mod (+ (div v_prenex_302 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (< v_prenex_302 0) (= (+ (mod (+ (div v_prenex_302 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_prenex_302 1000) 0))) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_28 1000) 0) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 1000) 4294967296)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 1000) 4294967296) 2147483647) (not (< main_~i~1 1000))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_28 0)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 1000) 4294967296) (- 4294967296)))) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_28 1000) 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 1000) 4294967296) (- 4294967296)))) (and (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 1000) 4294967296)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_28 0))) (and (<= (mod (+ (div v_prenex_302 1000) 1) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod (+ (div v_prenex_302 1000) 1) 4294967296) |main_#t~ret4|) (< v_prenex_302 0) (not (= (mod v_prenex_302 1000) 0)))))) [2019-10-06 22:49:33,034 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:49:33,034 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:33,034 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:49:33,035 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:49:34,017 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:34,017 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-06 22:49:34,019 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-10-06 22:49:34,019 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-10-06 22:49:34,020 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=360, Unknown=0, NotChecked=0, Total=420 [2019-10-06 22:49:34,020 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 21 states. [2019-10-06 22:50:02,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:02,810 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-06 22:50:02,812 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-10-06 22:50:02,812 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 32 [2019-10-06 22:50:02,812 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:02,813 INFO L225 Difference]: With dead ends: 44 [2019-10-06 22:50:02,813 INFO L226 Difference]: Without dead ends: 29 [2019-10-06 22:50:02,814 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 13.5s TimeCoverageRelationStatistics Valid=200, Invalid=1126, Unknown=6, NotChecked=0, Total=1332 [2019-10-06 22:50:02,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-06 22:50:02,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-06 22:50:02,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-06 22:50:02,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-06 22:50:02,829 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-06 22:50:02,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:02,830 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-06 22:50:02,830 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-10-06 22:50:02,830 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-06 22:50:02,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-06 22:50:02,831 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:02,831 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:03,034 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:03,035 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:03,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:03,035 INFO L82 PathProgramCache]: Analyzing trace with hash -682053593, now seen corresponding path program 3 times [2019-10-06 22:50:03,036 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:03,036 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:03,036 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:03,037 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:03,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:03,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:03,165 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:03,165 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:03,165 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:50:03,165 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:03,273 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:50:03,273 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:50:03,274 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-06 22:50:03,276 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:50:03,304 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:03,305 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:03,394 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:03,395 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:03,396 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:03,396 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:03,397 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:03,397 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:03,397 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:03,421 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:50:23,392 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:50:23,421 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:50:23,423 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:50:23,423 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:50:23,424 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:50:23,424 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:50:23,424 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:50:23,424 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:50:23,424 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:50:23,425 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 1000 mapavg_~i~0) (<= 0 mapavg_~i~0) (= (ite (<= (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) 2147483647) (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (+ (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 1000))) [2019-10-06 22:50:23,425 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:50:23,425 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:23,425 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:23,425 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:23,426 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:50:23,426 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:50:23,426 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:50:23,426 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:50:23,426 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_571 Int) (v_mapavg_~ret~0_BEFORE_RETURN_53 Int)) (or (and (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 1) 4294967296) 2147483647) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_53 1000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_571 1000) 4294967296) 2147483647) (not (< v_prenex_571 0)) (not (< main_~i~1 1000)) (= (mod (div v_prenex_571 1000) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_571 1000) 1) 4294967296) 2147483647))) (and (< v_mapavg_~ret~0_BEFORE_RETURN_53 0) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_53 1000))) (not (< main_~i~1 1000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 4294967296) 2147483647)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 1) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_prenex_571 1000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_571 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (< v_prenex_571 0) (not (= 0 (mod v_prenex_571 1000))) (= (mod (+ (div v_prenex_571 1000) 1) 4294967296) |main_#t~ret4|)) (and (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 4294967296) (- 4294967296))) (not (< v_mapavg_~ret~0_BEFORE_RETURN_53 0)) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 4294967296) 2147483647))) (and (<= (mod (+ (div v_prenex_571 1000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_571 1000) 4294967296) 2147483647) (not (< v_prenex_571 0)) (not (< main_~i~1 1000)) (= (mod (div v_prenex_571 1000) 4294967296) |main_#t~ret4|)) (and (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_53 1000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_571 1000) 4294967296) 2147483647) (= 0 (mod v_prenex_571 1000)) (not (< main_~i~1 1000)) (= (mod (div v_prenex_571 1000) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_571 1000) 1) 4294967296) 2147483647))) (and (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 4294967296) (- 4294967296))) (not (< v_mapavg_~ret~0_BEFORE_RETURN_53 0)) (not (< main_~i~1 1000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 4294967296) 2147483647))) (and (<= (mod (+ (div v_prenex_571 1000) 1) 4294967296) 2147483647) (= 0 (mod v_prenex_571 1000)) (<= (mod (div v_prenex_571 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod (div v_prenex_571 1000) 4294967296) |main_#t~ret4|)) (and (<= (mod (div v_prenex_571 1000) 4294967296) 2147483647) (= (+ (mod (+ (div v_prenex_571 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 1000)) (< v_prenex_571 0) (not (<= (mod (+ (div v_prenex_571 1000) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_571 1000)))) (and (< v_mapavg_~ret~0_BEFORE_RETURN_53 0) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_53 1000))) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 1000) 4294967296) 2147483647))))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_572 Int)) (or (and (<= (mod (+ (div v_prenex_572 1000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_prenex_572 1000) 1) 4294967296)) (not (< main_~i~1 1000)) (not (= (mod v_prenex_572 1000) 0)) (< v_prenex_572 0)) (and (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 1000) 4294967296) (- 4294967296))) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_54 1000) 0)) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 1000) 4294967296) |main_#t~ret4|) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_54 1000) 0)) (and (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 1000) 4294967296) (- 4294967296))) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_54 0))) (and (not (< main_~i~1 1000)) (not (= (mod v_prenex_572 1000) 0)) (not (<= (mod (+ (div v_prenex_572 1000) 1) 4294967296) 2147483647)) (< v_prenex_572 0) (= (+ (mod (+ (div v_prenex_572 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 1000) 4294967296) |main_#t~ret4|) (not (< v_mapavg_~ret~0_BEFORE_RETURN_54 0)))))) [2019-10-06 22:50:23,427 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:50:23,427 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:50:23,427 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:50:23,427 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:50:25,696 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:50:25,697 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-06 22:50:25,698 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-10-06 22:50:25,698 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-10-06 22:50:25,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=469, Unknown=1, NotChecked=0, Total=600 [2019-10-06 22:50:25,699 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 25 states. [2019-10-06 22:50:52,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:52,456 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-06 22:50:52,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-10-06 22:50:52,458 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 42 [2019-10-06 22:50:52,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:52,458 INFO L225 Difference]: With dead ends: 54 [2019-10-06 22:50:52,459 INFO L226 Difference]: Without dead ends: 36 [2019-10-06 22:50:52,460 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 487 ImplicationChecksByTransitivity, 12.8s TimeCoverageRelationStatistics Valid=359, Invalid=1527, Unknown=6, NotChecked=0, Total=1892 [2019-10-06 22:50:52,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-06 22:50:52,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-06 22:50:52,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-06 22:50:52,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-06 22:50:52,470 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-06 22:50:52,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:52,470 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-06 22:50:52,470 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-10-06 22:50:52,470 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-06 22:50:52,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-06 22:50:52,472 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:52,472 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:52,674 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:52,675 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:52,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:52,675 INFO L82 PathProgramCache]: Analyzing trace with hash -1538541913, now seen corresponding path program 4 times [2019-10-06 22:50:52,676 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:52,676 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:52,676 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:52,676 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:52,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:52,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:52,869 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:52,870 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:52,870 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:50:52,870 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:53,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:53,035 INFO L256 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-06 22:50:53,041 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:50:53,051 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:53,051 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:53,299 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:53,299 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:53,301 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:53,301 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:53,301 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:53,302 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:53,302 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:53,316 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:50:59,479 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:50:59,511 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:50:59,514 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:50:59,514 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:50:59,514 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:50:59,514 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:50:59,515 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:50:59,515 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:50:59,515 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:50:59,515 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 1000 mapavg_~i~0) (<= 0 mapavg_~i~0) (= (ite (<= (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) 2147483647) (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (+ (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 1000))) [2019-10-06 22:50:59,515 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:50:59,515 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:59,516 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:59,516 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:59,516 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:50:59,516 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:50:59,516 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:50:59,517 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:50:59,517 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_871 Int)) (or (and (not (= (mod v_prenex_871 1000) 0)) (= (+ (mod (+ (div v_prenex_871 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 1000)) (< v_prenex_871 0) (not (<= (mod (+ (div v_prenex_871 1000) 1) 4294967296) 2147483647))) (and (not (= (mod v_prenex_871 1000) 0)) (not (< main_~i~1 1000)) (= |main_#t~ret4| (mod (+ (div v_prenex_871 1000) 1) 4294967296)) (<= (mod (+ (div v_prenex_871 1000) 1) 4294967296) 2147483647) (< v_prenex_871 0)) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_79 0)) (not (< main_~i~1 1000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 1000) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 1000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 1000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 1000) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_79 1000) 0)) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_79 0)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 1000) 4294967296)) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 1000) 4294967296) 2147483647)) (and (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 1000) 4294967296)) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 1000) 4294967296) 2147483647) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_79 1000) 0)))) (exists ((v_prenex_872 Int) (v_mapavg_~ret~0_BEFORE_RETURN_80 Int)) (or (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_80 1000))) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_80 0)) (not (< main_~i~1 1000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 1000) 4294967296) |main_#t~ret4|) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 1000) 4294967296) 2147483647)) (and (= (+ (mod (+ (div v_prenex_872 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_prenex_872 0) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_prenex_872 1000) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_872 1000)))) (and (not (< main_~i~1 1000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 1000) 4294967296) |main_#t~ret4|) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_80 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 1000) 4294967296) 2147483647)) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_80 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 1000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= |main_#t~ret4| (mod (+ (div v_prenex_872 1000) 1) 4294967296)) (< v_prenex_872 0) (<= (mod (+ (div v_prenex_872 1000) 1) 4294967296) 2147483647) (not (< main_~i~1 1000)) (not (= 0 (mod v_prenex_872 1000))))))) [2019-10-06 22:50:59,517 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:50:59,517 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:50:59,517 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:50:59,517 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:51:01,803 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:51:01,804 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-06 22:51:01,805 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2019-10-06 22:51:01,806 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-10-06 22:51:01,807 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=431, Invalid=1050, Unknown=1, NotChecked=0, Total=1482 [2019-10-06 22:51:01,807 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 39 states. [2019-10-06 22:51:31,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:51:31,186 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-06 22:51:31,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-10-06 22:51:31,188 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 49 [2019-10-06 22:51:31,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:51:31,189 INFO L225 Difference]: With dead ends: 68 [2019-10-06 22:51:31,189 INFO L226 Difference]: Without dead ends: 50 [2019-10-06 22:51:31,192 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1243 ImplicationChecksByTransitivity, 15.7s TimeCoverageRelationStatistics Valid=1234, Invalid=3871, Unknown=7, NotChecked=0, Total=5112 [2019-10-06 22:51:31,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-06 22:51:31,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-06 22:51:31,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-06 22:51:31,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-06 22:51:31,200 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-06 22:51:31,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:51:31,200 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-06 22:51:31,200 INFO L463 AbstractCegarLoop]: Interpolant automaton has 39 states. [2019-10-06 22:51:31,200 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-06 22:51:31,201 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-06 22:51:31,201 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:51:31,201 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:51:31,402 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:31,403 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:51:31,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:51:31,404 INFO L82 PathProgramCache]: Analyzing trace with hash -511572313, now seen corresponding path program 5 times [2019-10-06 22:51:31,404 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:51:31,404 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:31,404 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:31,405 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:31,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:51:31,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:31,905 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:51:31,906 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:31,906 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:51:31,906 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:32,080 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:51:32,080 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:51:32,081 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:51:32,084 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:51:32,117 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-06 22:51:32,118 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:51:32,166 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-06 22:51:32,166 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:51:32,168 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:51:32,168 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:51:32,172 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:51:32,173 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:51:32,173 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:51:32,186 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:52:09,781 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:52:09,806 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:52:09,809 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:52:09,809 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:52:09,809 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:52:09,809 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:52:09,809 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:52:09,810 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:52:09,810 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:52:09,810 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 1000 mapavg_~i~0) (<= 0 mapavg_~i~0) (= (ite (<= (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) 2147483647) (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (+ (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 1000))) [2019-10-06 22:52:09,810 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:52:09,810 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:09,811 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:52:09,811 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:09,811 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:52:09,811 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:52:09,811 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:52:09,811 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:52:09,812 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_1112 Int)) (or (and (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_106 0)) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_106 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 4294967296) (- 4294967296)))) (and (= (mod v_prenex_1112 1000) 0) (= (mod (div v_prenex_1112 1000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_prenex_1112 1000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_1112 1000) 4294967296) 2147483647)) (and (not (< v_prenex_1112 0)) (= (mod (div v_prenex_1112 1000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_prenex_1112 1000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_1112 1000) 4294967296) 2147483647)) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 4294967296) (- 4294967296)))) (and (not (< v_prenex_1112 0)) (<= (mod (+ (div v_prenex_1112 1000) 1) 4294967296) 2147483647) (= (mod (div v_prenex_1112 1000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (<= (mod (div v_prenex_1112 1000) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 1) 4294967296) 2147483647)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 1000)) (not (= (mod v_prenex_1112 1000) 0)) (not (<= (mod (+ (div v_prenex_1112 1000) 1) 4294967296) 2147483647)) (< v_prenex_1112 0) (= (+ (mod (+ (div v_prenex_1112 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (div v_prenex_1112 1000) 4294967296) 2147483647)) (and (= (mod (+ (div v_prenex_1112 1000) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1112 1000) 1) 4294967296) 2147483647) (not (< main_~i~1 1000)) (not (= (mod v_prenex_1112 1000) 0)) (< v_prenex_1112 0) (<= (mod (div v_prenex_1112 1000) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 1) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_106 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 4294967296) (- 4294967296)))) (and (= (mod v_prenex_1112 1000) 0) (<= (mod (+ (div v_prenex_1112 1000) 1) 4294967296) 2147483647) (= (mod (div v_prenex_1112 1000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (<= (mod (div v_prenex_1112 1000) 4294967296) 2147483647)) (and (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 1) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_106 0) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 1000) 1) 4294967296) |main_#t~ret4|)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_1111 Int)) (or (and (= |main_#t~ret4| (+ (mod (div v_prenex_1111 1000) 4294967296) (- 4294967296))) (<= (mod (+ (div v_prenex_1111 1000) 1) 4294967296) 2147483647) (= (mod v_prenex_1111 1000) 0) (not (< main_~i~1 1000)) (not (<= (mod (div v_prenex_1111 1000) 4294967296) 2147483647))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 1) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_105 0) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 1) 4294967296) (- 4294967296))) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 0))) (and (not (= (mod v_prenex_1111 1000) 0)) (< v_prenex_1111 0) (<= (mod (+ (div v_prenex_1111 1000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_prenex_1111 1000) 1) 4294967296)) (not (< main_~i~1 1000)) (not (<= (mod (div v_prenex_1111 1000) 4294967296) 2147483647))) (and (= |main_#t~ret4| (+ (mod (div v_prenex_1111 1000) 4294967296) (- 4294967296))) (= (mod v_prenex_1111 1000) 0) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_prenex_1111 1000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_1111 1000) 4294967296) 2147483647))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 1) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 4294967296) |main_#t~ret4|) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 0) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 1) 4294967296) 2147483647)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 4294967296) |main_#t~ret4|) (not (< v_mapavg_~ret~0_BEFORE_RETURN_105 0)) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_prenex_1111 1000) 4294967296) (- 4294967296))) (<= (mod (+ (div v_prenex_1111 1000) 1) 4294967296) 2147483647) (not (< v_prenex_1111 0)) (not (< main_~i~1 1000)) (not (<= (mod (div v_prenex_1111 1000) 4294967296) 2147483647))) (and (not (= (mod v_prenex_1111 1000) 0)) (< v_prenex_1111 0) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1111 1000) 1) 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_prenex_1111 1000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_1111 1000) 4294967296) 2147483647))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 1) 4294967296) 2147483647)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 4294967296) |main_#t~ret4|) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 0) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_prenex_1111 1000) 4294967296) (- 4294967296))) (not (< v_prenex_1111 0)) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_prenex_1111 1000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_1111 1000) 4294967296) 2147483647))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 1) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_105 0) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 1) 4294967296)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 0))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 1) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 4294967296) |main_#t~ret4|) (not (< v_mapavg_~ret~0_BEFORE_RETURN_105 0)) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 1000) 4294967296) 2147483647))))) [2019-10-06 22:52:09,812 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:52:09,812 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:52:09,812 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:52:09,812 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:52:12,277 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:52:12,277 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-06 22:52:12,279 INFO L442 AbstractCegarLoop]: Interpolant automaton has 43 states [2019-10-06 22:52:12,280 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2019-10-06 22:52:12,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=445, Invalid=1360, Unknown=1, NotChecked=0, Total=1806 [2019-10-06 22:52:12,281 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 43 states. [2019-10-06 22:52:54,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:52:54,379 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-06 22:52:54,379 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2019-10-06 22:52:54,379 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 63 [2019-10-06 22:52:54,379 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:52:54,380 INFO L225 Difference]: With dead ends: 72 [2019-10-06 22:52:54,380 INFO L226 Difference]: Without dead ends: 54 [2019-10-06 22:52:54,382 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 177 SyntacticMatches, 0 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1240 ImplicationChecksByTransitivity, 28.5s TimeCoverageRelationStatistics Valid=1339, Invalid=5128, Unknown=13, NotChecked=0, Total=6480 [2019-10-06 22:52:54,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-06 22:52:54,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-06 22:52:54,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-06 22:52:54,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-06 22:52:54,391 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-06 22:52:54,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:52:54,392 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-06 22:52:54,392 INFO L463 AbstractCegarLoop]: Interpolant automaton has 43 states. [2019-10-06 22:52:54,392 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-06 22:52:54,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-06 22:52:54,393 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:52:54,393 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:52:54,594 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:52:54,594 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:52:54,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:52:54,595 INFO L82 PathProgramCache]: Analyzing trace with hash -637611949, now seen corresponding path program 6 times [2019-10-06 22:52:54,595 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:52:54,596 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:52:54,596 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:52:54,596 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:52:54,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:52:54,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:52:55,039 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:52:55,039 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:52:55,039 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:52:55,039 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:52:55,258 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:52:55,259 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:52:55,260 INFO L256 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-06 22:52:55,263 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:52:55,287 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:52:55,288 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:52:56,240 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:52:56,240 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:52:56,242 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:52:56,242 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:52:56,242 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:52:56,242 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:52:56,243 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:52:56,262 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:53:14,415 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:53:14,440 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:53:14,442 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:53:14,442 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:53:14,443 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:53:14,443 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:53:14,443 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:53:14,443 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:53:14,443 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:53:14,443 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 1000 mapavg_~i~0) (<= 0 mapavg_~i~0) (= (ite (<= (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) 2147483647) (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (+ (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 1000))) [2019-10-06 22:53:14,444 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:53:14,444 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:14,444 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:14,444 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:14,444 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:53:14,444 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:53:14,444 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:53:14,445 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:53:14,445 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1465 Int) (v_mapavg_~ret~0_BEFORE_RETURN_131 Int)) (or (and (= (mod (+ (div v_prenex_1465 1000) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (not (= (mod v_prenex_1465 1000) 0)) (<= (mod (+ (div v_prenex_1465 1000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1465 1000) 4294967296) 2147483647) (< v_prenex_1465 0)) (and (= (mod (+ (div v_prenex_1465 1000) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (not (= (mod v_prenex_1465 1000) 0)) (<= (mod (+ (div v_prenex_1465 1000) 1) 4294967296) 2147483647) (< v_prenex_1465 0) (not (<= (mod (div v_prenex_1465 1000) 4294967296) 2147483647))) (and (= (+ (mod (div v_prenex_1465 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_prenex_1465 1000) 0) (not (< main_~i~1 1000)) (<= (mod (+ (div v_prenex_1465 1000) 1) 4294967296) 2147483647) (not (<= (mod (div v_prenex_1465 1000) 4294967296) 2147483647))) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 1) 4294967296) 2147483647))) (and (< v_mapavg_~ret~0_BEFORE_RETURN_131 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 0)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 1000)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 0) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 4294967296) |main_#t~ret4|) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 4294967296) 2147483647) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 1) 4294967296) 2147483647))) (and (= (+ (mod (div v_prenex_1465 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 1000)) (<= (mod (+ (div v_prenex_1465 1000) 1) 4294967296) 2147483647) (not (< v_prenex_1465 0)) (not (<= (mod (div v_prenex_1465 1000) 4294967296) 2147483647))) (and (= (mod v_prenex_1465 1000) 0) (not (< main_~i~1 1000)) (<= (mod (div v_prenex_1465 1000) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_1465 1000) 1) 4294967296) 2147483647) (= (mod (div v_prenex_1465 1000) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 1000)) (<= (mod (+ (div v_prenex_1465 1000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1465 1000) 4294967296) 2147483647) (= (mod (div v_prenex_1465 1000) 4294967296) |main_#t~ret4|) (not (< v_prenex_1465 0))) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_131 0)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 1) 4294967296) 2147483647))) (and (< v_mapavg_~ret~0_BEFORE_RETURN_131 0) (not (< main_~i~1 1000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 0)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 1) 4294967296) (- 4294967296))) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 4294967296) 2147483647) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 1) 4294967296) 2147483647))) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_131 0)) (not (< main_~i~1 1000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 4294967296) |main_#t~ret4|) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 4294967296) 2147483647) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 1000) 1) 4294967296) 2147483647))))) (exists ((v_prenex_1466 Int) (v_mapavg_~ret~0_BEFORE_RETURN_132 Int)) (or (and (<= (mod (div v_prenex_1466 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= |main_#t~ret4| (mod (div v_prenex_1466 1000) 4294967296)) (not (< v_prenex_1466 0))) (and (= (mod v_prenex_1466 1000) 0) (<= (mod (div v_prenex_1466 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= |main_#t~ret4| (mod (div v_prenex_1466 1000) 4294967296))) (and (= (mod v_prenex_1466 1000) 0) (= |main_#t~ret4| (+ (mod (div v_prenex_1466 1000) 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (not (<= (mod (div v_prenex_1466 1000) 4294967296) 2147483647))) (and (= |main_#t~ret4| (+ (mod (div v_prenex_1466 1000) 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (not (<= (mod (div v_prenex_1466 1000) 4294967296) 2147483647)) (not (< v_prenex_1466 0))) (and (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 1000) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_132 1000) 0)) (not (< main_~i~1 1000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 1000) 1) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_132 0)) (and (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_132 1000) 0)) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 1000) 1) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_132 0))))) [2019-10-06 22:53:14,445 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:53:14,445 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:53:14,445 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:53:14,446 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:53:16,862 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:53:16,862 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-06 22:53:16,864 INFO L442 AbstractCegarLoop]: Interpolant automaton has 69 states [2019-10-06 22:53:16,865 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2019-10-06 22:53:16,866 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1736, Invalid=2955, Unknown=1, NotChecked=0, Total=4692 [2019-10-06 22:53:16,867 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 69 states. [2019-10-06 22:53:48,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:53:48,115 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-06 22:53:48,117 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2019-10-06 22:53:48,117 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 67 [2019-10-06 22:53:48,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:53:48,118 INFO L225 Difference]: With dead ends: 104 [2019-10-06 22:53:48,118 INFO L226 Difference]: Without dead ends: 83 [2019-10-06 22:53:48,123 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 295 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3688 ImplicationChecksByTransitivity, 18.5s TimeCoverageRelationStatistics Valid=5089, Invalid=12196, Unknown=7, NotChecked=0, Total=17292 [2019-10-06 22:53:48,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-06 22:53:48,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-06 22:53:48,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-06 22:53:48,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-06 22:53:48,132 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-06 22:53:48,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:53:48,133 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-06 22:53:48,133 INFO L463 AbstractCegarLoop]: Interpolant automaton has 69 states. [2019-10-06 22:53:48,133 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-06 22:53:48,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-06 22:53:48,135 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:53:48,135 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:53:48,337 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:53:48,338 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:53:48,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:53:48,339 INFO L82 PathProgramCache]: Analyzing trace with hash -421590573, now seen corresponding path program 7 times [2019-10-06 22:53:48,339 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:53:48,339 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:53:48,339 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:53:48,340 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:53:48,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:53:48,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:53:49,719 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:49,719 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:53:49,719 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:53:49,719 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:53:50,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:53:50,004 INFO L256 TraceCheckSpWp]: Trace formula consists of 529 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-06 22:53:50,008 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:53:50,026 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:50,027 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:53:53,669 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:53,669 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:53:53,671 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:53:53,671 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:53:53,671 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:53:53,671 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:53:53,672 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:53:53,684 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:54:10,393 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:54:10,422 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:54:10,425 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:54:10,425 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:54:10,425 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:54:10,425 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:54:10,425 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:54:10,426 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:54:10,426 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:54:10,426 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 1000 mapavg_~i~0) (<= 0 mapavg_~i~0) (= (ite (<= (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) 2147483647) (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (+ (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 1000))) [2019-10-06 22:54:10,426 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:54:10,426 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:10,426 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:10,427 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:10,427 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:54:10,427 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:54:10,427 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:54:10,427 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:54:10,427 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_157 Int) (v_prenex_1801 Int)) (or (and (<= (mod (div v_prenex_1801 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod (div v_prenex_1801 1000) 4294967296) |main_#t~ret4|) (= (mod v_prenex_1801 1000) 0)) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 1000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 1000) 1) 4294967296) (- 4294967296))) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_157 1000) 0)) (not (< main_~i~1 1000)) (< v_mapavg_~ret~0_BEFORE_RETURN_157 0)) (and (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 1000) 1) 4294967296)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_157 1000) 0)) (not (< main_~i~1 1000)) (< v_mapavg_~ret~0_BEFORE_RETURN_157 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 1000) 1) 4294967296) 2147483647)) (and (<= (mod (div v_prenex_1801 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (not (< v_prenex_1801 0)) (= (mod (div v_prenex_1801 1000) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (div v_prenex_1801 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (not (< v_prenex_1801 0)) (= |main_#t~ret4| (+ (mod (div v_prenex_1801 1000) 4294967296) (- 4294967296)))) (and (not (<= (mod (div v_prenex_1801 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= |main_#t~ret4| (+ (mod (div v_prenex_1801 1000) 4294967296) (- 4294967296))) (= (mod v_prenex_1801 1000) 0)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1802 Int)) (or (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 1) 4294967296) 2147483647) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 4294967296) |main_#t~ret4|) (not (< v_mapavg_~ret~0_BEFORE_RETURN_158 0))) (and (<= (mod (div v_prenex_1802 1000) 4294967296) 2147483647) (not (= (mod v_prenex_1802 1000) 0)) (not (<= (mod (+ (div v_prenex_1802 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1802 1000) 1) 4294967296) (- 4294967296))) (< v_prenex_1802 0)) (and (= (mod v_prenex_1802 1000) 0) (<= (mod (div v_prenex_1802 1000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_1802 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= (mod (div v_prenex_1802 1000) 4294967296) |main_#t~ret4|)) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 4294967296) 2147483647)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 4294967296) (- 4294967296))) (not (< main_~i~1 1000))) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 1) 4294967296) 2147483647) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 1) 4294967296) 2147483647) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 4294967296) 2147483647) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 0)) (not (< main_~i~1 1000)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_158 0)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 4294967296) 2147483647)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 1) 4294967296) 2147483647) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 0)) (not (< main_~i~1 1000)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_158 0)) (and (= (mod v_prenex_1802 1000) 0) (not (<= (mod (+ (div v_prenex_1802 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= |main_#t~ret4| (+ (mod (div v_prenex_1802 1000) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_1802 1000) 4294967296) 2147483647))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 4294967296) 2147483647)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 1000) 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_158 0))) (and (not (< v_prenex_1802 0)) (not (<= (mod (+ (div v_prenex_1802 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= |main_#t~ret4| (+ (mod (div v_prenex_1802 1000) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_1802 1000) 4294967296) 2147483647))) (and (not (= (mod v_prenex_1802 1000) 0)) (not (<= (mod (+ (div v_prenex_1802 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1802 1000) 1) 4294967296) (- 4294967296))) (< v_prenex_1802 0) (not (<= (mod (div v_prenex_1802 1000) 4294967296) 2147483647))) (and (not (< v_prenex_1802 0)) (<= (mod (div v_prenex_1802 1000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_1802 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= (mod (div v_prenex_1802 1000) 4294967296) |main_#t~ret4|))))) [2019-10-06 22:54:10,428 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:54:10,428 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:54:10,428 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:54:10,428 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:54:13,045 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:54:13,046 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 127 [2019-10-06 22:54:13,047 INFO L442 AbstractCegarLoop]: Interpolant automaton has 127 states [2019-10-06 22:54:13,049 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 127 interpolants. [2019-10-06 22:54:13,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6811, Invalid=9190, Unknown=1, NotChecked=0, Total=16002 [2019-10-06 22:54:13,053 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 127 states. [2019-10-06 22:54:46,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:54:46,635 INFO L93 Difference]: Finished difference Result 162 states and 227 transitions. [2019-10-06 22:54:46,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 126 states. [2019-10-06 22:54:46,637 INFO L78 Accepts]: Start accepts. Automaton has 127 states. Word has length 96 [2019-10-06 22:54:46,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:54:46,638 INFO L225 Difference]: With dead ends: 162 [2019-10-06 22:54:46,638 INFO L226 Difference]: Without dead ends: 141 [2019-10-06 22:54:46,644 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 223 SyntacticMatches, 0 SemanticMatches, 246 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11605 ImplicationChecksByTransitivity, 26.4s TimeCoverageRelationStatistics Valid=20198, Invalid=41052, Unknown=6, NotChecked=0, Total=61256 [2019-10-06 22:54:46,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2019-10-06 22:54:46,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2019-10-06 22:54:46,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2019-10-06 22:54:46,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 145 transitions. [2019-10-06 22:54:46,659 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 145 transitions. Word has length 96 [2019-10-06 22:54:46,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:54:46,659 INFO L462 AbstractCegarLoop]: Abstraction has 141 states and 145 transitions. [2019-10-06 22:54:46,659 INFO L463 AbstractCegarLoop]: Interpolant automaton has 127 states. [2019-10-06 22:54:46,659 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 145 transitions. [2019-10-06 22:54:46,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2019-10-06 22:54:46,661 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:54:46,661 INFO L385 BasicCegarLoop]: trace histogram [114, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:54:46,867 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:54:46,868 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:54:46,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:54:46,868 INFO L82 PathProgramCache]: Analyzing trace with hash 1491638739, now seen corresponding path program 8 times [2019-10-06 22:54:46,869 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:54:46,869 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:54:46,869 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:46,870 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:46,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:54:47,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:54:52,091 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 0 proven. 6555 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:54:52,091 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:54:52,091 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:54:52,091 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:54:52,393 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:54:52,394 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:54:52,394 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 22:54:52,399 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:54:52,645 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 22:54:52,646 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:54:52,944 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 22:54:52,944 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:54:52,945 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:54:52,945 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:54:52,946 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:54:52,946 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:54:52,946 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:54:52,961 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:55:10,698 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:55:10,718 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:55:10,720 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:55:10,720 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:55:10,720 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:55:10,720 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:55:10,720 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:55:10,720 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:55:10,720 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:55:10,721 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 1000 mapavg_~i~0) (<= 0 mapavg_~i~0) (= (ite (<= (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) 2147483647) (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (+ (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 1000))) [2019-10-06 22:55:10,721 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:55:10,721 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:10,721 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:10,721 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:10,721 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:55:10,721 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:55:10,721 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:55:10,721 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:55:10,722 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2126 Int) (v_mapavg_~ret~0_BEFORE_RETURN_184 Int)) (or (and (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_184 1000) 0)) (not (< main_~i~1 1000)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 1000) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_184 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 1000) 1) 4294967296) 2147483647)) (and (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_184 1000) 0)) (not (< main_~i~1 1000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 1000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 1000) 1) 4294967296) (- 4294967296))) (< v_mapavg_~ret~0_BEFORE_RETURN_184 0)) (and (not (< v_prenex_2126 0)) (= |main_#t~ret4| (mod (div v_prenex_2126 1000) 4294967296)) (not (< main_~i~1 1000)) (<= (mod (div v_prenex_2126 1000) 4294967296) 2147483647)) (and (= |main_#t~ret4| (mod (div v_prenex_2126 1000) 4294967296)) (not (< main_~i~1 1000)) (= (mod v_prenex_2126 1000) 0) (<= (mod (div v_prenex_2126 1000) 4294967296) 2147483647)) (and (not (< v_prenex_2126 0)) (not (<= (mod (div v_prenex_2126 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= |main_#t~ret4| (+ (mod (div v_prenex_2126 1000) 4294967296) (- 4294967296)))) (and (not (<= (mod (div v_prenex_2126 1000) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= (mod v_prenex_2126 1000) 0) (= |main_#t~ret4| (+ (mod (div v_prenex_2126 1000) 4294967296) (- 4294967296)))))) (exists ((v_prenex_2125 Int) (v_mapavg_~ret~0_BEFORE_RETURN_183 Int)) (or (and (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_183 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 4294967296) 2147483647)) (and (< v_prenex_2125 0) (not (< main_~i~1 1000)) (= (mod (+ (div v_prenex_2125 1000) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_2125 1000) 1) 4294967296) 2147483647) (not (<= (mod (div v_prenex_2125 1000) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_2125 1000)))) (and (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 1) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_183 0)) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 4294967296) 2147483647)) (and (< v_prenex_2125 0) (not (< main_~i~1 1000)) (= (mod (+ (div v_prenex_2125 1000) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_2125 1000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_2125 1000) 4294967296) 2147483647) (not (= 0 (mod v_prenex_2125 1000)))) (and (= (mod (div v_prenex_2125 1000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (not (< v_prenex_2125 0)) (<= (mod (+ (div v_prenex_2125 1000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_2125 1000) 4294967296) 2147483647)) (and (= (mod (div v_prenex_2125 1000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (<= (mod (+ (div v_prenex_2125 1000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_2125 1000) 4294967296) 2147483647) (= 0 (mod v_prenex_2125 1000))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 1) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_183 0)) (not (< main_~i~1 1000)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 1000)) (<= (mod (+ (div v_prenex_2125 1000) 1) 4294967296) 2147483647) (not (<= (mod (div v_prenex_2125 1000) 4294967296) 2147483647)) (= 0 (mod v_prenex_2125 1000)) (= |main_#t~ret4| (+ (mod (div v_prenex_2125 1000) 4294967296) (- 4294967296)))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (< v_mapavg_~ret~0_BEFORE_RETURN_183 0) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_183 1000))) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 4294967296) 2147483647)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_183 1000)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 1000)) (not (< v_prenex_2125 0)) (<= (mod (+ (div v_prenex_2125 1000) 1) 4294967296) 2147483647) (not (<= (mod (div v_prenex_2125 1000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_2125 1000) 4294967296) (- 4294967296)))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (< v_mapavg_~ret~0_BEFORE_RETURN_183 0) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_183 1000))) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|))))) [2019-10-06 22:55:10,722 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:55:10,722 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:55:10,722 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:55:10,722 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:55:13,798 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:55:13,799 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [117, 7, 7, 11] total 137 [2019-10-06 22:55:13,800 INFO L442 AbstractCegarLoop]: Interpolant automaton has 137 states [2019-10-06 22:55:13,802 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 137 interpolants. [2019-10-06 22:55:13,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6876, Invalid=11755, Unknown=1, NotChecked=0, Total=18632 [2019-10-06 22:55:13,803 INFO L87 Difference]: Start difference. First operand 141 states and 145 transitions. Second operand 137 states. [2019-10-06 22:55:52,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:55:52,885 INFO L93 Difference]: Finished difference Result 169 states and 186 transitions. [2019-10-06 22:55:52,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 137 states. [2019-10-06 22:55:52,887 INFO L78 Accepts]: Start accepts. Automaton has 137 states. Word has length 154 [2019-10-06 22:55:52,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:55:52,889 INFO L225 Difference]: With dead ends: 169 [2019-10-06 22:55:52,889 INFO L226 Difference]: Without dead ends: 148 [2019-10-06 22:55:52,893 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 710 GetRequests, 443 SyntacticMatches, 0 SemanticMatches, 267 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11913 ImplicationChecksByTransitivity, 32.0s TimeCoverageRelationStatistics Valid=20684, Invalid=51401, Unknown=7, NotChecked=0, Total=72092 [2019-10-06 22:55:52,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2019-10-06 22:55:52,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 148. [2019-10-06 22:55:52,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2019-10-06 22:55:52,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 152 transitions. [2019-10-06 22:55:52,908 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 152 transitions. Word has length 154 [2019-10-06 22:55:52,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:55:52,909 INFO L462 AbstractCegarLoop]: Abstraction has 148 states and 152 transitions. [2019-10-06 22:55:52,909 INFO L463 AbstractCegarLoop]: Interpolant automaton has 137 states. [2019-10-06 22:55:52,909 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 152 transitions. [2019-10-06 22:55:52,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2019-10-06 22:55:52,911 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:55:52,911 INFO L385 BasicCegarLoop]: trace histogram [115, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:55:53,112 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:55:53,112 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:55:53,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:55:53,112 INFO L82 PathProgramCache]: Analyzing trace with hash 1419883091, now seen corresponding path program 9 times [2019-10-06 22:55:53,112 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:55:53,113 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:55:53,113 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:55:53,113 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:55:53,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:55:53,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:55:58,351 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:55:58,352 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:55:58,352 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:55:58,352 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:55:58,782 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:55:58,784 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:55:58,790 INFO L256 TraceCheckSpWp]: Trace formula consists of 973 conjuncts, 117 conjunts are in the unsatisfiable core [2019-10-06 22:55:58,797 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:55:58,837 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:55:58,837 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:56:13,890 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:56:13,890 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:56:13,891 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:56:13,892 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:56:13,892 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:56:13,892 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:56:13,892 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:56:13,907 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:56:35,604 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:56:35,621 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:56:35,624 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:56:35,624 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:56:35,624 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:56:35,624 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:56:35,624 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:56:35,625 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:56:35,625 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:56:35,625 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 1000 mapavg_~i~0) (<= 0 mapavg_~i~0) (= (ite (<= (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) 2147483647) (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (+ (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 1000))) [2019-10-06 22:56:35,625 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:56:35,625 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:35,625 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:56:35,626 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:35,626 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:56:35,626 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:56:35,626 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:56:35,626 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:56:35,626 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2431 Int) (v_mapavg_~ret~0_BEFORE_RETURN_209 Int)) (or (and (= (+ (mod (+ (div v_prenex_2431 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_2431 1000) 1) 4294967296) 2147483647)) (not (= (mod v_prenex_2431 1000) 0)) (< v_prenex_2431 0) (not (< main_~i~1 1000)) (not (<= (mod (div v_prenex_2431 1000) 4294967296) 2147483647))) (and (not (<= (mod (+ (div v_prenex_2431 1000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_2431 1000) 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (= (mod v_prenex_2431 1000) 0) (not (<= (mod (div v_prenex_2431 1000) 4294967296) 2147483647))) (and (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 4294967296) 2147483647)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 1) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 1) 4294967296)) (< v_mapavg_~ret~0_BEFORE_RETURN_209 0)) (and (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 4294967296) 2147483647) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 1) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 1) 4294967296)) (< v_mapavg_~ret~0_BEFORE_RETURN_209 0)) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 4294967296) 2147483647) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 1) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_209 0)) (not (< main_~i~1 1000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (+ (div v_prenex_2431 1000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2431 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod v_prenex_2431 1000) 0) (= (mod (div v_prenex_2431 1000) 4294967296) |main_#t~ret4|)) (and (= (+ (mod (+ (div v_prenex_2431 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_2431 1000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2431 1000) 4294967296) 2147483647) (not (= (mod v_prenex_2431 1000) 0)) (< v_prenex_2431 0) (not (< main_~i~1 1000))) (and (not (<= (mod (+ (div v_prenex_2431 1000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2431 1000) 4294967296) 2147483647) (not (< main_~i~1 1000)) (not (< v_prenex_2431 0)) (= (mod (div v_prenex_2431 1000) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (+ (div v_prenex_2431 1000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_2431 1000) 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (not (< v_prenex_2431 0)) (not (<= (mod (div v_prenex_2431 1000) 4294967296) 2147483647))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 4294967296) 2147483647)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 1) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 0) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 4294967296) (- 4294967296)))) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 4294967296) 2147483647) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 1) 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 4294967296) |main_#t~ret4|) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 0)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 4294967296) 2147483647)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 1) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_209 0)) (not (< main_~i~1 1000)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 1000) 4294967296) (- 4294967296)))))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_210 Int) (v_prenex_2432 Int)) (or (and (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 1000) 4294967296) |main_#t~ret4|) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_210 1000) 0) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 1000) 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (= (mod (+ (div v_prenex_2432 1000) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_2432 1000) 1) 4294967296) 2147483647) (< v_prenex_2432 0) (not (= (mod v_prenex_2432 1000) 0))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 1000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 1000) 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_210 0))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 1000) 4294967296) 2147483647)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_210 1000) 0) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 1000) 4294967296) (- 4294967296))) (not (< main_~i~1 1000))) (and (not (< main_~i~1 1000)) (< v_prenex_2432 0) (not (<= (mod (+ (div v_prenex_2432 1000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_2432 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_prenex_2432 1000) 0))) (and (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 1000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_210 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 1000) 4294967296) 2147483647))))) [2019-10-06 22:56:35,627 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:56:35,627 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:56:35,627 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:56:35,627 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:56:36,707 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:56:36,708 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [118, 118, 118, 11] total 245 [2019-10-06 22:56:36,709 INFO L442 AbstractCegarLoop]: Interpolant automaton has 245 states [2019-10-06 22:56:36,716 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 245 interpolants. [2019-10-06 22:56:36,719 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27520, Invalid=32260, Unknown=0, NotChecked=0, Total=59780 [2019-10-06 22:56:36,719 INFO L87 Difference]: Start difference. First operand 148 states and 152 transitions. Second operand 245 states. [2019-10-06 22:57:35,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:57:35,308 INFO L93 Difference]: Finished difference Result 292 states and 416 transitions. [2019-10-06 22:57:35,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 244 states. [2019-10-06 22:57:35,310 INFO L78 Accepts]: Start accepts. Automaton has 245 states. Word has length 173 [2019-10-06 22:57:35,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:57:35,312 INFO L225 Difference]: With dead ends: 292 [2019-10-06 22:57:35,313 INFO L226 Difference]: Without dead ends: 265 [2019-10-06 22:57:35,320 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 877 GetRequests, 395 SyntacticMatches, 0 SemanticMatches, 482 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40692 ImplicationChecksByTransitivity, 64.0s TimeCoverageRelationStatistics Valid=82089, Invalid=151677, Unknown=6, NotChecked=0, Total=233772 [2019-10-06 22:57:35,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2019-10-06 22:57:35,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 265. [2019-10-06 22:57:35,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2019-10-06 22:57:35,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 269 transitions. [2019-10-06 22:57:35,342 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 269 transitions. Word has length 173 [2019-10-06 22:57:35,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:57:35,342 INFO L462 AbstractCegarLoop]: Abstraction has 265 states and 269 transitions. [2019-10-06 22:57:35,343 INFO L463 AbstractCegarLoop]: Interpolant automaton has 245 states. [2019-10-06 22:57:35,343 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 269 transitions. [2019-10-06 22:57:35,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2019-10-06 22:57:35,346 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:57:35,347 INFO L385 BasicCegarLoop]: trace histogram [232, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:57:35,553 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:57:35,554 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:57:35,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:57:35,554 INFO L82 PathProgramCache]: Analyzing trace with hash -424031277, now seen corresponding path program 10 times [2019-10-06 22:57:35,555 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:57:35,555 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:57:35,555 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:57:35,555 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:57:35,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:57:36,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:57:56,277 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:57:56,277 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:57:56,277 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:57:56,277 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:57:56,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:57:56,906 INFO L256 TraceCheckSpWp]: Trace formula consists of 1675 conjuncts, 234 conjunts are in the unsatisfiable core [2019-10-06 22:57:56,914 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:57:56,982 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:57:56,983 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:58:57,744 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:58:57,745 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:58:57,750 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:58:57,751 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:58:57,751 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:58:57,751 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:58:57,751 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:58:57,778 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:59:03,616 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:59:03,631 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:59:03,634 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:59:03,634 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:59:03,634 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 22:59:03,634 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:59:03,634 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:59:03,635 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:59:03,635 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:59:03,635 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 1000 mapavg_~i~0) (<= 0 mapavg_~i~0) (= (ite (<= (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) 2147483647) (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (+ (mod (ite (and (not (= (mod mapavg_~ret~0 1000) 0)) (< mapavg_~ret~0 0)) (+ (div mapavg_~ret~0 1000) 1) (div mapavg_~ret~0 1000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 1000))) [2019-10-06 22:59:03,635 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:59:03,635 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:59:03,635 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:59:03,635 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:59:03,635 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:59:03,636 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:59:03,636 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 22:59:03,636 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:59:03,636 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_235 Int) (v_prenex_2707 Int)) (or (and (<= (mod (div v_prenex_2707 1000) 4294967296) 2147483647) (= (mod (div v_prenex_2707 1000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (not (< v_prenex_2707 0))) (and (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 1000) 1) 4294967296)) (not (< main_~i~1 1000)) (< v_mapavg_~ret~0_BEFORE_RETURN_235 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_235 1000) 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 1000) 1) 4294967296) 2147483647)) (and (<= (mod (div v_prenex_2707 1000) 4294967296) 2147483647) (= (mod v_prenex_2707 1000) 0) (= (mod (div v_prenex_2707 1000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000))) (and (not (<= (mod (div v_prenex_2707 1000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_2707 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_prenex_2707 1000) 0) (not (< main_~i~1 1000))) (and (not (<= (mod (div v_prenex_2707 1000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_2707 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 1000)) (not (< v_prenex_2707 0))) (and (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 1000) 1) 4294967296) 2147483647)) (not (< main_~i~1 1000)) (< v_mapavg_~ret~0_BEFORE_RETURN_235 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_235 1000) 0))))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_2708 Int)) (or (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_236 0)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 1000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 1000) 4294967296) 2147483647)) (and (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 1000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 1000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 1000) 4294967296) 2147483647) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_236 1000))) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 1000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_236 1000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 1000) 4294967296) 2147483647))) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_236 0)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 1000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 1000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 1000) 4294967296) 2147483647))) (and (not (= 0 (mod v_prenex_2708 1000))) (not (< main_~i~1 1000)) (<= (mod (+ (div v_prenex_2708 1000) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_2708 1000) 1) 4294967296) |main_#t~ret4|) (< v_prenex_2708 0)) (and (not (= 0 (mod v_prenex_2708 1000))) (not (< main_~i~1 1000)) (= (+ (mod (+ (div v_prenex_2708 1000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_2708 1000) 1) 4294967296) 2147483647)) (< v_prenex_2708 0))))) [2019-10-06 22:59:03,636 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:59:03,636 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:59:03,636 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:59:03,636 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:59:07,345 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:59:07,345 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [235, 235, 235, 11] total 479 [2019-10-06 22:59:07,347 INFO L442 AbstractCegarLoop]: Interpolant automaton has 479 states [2019-10-06 22:59:07,356 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 479 interpolants. [2019-10-06 22:59:07,363 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=109771, Invalid=119190, Unknown=1, NotChecked=0, Total=228962 [2019-10-06 22:59:07,363 INFO L87 Difference]: Start difference. First operand 265 states and 269 transitions. Second operand 479 states. [2019-10-06 23:01:37,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:37,154 INFO L93 Difference]: Finished difference Result 526 states and 767 transitions. [2019-10-06 23:01:37,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 478 states. [2019-10-06 23:01:37,156 INFO L78 Accepts]: Start accepts. Automaton has 479 states. Word has length 290 [2019-10-06 23:01:37,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:37,163 INFO L225 Difference]: With dead ends: 526 [2019-10-06 23:01:37,163 INFO L226 Difference]: Without dead ends: 499 [2019-10-06 23:01:37,190 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1579 GetRequests, 629 SyntacticMatches, 0 SemanticMatches, 950 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 149853 ImplicationChecksByTransitivity, 207.0s TimeCoverageRelationStatistics Valid=328374, Invalid=576972, Unknown=6, NotChecked=0, Total=905352 [2019-10-06 23:01:37,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 499 states. [2019-10-06 23:01:37,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 499 to 499. [2019-10-06 23:01:37,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 499 states. [2019-10-06 23:01:37,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 499 states to 499 states and 503 transitions. [2019-10-06 23:01:37,216 INFO L78 Accepts]: Start accepts. Automaton has 499 states and 503 transitions. Word has length 290 [2019-10-06 23:01:37,217 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:37,217 INFO L462 AbstractCegarLoop]: Abstraction has 499 states and 503 transitions. [2019-10-06 23:01:37,217 INFO L463 AbstractCegarLoop]: Interpolant automaton has 479 states. [2019-10-06 23:01:37,217 INFO L276 IsEmpty]: Start isEmpty. Operand 499 states and 503 transitions. [2019-10-06 23:01:37,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 525 [2019-10-06 23:01:37,228 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:37,228 INFO L385 BasicCegarLoop]: trace histogram [466, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:37,429 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:37,429 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:37,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:37,430 INFO L82 PathProgramCache]: Analyzing trace with hash 466017235, now seen corresponding path program 11 times [2019-10-06 23:01:37,430 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:37,431 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:37,431 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:37,431 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:37,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:39,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat