java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/array-crafted/mapavg3.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-06 22:48:37,322 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-06 22:48:37,326 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-06 22:48:37,344 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-06 22:48:37,345 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-06 22:48:37,347 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-06 22:48:37,349 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-06 22:48:37,358 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-06 22:48:37,364 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-06 22:48:37,367 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-06 22:48:37,369 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-06 22:48:37,370 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-06 22:48:37,371 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-06 22:48:37,372 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-06 22:48:37,375 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-06 22:48:37,377 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-06 22:48:37,378 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-06 22:48:37,379 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-06 22:48:37,380 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-06 22:48:37,385 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-06 22:48:37,388 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-06 22:48:37,389 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-06 22:48:37,392 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-06 22:48:37,393 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-06 22:48:37,395 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-06 22:48:37,402 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-06 22:48:37,403 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-06 22:48:37,404 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-06 22:48:37,404 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-06 22:48:37,418 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-06 22:48:37,419 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-06 22:48:37,420 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-06 22:48:37,420 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-06 22:48:37,420 INFO L138 SettingsManager]: * Use SBE=true [2019-10-06 22:48:37,421 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-06 22:48:37,421 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-06 22:48:37,421 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-06 22:48:37,421 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-06 22:48:37,421 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-06 22:48:37,422 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-06 22:48:37,422 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-06 22:48:37,422 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-06 22:48:37,422 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-06 22:48:37,422 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-06 22:48:37,423 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-06 22:48:37,423 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-06 22:48:37,423 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-06 22:48:37,423 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-06 22:48:37,423 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-06 22:48:37,424 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-06 22:48:37,424 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:37,424 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-06 22:48:37,424 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-06 22:48:37,424 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-06 22:48:37,425 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-06 22:48:37,425 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-06 22:48:37,425 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-06 22:48:37,425 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-06 22:48:37,702 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-06 22:48:37,716 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-06 22:48:37,720 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-06 22:48:37,721 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-06 22:48:37,722 INFO L275 PluginConnector]: CDTParser initialized [2019-10-06 22:48:37,723 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-crafted/mapavg3.i [2019-10-06 22:48:37,805 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/62832b17c/4c930215256d48a8a9ff3a856041a4cf/FLAG436b45f92 [2019-10-06 22:48:38,275 INFO L306 CDTParser]: Found 1 translation units. [2019-10-06 22:48:38,277 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-crafted/mapavg3.i [2019-10-06 22:48:38,283 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/62832b17c/4c930215256d48a8a9ff3a856041a4cf/FLAG436b45f92 [2019-10-06 22:48:38,608 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/62832b17c/4c930215256d48a8a9ff3a856041a4cf [2019-10-06 22:48:38,618 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-06 22:48:38,620 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-06 22:48:38,621 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,621 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-06 22:48:38,624 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-06 22:48:38,625 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,628 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@261d964e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38, skipping insertion in model container [2019-10-06 22:48:38,629 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,636 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-06 22:48:38,658 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-06 22:48:38,917 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,930 INFO L188 MainTranslator]: Completed pre-run [2019-10-06 22:48:38,960 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,976 INFO L192 MainTranslator]: Completed translation [2019-10-06 22:48:38,977 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38 WrapperNode [2019-10-06 22:48:38,977 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,978 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-06 22:48:38,978 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-06 22:48:38,978 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-06 22:48:39,081 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,081 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,091 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,093 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,109 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,114 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,116 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:39,118 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-06 22:48:39,119 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-06 22:48:39,119 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-06 22:48:39,119 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-06 22:48:39,120 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:39,183 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-06 22:48:39,184 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-06 22:48:39,184 INFO L138 BoogieDeclarations]: Found implementation of procedure mapavg [2019-10-06 22:48:39,184 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-06 22:48:39,184 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-06 22:48:39,185 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-06 22:48:39,185 INFO L130 BoogieDeclarations]: Found specification of procedure mapavg [2019-10-06 22:48:39,185 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-06 22:48:39,185 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-06 22:48:39,185 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-06 22:48:39,185 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-06 22:48:39,186 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-06 22:48:39,186 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-06 22:48:39,186 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-06 22:48:39,593 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-06 22:48:39,593 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-06 22:48:39,595 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39 BoogieIcfgContainer [2019-10-06 22:48:39,595 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-06 22:48:39,596 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-06 22:48:39,597 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-06 22:48:39,600 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-06 22:48:39,600 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.10 10:48:38" (1/3) ... [2019-10-06 22:48:39,601 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@77d43de4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,601 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38" (2/3) ... [2019-10-06 22:48:39,602 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@77d43de4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,602 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39" (3/3) ... [2019-10-06 22:48:39,604 INFO L109 eAbstractionObserver]: Analyzing ICFG mapavg3.i [2019-10-06 22:48:39,613 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-06 22:48:39,619 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-06 22:48:39,631 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-06 22:48:39,656 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-06 22:48:39,657 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-06 22:48:39,657 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-06 22:48:39,657 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-06 22:48:39,657 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-06 22:48:39,658 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-06 22:48:39,658 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-06 22:48:39,658 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-06 22:48:39,677 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-06 22:48:39,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-06 22:48:39,683 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,684 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,685 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,690 INFO L82 PathProgramCache]: Analyzing trace with hash -1953355565, now seen corresponding path program 1 times [2019-10-06 22:48:39,697 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,697 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,697 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,698 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,881 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-06 22:48:39,882 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,883 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:39,883 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:39,888 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:39,901 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:39,902 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,903 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-06 22:48:39,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:39,934 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-06 22:48:39,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:39,936 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-06 22:48:39,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:39,946 INFO L225 Difference]: With dead ends: 41 [2019-10-06 22:48:39,946 INFO L226 Difference]: Without dead ends: 20 [2019-10-06 22:48:39,950 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-06 22:48:39,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-06 22:48:39,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-06 22:48:39,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-06 22:48:39,991 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-06 22:48:39,991 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:39,991 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-06 22:48:39,992 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:39,992 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-06 22:48:39,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-06 22:48:39,994 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,994 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,994 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,995 INFO L82 PathProgramCache]: Analyzing trace with hash -1072677037, now seen corresponding path program 1 times [2019-10-06 22:48:39,995 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,996 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,996 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,996 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,109 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,110 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,110 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:40,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,183 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,190 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,219 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,220 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,263 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,263 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-06 22:48:40,263 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-06 22:48:40,265 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,265 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,266 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,266 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-06 22:48:40,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,277 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-06 22:48:40,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,278 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-06 22:48:40,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,279 INFO L225 Difference]: With dead ends: 33 [2019-10-06 22:48:40,279 INFO L226 Difference]: Without dead ends: 21 [2019-10-06 22:48:40,280 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-06 22:48:40,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-06 22:48:40,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-06 22:48:40,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-06 22:48:40,286 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-06 22:48:40,286 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,286 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-06 22:48:40,286 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,287 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-06 22:48:40,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-06 22:48:40,288 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,288 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,493 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,494 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,495 INFO L82 PathProgramCache]: Analyzing trace with hash 608739335, now seen corresponding path program 1 times [2019-10-06 22:48:40,495 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,495 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,495 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,495 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,600 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,600 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,600 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:40,601 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:40,601 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,602 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-06 22:48:40,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,621 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-06 22:48:40,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,623 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-06 22:48:40,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,624 INFO L225 Difference]: With dead ends: 31 [2019-10-06 22:48:40,624 INFO L226 Difference]: Without dead ends: 22 [2019-10-06 22:48:40,626 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-06 22:48:40,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-06 22:48:40,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-06 22:48:40,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-06 22:48:40,636 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-06 22:48:40,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,643 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-06 22:48:40,643 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,643 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-06 22:48:40,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-06 22:48:40,645 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,646 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,646 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,646 INFO L82 PathProgramCache]: Analyzing trace with hash -824983385, now seen corresponding path program 1 times [2019-10-06 22:48:40,647 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,647 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,647 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,647 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,764 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,764 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,765 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:40,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,877 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,882 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,901 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,901 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,940 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,941 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:40,972 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:40,973 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:40,983 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:40,998 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:40,998 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:41,225 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:20,844 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:49:20,876 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:20,880 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:20,880 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:20,880 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:49:20,881 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:49:20,881 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:20,881 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:20,881 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 0 mapavg_~i~0) (<= 10000 mapavg_~i~0) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 10000))) [2019-10-06 22:49:20,881 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:49:20,881 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:20,882 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:20,882 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:20,882 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:49:20,882 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:20,882 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:49:20,883 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:49:20,883 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2 Int) (v_mapavg_~ret~0_BEFORE_RETURN_2 Int)) (or (and (not (< main_~i~1 10000)) (= 0 (mod v_prenex_2 10000)) (= |main_#t~ret4| (+ (mod (div v_prenex_2 10000) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_2 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2 10000) 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (not (< v_prenex_2 0)) (<= (mod (div v_prenex_2 10000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2 10000) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_2 10000) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (not (= 0 (mod v_prenex_2 10000))) (= (+ (mod (+ (div v_prenex_2 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_2 10000) 1) 4294967296) 2147483647)) (< v_prenex_2 0) (not (<= (mod (div v_prenex_2 10000) 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (not (< v_prenex_2 0)) (= |main_#t~ret4| (+ (mod (div v_prenex_2 10000) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_2 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2 10000) 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 1) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (= 0 (mod v_prenex_2 10000)) (<= (mod (div v_prenex_2 10000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2 10000) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_2 10000) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 1) 4294967296) 2147483647) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_2 10000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 4294967296) 2147483647)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_2 10000))) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (and (not (< main_~i~1 10000)) (not (= 0 (mod v_prenex_2 10000))) (= (+ (mod (+ (div v_prenex_2 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (div v_prenex_2 10000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2 10000) 1) 4294967296) 2147483647)) (< v_prenex_2 0)) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 1) 4294967296) 2147483647) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_2 10000))) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 4294967296) 2147483647) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 1) 4294967296) 2147483647) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_2 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 10000) 4294967296) |main_#t~ret4|)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod (div v_prenex_1 10000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_1 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_1 10000) 1) 4294967296) 2147483647)) (= 0 (mod v_prenex_1 10000))) (and (<= (mod (div v_prenex_1 10000) 4294967296) 2147483647) (not (< main_~i~1 10000)) (not (< v_prenex_1 0)) (= |main_#t~ret4| (mod (div v_prenex_1 10000) 4294967296)) (not (<= (mod (+ (div v_prenex_1 10000) 1) 4294967296) 2147483647))) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_1 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_1 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 4294967296))) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_1 10000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 4294967296) 2147483647)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (not (< v_prenex_1 0)) (not (<= (mod (div v_prenex_1 10000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_1 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_1 10000) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 1) 4294967296)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 4294967296) 2147483647)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_1 10000))) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 1) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_1 0)) (and (not (< main_~i~1 10000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_1 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 4294967296) 2147483647) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 4294967296))) (and (not (< main_~i~1 10000)) (not (= 0 (mod v_prenex_1 10000))) (not (<= (mod (div v_prenex_1 10000) 4294967296) 2147483647)) (< v_prenex_1 0) (= (+ (mod (+ (div v_prenex_1 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_1 10000) 1) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_1 10000) 4294967296) 2147483647) (not (< main_~i~1 10000)) (not (= 0 (mod v_prenex_1 10000))) (< v_prenex_1 0) (= (+ (mod (+ (div v_prenex_1 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_1 10000) 1) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_1 10000) 4294967296) 2147483647) (not (< main_~i~1 10000)) (= |main_#t~ret4| (mod (div v_prenex_1 10000) 4294967296)) (not (<= (mod (+ (div v_prenex_1 10000) 1) 4294967296) 2147483647)) (= 0 (mod v_prenex_1 10000))) (and (not (< main_~i~1 10000)) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 1) 4294967296)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 4294967296) 2147483647) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_1 10000))) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 10000) 1) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_1 0))))) [2019-10-06 22:49:20,883 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:49:20,883 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:20,884 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:49:20,884 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:49:20,884 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:23,164 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:23,165 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 12] total 17 [2019-10-06 22:49:23,166 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-10-06 22:49:23,166 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-10-06 22:49:23,167 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=225, Unknown=1, NotChecked=0, Total=272 [2019-10-06 22:49:23,167 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 17 states. [2019-10-06 22:49:38,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:38,174 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-06 22:49:38,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-10-06 22:49:38,175 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 29 [2019-10-06 22:49:38,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:38,177 INFO L225 Difference]: With dead ends: 40 [2019-10-06 22:49:38,177 INFO L226 Difference]: Without dead ends: 25 [2019-10-06 22:49:38,178 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 167 ImplicationChecksByTransitivity, 8.9s TimeCoverageRelationStatistics Valid=123, Invalid=630, Unknown=3, NotChecked=0, Total=756 [2019-10-06 22:49:38,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-06 22:49:38,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-06 22:49:38,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-06 22:49:38,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-06 22:49:38,185 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-06 22:49:38,185 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:38,185 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-06 22:49:38,185 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-10-06 22:49:38,185 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-06 22:49:38,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-06 22:49:38,186 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:38,187 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:38,388 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:38,392 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:38,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:38,392 INFO L82 PathProgramCache]: Analyzing trace with hash 1686538791, now seen corresponding path program 2 times [2019-10-06 22:49:38,393 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:38,393 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:38,393 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:38,393 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:38,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:38,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:38,525 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:49:38,525 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:38,525 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:38,526 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:38,605 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-06 22:49:38,606 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:38,607 INFO L256 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:49:38,609 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:38,632 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:49:38,632 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:38,670 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:49:38,671 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:38,672 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:38,672 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:38,673 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:38,673 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:38,673 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:38,714 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:56,875 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:49:56,905 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:56,908 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:56,908 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:56,909 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:49:56,909 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:49:56,909 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:56,909 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:56,909 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 0 mapavg_~i~0) (<= 10000 mapavg_~i~0) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 10000))) [2019-10-06 22:49:56,910 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:49:56,910 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:56,910 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:56,916 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:56,917 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:49:56,917 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:56,917 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:49:56,917 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:49:56,918 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_361 Int)) (or (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 1) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_27 0)) (not (< main_~i~1 10000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (< v_prenex_361 0) (not (= 0 (mod v_prenex_361 10000))) (not (<= (mod (+ (div v_prenex_361 10000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_361 10000) 1) 4294967296) (- 4294967296))) (<= (mod (div v_prenex_361 10000) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= (+ (mod (div v_prenex_361 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_361 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_361 10000) 4294967296) 2147483647)) (= 0 (mod v_prenex_361 10000))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 1) 4294967296) 2147483647) (not (< main_~i~1 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 4294967296) 2147483647) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_27 10000))) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_27 0)) (and (not (< main_~i~1 10000)) (< v_prenex_361 0) (not (= 0 (mod v_prenex_361 10000))) (not (<= (mod (+ (div v_prenex_361 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_361 10000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_361 10000) 1) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (= (+ (mod (div v_prenex_361 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_361 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_361 10000) 4294967296) 2147483647)) (not (< v_prenex_361 0))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 1) 4294967296) 2147483647) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_27 10000)) (not (< main_~i~1 10000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (not (<= (mod (+ (div v_prenex_361 10000) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_361 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_361 10000) 4294967296) 2147483647) (= 0 (mod v_prenex_361 10000))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 1) 4294967296) 2147483647) (not (< main_~i~1 10000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 4294967296) 2147483647)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_27 10000))) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_27 0)) (and (not (< main_~i~1 10000)) (not (<= (mod (+ (div v_prenex_361 10000) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_361 10000) 4294967296) |main_#t~ret4|) (not (< v_prenex_361 0)) (<= (mod (div v_prenex_361 10000) 4294967296) 2147483647)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 1) 4294967296) 2147483647) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_27 10000)) (not (< main_~i~1 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 1) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_27 0)) (not (< main_~i~1 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_27 10000) 4294967296) |main_#t~ret4|)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_28 Int) (v_prenex_362 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod (div v_prenex_362 10000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_362 10000) 4294967296) (- 4294967296))) (= (mod v_prenex_362 10000) 0)) (and (not (< main_~i~1 10000)) (= (mod (div v_prenex_362 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_362 10000) 4294967296) 2147483647) (not (< v_prenex_362 0))) (and (not (< main_~i~1 10000)) (= (mod (div v_prenex_362 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_362 10000) 4294967296) 2147483647) (= (mod v_prenex_362 10000) 0)) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_28 10000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_28 10000) 1) 4294967296)) (< v_mapavg_~ret~0_BEFORE_RETURN_28 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_28 10000) 0))) (and (not (< main_~i~1 10000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_28 10000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_28 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_28 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_28 10000) 0))) (and (not (< main_~i~1 10000)) (not (<= (mod (div v_prenex_362 10000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_362 10000) 4294967296) (- 4294967296))) (not (< v_prenex_362 0)))))) [2019-10-06 22:49:56,918 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:49:56,918 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:56,920 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:49:56,920 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:49:56,921 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:59,220 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:59,221 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-06 22:49:59,222 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-10-06 22:49:59,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-10-06 22:49:59,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=359, Unknown=1, NotChecked=0, Total=420 [2019-10-06 22:49:59,223 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 21 states. [2019-10-06 22:50:28,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:28,005 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-06 22:50:28,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-10-06 22:50:28,007 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 32 [2019-10-06 22:50:28,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:28,007 INFO L225 Difference]: With dead ends: 44 [2019-10-06 22:50:28,008 INFO L226 Difference]: Without dead ends: 29 [2019-10-06 22:50:28,009 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 14.8s TimeCoverageRelationStatistics Valid=200, Invalid=1125, Unknown=7, NotChecked=0, Total=1332 [2019-10-06 22:50:28,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-06 22:50:28,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-06 22:50:28,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-06 22:50:28,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-06 22:50:28,016 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-06 22:50:28,016 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:28,016 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-06 22:50:28,016 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-10-06 22:50:28,016 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-06 22:50:28,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-06 22:50:28,017 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:28,017 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:28,220 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:28,221 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:28,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:28,222 INFO L82 PathProgramCache]: Analyzing trace with hash -682053593, now seen corresponding path program 3 times [2019-10-06 22:50:28,222 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:28,222 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:28,223 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:28,223 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:28,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:28,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:28,348 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:28,348 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:28,349 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:50:28,349 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:28,452 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:50:28,452 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:50:28,453 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-06 22:50:28,456 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:50:28,464 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:28,464 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:28,534 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:28,535 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:28,537 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:28,537 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:28,537 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:28,538 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:28,538 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:28,556 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:50:46,289 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:50:46,311 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:50:46,312 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:50:46,313 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:50:46,313 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:50:46,313 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:50:46,313 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:50:46,313 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:50:46,314 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 0 mapavg_~i~0) (<= 10000 mapavg_~i~0) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 10000))) [2019-10-06 22:50:46,314 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:50:46,314 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:46,314 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:46,314 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:46,315 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:50:46,315 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:50:46,315 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:50:46,315 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:50:46,315 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_674 Int)) (or (and (not (< main_~i~1 10000)) (= (mod (div v_prenex_674 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_674 10000) 4294967296) 2147483647) (= (mod v_prenex_674 10000) 0)) (and (not (< main_~i~1 10000)) (= (mod (div v_prenex_674 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_674 10000) 4294967296) 2147483647) (not (< v_prenex_674 0))) (and (not (< main_~i~1 10000)) (= |main_#t~ret4| (+ (mod (div v_prenex_674 10000) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_674 10000) 4294967296) 2147483647)) (not (< v_prenex_674 0))) (and (not (< main_~i~1 10000)) (= |main_#t~ret4| (+ (mod (div v_prenex_674 10000) 4294967296) (- 4294967296))) (= (mod v_prenex_674 10000) 0) (not (<= (mod (div v_prenex_674 10000) 4294967296) 2147483647))) (and (< v_mapavg_~ret~0_BEFORE_RETURN_54 0) (not (< main_~i~1 10000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_54 10000) 1) 4294967296) 2147483647)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_54 10000) 0)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_54 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (< v_mapavg_~ret~0_BEFORE_RETURN_54 0) (not (< main_~i~1 10000)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_54 10000) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_54 10000) 1) 4294967296) 2147483647) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_54 10000) 0))))) (exists ((v_prenex_673 Int) (v_mapavg_~ret~0_BEFORE_RETURN_53 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod (div v_prenex_673 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_673 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_673 10000) 4294967296) 2147483647)) (= (mod v_prenex_673 10000) 0)) (and (not (< main_~i~1 10000)) (<= (mod (div v_prenex_673 10000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_673 10000) 1) 4294967296) 2147483647)) (= (mod (div v_prenex_673 10000) 4294967296) |main_#t~ret4|) (= (mod v_prenex_673 10000) 0)) (and (= (+ (mod (+ (div v_prenex_673 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10000)) (<= (mod (div v_prenex_673 10000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_673 10000) 1) 4294967296) 2147483647)) (< v_prenex_673 0) (not (= (mod v_prenex_673 10000) 0))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 1) 4294967296) 2147483647) (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_53 0)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 4294967296) 2147483647))) (and (= (+ (mod (+ (div v_prenex_673 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10000)) (not (<= (mod (+ (div v_prenex_673 10000) 1) 4294967296) 2147483647)) (< v_prenex_673 0) (not (= (mod v_prenex_673 10000) 0)) (not (<= (mod (div v_prenex_673 10000) 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (<= (mod (div v_prenex_673 10000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_673 10000) 1) 4294967296) 2147483647)) (not (< v_prenex_673 0)) (= (mod (div v_prenex_673 10000) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 1) 4294967296) 2147483647) (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_53 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 1) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_53 0) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 1) 4294967296)) (not (< main_~i~1 10000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 4294967296) 2147483647))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 1) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_53 0) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 1) 4294967296)) (not (< main_~i~1 10000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 4294967296) 2147483647)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 1) 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 0) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (= (+ (mod (div v_prenex_673 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_673 10000) 1) 4294967296) 2147483647)) (not (< v_prenex_673 0)) (not (<= (mod (div v_prenex_673 10000) 4294967296) 2147483647))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 1) 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 0) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 10000) 4294967296) 2147483647)))))) [2019-10-06 22:50:46,315 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:50:46,315 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:50:46,316 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:50:46,316 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:50:46,316 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:50:48,602 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:50:48,603 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-06 22:50:48,606 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-10-06 22:50:48,606 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-10-06 22:50:48,607 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=469, Unknown=1, NotChecked=0, Total=600 [2019-10-06 22:50:48,607 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 25 states. [2019-10-06 22:51:18,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:51:18,448 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-06 22:51:18,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-10-06 22:51:18,450 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 42 [2019-10-06 22:51:18,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:51:18,450 INFO L225 Difference]: With dead ends: 54 [2019-10-06 22:51:18,451 INFO L226 Difference]: Without dead ends: 36 [2019-10-06 22:51:18,453 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 487 ImplicationChecksByTransitivity, 14.9s TimeCoverageRelationStatistics Valid=359, Invalid=1526, Unknown=7, NotChecked=0, Total=1892 [2019-10-06 22:51:18,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-06 22:51:18,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-06 22:51:18,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-06 22:51:18,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-06 22:51:18,460 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-06 22:51:18,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:51:18,461 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-06 22:51:18,461 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-10-06 22:51:18,461 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-06 22:51:18,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-06 22:51:18,462 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:51:18,463 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:51:18,669 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:18,669 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:51:18,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:51:18,670 INFO L82 PathProgramCache]: Analyzing trace with hash -1538541913, now seen corresponding path program 4 times [2019-10-06 22:51:18,670 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:51:18,670 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:18,670 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:18,671 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:18,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:51:18,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:18,901 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:51:18,902 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:18,902 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:51:18,902 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:19,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:19,062 INFO L256 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-06 22:51:19,069 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:51:19,086 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:51:19,086 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:51:19,348 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:51:19,348 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:51:19,350 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:51:19,350 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:51:19,350 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:51:19,350 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:51:19,351 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:51:19,377 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:51:25,807 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:51:25,825 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:51:25,827 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:51:25,828 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:51:25,828 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:51:25,828 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:51:25,828 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:51:25,829 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:51:25,829 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 0 mapavg_~i~0) (<= 10000 mapavg_~i~0) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 10000))) [2019-10-06 22:51:25,829 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:51:25,830 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:51:25,830 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:51:25,830 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:51:25,830 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:51:25,831 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:51:25,831 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:51:25,831 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:51:25,831 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_973 Int)) (or (and (not (< main_~i~1 10000)) (not (< v_prenex_973 0)) (= (mod (div v_prenex_973 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_973 10000) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= (mod (div v_prenex_973 10000) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_973 10000)) (<= (mod (div v_prenex_973 10000) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (< v_mapavg_~ret~0_BEFORE_RETURN_79 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 10000) 1) 4294967296) 2147483647) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 10000) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_79 10000)))) (and (not (< main_~i~1 10000)) (= 0 (mod v_prenex_973 10000)) (= (+ (mod (div v_prenex_973 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_973 10000) 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (not (< v_prenex_973 0)) (= (+ (mod (div v_prenex_973 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_973 10000) 4294967296) 2147483647))) (and (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10000)) (< v_mapavg_~ret~0_BEFORE_RETURN_79 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 10000) 1) 4294967296) 2147483647)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_79 10000)))))) (exists ((v_prenex_974 Int) (v_mapavg_~ret~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 10000)) (= (mod (div v_prenex_974 10000) 4294967296) |main_#t~ret4|) (= (mod v_prenex_974 10000) 0) (<= (mod (div v_prenex_974 10000) 4294967296) 2147483647)) (and (not (< v_prenex_974 0)) (not (< main_~i~1 10000)) (= (mod (div v_prenex_974 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_974 10000) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (< v_mapavg_~ret~0_BEFORE_RETURN_80 0) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_80 10000) 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 10000) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (= (+ (mod (div v_prenex_974 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_974 10000) 4294967296) 2147483647)) (= (mod v_prenex_974 10000) 0)) (and (not (< v_prenex_974 0)) (not (< main_~i~1 10000)) (= (+ (mod (div v_prenex_974 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_974 10000) 4294967296) 2147483647))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 10000) 1) 4294967296) 2147483647) (not (< main_~i~1 10000)) (< v_mapavg_~ret~0_BEFORE_RETURN_80 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_80 10000) 0)) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 10000) 1) 4294967296)))))) [2019-10-06 22:51:25,832 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:51:25,832 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:51:25,832 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:51:25,832 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:51:25,832 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:51:28,133 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:51:28,133 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-06 22:51:28,135 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2019-10-06 22:51:28,136 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-10-06 22:51:28,137 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=431, Invalid=1050, Unknown=1, NotChecked=0, Total=1482 [2019-10-06 22:51:28,137 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 39 states. [2019-10-06 22:51:55,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:51:55,612 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-06 22:51:55,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-10-06 22:51:55,614 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 49 [2019-10-06 22:51:55,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:51:55,615 INFO L225 Difference]: With dead ends: 68 [2019-10-06 22:51:55,615 INFO L226 Difference]: Without dead ends: 50 [2019-10-06 22:51:55,620 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1243 ImplicationChecksByTransitivity, 15.7s TimeCoverageRelationStatistics Valid=1234, Invalid=3871, Unknown=7, NotChecked=0, Total=5112 [2019-10-06 22:51:55,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-06 22:51:55,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-06 22:51:55,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-06 22:51:55,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-06 22:51:55,631 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-06 22:51:55,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:51:55,632 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-06 22:51:55,632 INFO L463 AbstractCegarLoop]: Interpolant automaton has 39 states. [2019-10-06 22:51:55,632 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-06 22:51:55,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-06 22:51:55,638 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:51:55,639 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:51:55,839 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:55,840 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:51:55,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:51:55,841 INFO L82 PathProgramCache]: Analyzing trace with hash -511572313, now seen corresponding path program 5 times [2019-10-06 22:51:55,841 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:51:55,841 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:55,841 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:55,842 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:55,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:51:55,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:56,378 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:51:56,378 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:56,378 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:51:56,378 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:56,552 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:51:56,552 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:51:56,553 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:51:56,556 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:51:56,587 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-06 22:51:56,587 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:51:56,623 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-06 22:51:56,623 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:51:56,625 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:51:56,625 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:51:56,625 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:51:56,625 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:51:56,625 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:51:56,640 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:52:13,743 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:52:13,763 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:52:13,766 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:52:13,766 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:52:13,766 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:52:13,766 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:52:13,767 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:52:13,767 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:52:13,767 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 0 mapavg_~i~0) (<= 10000 mapavg_~i~0) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 10000))) [2019-10-06 22:52:13,768 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:52:13,768 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:13,768 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:52:13,768 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:13,769 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:52:13,769 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:52:13,769 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:52:13,769 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:52:13,770 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_1213 Int)) (or (and (not (<= (mod (+ (div v_prenex_1213 10000) 1) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= |main_#t~ret4| (mod (div v_prenex_1213 10000) 4294967296)) (<= (mod (div v_prenex_1213 10000) 4294967296) 2147483647) (not (< v_prenex_1213 0))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 1) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_105 0)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (= (mod v_prenex_1213 10000) 0) (= |main_#t~ret4| (mod (div v_prenex_1213 10000) 4294967296)) (<= (mod (+ (div v_prenex_1213 10000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1213 10000) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_1213 10000) 1) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (mod v_prenex_1213 10000) 0) (= |main_#t~ret4| (mod (div v_prenex_1213 10000) 4294967296)) (<= (mod (div v_prenex_1213 10000) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= |main_#t~ret4| (mod (div v_prenex_1213 10000) 4294967296)) (<= (mod (+ (div v_prenex_1213 10000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1213 10000) 4294967296) 2147483647) (not (< v_prenex_1213 0))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (< v_mapavg_~ret~0_BEFORE_RETURN_105 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 0)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 1) 4294967296) 2147483647))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 4294967296) (- 4294967296)))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (< v_mapavg_~ret~0_BEFORE_RETURN_105 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 1) 4294967296) 2147483647) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 1) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (< v_prenex_1213 0) (not (= (mod v_prenex_1213 10000) 0)) (<= (mod (+ (div v_prenex_1213 10000) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_1213 10000) 1) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_1213 10000) 4294967296) 2147483647)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 4294967296) (- 4294967296)))) (and (not (<= (mod (+ (div v_prenex_1213 10000) 1) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (< v_prenex_1213 0) (not (= (mod v_prenex_1213 10000) 0)) (= (+ (mod (+ (div v_prenex_1213 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (div v_prenex_1213 10000) 4294967296) 2147483647)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_105 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 10000) 4294967296) (- 4294967296)))))) (exists ((v_prenex_1214 Int) (v_mapavg_~ret~0_BEFORE_RETURN_106 Int)) (or (and (not (<= (mod (div v_prenex_1214 10000) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (mod v_prenex_1214 10000) 0) (= |main_#t~ret4| (+ (mod (div v_prenex_1214 10000) 4294967296) (- 4294967296)))) (and (not (<= (mod (div v_prenex_1214 10000) 4294967296) 2147483647)) (not (< v_prenex_1214 0)) (not (< main_~i~1 10000)) (= |main_#t~ret4| (+ (mod (div v_prenex_1214 10000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 10000) 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 10000) 1) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_106 0) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 10000) 1) 4294967296))) (and (not (< main_~i~1 10000)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 10000) 1) 4294967296) (- 4294967296))) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 10000) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_106 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 10000) 1) 4294967296) 2147483647))) (and (not (< v_prenex_1214 0)) (not (< main_~i~1 10000)) (<= (mod (div v_prenex_1214 10000) 4294967296) 2147483647) (= (mod (div v_prenex_1214 10000) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (<= (mod (div v_prenex_1214 10000) 4294967296) 2147483647) (= (mod (div v_prenex_1214 10000) 4294967296) |main_#t~ret4|) (= (mod v_prenex_1214 10000) 0))))) [2019-10-06 22:52:13,770 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:52:13,770 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:52:13,770 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:52:13,770 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:52:13,771 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:52:16,208 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:52:16,209 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-06 22:52:16,210 INFO L442 AbstractCegarLoop]: Interpolant automaton has 43 states [2019-10-06 22:52:16,210 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2019-10-06 22:52:16,211 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=445, Invalid=1360, Unknown=1, NotChecked=0, Total=1806 [2019-10-06 22:52:16,211 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 43 states. [2019-10-06 22:53:04,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:53:04,234 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-06 22:53:04,234 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2019-10-06 22:53:04,234 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 63 [2019-10-06 22:53:04,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:53:04,235 INFO L225 Difference]: With dead ends: 72 [2019-10-06 22:53:04,236 INFO L226 Difference]: Without dead ends: 54 [2019-10-06 22:53:04,238 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 177 SyntacticMatches, 0 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1240 ImplicationChecksByTransitivity, 32.5s TimeCoverageRelationStatistics Valid=1339, Invalid=5126, Unknown=15, NotChecked=0, Total=6480 [2019-10-06 22:53:04,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-06 22:53:04,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-06 22:53:04,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-06 22:53:04,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-06 22:53:04,245 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-06 22:53:04,245 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:53:04,245 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-06 22:53:04,245 INFO L463 AbstractCegarLoop]: Interpolant automaton has 43 states. [2019-10-06 22:53:04,246 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-06 22:53:04,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-06 22:53:04,247 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:53:04,247 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:53:04,447 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:53:04,448 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:53:04,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:53:04,448 INFO L82 PathProgramCache]: Analyzing trace with hash -637611949, now seen corresponding path program 6 times [2019-10-06 22:53:04,449 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:53:04,449 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:53:04,449 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:53:04,449 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:53:04,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:53:04,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:53:04,975 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:04,975 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:53:04,975 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:53:04,975 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:53:05,225 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:53:05,226 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:53:05,227 INFO L256 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-06 22:53:05,231 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:53:05,247 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:05,247 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:53:06,190 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:06,190 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:53:06,192 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:53:06,192 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:53:06,192 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:53:06,193 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:53:06,193 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:53:06,209 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:53:22,885 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:53:22,909 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:53:22,911 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:53:22,911 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:53:22,911 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:53:22,911 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:53:22,912 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:53:22,912 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:53:22,912 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 0 mapavg_~i~0) (<= 10000 mapavg_~i~0) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 10000))) [2019-10-06 22:53:22,912 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:53:22,912 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:22,912 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:22,913 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:22,913 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:53:22,913 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:53:22,913 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:53:22,913 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:53:22,914 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1525 Int) (v_mapavg_~ret~0_BEFORE_RETURN_131 Int)) (or (and (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_131 10000)) (not (< main_~i~1 10000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 1) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (< v_mapavg_~ret~0_BEFORE_RETURN_131 0) (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 4294967296) 2147483647)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_131 10000)))) (and (not (< main_~i~1 10000)) (not (= 0 (mod v_prenex_1525 10000))) (<= (mod (+ (div v_prenex_1525 10000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1525 10000) 4294967296) 2147483647) (< v_prenex_1525 0) (= (mod (+ (div v_prenex_1525 10000) 1) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_131 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 1) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (+ (div v_prenex_1525 10000) 1) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= (mod (div v_prenex_1525 10000) 4294967296) 2147483647) (= 0 (mod v_prenex_1525 10000)) (= (mod (div v_prenex_1525 10000) 4294967296) |main_#t~ret4|)) (and (< v_mapavg_~ret~0_BEFORE_RETURN_131 0) (not (< main_~i~1 10000)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 4294967296) 2147483647)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_131 10000))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 1) 4294967296) 2147483647))) (and (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_131 10000)) (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 1) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_131 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (+ (div v_prenex_1525 10000) 1) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (not (= 0 (mod v_prenex_1525 10000))) (= (+ (mod (+ (div v_prenex_1525 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (div v_prenex_1525 10000) 4294967296) 2147483647) (< v_prenex_1525 0)) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_prenex_1525 10000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1525 10000) 4294967296) 2147483647) (not (< v_prenex_1525 0)) (= (mod (div v_prenex_1525 10000) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (+ (div v_prenex_1525 10000) 1) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= (mod (div v_prenex_1525 10000) 4294967296) 2147483647) (not (< v_prenex_1525 0)) (= (mod (div v_prenex_1525 10000) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_prenex_1525 10000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_1525 10000) 4294967296) 2147483647) (= 0 (mod v_prenex_1525 10000)) (= (mod (div v_prenex_1525 10000) 4294967296) |main_#t~ret4|)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_132 Int) (v_prenex_1526 Int)) (or (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 10000) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_132 10000))) (and (not (< main_~i~1 10000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_132 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 10000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 10000) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_132 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 10000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 10000) 4294967296) |main_#t~ret4|)) (and (<= (mod (+ (div v_prenex_1526 10000) 1) 4294967296) 2147483647) (not (< main_~i~1 10000)) (< v_prenex_1526 0) (= |main_#t~ret4| (mod (+ (div v_prenex_1526 10000) 1) 4294967296)) (not (= 0 (mod v_prenex_1526 10000)))) (and (not (< main_~i~1 10000)) (< v_prenex_1526 0) (not (= 0 (mod v_prenex_1526 10000))) (= (+ (mod (+ (div v_prenex_1526 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_1526 10000) 1) 4294967296) 2147483647))) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 10000) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_132 0)))))) [2019-10-06 22:53:22,914 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:53:22,914 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:53:22,914 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:53:22,914 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:53:22,914 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:53:25,345 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:53:25,346 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-06 22:53:25,347 INFO L442 AbstractCegarLoop]: Interpolant automaton has 69 states [2019-10-06 22:53:25,348 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2019-10-06 22:53:25,350 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1736, Invalid=2955, Unknown=1, NotChecked=0, Total=4692 [2019-10-06 22:53:25,350 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 69 states. [2019-10-06 22:53:53,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:53:53,121 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-06 22:53:53,123 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2019-10-06 22:53:53,124 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 67 [2019-10-06 22:53:53,124 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:53:53,125 INFO L225 Difference]: With dead ends: 104 [2019-10-06 22:53:53,125 INFO L226 Difference]: Without dead ends: 83 [2019-10-06 22:53:53,130 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 295 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3688 ImplicationChecksByTransitivity, 18.6s TimeCoverageRelationStatistics Valid=5089, Invalid=12196, Unknown=7, NotChecked=0, Total=17292 [2019-10-06 22:53:53,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-06 22:53:53,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-06 22:53:53,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-06 22:53:53,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-06 22:53:53,139 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-06 22:53:53,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:53:53,140 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-06 22:53:53,140 INFO L463 AbstractCegarLoop]: Interpolant automaton has 69 states. [2019-10-06 22:53:53,140 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-06 22:53:53,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-06 22:53:53,141 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:53:53,142 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:53:53,345 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:53:53,346 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:53:53,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:53:53,346 INFO L82 PathProgramCache]: Analyzing trace with hash -421590573, now seen corresponding path program 7 times [2019-10-06 22:53:53,347 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:53:53,347 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:53:53,347 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:53:53,347 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:53:53,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:53:53,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:53:54,798 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:54,799 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:53:54,799 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:53:54,799 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:53:55,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:53:55,082 INFO L256 TraceCheckSpWp]: Trace formula consists of 529 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-06 22:53:55,086 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:53:55,116 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:55,116 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:53:58,875 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:58,875 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:53:58,876 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:53:58,876 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:53:58,877 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:53:58,877 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:53:58,877 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:53:58,896 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:54:15,544 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:54:15,561 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:54:15,563 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:54:15,563 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:54:15,563 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:54:15,564 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:54:15,564 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:54:15,564 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:54:15,564 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 0 mapavg_~i~0) (<= 10000 mapavg_~i~0) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 10000))) [2019-10-06 22:54:15,564 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:54:15,564 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:15,564 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:15,564 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:15,564 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:54:15,564 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:54:15,565 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:54:15,565 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:54:15,565 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1814 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod (div v_prenex_1814 10000) 4294967296) 2147483647)) (not (< v_prenex_1814 0)) (= |main_#t~ret4| (+ (mod (div v_prenex_1814 10000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (= (mod v_prenex_1814 10000) 0) (<= (mod (div v_prenex_1814 10000) 4294967296) 2147483647) (= (mod (div v_prenex_1814 10000) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (not (<= (mod (div v_prenex_1814 10000) 4294967296) 2147483647)) (= (mod v_prenex_1814 10000) 0) (= |main_#t~ret4| (+ (mod (div v_prenex_1814 10000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (not (< v_prenex_1814 0)) (<= (mod (div v_prenex_1814 10000) 4294967296) 2147483647) (= (mod (div v_prenex_1814 10000) 4294967296) |main_#t~ret4|)) (and (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 10000) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_158 10000) 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 10000) 1) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_158 0)) (and (not (< main_~i~1 10000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_158 10000) 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 10000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_158 0)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_157 Int) (v_prenex_1813 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod (+ (div v_prenex_1813 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_1813 10000) 4294967296) 2147483647)) (= 0 (mod v_prenex_1813 10000)) (= (+ (mod (div v_prenex_1813 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_157 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 4294967296)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 4294967296)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_157 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 1) 4294967296) 2147483647)) (and (<= (mod (div v_prenex_1813 10000) 4294967296) 2147483647) (not (< main_~i~1 10000)) (not (< v_prenex_1813 0)) (not (<= (mod (+ (div v_prenex_1813 10000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (mod (div v_prenex_1813 10000) 4294967296))) (and (not (< main_~i~1 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_157 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 1) 4294967296) 2147483647) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_157 10000)))) (and (not (< main_~i~1 10000)) (= (+ (mod (+ (div v_prenex_1813 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_prenex_1813 10000))) (not (<= (mod (+ (div v_prenex_1813 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_1813 10000) 4294967296) 2147483647)) (< v_prenex_1813 0)) (and (<= (mod (div v_prenex_1813 10000) 4294967296) 2147483647) (not (< main_~i~1 10000)) (not (<= (mod (+ (div v_prenex_1813 10000) 1) 4294967296) 2147483647)) (= 0 (mod v_prenex_1813 10000)) (= |main_#t~ret4| (mod (div v_prenex_1813 10000) 4294967296))) (and (not (< main_~i~1 10000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_157 10000)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (< v_mapavg_~ret~0_BEFORE_RETURN_157 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 4294967296) 2147483647)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_157 10000)))) (and (not (< main_~i~1 10000)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_mapavg_~ret~0_BEFORE_RETURN_157 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 10000) 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (not (< v_prenex_1813 0)) (not (<= (mod (+ (div v_prenex_1813 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_1813 10000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_1813 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (div v_prenex_1813 10000) 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (+ (mod (+ (div v_prenex_1813 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_prenex_1813 10000))) (not (<= (mod (+ (div v_prenex_1813 10000) 1) 4294967296) 2147483647)) (< v_prenex_1813 0))))) [2019-10-06 22:54:15,565 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:54:15,565 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:54:15,565 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:54:15,566 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:54:15,566 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:54:18,204 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:54:18,205 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 127 [2019-10-06 22:54:18,206 INFO L442 AbstractCegarLoop]: Interpolant automaton has 127 states [2019-10-06 22:54:18,208 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 127 interpolants. [2019-10-06 22:54:18,212 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6811, Invalid=9190, Unknown=1, NotChecked=0, Total=16002 [2019-10-06 22:54:18,212 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 127 states. [2019-10-06 22:54:46,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:54:46,444 INFO L93 Difference]: Finished difference Result 162 states and 227 transitions. [2019-10-06 22:54:46,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 126 states. [2019-10-06 22:54:46,444 INFO L78 Accepts]: Start accepts. Automaton has 127 states. Word has length 96 [2019-10-06 22:54:46,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:54:46,447 INFO L225 Difference]: With dead ends: 162 [2019-10-06 22:54:46,447 INFO L226 Difference]: Without dead ends: 141 [2019-10-06 22:54:46,455 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 223 SyntacticMatches, 0 SemanticMatches, 246 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11606 ImplicationChecksByTransitivity, 25.0s TimeCoverageRelationStatistics Valid=20198, Invalid=41054, Unknown=4, NotChecked=0, Total=61256 [2019-10-06 22:54:46,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2019-10-06 22:54:46,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2019-10-06 22:54:46,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2019-10-06 22:54:46,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 145 transitions. [2019-10-06 22:54:46,469 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 145 transitions. Word has length 96 [2019-10-06 22:54:46,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:54:46,470 INFO L462 AbstractCegarLoop]: Abstraction has 141 states and 145 transitions. [2019-10-06 22:54:46,470 INFO L463 AbstractCegarLoop]: Interpolant automaton has 127 states. [2019-10-06 22:54:46,470 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 145 transitions. [2019-10-06 22:54:46,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2019-10-06 22:54:46,472 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:54:46,472 INFO L385 BasicCegarLoop]: trace histogram [114, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:54:46,676 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:54:46,676 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:54:46,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:54:46,677 INFO L82 PathProgramCache]: Analyzing trace with hash 1491638739, now seen corresponding path program 8 times [2019-10-06 22:54:46,677 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:54:46,677 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:54:46,677 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:46,678 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:46,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:54:46,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:54:52,033 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 0 proven. 6555 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:54:52,033 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:54:52,033 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:54:52,033 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:54:52,348 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:54:52,349 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:54:52,349 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 22:54:52,352 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:54:52,609 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 22:54:52,609 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:54:52,906 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 22:54:52,906 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:54:52,908 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:54:52,908 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:54:52,908 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:54:52,908 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:54:52,909 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:54:52,922 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:55:11,405 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:55:11,433 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:55:11,435 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:55:11,436 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:55:11,436 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:55:11,436 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:55:11,436 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:55:11,436 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:55:11,436 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 0 mapavg_~i~0) (<= 10000 mapavg_~i~0) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 10000))) [2019-10-06 22:55:11,437 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:55:11,437 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:11,437 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:11,437 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:55:11,437 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:55:11,437 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:55:11,438 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:55:11,438 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:55:11,438 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2125 Int) (v_mapavg_~ret~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod (div v_prenex_2125 10000) 4294967296) 2147483647)) (not (< v_prenex_2125 0)) (= |main_#t~ret4| (+ (mod (div v_prenex_2125 10000) 4294967296) (- 4294967296)))) (and (<= (mod (div v_prenex_2125 10000) 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod (div v_prenex_2125 10000) 4294967296) |main_#t~ret4|) (= 0 (mod v_prenex_2125 10000))) (and (not (< main_~i~1 10000)) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 10000) 1) 4294967296)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 10000) 1) 4294967296) 2147483647) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_183 10000))) (< v_mapavg_~ret~0_BEFORE_RETURN_183 0)) (and (not (< main_~i~1 10000)) (not (<= (mod (div v_prenex_2125 10000) 4294967296) 2147483647)) (= 0 (mod v_prenex_2125 10000)) (= |main_#t~ret4| (+ (mod (div v_prenex_2125 10000) 4294967296) (- 4294967296)))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 10000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10000)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_183 10000))) (< v_mapavg_~ret~0_BEFORE_RETURN_183 0)) (and (<= (mod (div v_prenex_2125 10000) 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod (div v_prenex_2125 10000) 4294967296) |main_#t~ret4|) (not (< v_prenex_2125 0))))) (exists ((v_prenex_2126 Int) (v_mapavg_~ret~0_BEFORE_RETURN_184 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod (div v_prenex_2126 10000) 4294967296) 2147483647)) (= |main_#t~ret4| (mod (+ (div v_prenex_2126 10000) 1) 4294967296)) (not (= 0 (mod v_prenex_2126 10000))) (<= (mod (+ (div v_prenex_2126 10000) 1) 4294967296) 2147483647) (< v_prenex_2126 0)) (and (not (< main_~i~1 10000)) (= 0 (mod v_prenex_2126 10000)) (not (<= (mod (div v_prenex_2126 10000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_2126 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_prenex_2126 10000) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 1) 4294967296) 2147483647) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 4294967296) |main_#t~ret4|) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_184 10000))) (and (not (< main_~i~1 10000)) (= 0 (mod v_prenex_2126 10000)) (not (<= (mod (+ (div v_prenex_2126 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2126 10000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_2126 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (not (<= (mod (+ (div v_prenex_2126 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2126 10000) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_2126 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_prenex_2126 10000))) (< v_prenex_2126 0)) (and (not (< main_~i~1 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 4294967296) |main_#t~ret4|) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_184 10000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 4294967296) 2147483647) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_184 10000))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 1) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_184 0) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 1) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_184 0))) (and (not (< main_~i~1 10000)) (not (< v_prenex_2126 0)) (not (<= (mod (+ (div v_prenex_2126 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2126 10000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_2126 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 1) 4294967296) 2147483647) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 4294967296) 2147483647) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_184 10000))) (< v_mapavg_~ret~0_BEFORE_RETURN_184 0) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 1) 4294967296))) (and (not (< main_~i~1 10000)) (not (< v_prenex_2126 0)) (not (<= (mod (div v_prenex_2126 10000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_2126 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_prenex_2126 10000) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 4294967296) 2147483647) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 1) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 10000) 4294967296) |main_#t~ret4|) (not (< v_mapavg_~ret~0_BEFORE_RETURN_184 0)))))) [2019-10-06 22:55:11,438 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:55:11,438 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:55:11,438 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:55:11,439 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:55:11,439 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:55:12,572 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:55:12,572 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [117, 7, 7, 11] total 137 [2019-10-06 22:55:12,573 INFO L442 AbstractCegarLoop]: Interpolant automaton has 137 states [2019-10-06 22:55:12,574 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 137 interpolants. [2019-10-06 22:55:12,576 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6876, Invalid=11756, Unknown=0, NotChecked=0, Total=18632 [2019-10-06 22:55:12,576 INFO L87 Difference]: Start difference. First operand 141 states and 145 transitions. Second operand 137 states. [2019-10-06 22:55:49,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:55:49,887 INFO L93 Difference]: Finished difference Result 169 states and 186 transitions. [2019-10-06 22:55:49,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 137 states. [2019-10-06 22:55:49,888 INFO L78 Accepts]: Start accepts. Automaton has 137 states. Word has length 154 [2019-10-06 22:55:49,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:55:49,890 INFO L225 Difference]: With dead ends: 169 [2019-10-06 22:55:49,890 INFO L226 Difference]: Without dead ends: 148 [2019-10-06 22:55:49,893 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 710 GetRequests, 443 SyntacticMatches, 0 SemanticMatches, 267 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11913 ImplicationChecksByTransitivity, 30.2s TimeCoverageRelationStatistics Valid=20684, Invalid=51402, Unknown=6, NotChecked=0, Total=72092 [2019-10-06 22:55:49,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2019-10-06 22:55:49,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 148. [2019-10-06 22:55:49,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2019-10-06 22:55:49,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 152 transitions. [2019-10-06 22:55:49,909 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 152 transitions. Word has length 154 [2019-10-06 22:55:49,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:55:49,909 INFO L462 AbstractCegarLoop]: Abstraction has 148 states and 152 transitions. [2019-10-06 22:55:49,909 INFO L463 AbstractCegarLoop]: Interpolant automaton has 137 states. [2019-10-06 22:55:49,910 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 152 transitions. [2019-10-06 22:55:49,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2019-10-06 22:55:49,912 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:55:49,912 INFO L385 BasicCegarLoop]: trace histogram [115, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:55:50,116 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:55:50,116 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:55:50,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:55:50,117 INFO L82 PathProgramCache]: Analyzing trace with hash 1419883091, now seen corresponding path program 9 times [2019-10-06 22:55:50,117 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:55:50,117 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:55:50,118 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:55:50,118 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:55:50,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:55:50,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:55:55,395 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:55:55,396 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:55:55,396 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:55:55,396 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:55:56,057 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:55:56,057 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:55:56,063 INFO L256 TraceCheckSpWp]: Trace formula consists of 973 conjuncts, 117 conjunts are in the unsatisfiable core [2019-10-06 22:55:56,067 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:55:56,106 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:55:56,106 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:56:11,287 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:56:11,287 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:56:11,288 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:56:11,288 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:56:11,289 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:56:11,289 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:56:11,289 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:56:11,301 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:56:29,079 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:56:29,097 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:56:29,099 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:56:29,100 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:56:29,100 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:56:29,100 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:56:29,100 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:56:29,100 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:56:29,101 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 0 mapavg_~i~0) (<= 10000 mapavg_~i~0) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 10000))) [2019-10-06 22:56:29,101 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:56:29,101 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:29,101 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:56:29,101 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:29,102 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:56:29,102 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:56:29,102 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:56:29,102 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:56:29,102 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2401 Int) (v_mapavg_~ret~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 10000) 4294967296) 2147483647)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_209 10000))) (and (not (< main_~i~1 10000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 10000) 4294967296) 2147483647) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_209 10000))) (and (< v_prenex_2401 0) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2401 10000) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_2401 10000) 1) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (not (= 0 (mod v_prenex_2401 10000)))) (and (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_209 0)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 10000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 10000) 4294967296) 2147483647))) (and (< v_prenex_2401 0) (not (< main_~i~1 10000)) (= (mod (+ (div v_prenex_2401 10000) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_2401 10000) 1) 4294967296) 2147483647) (not (= 0 (mod v_prenex_2401 10000)))) (and (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_209 0)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 10000) 4294967296) 2147483647)))) (exists ((v_prenex_2402 Int) (v_mapavg_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 1) 4294967296) 2147483647) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_210 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_prenex_2402 10000) 1) 4294967296) 2147483647) (= (mod (div v_prenex_2402 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2402 10000) 4294967296) 2147483647) (not (< v_prenex_2402 0))) (and (not (< main_~i~1 10000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 1) 4294967296) 2147483647)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 10000)) (= |main_#t~ret4| (mod (+ (div v_prenex_2402 10000) 1) 4294967296)) (<= (mod (+ (div v_prenex_2402 10000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_2402 10000) 4294967296) 2147483647) (not (= (mod v_prenex_2402 10000) 0)) (< v_prenex_2402 0)) (and (= (mod v_prenex_2402 10000) 0) (not (< main_~i~1 10000)) (<= (mod (+ (div v_prenex_2402 10000) 1) 4294967296) 2147483647) (= (mod (div v_prenex_2402 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2402 10000) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_210 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (mod v_prenex_2402 10000) 0) (not (< main_~i~1 10000)) (= (mod (div v_prenex_2402 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2402 10000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2402 10000) 1) 4294967296) 2147483647))) (and (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 1) 4294967296)) (not (< main_~i~1 10000)) (< v_mapavg_~ret~0_BEFORE_RETURN_210 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (<= (mod (div v_prenex_2402 10000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2402 10000) 1) 4294967296) 2147483647)) (not (= (mod v_prenex_2402 10000) 0)) (< v_prenex_2402 0) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2402 10000) 1) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (= (mod (div v_prenex_2402 10000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2402 10000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2402 10000) 1) 4294967296) 2147483647)) (not (< v_prenex_2402 0))) (and (not (< main_~i~1 10000)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 1) 4294967296) (- 4294967296))) (< v_mapavg_~ret~0_BEFORE_RETURN_210 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 10000) 4294967296) 2147483647)))))) [2019-10-06 22:56:29,103 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:56:29,103 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:56:29,103 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:56:29,103 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:56:29,104 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:56:32,170 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:56:32,170 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [118, 118, 118, 11] total 245 [2019-10-06 22:56:32,172 INFO L442 AbstractCegarLoop]: Interpolant automaton has 245 states [2019-10-06 22:56:32,178 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 245 interpolants. [2019-10-06 22:56:32,180 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27520, Invalid=32259, Unknown=1, NotChecked=0, Total=59780 [2019-10-06 22:56:32,181 INFO L87 Difference]: Start difference. First operand 148 states and 152 transitions. Second operand 245 states. [2019-10-06 22:57:32,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:57:32,301 INFO L93 Difference]: Finished difference Result 292 states and 416 transitions. [2019-10-06 22:57:32,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 244 states. [2019-10-06 22:57:32,303 INFO L78 Accepts]: Start accepts. Automaton has 245 states. Word has length 173 [2019-10-06 22:57:32,304 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:57:32,305 INFO L225 Difference]: With dead ends: 292 [2019-10-06 22:57:32,306 INFO L226 Difference]: Without dead ends: 265 [2019-10-06 22:57:32,313 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 877 GetRequests, 395 SyntacticMatches, 0 SemanticMatches, 482 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40692 ImplicationChecksByTransitivity, 67.6s TimeCoverageRelationStatistics Valid=82089, Invalid=151676, Unknown=7, NotChecked=0, Total=233772 [2019-10-06 22:57:32,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2019-10-06 22:57:32,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 265. [2019-10-06 22:57:32,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2019-10-06 22:57:32,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 269 transitions. [2019-10-06 22:57:32,346 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 269 transitions. Word has length 173 [2019-10-06 22:57:32,347 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:57:32,347 INFO L462 AbstractCegarLoop]: Abstraction has 265 states and 269 transitions. [2019-10-06 22:57:32,347 INFO L463 AbstractCegarLoop]: Interpolant automaton has 245 states. [2019-10-06 22:57:32,347 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 269 transitions. [2019-10-06 22:57:32,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2019-10-06 22:57:32,352 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:57:32,352 INFO L385 BasicCegarLoop]: trace histogram [232, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:57:32,556 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:57:32,557 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:57:32,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:57:32,557 INFO L82 PathProgramCache]: Analyzing trace with hash -424031277, now seen corresponding path program 10 times [2019-10-06 22:57:32,558 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:57:32,558 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:57:32,558 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:57:32,558 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:57:32,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:57:33,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:57:53,120 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:57:53,121 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:57:53,121 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:57:53,121 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:57:53,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:57:53,751 INFO L256 TraceCheckSpWp]: Trace formula consists of 1675 conjuncts, 234 conjunts are in the unsatisfiable core [2019-10-06 22:57:53,756 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:57:53,824 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:57:53,824 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:58:55,075 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:58:55,075 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:58:55,077 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:58:55,077 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:58:55,077 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:58:55,078 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:58:55,078 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:58:55,107 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:59:34,917 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:59:34,938 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:59:34,940 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:59:34,940 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:59:34,940 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-06 22:59:34,940 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:59:34,940 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:59:34,940 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:59:34,941 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (<= 0 mapavg_~i~0) (<= 10000 mapavg_~i~0) (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= (mod mapavg_~ret~0 10000) 0))) (+ (div mapavg_~ret~0 10000) 1) (div mapavg_~ret~0 10000)) 4294967296) (- 4294967296))) |mapavg_#res|) (not (< mapavg_~i~0 10000))) [2019-10-06 22:59:34,941 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:59:34,941 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:59:34,941 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:59:34,941 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:59:34,941 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:59:34,941 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:59:34,941 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-06 22:59:34,941 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:59:34,942 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2713 Int) (v_mapavg_~ret~0_BEFORE_RETURN_235 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod (div v_prenex_2713 10000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2713 10000) 1) 4294967296) 2147483647)) (not (< v_prenex_2713 0)) (= |main_#t~ret4| (mod (div v_prenex_2713 10000) 4294967296))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 1) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_235 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 4294967296) (- 4294967296))) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 0)) (and (not (< main_~i~1 10000)) (<= (mod (div v_prenex_2713 10000) 4294967296) 2147483647) (not (< v_prenex_2713 0)) (<= (mod (+ (div v_prenex_2713 10000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_2713 10000) 4294967296))) (and (not (< main_~i~1 10000)) (= (mod v_prenex_2713 10000) 0) (<= (mod (div v_prenex_2713 10000) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_2713 10000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_2713 10000) 4294967296))) (and (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 1) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_235 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 4294967296) (- 4294967296)))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 1) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 4294967296) (- 4294967296))) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 0)) (and (not (< main_~i~1 10000)) (= (+ (mod (+ (div v_prenex_2713 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_prenex_2713 10000) 0)) (<= (mod (div v_prenex_2713 10000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2713 10000) 1) 4294967296) 2147483647)) (< v_prenex_2713 0)) (and (not (< main_~i~1 10000)) (= (mod v_prenex_2713 10000) 0) (<= (mod (div v_prenex_2713 10000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2713 10000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (mod (div v_prenex_2713 10000) 4294967296))) (and (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_235 0) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 0))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 1) 4294967296) 2147483647)) (not (< main_~i~1 10000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_235 0) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_235 10000) 0))) (and (not (< main_~i~1 10000)) (not (= (mod v_prenex_2713 10000) 0)) (<= (mod (div v_prenex_2713 10000) 4294967296) 2147483647) (= (mod (+ (div v_prenex_2713 10000) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_2713 10000) 1) 4294967296) 2147483647) (< v_prenex_2713 0)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_2714 Int)) (or (and (not (< main_~i~1 10000)) (= |main_#t~ret4| (mod (div v_prenex_2714 10000) 4294967296)) (= (mod v_prenex_2714 10000) 0) (not (<= (mod (+ (div v_prenex_2714 10000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2714 10000) 4294967296) 2147483647)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 1) 4294967296) 2147483647) (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_236 0)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 4294967296) (- 4294967296))) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 4294967296) 2147483647)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 0)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 1) 4294967296) 2147483647) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 10000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_236 0)) (and (not (< v_prenex_2714 0)) (not (< main_~i~1 10000)) (= |main_#t~ret4| (mod (div v_prenex_2714 10000) 4294967296)) (not (<= (mod (+ (div v_prenex_2714 10000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2714 10000) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= (mod (+ (div v_prenex_2714 10000) 1) 4294967296) |main_#t~ret4|) (< v_prenex_2714 0) (<= (mod (+ (div v_prenex_2714 10000) 1) 4294967296) 2147483647) (not (= (mod v_prenex_2714 10000) 0)) (<= (mod (div v_prenex_2714 10000) 4294967296) 2147483647)) (and (not (< v_prenex_2714 0)) (not (< main_~i~1 10000)) (= |main_#t~ret4| (mod (div v_prenex_2714 10000) 4294967296)) (<= (mod (+ (div v_prenex_2714 10000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_2714 10000) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= |main_#t~ret4| (mod (div v_prenex_2714 10000) 4294967296)) (= (mod v_prenex_2714 10000) 0) (<= (mod (+ (div v_prenex_2714 10000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_2714 10000) 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_236 0)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 4294967296) 2147483647))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 1) 4294967296) 2147483647) (not (< main_~i~1 10000)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 4294967296) (- 4294967296))) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 4294967296) 2147483647)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 0)) (and (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 10000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 10000) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_236 0)) (and (not (< main_~i~1 10000)) (< v_prenex_2714 0) (not (<= (mod (+ (div v_prenex_2714 10000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_2714 10000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_prenex_2714 10000) 0)) (<= (mod (div v_prenex_2714 10000) 4294967296) 2147483647))))) [2019-10-06 22:59:34,942 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:59:34,942 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:59:34,942 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:59:34,942 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:59:34,942 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:59:39,066 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:59:39,067 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [235, 235, 235, 11] total 479 [2019-10-06 22:59:39,069 INFO L442 AbstractCegarLoop]: Interpolant automaton has 479 states [2019-10-06 22:59:39,078 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 479 interpolants. [2019-10-06 22:59:39,084 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=109771, Invalid=119190, Unknown=1, NotChecked=0, Total=228962 [2019-10-06 22:59:39,084 INFO L87 Difference]: Start difference. First operand 265 states and 269 transitions. Second operand 479 states. [2019-10-06 23:02:05,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:02:05,287 INFO L93 Difference]: Finished difference Result 526 states and 767 transitions. [2019-10-06 23:02:05,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 478 states. [2019-10-06 23:02:05,289 INFO L78 Accepts]: Start accepts. Automaton has 479 states. Word has length 290 [2019-10-06 23:02:05,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:02:05,293 INFO L225 Difference]: With dead ends: 526 [2019-10-06 23:02:05,293 INFO L226 Difference]: Without dead ends: 499 [2019-10-06 23:02:05,323 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1579 GetRequests, 629 SyntacticMatches, 0 SemanticMatches, 950 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 149853 ImplicationChecksByTransitivity, 211.7s TimeCoverageRelationStatistics Valid=328374, Invalid=576973, Unknown=5, NotChecked=0, Total=905352 [2019-10-06 23:02:05,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 499 states. [2019-10-06 23:02:05,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 499 to 499. [2019-10-06 23:02:05,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 499 states. [2019-10-06 23:02:05,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 499 states to 499 states and 503 transitions. [2019-10-06 23:02:05,347 INFO L78 Accepts]: Start accepts. Automaton has 499 states and 503 transitions. Word has length 290 [2019-10-06 23:02:05,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:02:05,348 INFO L462 AbstractCegarLoop]: Abstraction has 499 states and 503 transitions. [2019-10-06 23:02:05,348 INFO L463 AbstractCegarLoop]: Interpolant automaton has 479 states. [2019-10-06 23:02:05,348 INFO L276 IsEmpty]: Start isEmpty. Operand 499 states and 503 transitions. [2019-10-06 23:02:05,358 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 525 [2019-10-06 23:02:05,358 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:02:05,359 INFO L385 BasicCegarLoop]: trace histogram [466, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:02:05,565 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:05,566 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:02:05,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:02:05,566 INFO L82 PathProgramCache]: Analyzing trace with hash 466017235, now seen corresponding path program 11 times [2019-10-06 23:02:05,567 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:02:05,567 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:05,567 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:05,567 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:05,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:02:07,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat