java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/array-crafted/mapavg4.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-06 22:48:37,170 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-06 22:48:37,176 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-06 22:48:37,188 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-06 22:48:37,189 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-06 22:48:37,190 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-06 22:48:37,191 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-06 22:48:37,193 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-06 22:48:37,195 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-06 22:48:37,196 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-06 22:48:37,197 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-06 22:48:37,198 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-06 22:48:37,198 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-06 22:48:37,199 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-06 22:48:37,200 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-06 22:48:37,201 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-06 22:48:37,202 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-06 22:48:37,203 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-06 22:48:37,204 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-06 22:48:37,206 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-06 22:48:37,208 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-06 22:48:37,209 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-06 22:48:37,210 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-06 22:48:37,211 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-06 22:48:37,213 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-06 22:48:37,221 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-06 22:48:37,222 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-06 22:48:37,223 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-06 22:48:37,224 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-06 22:48:37,238 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-06 22:48:37,238 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-06 22:48:37,239 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-06 22:48:37,240 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-06 22:48:37,240 INFO L138 SettingsManager]: * Use SBE=true [2019-10-06 22:48:37,240 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-06 22:48:37,240 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-06 22:48:37,240 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-06 22:48:37,241 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-06 22:48:37,241 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-06 22:48:37,241 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-06 22:48:37,241 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-06 22:48:37,241 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-06 22:48:37,242 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-06 22:48:37,242 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-06 22:48:37,242 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-06 22:48:37,242 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-06 22:48:37,242 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-06 22:48:37,243 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-06 22:48:37,243 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-06 22:48:37,243 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-06 22:48:37,243 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:37,244 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-06 22:48:37,244 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-06 22:48:37,244 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-06 22:48:37,244 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-06 22:48:37,244 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-06 22:48:37,245 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-06 22:48:37,245 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-06 22:48:37,554 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-06 22:48:37,576 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-06 22:48:37,580 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-06 22:48:37,582 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-06 22:48:37,582 INFO L275 PluginConnector]: CDTParser initialized [2019-10-06 22:48:37,583 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-crafted/mapavg4.i [2019-10-06 22:48:37,659 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/92d6ff119/afd48463f6904ae691033d93d80ead27/FLAGa6714f2f5 [2019-10-06 22:48:38,164 INFO L306 CDTParser]: Found 1 translation units. [2019-10-06 22:48:38,165 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-crafted/mapavg4.i [2019-10-06 22:48:38,171 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/92d6ff119/afd48463f6904ae691033d93d80ead27/FLAGa6714f2f5 [2019-10-06 22:48:38,581 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/92d6ff119/afd48463f6904ae691033d93d80ead27 [2019-10-06 22:48:38,592 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-06 22:48:38,594 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-06 22:48:38,595 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:38,595 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-06 22:48:38,599 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-06 22:48:38,600 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,603 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6d20a304 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:38, skipping insertion in model container [2019-10-06 22:48:38,603 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 10:48:38" (1/1) ... [2019-10-06 22:48:38,611 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-06 22:48:38,635 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-06 22:48:38,862 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:38,872 INFO L188 MainTranslator]: Completed pre-run [2019-10-06 22:48:38,899 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 22:48:39,008 INFO L192 MainTranslator]: Completed translation [2019-10-06 22:48:39,008 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:39 WrapperNode [2019-10-06 22:48:39,008 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-06 22:48:39,009 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-06 22:48:39,009 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-06 22:48:39,010 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-06 22:48:39,024 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:39" (1/1) ... [2019-10-06 22:48:39,024 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:39" (1/1) ... [2019-10-06 22:48:39,033 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:39" (1/1) ... [2019-10-06 22:48:39,033 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:39" (1/1) ... [2019-10-06 22:48:39,042 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:39" (1/1) ... [2019-10-06 22:48:39,047 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:39" (1/1) ... [2019-10-06 22:48:39,049 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:39" (1/1) ... [2019-10-06 22:48:39,052 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-06 22:48:39,052 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-06 22:48:39,052 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-06 22:48:39,052 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-06 22:48:39,053 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:39" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 22:48:39,125 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-06 22:48:39,125 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-06 22:48:39,125 INFO L138 BoogieDeclarations]: Found implementation of procedure mapavg [2019-10-06 22:48:39,126 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-06 22:48:39,126 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-06 22:48:39,126 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-06 22:48:39,126 INFO L130 BoogieDeclarations]: Found specification of procedure mapavg [2019-10-06 22:48:39,126 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-06 22:48:39,126 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-06 22:48:39,126 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-06 22:48:39,127 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-06 22:48:39,127 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-06 22:48:39,127 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-06 22:48:39,127 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-06 22:48:39,534 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-06 22:48:39,534 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-06 22:48:39,536 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39 BoogieIcfgContainer [2019-10-06 22:48:39,536 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-06 22:48:39,537 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-06 22:48:39,538 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-06 22:48:39,540 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-06 22:48:39,541 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.10 10:48:38" (1/3) ... [2019-10-06 22:48:39,541 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@612c7a2a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,542 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 10:48:39" (2/3) ... [2019-10-06 22:48:39,543 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@612c7a2a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 10:48:39, skipping insertion in model container [2019-10-06 22:48:39,543 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 10:48:39" (3/3) ... [2019-10-06 22:48:39,545 INFO L109 eAbstractionObserver]: Analyzing ICFG mapavg4.i [2019-10-06 22:48:39,555 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-06 22:48:39,563 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-06 22:48:39,575 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-06 22:48:39,599 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-06 22:48:39,599 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-06 22:48:39,599 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-06 22:48:39,599 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-06 22:48:39,600 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-06 22:48:39,600 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-06 22:48:39,600 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-06 22:48:39,600 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-06 22:48:39,616 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-06 22:48:39,621 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-06 22:48:39,622 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,623 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,625 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,629 INFO L82 PathProgramCache]: Analyzing trace with hash -1953355565, now seen corresponding path program 1 times [2019-10-06 22:48:39,637 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,637 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,638 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,638 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:39,819 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-06 22:48:39,820 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,821 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:39,822 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:39,826 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:39,837 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:39,838 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,840 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-06 22:48:39,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:39,872 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-06 22:48:39,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:39,874 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-06 22:48:39,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:39,883 INFO L225 Difference]: With dead ends: 41 [2019-10-06 22:48:39,884 INFO L226 Difference]: Without dead ends: 20 [2019-10-06 22:48:39,887 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:39,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-06 22:48:39,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-06 22:48:39,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-06 22:48:39,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-06 22:48:39,926 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-06 22:48:39,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:39,926 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-06 22:48:39,927 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:39,927 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-06 22:48:39,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-06 22:48:39,929 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:39,929 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:39,930 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:39,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:39,930 INFO L82 PathProgramCache]: Analyzing trace with hash -1072677037, now seen corresponding path program 1 times [2019-10-06 22:48:39,931 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:39,931 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:39,931 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,931 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:39,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:39,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,036 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,037 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,037 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:40,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,108 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,115 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,146 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,146 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,205 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 22:48:40,206 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-06 22:48:40,206 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-06 22:48:40,208 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,208 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,208 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,209 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-06 22:48:40,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,224 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-06 22:48:40,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,224 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-06 22:48:40,225 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,226 INFO L225 Difference]: With dead ends: 33 [2019-10-06 22:48:40,226 INFO L226 Difference]: Without dead ends: 21 [2019-10-06 22:48:40,227 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 22:48:40,227 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-06 22:48:40,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-06 22:48:40,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-06 22:48:40,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-06 22:48:40,242 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-06 22:48:40,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,243 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-06 22:48:40,243 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,243 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-06 22:48:40,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-06 22:48:40,245 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,245 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,457 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,457 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,458 INFO L82 PathProgramCache]: Analyzing trace with hash 608739335, now seen corresponding path program 1 times [2019-10-06 22:48:40,458 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,458 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,458 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,459 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,619 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,619 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,620 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 22:48:40,620 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 22:48:40,621 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 22:48:40,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 22:48:40,621 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,622 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-06 22:48:40,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:48:40,632 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-06 22:48:40,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 22:48:40,633 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-06 22:48:40,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:48:40,634 INFO L225 Difference]: With dead ends: 31 [2019-10-06 22:48:40,635 INFO L226 Difference]: Without dead ends: 22 [2019-10-06 22:48:40,635 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 22:48:40,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-06 22:48:40,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-06 22:48:40,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-06 22:48:40,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-06 22:48:40,642 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-06 22:48:40,644 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:48:40,644 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-06 22:48:40,644 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 22:48:40,645 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-06 22:48:40,646 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-06 22:48:40,646 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:48:40,646 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:48:40,647 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:48:40,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:48:40,647 INFO L82 PathProgramCache]: Analyzing trace with hash -824983385, now seen corresponding path program 1 times [2019-10-06 22:48:40,647 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:48:40,648 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,648 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,648 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:48:40,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:48:40,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,772 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,773 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:48:40,773 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:48:40,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:48:40,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:48:40,856 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:48:40,862 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:48:40,905 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,906 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:48:40,958 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:48:40,959 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:48:41,005 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:48:41,006 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:48:41,018 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:48:41,033 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:48:41,034 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:48:41,199 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:48:55,463 WARN L160 IndexEqualityManager]: solver failed to check if following equality is implied: (let ((.cse0 (select |v_#memory_int_46| |main_~#x~0.base|))) (= (select .cse0 (+ |main_~#x~0.offset| 4)) (select .cse0 |main_~#x~0.offset|))) [2019-10-06 22:49:14,146 WARN L160 IndexEqualityManager]: solver failed to check if following equality is implied: (= |main_~#x~0.offset| (+ |main_~#x~0.offset| 4)) [2019-10-06 22:49:24,606 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:49:24,644 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:24,648 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:24,648 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:24,648 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100000)) (<= 100000 main_~i~1)) [2019-10-06 22:49:24,649 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:49:24,649 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:24,649 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:24,649 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 100000 mapavg_~i~0) (<= 0 mapavg_~i~0) (not (< mapavg_~i~0 100000))) [2019-10-06 22:49:24,650 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:24,650 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:49:24,650 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:24,650 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:24,651 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:24,651 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:49:24,651 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:24,651 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 99999)) (<= 99999 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 399996)))) [2019-10-06 22:49:24,652 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:49:24,652 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (not (<= (mod (div v_prenex_1 100000) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_1 100000) 1) 4294967296) 2147483647) (not (= 0 (mod v_prenex_1 100000))) (not (< main_~i~1 100000)) (= (mod (+ (div v_prenex_1 100000) 1) 4294967296) |main_#t~ret4|) (< v_prenex_1 0)) (and (not (<= (mod (div v_prenex_1 100000) 4294967296) 2147483647)) (not (< v_prenex_1 0)) (not (< main_~i~1 100000)) (= |main_#t~ret4| (+ (mod (div v_prenex_1 100000) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_1 100000) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 100000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 1) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_1 0) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 1) 4294967296) (- 4294967296))) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_1 100000))) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 4294967296) 2147483647)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_1 0) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_1 100000))) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 4294967296) 2147483647)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_1 0)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 4294967296)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 4294967296) 2147483647)) (and (not (< main_~i~1 100000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 1) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_1 0)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 4294967296)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 4294967296) 2147483647)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_1 100000)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 4294967296)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 4294967296) 2147483647)) (and (not (<= (mod (div v_prenex_1 100000) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= |main_#t~ret4| (+ (mod (div v_prenex_1 100000) 4294967296) (- 4294967296))) (= 0 (mod v_prenex_1 100000)) (not (<= (mod (+ (div v_prenex_1 100000) 1) 4294967296) 2147483647))) (and (not (<= (mod (div v_prenex_1 100000) 4294967296) 2147483647)) (<= (mod (+ (div v_prenex_1 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (= |main_#t~ret4| (+ (mod (div v_prenex_1 100000) 4294967296) (- 4294967296))) (= 0 (mod v_prenex_1 100000))) (and (not (<= (mod (div v_prenex_1 100000) 4294967296) 2147483647)) (not (< v_prenex_1 0)) (<= (mod (+ (div v_prenex_1 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (= |main_#t~ret4| (+ (mod (div v_prenex_1 100000) 4294967296) (- 4294967296)))) (and (not (<= (mod (div v_prenex_1 100000) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_1 100000))) (not (< main_~i~1 100000)) (< v_prenex_1 0) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1 100000) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_1 100000) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 100000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 1) 4294967296) 2147483647)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_1 100000)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 4294967296)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_1 100000) 4294967296) 2147483647)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_2 Int) (v_prenex_2 Int)) (or (and (not (< main_~i~1 100000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 4294967296) |main_#t~ret4|) (not (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 4294967296) 2147483647) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 100000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 4294967296) |main_#t~ret4|) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 0) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 4294967296) 2147483647) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 1) 4294967296) 2147483647))) (and (not (<= (mod (div v_prenex_2 100000) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= (mod v_prenex_2 100000) 0) (<= (mod (+ (div v_prenex_2 100000) 1) 4294967296) 2147483647) (= (+ (mod (div v_prenex_2 100000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (= (mod v_prenex_2 100000) 0)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_2 100000) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_2 100000) 1) 4294967296) |main_#t~ret4|) (< v_prenex_2 0) (<= (mod (div v_prenex_2 100000) 4294967296) 2147483647)) (and (not (= (mod v_prenex_2 100000) 0)) (not (<= (mod (div v_prenex_2 100000) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_2 100000) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_2 100000) 1) 4294967296) |main_#t~ret4|) (< v_prenex_2 0)) (and (not (< main_~i~1 100000)) (= (mod v_prenex_2 100000) 0) (<= (mod (+ (div v_prenex_2 100000) 1) 4294967296) 2147483647) (= (mod (div v_prenex_2 100000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2 100000) 4294967296) 2147483647)) (and (not (< v_prenex_2 0)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_2 100000) 1) 4294967296) 2147483647) (= (mod (div v_prenex_2 100000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2 100000) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 1) 4294967296) (- 4294967296))) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 0)) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 1) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (and (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_2 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 1) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< v_prenex_2 0)) (not (<= (mod (div v_prenex_2 100000) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_2 100000) 1) 4294967296) 2147483647) (= (+ (mod (div v_prenex_2 100000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 4294967296) 2147483647)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 1) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 1) 4294967296) (- 4294967296))) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 0)) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 4294967296) 2147483647) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_2 100000) 1) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_2 0))))) [2019-10-06 22:49:24,652 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:49:24,653 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:24,653 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:49:24,653 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:49:27,047 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:27,048 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 12] total 17 [2019-10-06 22:49:27,050 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-10-06 22:49:27,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-10-06 22:49:27,054 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=225, Unknown=1, NotChecked=0, Total=272 [2019-10-06 22:49:27,055 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 17 states. [2019-10-06 22:49:47,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:49:47,446 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-06 22:49:47,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-10-06 22:49:47,448 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 29 [2019-10-06 22:49:47,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:49:47,448 INFO L225 Difference]: With dead ends: 40 [2019-10-06 22:49:47,449 INFO L226 Difference]: Without dead ends: 25 [2019-10-06 22:49:47,449 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 11.6s TimeCoverageRelationStatistics Valid=123, Invalid=628, Unknown=5, NotChecked=0, Total=756 [2019-10-06 22:49:47,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-06 22:49:47,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-06 22:49:47,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-06 22:49:47,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-06 22:49:47,465 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-06 22:49:47,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:49:47,467 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-06 22:49:47,467 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-10-06 22:49:47,467 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-06 22:49:47,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-06 22:49:47,470 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:49:47,470 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:49:47,676 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:47,677 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:49:47,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:49:47,677 INFO L82 PathProgramCache]: Analyzing trace with hash 1686538791, now seen corresponding path program 2 times [2019-10-06 22:49:47,677 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:49:47,678 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:47,678 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:47,678 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:49:47,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:49:47,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:49:47,772 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 22:49:47,772 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:49:47,772 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:49:47,773 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:49:47,857 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-06 22:49:47,858 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:49:47,860 INFO L256 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:49:47,864 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:49:47,884 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:49:47,884 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:49:47,915 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 22:49:47,915 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:49:47,917 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:49:47,918 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:49:47,918 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:49:47,919 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:49:47,919 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:49:47,939 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:49:55,069 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:49:55,099 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:49:55,102 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:49:55,102 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:49:55,103 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100000)) (<= 100000 main_~i~1)) [2019-10-06 22:49:55,109 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:49:55,110 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:49:55,110 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:49:55,110 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 100000 mapavg_~i~0) (<= 0 mapavg_~i~0) (not (< mapavg_~i~0 100000))) [2019-10-06 22:49:55,110 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:55,111 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:49:55,111 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:55,111 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:55,111 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:49:55,111 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:49:55,112 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:49:55,112 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 99999)) (<= 99999 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 399996)))) [2019-10-06 22:49:55,114 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:49:55,114 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_361 Int)) (or (and (not (< main_~i~1 100000)) (= (mod (div v_prenex_361 100000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_361 100000) 4294967296) 2147483647) (not (< v_prenex_361 0))) (and (not (< main_~i~1 100000)) (= (+ (mod (div v_prenex_361 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_prenex_361 100000) 0) (not (<= (mod (div v_prenex_361 100000) 4294967296) 2147483647))) (and (not (< main_~i~1 100000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 100000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_27 100000) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_27 0)) (and (not (< main_~i~1 100000)) (= (mod (div v_prenex_361 100000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_361 100000) 4294967296) 2147483647) (= (mod v_prenex_361 100000) 0)) (and (not (< main_~i~1 100000)) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 100000) 1) 4294967296)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_27 100000) 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_27 100000) 1) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_27 0)) (and (not (< main_~i~1 100000)) (= (+ (mod (div v_prenex_361 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< v_prenex_361 0)) (not (<= (mod (div v_prenex_361 100000) 4294967296) 2147483647))))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_28 Int) (v_prenex_362 Int)) (or (and (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100000) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_28 0)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100000) 4294967296) |main_#t~ret4|)) (and (< v_prenex_362 0) (not (< main_~i~1 100000)) (not (= (mod v_prenex_362 100000) 0)) (= (+ (mod (+ (div v_prenex_362 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_362 100000) 1) 4294967296) 2147483647))) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_28 100000) 0) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100000) 4294967296) 2147483647))) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_28 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100000) 4294967296) 2147483647))) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_28 100000) 0) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_28 100000) 4294967296) |main_#t~ret4|)) (and (< v_prenex_362 0) (<= (mod (+ (div v_prenex_362 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (= (mod v_prenex_362 100000) 0)) (= |main_#t~ret4| (mod (+ (div v_prenex_362 100000) 1) 4294967296)))))) [2019-10-06 22:49:55,114 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:49:55,115 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:49:55,115 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:49:55,115 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:49:57,384 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:49:57,385 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-06 22:49:57,386 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-10-06 22:49:57,387 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-10-06 22:49:57,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=359, Unknown=1, NotChecked=0, Total=420 [2019-10-06 22:49:57,387 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 21 states. [2019-10-06 22:50:26,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:50:26,170 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-06 22:50:26,172 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-10-06 22:50:26,173 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 32 [2019-10-06 22:50:26,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:50:26,173 INFO L225 Difference]: With dead ends: 44 [2019-10-06 22:50:26,174 INFO L226 Difference]: Without dead ends: 29 [2019-10-06 22:50:26,175 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 14.8s TimeCoverageRelationStatistics Valid=200, Invalid=1125, Unknown=7, NotChecked=0, Total=1332 [2019-10-06 22:50:26,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-06 22:50:26,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-06 22:50:26,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-06 22:50:26,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-06 22:50:26,181 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-06 22:50:26,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:50:26,182 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-06 22:50:26,182 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-10-06 22:50:26,182 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-06 22:50:26,183 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-06 22:50:26,183 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:50:26,183 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:50:26,386 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:26,386 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:50:26,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:50:26,387 INFO L82 PathProgramCache]: Analyzing trace with hash -682053593, now seen corresponding path program 3 times [2019-10-06 22:50:26,387 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:50:26,388 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:26,388 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:26,388 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:50:26,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:50:26,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:50:26,513 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:26,513 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:50:26,514 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:50:26,514 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:50:26,659 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:50:26,659 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:50:26,661 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-06 22:50:26,671 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:50:26,680 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:26,680 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:50:26,759 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:50:26,759 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:50:26,761 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:50:26,761 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:50:26,762 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:50:26,762 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:50:26,762 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:50:26,776 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:50:44,503 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:50:44,528 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:50:44,530 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:50:44,530 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:50:44,531 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100000)) (<= 100000 main_~i~1)) [2019-10-06 22:50:44,531 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:50:44,531 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:50:44,531 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:50:44,531 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 100000 mapavg_~i~0) (<= 0 mapavg_~i~0) (not (< mapavg_~i~0 100000))) [2019-10-06 22:50:44,532 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:50:44,532 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:50:44,532 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:44,532 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:44,532 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:50:44,532 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:50:44,533 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:50:44,533 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 99999)) (<= 99999 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 399996)))) [2019-10-06 22:50:44,533 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:50:44,533 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_596 Int)) (or (and (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 100000) 4294967296) |main_#t~ret4|) (not (< v_mapavg_~ret~0_BEFORE_RETURN_54 0))) (and (not (< main_~i~1 100000)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_596 100000) 1) 4294967296) (- 4294967296))) (< v_prenex_596 0) (not (<= (mod (+ (div v_prenex_596 100000) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_596 100000)))) (and (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_596 100000) 1) 4294967296) 2147483647) (< v_prenex_596 0) (= (mod (+ (div v_prenex_596 100000) 1) 4294967296) |main_#t~ret4|) (not (= 0 (mod v_prenex_596 100000)))) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 100000) 4294967296) 2147483647)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_54 100000))) (and (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 100000) 4294967296) |main_#t~ret4|) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_54 100000))) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_54 100000) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_54 0))))) (exists ((v_prenex_595 Int) (v_mapavg_~ret~0_BEFORE_RETURN_53 Int)) (or (and (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 1) 4294967296)) (< v_mapavg_~ret~0_BEFORE_RETURN_53 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 1) 4294967296) 2147483647) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 0))) (and (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 4294967296)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 1) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_53 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 4294967296) 2147483647)) (and (<= (mod (div v_prenex_595 100000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_595 100000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_595 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (< v_prenex_595 0) (not (= (mod v_prenex_595 100000) 0))) (and (not (< v_prenex_595 0)) (not (<= (mod (+ (div v_prenex_595 100000) 1) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_595 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_595 100000) 4294967296) 2147483647))) (and (<= (mod (div v_prenex_595 100000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_595 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= |main_#t~ret4| (mod (div v_prenex_595 100000) 4294967296)) (= (mod v_prenex_595 100000) 0)) (and (not (<= (mod (+ (div v_prenex_595 100000) 1) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_595 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_595 100000) 4294967296) 2147483647)) (= (mod v_prenex_595 100000) 0)) (and (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 1) 4294967296)) (< v_mapavg_~ret~0_BEFORE_RETURN_53 0) (not (< main_~i~1 100000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 1) 4294967296) 2147483647) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 4294967296) 2147483647)) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 0) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 1) 4294967296) 2147483647) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (div v_prenex_595 100000) 4294967296) 2147483647) (not (< v_prenex_595 0)) (not (<= (mod (+ (div v_prenex_595 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= |main_#t~ret4| (mod (div v_prenex_595 100000) 4294967296))) (and (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 4294967296)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 0) (not (< main_~i~1 100000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 1) 4294967296) 2147483647) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 4294967296) 2147483647)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 1) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_53 0)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_53 100000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (<= (mod (+ (div v_prenex_595 100000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_595 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_595 100000) 4294967296) 2147483647)) (< v_prenex_595 0) (not (= (mod v_prenex_595 100000) 0)))))) [2019-10-06 22:50:44,533 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:50:44,534 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:50:44,534 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:50:44,534 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:50:46,820 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:50:46,820 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-06 22:50:46,821 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-10-06 22:50:46,822 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-10-06 22:50:46,822 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=469, Unknown=1, NotChecked=0, Total=600 [2019-10-06 22:50:46,822 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 25 states. [2019-10-06 22:51:15,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:51:15,975 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-06 22:51:15,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-10-06 22:51:15,977 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 42 [2019-10-06 22:51:15,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:51:15,978 INFO L225 Difference]: With dead ends: 54 [2019-10-06 22:51:15,978 INFO L226 Difference]: Without dead ends: 36 [2019-10-06 22:51:15,979 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 487 ImplicationChecksByTransitivity, 14.8s TimeCoverageRelationStatistics Valid=359, Invalid=1526, Unknown=7, NotChecked=0, Total=1892 [2019-10-06 22:51:15,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-06 22:51:15,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-06 22:51:15,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-06 22:51:15,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-06 22:51:15,990 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-06 22:51:15,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:51:15,991 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-06 22:51:15,991 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-10-06 22:51:15,991 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-06 22:51:15,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-06 22:51:15,992 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:51:15,992 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:51:16,194 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:16,195 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:51:16,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:51:16,195 INFO L82 PathProgramCache]: Analyzing trace with hash -1538541913, now seen corresponding path program 4 times [2019-10-06 22:51:16,196 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:51:16,196 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:16,196 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:16,197 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:51:16,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:51:16,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:16,369 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:51:16,369 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:51:16,369 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:51:16,369 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:51:16,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:51:16,516 INFO L256 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-06 22:51:16,519 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:51:16,534 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:51:16,535 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:51:16,822 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:51:16,822 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:51:16,824 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:51:16,824 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:51:16,824 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:51:16,825 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:51:16,825 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:51:16,846 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:51:54,893 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:51:54,916 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:51:54,918 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:51:54,918 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:51:54,919 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100000)) (<= 100000 main_~i~1)) [2019-10-06 22:51:54,919 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:51:54,919 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:51:54,919 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:51:54,919 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 100000 mapavg_~i~0) (<= 0 mapavg_~i~0) (not (< mapavg_~i~0 100000))) [2019-10-06 22:51:54,919 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:51:54,920 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:51:54,920 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:51:54,920 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:51:54,920 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:51:54,920 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:51:54,920 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:51:54,920 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 99999)) (<= 99999 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 399996)))) [2019-10-06 22:51:54,920 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:51:54,921 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_890 Int) (v_mapavg_~ret~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 100000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 1) 4294967296) 2147483647) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_80 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 4294967296) (- 4294967296)))) (and (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 1) 4294967296) 2147483647) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_80 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 4294967296) 2147483647)) (and (not (= 0 (mod v_prenex_890 100000))) (not (< main_~i~1 100000)) (< v_prenex_890 0) (not (<= (mod (+ (div v_prenex_890 100000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_890 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (div v_prenex_890 100000) 4294967296) 2147483647)) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_80 0)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 4294967296) (- 4294967296)))) (and (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_80 100000))) (< v_mapavg_~ret~0_BEFORE_RETURN_80 0) (not (< main_~i~1 100000)) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 1) 4294967296)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 4294967296) 2147483647))) (and (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_80 100000))) (< v_mapavg_~ret~0_BEFORE_RETURN_80 0) (not (< main_~i~1 100000)) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 1) 4294967296)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 1) 4294967296) 2147483647) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 4294967296) 2147483647)) (and (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_890 100000) 4294967296) 2147483647)) (= 0 (mod v_prenex_890 100000)) (not (<= (mod (+ (div v_prenex_890 100000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_890 100000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100000)) (= 0 (mod v_prenex_890 100000)) (= (mod (div v_prenex_890 100000) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_890 100000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_890 100000) 4294967296) 2147483647)) (and (not (< main_~i~1 100000)) (not (< v_prenex_890 0)) (= (mod (div v_prenex_890 100000) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_890 100000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_890 100000) 4294967296) 2147483647)) (and (not (= 0 (mod v_prenex_890 100000))) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_890 100000) 4294967296) 2147483647)) (< v_prenex_890 0) (not (<= (mod (+ (div v_prenex_890 100000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_890 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_80 0)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 1) 4294967296) 2147483647) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_80 100000) 4294967296) 2147483647)) (and (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_890 100000) 4294967296) 2147483647)) (not (< v_prenex_890 0)) (not (<= (mod (+ (div v_prenex_890 100000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_890 100000) 4294967296) (- 4294967296)))))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_889 Int)) (or (and (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_79 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 1) 4294967296) 2147483647)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 4294967296) |main_#t~ret4|)) (and (< v_prenex_889 0) (= (+ (mod (+ (div v_prenex_889 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_889 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_prenex_889 100000) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_889 100000)))) (and (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_889 100000) 4294967296) 2147483647)) (not (< v_prenex_889 0)) (= (+ (mod (div v_prenex_889 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_prenex_889 100000) 1) 4294967296) 2147483647)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_79 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_889 100000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_889 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_889 100000) 1) 4294967296) 2147483647)) (= 0 (mod v_prenex_889 100000))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 4294967296) 2147483647) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_79 100000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 4294967296) |main_#t~ret4|)) (and (< v_mapavg_~ret~0_BEFORE_RETURN_79 0) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 1) 4294967296)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_79 100000))) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 4294967296) 2147483647)) (and (< v_prenex_889 0) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_889 100000) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_889 100000))) (= |main_#t~ret4| (mod (+ (div v_prenex_889 100000) 1) 4294967296)) (<= (mod (+ (div v_prenex_889 100000) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_889 100000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_889 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_prenex_889 100000) 1) 4294967296) 2147483647) (= 0 (mod v_prenex_889 100000))) (and (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_889 100000) 4294967296) 2147483647)) (not (< v_prenex_889 0)) (= (+ (mod (div v_prenex_889 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_889 100000) 1) 4294967296) 2147483647))) (and (< v_mapavg_~ret~0_BEFORE_RETURN_79 0) (not (< main_~i~1 100000)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_79 100000))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 1) 4294967296) 2147483647)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 4294967296) 2147483647) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 100000)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 1) 4294967296) 2147483647)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 4294967296) 2147483647) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_79 100000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_79 100000) 4294967296) |main_#t~ret4|))))) [2019-10-06 22:51:54,921 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:51:54,921 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:51:54,921 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:51:54,921 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:51:57,288 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:51:57,289 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-06 22:51:57,290 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2019-10-06 22:51:57,290 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-10-06 22:51:57,291 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=431, Invalid=1050, Unknown=1, NotChecked=0, Total=1482 [2019-10-06 22:51:57,291 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 39 states. [2019-10-06 22:52:22,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:52:22,794 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-06 22:52:22,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-10-06 22:52:22,796 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 49 [2019-10-06 22:52:22,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:52:22,797 INFO L225 Difference]: With dead ends: 68 [2019-10-06 22:52:22,797 INFO L226 Difference]: Without dead ends: 50 [2019-10-06 22:52:22,801 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1243 ImplicationChecksByTransitivity, 15.9s TimeCoverageRelationStatistics Valid=1234, Invalid=3871, Unknown=7, NotChecked=0, Total=5112 [2019-10-06 22:52:22,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-06 22:52:22,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-06 22:52:22,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-06 22:52:22,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-06 22:52:22,809 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-06 22:52:22,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:52:22,809 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-06 22:52:22,809 INFO L463 AbstractCegarLoop]: Interpolant automaton has 39 states. [2019-10-06 22:52:22,809 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-06 22:52:22,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-06 22:52:22,811 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:52:22,811 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:52:23,014 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:52:23,015 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:52:23,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:52:23,015 INFO L82 PathProgramCache]: Analyzing trace with hash -511572313, now seen corresponding path program 5 times [2019-10-06 22:52:23,015 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:52:23,015 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:52:23,015 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:52:23,015 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:52:23,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:52:23,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:52:23,562 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 22:52:23,562 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:52:23,563 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:52:23,563 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:52:23,739 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:52:23,740 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:52:23,741 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 22:52:23,744 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:52:23,791 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-06 22:52:23,791 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:52:23,833 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-06 22:52:23,833 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:52:23,835 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:52:23,835 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:52:23,835 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:52:23,835 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:52:23,835 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:52:23,847 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:52:41,892 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:52:41,936 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:52:41,938 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:52:41,938 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:52:41,939 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100000)) (<= 100000 main_~i~1)) [2019-10-06 22:52:41,939 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:52:41,939 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:52:41,939 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:52:41,939 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 100000 mapavg_~i~0) (<= 0 mapavg_~i~0) (not (< mapavg_~i~0 100000))) [2019-10-06 22:52:41,940 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:52:41,940 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:52:41,940 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:41,940 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:52:41,940 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:52:41,941 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:52:41,941 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:52:41,941 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 99999)) (<= 99999 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 399996)))) [2019-10-06 22:52:41,941 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:52:41,941 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_1267 Int)) (or (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_105 100000) 0) (not (< main_~i~1 100000)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 100000) 4294967296)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 100000) 4294967296) 2147483647)) (and (not (= (mod v_prenex_1267 100000) 0)) (<= (mod (+ (div v_prenex_1267 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (< v_prenex_1267 0) (= |main_#t~ret4| (mod (+ (div v_prenex_1267 100000) 1) 4294967296))) (and (not (= (mod v_prenex_1267 100000) 0)) (not (<= (mod (+ (div v_prenex_1267 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= (+ (mod (+ (div v_prenex_1267 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (< v_prenex_1267 0)) (and (not (< main_~i~1 100000)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 100000) 4294967296)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_105 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 100000) 4294967296) 2147483647)) (and (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_105 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 100000) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 100000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_105 100000) 0) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 100000) 4294967296) 2147483647)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_105 100000) 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_1268 Int)) (or (and (= (mod v_prenex_1268 100000) 0) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_1268 100000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_1268 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1268 100000) 1) 4294967296) 2147483647)) (and (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_106 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 1) 4294967296) 2147483647)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 0))) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_106 0)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 100000)) (not (< v_prenex_1268 0)) (not (<= (mod (div v_prenex_1268 100000) 4294967296) 2147483647)) (= (+ (mod (div v_prenex_1268 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1268 100000) 1) 4294967296) 2147483647)) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 4294967296) 2147483647)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 1) 4294967296) 2147483647))) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_106 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 100000)) (<= (mod (div v_prenex_1268 100000) 4294967296) 2147483647) (not (< v_prenex_1268 0)) (<= (mod (+ (div v_prenex_1268 100000) 1) 4294967296) 2147483647) (= (mod (div v_prenex_1268 100000) 4294967296) |main_#t~ret4|)) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 4294967296) 2147483647) (not (< main_~i~1 100000)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 4294967296) |main_#t~ret4|) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 1) 4294967296) 2147483647))) (and (not (= (mod v_prenex_1268 100000) 0)) (not (< main_~i~1 100000)) (<= (mod (div v_prenex_1268 100000) 4294967296) 2147483647) (= (mod (+ (div v_prenex_1268 100000) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1268 100000) 1) 4294967296) 2147483647) (< v_prenex_1268 0)) (and (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 4294967296) 2147483647) (not (< main_~i~1 100000)) (< v_mapavg_~ret~0_BEFORE_RETURN_106 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 1) 4294967296) 2147483647)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_106 100000) 0))) (and (= (mod v_prenex_1268 100000) 0) (not (< main_~i~1 100000)) (<= (mod (div v_prenex_1268 100000) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_1268 100000) 1) 4294967296) 2147483647) (= (mod (div v_prenex_1268 100000) 4294967296) |main_#t~ret4|)) (and (not (= (mod v_prenex_1268 100000) 0)) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_1268 100000) 4294967296) 2147483647)) (= (mod (+ (div v_prenex_1268 100000) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1268 100000) 1) 4294967296) 2147483647) (< v_prenex_1268 0))))) [2019-10-06 22:52:41,942 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:52:41,942 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:52:41,942 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:52:41,942 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:52:44,424 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:52:44,424 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-06 22:52:44,426 INFO L442 AbstractCegarLoop]: Interpolant automaton has 43 states [2019-10-06 22:52:44,426 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2019-10-06 22:52:44,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=445, Invalid=1360, Unknown=1, NotChecked=0, Total=1806 [2019-10-06 22:52:44,428 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 43 states. [2019-10-06 22:53:17,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:53:17,162 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-06 22:53:17,163 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2019-10-06 22:53:17,163 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 63 [2019-10-06 22:53:17,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:53:17,164 INFO L225 Difference]: With dead ends: 72 [2019-10-06 22:53:17,164 INFO L226 Difference]: Without dead ends: 54 [2019-10-06 22:53:17,167 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 177 SyntacticMatches, 0 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1241 ImplicationChecksByTransitivity, 28.4s TimeCoverageRelationStatistics Valid=1339, Invalid=5129, Unknown=12, NotChecked=0, Total=6480 [2019-10-06 22:53:17,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-06 22:53:17,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-06 22:53:17,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-06 22:53:17,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-06 22:53:17,176 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-06 22:53:17,176 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:53:17,176 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-06 22:53:17,176 INFO L463 AbstractCegarLoop]: Interpolant automaton has 43 states. [2019-10-06 22:53:17,176 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-06 22:53:17,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-06 22:53:17,177 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:53:17,178 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:53:17,380 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:53:17,381 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:53:17,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:53:17,382 INFO L82 PathProgramCache]: Analyzing trace with hash -637611949, now seen corresponding path program 6 times [2019-10-06 22:53:17,382 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:53:17,382 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:53:17,382 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:53:17,383 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:53:17,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:53:17,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:53:17,837 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:17,837 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:53:17,837 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:53:17,837 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:53:18,087 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:53:18,088 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:53:18,089 INFO L256 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-06 22:53:18,092 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:53:18,112 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:18,112 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:53:19,110 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:53:19,110 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:53:19,112 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:53:19,112 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:53:19,112 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:53:19,112 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:53:19,113 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:53:19,136 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:53:29,588 WARN L160 IndexEqualityManager]: solver failed to check if following equality is implied: (= |main_~#x~0.offset| (+ |main_~#x~0.offset| 4)) [2019-10-06 22:53:38,901 WARN L176 IndexEqualityManager]: solver failed to check if following not equals relation is implied: (let ((.cse0 (select |v_#memory_int_245| |main_~#x~0.base|))) (= (select .cse0 |main_~#x~0.offset|) (select .cse0 (+ |main_~#x~0.offset| 4)))) [2019-10-06 22:53:45,334 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:53:45,370 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:53:45,372 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:53:45,372 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:53:45,372 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100000)) (<= 100000 main_~i~1)) [2019-10-06 22:53:45,373 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:53:45,373 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:53:45,373 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:53:45,373 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 100000 mapavg_~i~0) (<= 0 mapavg_~i~0) (not (< mapavg_~i~0 100000))) [2019-10-06 22:53:45,373 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:53:45,374 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:53:45,374 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:45,374 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:45,375 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:53:45,375 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:53:45,375 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:53:45,375 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 99999)) (<= 99999 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 399996)))) [2019-10-06 22:53:45,375 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:53:45,375 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1573 Int) (v_mapavg_~ret~0_BEFORE_RETURN_131 Int)) (or (and (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_131 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100000) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 100000)) (< v_prenex_1573 0) (not (<= (mod (+ (div v_prenex_1573 100000) 1) 4294967296) 2147483647)) (not (= (mod v_prenex_1573 100000) 0)) (= (+ (mod (+ (div v_prenex_1573 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_131 100000) 0) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100000) 4294967296) |main_#t~ret4|)) (and (= |main_#t~ret4| (mod (+ (div v_prenex_1573 100000) 1) 4294967296)) (not (< main_~i~1 100000)) (< v_prenex_1573 0) (not (= (mod v_prenex_1573 100000) 0)) (<= (mod (+ (div v_prenex_1573 100000) 1) 4294967296) 2147483647)) (and (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_131 0)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100000) 4294967296) (- 4294967296))) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100000) 4294967296) 2147483647))) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_131 100000) 0) (not (< main_~i~1 100000)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100000) 4294967296) (- 4294967296))) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_131 100000) 4294967296) 2147483647))))) (exists ((v_prenex_1574 Int) (v_mapavg_~ret~0_BEFORE_RETURN_132 Int)) (or (and (not (<= (mod (div v_prenex_1574 100000) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (= 0 (mod v_prenex_1574 100000))) (<= (mod (+ (div v_prenex_1574 100000) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_1574 100000) 1) 4294967296) |main_#t~ret4|) (< v_prenex_1574 0)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_132 100000))) (not (< main_~i~1 100000)) (< v_mapavg_~ret~0_BEFORE_RETURN_132 0)) (and (not (<= (mod (div v_prenex_1574 100000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_1574 100000) 4294967296) (- 4294967296))) (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_1574 100000) 1) 4294967296) 2147483647) (not (< v_prenex_1574 0))) (and (= (mod (div v_prenex_1574 100000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100000)) (<= (mod (div v_prenex_1574 100000) 4294967296) 2147483647) (<= (mod (+ (div v_prenex_1574 100000) 1) 4294967296) 2147483647) (not (< v_prenex_1574 0))) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_132 100000))) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_132 0)) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_132 0)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 100000)) (<= (mod (div v_prenex_1574 100000) 4294967296) 2147483647) (not (= 0 (mod v_prenex_1574 100000))) (<= (mod (+ (div v_prenex_1574 100000) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_1574 100000) 1) 4294967296) |main_#t~ret4|) (< v_prenex_1574 0)) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_132 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 4294967296) |main_#t~ret4|)) (and (not (<= (mod (div v_prenex_1574 100000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_prenex_1574 100000) 4294967296) (- 4294967296))) (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_1574 100000) 1) 4294967296) 2147483647) (= 0 (mod v_prenex_1574 100000))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_132 100000)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 4294967296) (- 4294967296)))) (and (= (mod (div v_prenex_1574 100000) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100000)) (<= (mod (div v_prenex_1574 100000) 4294967296) 2147483647) (= 0 (mod v_prenex_1574 100000)) (<= (mod (+ (div v_prenex_1574 100000) 1) 4294967296) 2147483647)) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_132 0)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_132 100000) 4294967296) (- 4294967296))))))) [2019-10-06 22:53:45,376 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:53:45,376 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:53:45,376 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:53:45,376 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:53:47,822 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:53:47,823 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-06 22:53:47,824 INFO L442 AbstractCegarLoop]: Interpolant automaton has 69 states [2019-10-06 22:53:47,825 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2019-10-06 22:53:47,826 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1736, Invalid=2955, Unknown=1, NotChecked=0, Total=4692 [2019-10-06 22:53:47,827 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 69 states. [2019-10-06 22:54:04,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:54:04,291 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-06 22:54:04,292 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2019-10-06 22:54:04,292 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 67 [2019-10-06 22:54:04,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:54:04,293 INFO L225 Difference]: With dead ends: 104 [2019-10-06 22:54:04,294 INFO L226 Difference]: Without dead ends: 83 [2019-10-06 22:54:04,299 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 295 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3690 ImplicationChecksByTransitivity, 11.2s TimeCoverageRelationStatistics Valid=5089, Invalid=12200, Unknown=3, NotChecked=0, Total=17292 [2019-10-06 22:54:04,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-06 22:54:04,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-06 22:54:04,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-06 22:54:04,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-06 22:54:04,309 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-06 22:54:04,309 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:54:04,309 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-06 22:54:04,309 INFO L463 AbstractCegarLoop]: Interpolant automaton has 69 states. [2019-10-06 22:54:04,310 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-06 22:54:04,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-06 22:54:04,311 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:54:04,311 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:54:04,514 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:54:04,514 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:54:04,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:54:04,515 INFO L82 PathProgramCache]: Analyzing trace with hash -421590573, now seen corresponding path program 7 times [2019-10-06 22:54:04,515 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:54:04,515 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:54:04,516 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:04,516 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:54:04,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:54:04,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:54:06,035 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:54:06,035 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:54:06,035 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:54:06,036 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:54:06,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:54:06,331 INFO L256 TraceCheckSpWp]: Trace formula consists of 529 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-06 22:54:06,334 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:54:06,367 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:54:06,367 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:54:10,102 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:54:10,103 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:54:10,104 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:54:10,104 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:54:10,104 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:54:10,105 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:54:10,105 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:54:10,117 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:54:32,940 WARN L176 IndexEqualityManager]: solver failed to check if following not equals relation is implied: (= (select (select |v_#memory_int_328| |main_~#x~0.base|) |main_~#x~0.offset|) main_~temp~0) [2019-10-06 22:54:52,351 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:54:52,373 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:54:52,375 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:54:52,375 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:54:52,375 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100000)) (<= 100000 main_~i~1)) [2019-10-06 22:54:52,375 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:54:52,375 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:54:52,375 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:54:52,376 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 100000 mapavg_~i~0) (<= 0 mapavg_~i~0) (not (< mapavg_~i~0 100000))) [2019-10-06 22:54:52,376 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:54:52,376 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:54:52,376 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:52,376 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:52,376 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:54:52,377 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:54:52,377 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:54:52,377 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 99999)) (<= 99999 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 399996)))) [2019-10-06 22:54:52,377 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:54:52,378 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_157 Int) (v_prenex_1867 Int)) (or (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 4294967296) |main_#t~ret4|) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 0)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 1) 4294967296) 2147483647) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 0)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_157 0)) (and (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 0)) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_157 0) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 1) 4294967296) (- 4294967296)))) (and (= (+ (mod (div v_prenex_1867 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1867 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_1867 100000) 4294967296) 2147483647)) (= (mod v_prenex_1867 100000) 0)) (and (= (+ (mod (div v_prenex_1867 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1867 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_1867 100000) 4294967296) 2147483647)) (not (< v_prenex_1867 0))) (and (<= (mod (+ (div v_prenex_1867 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_1867 100000) 4294967296) 2147483647)) (< v_prenex_1867 0) (= (mod (+ (div v_prenex_1867 100000) 1) 4294967296) |main_#t~ret4|) (not (= (mod v_prenex_1867 100000) 0))) (and (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 1) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_157 0))) (and (= (+ (mod (div v_prenex_1867 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_1867 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_1867 100000) 4294967296) 2147483647)) (not (< v_prenex_1867 0))) (and (= (+ (mod (div v_prenex_1867 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_1867 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_1867 100000) 4294967296) 2147483647)) (= (mod v_prenex_1867 100000) 0)) (and (not (<= (mod (+ (div v_prenex_1867 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_1867 100000) 1) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_1867 100000) 4294967296) 2147483647)) (< v_prenex_1867 0) (not (= (mod v_prenex_1867 100000) 0))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 4294967296) |main_#t~ret4|) (not (< v_mapavg_~ret~0_BEFORE_RETURN_157 0))) (and (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 4294967296) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 1) 4294967296) 2147483647)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_157 100000) 0)))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1868 Int)) (or (and (<= (mod (div v_prenex_1868 100000) 4294967296) 2147483647) (not (< v_prenex_1868 0)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_1868 100000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_1868 100000) 4294967296))) (and (= |main_#t~ret4| (+ (mod (div v_prenex_1868 100000) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_1868 100000) 4294967296) 2147483647)) (not (< v_prenex_1868 0)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_1868 100000) 1) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_158 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 4294967296))) (and (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_158 100000))) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_158 0)) (and (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 4294967296)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_158 0))) (and (= |main_#t~ret4| (+ (mod (div v_prenex_1868 100000) 4294967296) (- 4294967296))) (not (<= (mod (div v_prenex_1868 100000) 4294967296) 2147483647)) (= 0 (mod v_prenex_1868 100000)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_1868 100000) 1) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_158 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 4294967296) 2147483647))) (and (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 4294967296) 2147483647) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_158 100000))) (< v_mapavg_~ret~0_BEFORE_RETURN_158 0)) (and (<= (mod (div v_prenex_1868 100000) 4294967296) 2147483647) (not (< main_~i~1 100000)) (< v_prenex_1868 0) (not (= 0 (mod v_prenex_1868 100000))) (= (mod (+ (div v_prenex_1868 100000) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1868 100000) 1) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_158 100000) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_158 0))) (and (<= (mod (div v_prenex_1868 100000) 4294967296) 2147483647) (= 0 (mod v_prenex_1868 100000)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_1868 100000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_1868 100000) 4294967296))) (and (not (<= (mod (div v_prenex_1868 100000) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (< v_prenex_1868 0) (not (= 0 (mod v_prenex_1868 100000))) (= (mod (+ (div v_prenex_1868 100000) 1) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_prenex_1868 100000) 1) 4294967296) 2147483647))))) [2019-10-06 22:54:52,378 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:54:52,378 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:54:52,378 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:54:52,378 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:54:55,107 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:54:55,108 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 127 [2019-10-06 22:54:55,109 INFO L442 AbstractCegarLoop]: Interpolant automaton has 127 states [2019-10-06 22:54:55,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 127 interpolants. [2019-10-06 22:54:55,115 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6811, Invalid=9190, Unknown=1, NotChecked=0, Total=16002 [2019-10-06 22:54:55,115 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 127 states. [2019-10-06 22:55:29,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:55:29,381 INFO L93 Difference]: Finished difference Result 162 states and 227 transitions. [2019-10-06 22:55:29,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 126 states. [2019-10-06 22:55:29,382 INFO L78 Accepts]: Start accepts. Automaton has 127 states. Word has length 96 [2019-10-06 22:55:29,383 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:55:29,383 INFO L225 Difference]: With dead ends: 162 [2019-10-06 22:55:29,384 INFO L226 Difference]: Without dead ends: 141 [2019-10-06 22:55:29,389 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 223 SyntacticMatches, 0 SemanticMatches, 246 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11605 ImplicationChecksByTransitivity, 27.2s TimeCoverageRelationStatistics Valid=20198, Invalid=41052, Unknown=6, NotChecked=0, Total=61256 [2019-10-06 22:55:29,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2019-10-06 22:55:29,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2019-10-06 22:55:29,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2019-10-06 22:55:29,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 145 transitions. [2019-10-06 22:55:29,406 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 145 transitions. Word has length 96 [2019-10-06 22:55:29,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:55:29,407 INFO L462 AbstractCegarLoop]: Abstraction has 141 states and 145 transitions. [2019-10-06 22:55:29,407 INFO L463 AbstractCegarLoop]: Interpolant automaton has 127 states. [2019-10-06 22:55:29,407 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 145 transitions. [2019-10-06 22:55:29,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2019-10-06 22:55:29,409 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:55:29,410 INFO L385 BasicCegarLoop]: trace histogram [114, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:55:29,614 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:55:29,614 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:55:29,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:55:29,615 INFO L82 PathProgramCache]: Analyzing trace with hash 1491638739, now seen corresponding path program 8 times [2019-10-06 22:55:29,615 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:55:29,615 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:55:29,616 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:55:29,616 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:55:29,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:55:29,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:55:34,994 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 0 proven. 6555 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 22:55:34,995 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:55:34,995 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:55:34,995 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:55:35,304 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 22:55:35,304 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:55:35,305 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 22:55:35,308 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:55:35,577 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 22:55:35,577 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:55:35,864 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 22:55:35,865 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:55:35,866 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:55:35,866 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:55:35,867 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:55:35,867 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:55:35,867 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:55:35,880 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:56:04,673 WARN L160 IndexEqualityManager]: solver failed to check if following equality is implied: (= |main_~#x~0.offset| (+ |main_~#x~0.offset| 4)) [2019-10-06 22:56:17,038 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:56:17,059 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:56:17,061 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:56:17,061 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:56:17,062 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100000)) (<= 100000 main_~i~1)) [2019-10-06 22:56:17,062 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:56:17,062 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:56:17,062 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:56:17,062 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 100000 mapavg_~i~0) (<= 0 mapavg_~i~0) (not (< mapavg_~i~0 100000))) [2019-10-06 22:56:17,063 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:56:17,063 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:56:17,063 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:17,063 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:17,063 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:56:17,063 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:56:17,063 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:56:17,064 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 99999)) (<= 99999 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 399996)))) [2019-10-06 22:56:17,064 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:56:17,064 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2221 Int) (v_mapavg_~ret~0_BEFORE_RETURN_183 Int)) (or (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_183 0)) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 4294967296) |main_#t~ret4|) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 1) 4294967296) 2147483647)) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 4294967296) 2147483647) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 0) (not (< main_~i~1 100000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 1) 4294967296) 2147483647) (= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 4294967296) |main_#t~ret4|)) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 0)) (< v_mapavg_~ret~0_BEFORE_RETURN_183 0) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 1) 4294967296)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 1) 4294967296) 2147483647)) (and (= (+ (mod (+ (div v_prenex_2221 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_2221 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (= (mod v_prenex_2221 100000) 0)) (not (<= (mod (div v_prenex_2221 100000) 4294967296) 2147483647)) (< v_prenex_2221 0)) (and (not (<= (mod (+ (div v_prenex_2221 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (< v_prenex_2221 0)) (= (+ (mod (div v_prenex_2221 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2221 100000) 4294967296) 2147483647))) (and (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_183 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 4294967296) 2147483647)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 1) 4294967296) 2147483647)) (and (<= (mod (div v_prenex_2221 100000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2221 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (< v_prenex_2221 0)) (= (mod (div v_prenex_2221 100000) 4294967296) |main_#t~ret4|)) (and (<= (mod (div v_prenex_2221 100000) 4294967296) 2147483647) (= (+ (mod (+ (div v_prenex_2221 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_2221 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (= (mod v_prenex_2221 100000) 0)) (< v_prenex_2221 0)) (and (not (< main_~i~1 100000)) (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_183 0) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 1) 4294967296))) (and (= (mod v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 0) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 4294967296) 2147483647)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_183 100000) 1) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_2221 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= (+ (mod (div v_prenex_2221 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2221 100000) 4294967296) 2147483647)) (= (mod v_prenex_2221 100000) 0)) (and (<= (mod (div v_prenex_2221 100000) 4294967296) 2147483647) (not (<= (mod (+ (div v_prenex_2221 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= (mod (div v_prenex_2221 100000) 4294967296) |main_#t~ret4|) (= (mod v_prenex_2221 100000) 0)))) (exists ((v_prenex_2222 Int) (v_mapavg_~ret~0_BEFORE_RETURN_184 Int)) (or (and (= |main_#t~ret4| (mod (div v_prenex_2222 100000) 4294967296)) (not (< main_~i~1 100000)) (not (<= (mod (+ (div v_prenex_2222 100000) 1) 4294967296) 2147483647)) (= 0 (mod v_prenex_2222 100000)) (<= (mod (div v_prenex_2222 100000) 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod (div v_prenex_2222 100000) 4294967296) (- 4294967296))) (not (< v_prenex_2222 0)) (not (< main_~i~1 100000)) (not (<= (mod (+ (div v_prenex_2222 100000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2222 100000) 4294967296) 2147483647))) (and (not (= 0 (mod v_prenex_2222 100000))) (< v_prenex_2222 0) (not (< main_~i~1 100000)) (= (+ (mod (+ (div v_prenex_2222 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_2222 100000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2222 100000) 4294967296) 2147483647)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 4294967296) (- 4294967296))) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_184 100000))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_184 0)) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 4294967296))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 4294967296)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_184 100000))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 1) 4294967296) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_184 0) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_184 100000)))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 4294967296) 2147483647)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_184 0)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 4294967296) (- 4294967296)))) (and (not (< v_prenex_2222 0)) (= |main_#t~ret4| (mod (div v_prenex_2222 100000) 4294967296)) (not (< main_~i~1 100000)) (not (<= (mod (+ (div v_prenex_2222 100000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2222 100000) 4294967296) 2147483647)) (and (not (= 0 (mod v_prenex_2222 100000))) (< v_prenex_2222 0) (not (< main_~i~1 100000)) (= (+ (mod (+ (div v_prenex_2222 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (+ (div v_prenex_2222 100000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2222 100000) 4294967296) 2147483647))) (and (= |main_#t~ret4| (+ (mod (div v_prenex_2222 100000) 4294967296) (- 4294967296))) (not (< main_~i~1 100000)) (not (<= (mod (+ (div v_prenex_2222 100000) 1) 4294967296) 2147483647)) (not (<= (mod (div v_prenex_2222 100000) 4294967296) 2147483647)) (= 0 (mod v_prenex_2222 100000))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 1) 4294967296) |main_#t~ret4|) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_184 100000) 4294967296) 2147483647) (< v_mapavg_~ret~0_BEFORE_RETURN_184 0) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_184 100000))))))) [2019-10-06 22:56:17,064 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:56:17,065 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:56:17,065 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:56:17,065 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:56:20,613 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:56:20,614 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [117, 7, 7, 11] total 137 [2019-10-06 22:56:20,615 INFO L442 AbstractCegarLoop]: Interpolant automaton has 137 states [2019-10-06 22:56:20,617 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 137 interpolants. [2019-10-06 22:56:20,618 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6876, Invalid=11755, Unknown=1, NotChecked=0, Total=18632 [2019-10-06 22:56:20,619 INFO L87 Difference]: Start difference. First operand 141 states and 145 transitions. Second operand 137 states. [2019-10-06 22:56:58,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:56:58,307 INFO L93 Difference]: Finished difference Result 169 states and 186 transitions. [2019-10-06 22:56:58,308 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 137 states. [2019-10-06 22:56:58,308 INFO L78 Accepts]: Start accepts. Automaton has 137 states. Word has length 154 [2019-10-06 22:56:58,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:56:58,310 INFO L225 Difference]: With dead ends: 169 [2019-10-06 22:56:58,310 INFO L226 Difference]: Without dead ends: 148 [2019-10-06 22:56:58,315 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 710 GetRequests, 443 SyntacticMatches, 0 SemanticMatches, 267 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11913 ImplicationChecksByTransitivity, 33.0s TimeCoverageRelationStatistics Valid=20684, Invalid=51401, Unknown=7, NotChecked=0, Total=72092 [2019-10-06 22:56:58,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2019-10-06 22:56:58,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 148. [2019-10-06 22:56:58,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2019-10-06 22:56:58,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 152 transitions. [2019-10-06 22:56:58,330 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 152 transitions. Word has length 154 [2019-10-06 22:56:58,331 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:56:58,331 INFO L462 AbstractCegarLoop]: Abstraction has 148 states and 152 transitions. [2019-10-06 22:56:58,331 INFO L463 AbstractCegarLoop]: Interpolant automaton has 137 states. [2019-10-06 22:56:58,331 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 152 transitions. [2019-10-06 22:56:58,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2019-10-06 22:56:58,333 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:56:58,333 INFO L385 BasicCegarLoop]: trace histogram [115, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:56:58,534 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:56:58,534 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:56:58,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:56:58,535 INFO L82 PathProgramCache]: Analyzing trace with hash 1419883091, now seen corresponding path program 9 times [2019-10-06 22:56:58,535 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:56:58,535 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:56:58,536 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:56:58,536 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:56:58,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:56:58,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:57:04,336 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:57:04,336 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:57:04,336 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:57:04,337 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:57:04,771 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 22:57:04,772 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 22:57:04,777 INFO L256 TraceCheckSpWp]: Trace formula consists of 973 conjuncts, 117 conjunts are in the unsatisfiable core [2019-10-06 22:57:04,781 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:57:04,824 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:57:04,824 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 22:57:20,454 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:57:20,454 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 22:57:20,455 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 22:57:20,456 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 22:57:20,456 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 22:57:20,456 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 22:57:20,456 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 22:57:20,473 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 22:57:58,230 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 22:57:58,250 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 22:57:58,252 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 22:57:58,252 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 22:57:58,252 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100000)) (<= 100000 main_~i~1)) [2019-10-06 22:57:58,252 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 22:57:58,253 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 22:57:58,253 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 22:57:58,253 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 100000 mapavg_~i~0) (<= 0 mapavg_~i~0) (not (< mapavg_~i~0 100000))) [2019-10-06 22:57:58,253 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:57:58,253 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 22:57:58,253 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:57:58,253 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 22:57:58,253 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 22:57:58,254 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 22:57:58,254 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 22:57:58,254 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 99999)) (<= 99999 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 399996)))) [2019-10-06 22:57:58,254 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 22:57:58,255 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2600 Int) (v_mapavg_~ret~0_BEFORE_RETURN_210 Int)) (or (and (< v_mapavg_~ret~0_BEFORE_RETURN_210 0) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 4294967296) 2147483647) (= (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_210 100000))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 1) 4294967296) 2147483647))) (and (< v_prenex_2600 0) (not (= 0 (mod v_prenex_2600 100000))) (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_2600 100000) 1) 4294967296) 2147483647) (= (mod (+ (div v_prenex_2600 100000) 1) 4294967296) |main_#t~ret4|) (not (<= (mod (div v_prenex_2600 100000) 4294967296) 2147483647))) (and (not (< main_~i~1 100000)) (= (+ (mod (div v_prenex_2600 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2600 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_prenex_2600 100000) 1) 4294967296) 2147483647)) (not (< v_prenex_2600 0))) (and (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_2600 100000) 1) 4294967296) 2147483647) (= 0 (mod v_prenex_2600 100000)) (= (+ (mod (div v_prenex_2600 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2600 100000) 4294967296) 2147483647))) (and (< v_mapavg_~ret~0_BEFORE_RETURN_210 0) (not (< main_~i~1 100000)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 1) 4294967296) |main_#t~ret4|) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 4294967296) 2147483647) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_210 100000))) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 1) 4294967296) 2147483647)) (and (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 4294967296)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_210 100000)) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 4294967296) 2147483647) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 1) 4294967296) 2147483647)) (and (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 4294967296)) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_210 0)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 1) 4294967296) 2147483647))) (and (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 4294967296)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_210 100000)) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 4294967296) 2147483647) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 1) 4294967296) 2147483647))) (and (not (< main_~i~1 100000)) (= 0 (mod v_prenex_2600 100000)) (= (+ (mod (div v_prenex_2600 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2600 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_prenex_2600 100000) 1) 4294967296) 2147483647))) (and (< v_prenex_2600 0) (not (= 0 (mod v_prenex_2600 100000))) (not (< main_~i~1 100000)) (not (<= (mod (div v_prenex_2600 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_prenex_2600 100000) 1) 4294967296) 2147483647)) (= (+ (mod (+ (div v_prenex_2600 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_2600 100000) 1) 4294967296) 2147483647) (= (+ (mod (div v_prenex_2600 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_prenex_2600 100000) 4294967296) 2147483647)) (not (< v_prenex_2600 0))) (and (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 4294967296)) (not (< main_~i~1 100000)) (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 4294967296) 2147483647) (not (< v_mapavg_~ret~0_BEFORE_RETURN_210 0)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_210 100000) 1) 4294967296) 2147483647)))) (exists ((v_prenex_2599 Int) (v_mapavg_~ret~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 100000)) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2599 100000) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_prenex_2599 100000) 1) 4294967296) 2147483647)) (not (= 0 (mod v_prenex_2599 100000))) (<= (mod (div v_prenex_2599 100000) 4294967296) 2147483647) (< v_prenex_2599 0)) (and (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_209 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100000)) (<= (mod (+ (div v_prenex_2599 100000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_2599 100000) 4294967296)) (<= (mod (div v_prenex_2599 100000) 4294967296) 2147483647) (= 0 (mod v_prenex_2599 100000))) (and (not (< main_~i~1 100000)) (= |main_#t~ret4| (mod (div v_prenex_2599 100000) 4294967296)) (not (<= (mod (+ (div v_prenex_2599 100000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2599 100000) 4294967296) 2147483647) (= 0 (mod v_prenex_2599 100000))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_209 0) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_209 100000))) (= |main_#t~ret4| (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 1) 4294967296))) (and (not (< main_~i~1 100000)) (not (< v_prenex_2599 0)) (= |main_#t~ret4| (mod (div v_prenex_2599 100000) 4294967296)) (not (<= (mod (+ (div v_prenex_2599 100000) 1) 4294967296) 2147483647)) (<= (mod (div v_prenex_2599 100000) 4294967296) 2147483647)) (and (not (< main_~i~1 100000)) (= |main_#t~ret4| (mod (+ (div v_prenex_2599 100000) 1) 4294967296)) (<= (mod (+ (div v_prenex_2599 100000) 1) 4294967296) 2147483647) (not (= 0 (mod v_prenex_2599 100000))) (<= (mod (div v_prenex_2599 100000) 4294967296) 2147483647) (< v_prenex_2599 0)) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_209 0)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 1) 4294967296) 2147483647)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_209 100000)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100000)) (not (< v_prenex_2599 0)) (<= (mod (+ (div v_prenex_2599 100000) 1) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_prenex_2599 100000) 4294967296)) (<= (mod (div v_prenex_2599 100000) 4294967296) 2147483647)) (and (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 1) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 1) 4294967296) (- 4294967296))) (< v_mapavg_~ret~0_BEFORE_RETURN_209 0) (not (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_209 100000)))) (and (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 1) 4294967296) 2147483647) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 4294967296) 2147483647)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_209 100000)) (= |main_#t~ret4| (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_209 100000) 4294967296) (- 4294967296))))))) [2019-10-06 22:57:58,255 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 22:57:58,255 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 22:57:58,255 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 22:57:58,255 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 22:58:01,482 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 22:58:01,483 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [118, 118, 118, 11] total 245 [2019-10-06 22:58:01,484 INFO L442 AbstractCegarLoop]: Interpolant automaton has 245 states [2019-10-06 22:58:01,489 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 245 interpolants. [2019-10-06 22:58:01,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27520, Invalid=32259, Unknown=1, NotChecked=0, Total=59780 [2019-10-06 22:58:01,492 INFO L87 Difference]: Start difference. First operand 148 states and 152 transitions. Second operand 245 states. [2019-10-06 22:59:02,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 22:59:02,534 INFO L93 Difference]: Finished difference Result 292 states and 416 transitions. [2019-10-06 22:59:02,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 244 states. [2019-10-06 22:59:02,535 INFO L78 Accepts]: Start accepts. Automaton has 245 states. Word has length 173 [2019-10-06 22:59:02,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 22:59:02,537 INFO L225 Difference]: With dead ends: 292 [2019-10-06 22:59:02,538 INFO L226 Difference]: Without dead ends: 265 [2019-10-06 22:59:02,546 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 877 GetRequests, 395 SyntacticMatches, 0 SemanticMatches, 482 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40692 ImplicationChecksByTransitivity, 69.4s TimeCoverageRelationStatistics Valid=82089, Invalid=151676, Unknown=7, NotChecked=0, Total=233772 [2019-10-06 22:59:02,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2019-10-06 22:59:02,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 265. [2019-10-06 22:59:02,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2019-10-06 22:59:02,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 269 transitions. [2019-10-06 22:59:02,568 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 269 transitions. Word has length 173 [2019-10-06 22:59:02,573 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 22:59:02,573 INFO L462 AbstractCegarLoop]: Abstraction has 265 states and 269 transitions. [2019-10-06 22:59:02,573 INFO L463 AbstractCegarLoop]: Interpolant automaton has 245 states. [2019-10-06 22:59:02,573 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 269 transitions. [2019-10-06 22:59:02,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2019-10-06 22:59:02,578 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 22:59:02,578 INFO L385 BasicCegarLoop]: trace histogram [232, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 22:59:02,783 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:59:02,783 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 22:59:02,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 22:59:02,784 INFO L82 PathProgramCache]: Analyzing trace with hash -424031277, now seen corresponding path program 10 times [2019-10-06 22:59:02,784 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 22:59:02,784 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:59:02,784 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:59:02,785 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 22:59:02,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 22:59:03,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:59:24,048 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:59:24,048 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 22:59:24,048 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 22:59:24,048 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 22:59:24,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 22:59:24,682 INFO L256 TraceCheckSpWp]: Trace formula consists of 1675 conjuncts, 234 conjunts are in the unsatisfiable core [2019-10-06 22:59:24,691 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 22:59:24,762 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 22:59:24,762 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:00:26,301 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 23:00:26,302 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:00:26,305 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:00:26,306 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:00:26,306 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:00:26,306 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:00:26,307 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:00:26,323 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:00:45,045 INFO L199 IcfgInterpreter]: Interpreting procedure mapavg with input of size 1 for LOIs [2019-10-06 23:00:45,062 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:00:45,065 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:00:45,065 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:00:45,065 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100000)) (<= 100000 main_~i~1)) [2019-10-06 23:00:45,065 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 648#true [2019-10-06 23:00:45,066 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 704#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:00:45,066 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:00:45,066 INFO L193 IcfgInterpreter]: Reachable states at location mapavgEXIT satisfy 700#(and (= (ite (<= (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) 2147483647) (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (+ (mod (ite (and (< mapavg_~ret~0 0) (not (= 0 (mod mapavg_~ret~0 100000)))) (+ (div mapavg_~ret~0 100000) 1) (div mapavg_~ret~0 100000)) 4294967296) (- 4294967296))) |mapavg_#res|) (<= 100000 mapavg_~i~0) (<= 0 mapavg_~i~0) (not (< mapavg_~i~0 100000))) [2019-10-06 23:00:45,066 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 23:00:45,066 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 695#(<= 0 mapavg_~i~0) [2019-10-06 23:00:45,066 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:00:45,066 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:00:45,066 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 709#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:00:45,066 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 514#true [2019-10-06 23:00:45,067 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:00:45,067 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 563#(and (not (< main_~i~2 99999)) (<= 99999 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 399996)))) [2019-10-06 23:00:45,067 INFO L193 IcfgInterpreter]: Reachable states at location mapavgENTRY satisfy 657#true [2019-10-06 23:00:45,067 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_mapavg_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_2960 Int)) (or (and (not (<= (mod (+ (div v_prenex_2960 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (< v_prenex_2960 0)) (= (mod (div v_prenex_2960 100000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2960 100000) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_2960 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (= (mod v_prenex_2960 100000) 0)) (< v_prenex_2960 0) (= |main_#t~ret4| (+ (mod (+ (div v_prenex_2960 100000) 1) 4294967296) (- 4294967296))) (<= (mod (div v_prenex_2960 100000) 4294967296) 2147483647)) (and (not (< main_~i~1 100000)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 1) 4294967296) 2147483647)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 0)) (and (not (< main_~i~1 100000)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 4294967296) 2147483647)) (= (mod v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 0)) (and (= (mod (+ (div v_prenex_2960 100000) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100000)) (not (= (mod v_prenex_2960 100000) 0)) (< v_prenex_2960 0) (<= (mod (+ (div v_prenex_2960 100000) 1) 4294967296) 2147483647) (<= (mod (div v_prenex_2960 100000) 4294967296) 2147483647)) (and (not (<= (mod (+ (div v_prenex_2960 100000) 1) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= (mod v_prenex_2960 100000) 0) (= (mod (div v_prenex_2960 100000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2960 100000) 4294967296) 2147483647)) (and (not (< main_~i~1 100000)) (= (mod v_prenex_2960 100000) 0) (<= (mod (+ (div v_prenex_2960 100000) 1) 4294967296) 2147483647) (= (mod (div v_prenex_2960 100000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2960 100000) 4294967296) 2147483647)) (and (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 0)) (not (< main_~i~1 100000)) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 4294967296) 2147483647)) (= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 1) 4294967296) |main_#t~ret4|) (< v_mapavg_~ret~0_BEFORE_RETURN_236 0)) (and (not (< main_~i~1 100000)) (not (< v_prenex_2960 0)) (<= (mod (+ (div v_prenex_2960 100000) 1) 4294967296) 2147483647) (= (mod (div v_prenex_2960 100000) 4294967296) |main_#t~ret4|) (<= (mod (div v_prenex_2960 100000) 4294967296) 2147483647)) (and (not (= (mod v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 0)) (not (< main_~i~1 100000)) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 1) 4294967296) (- 4294967296))) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 1) 4294967296) 2147483647)) (< v_mapavg_~ret~0_BEFORE_RETURN_236 0)) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_236 0)) (not (< main_~i~1 100000)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 1) 4294967296) 2147483647) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 4294967296) 2147483647))) (and (not (< v_mapavg_~ret~0_BEFORE_RETURN_236 0)) (not (< main_~i~1 100000)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 4294967296) 2147483647)) (not (<= (mod (+ (div v_mapavg_~ret~0_BEFORE_RETURN_236 100000) 1) 4294967296) 2147483647))))) (exists ((v_mapavg_~ret~0_BEFORE_RETURN_235 Int) (v_prenex_2959 Int)) (or (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 100000) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 100000) 4294967296)) (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_235 0))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 100000) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_235 100000)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 100000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (mod (+ (div v_prenex_2959 100000) 1) 4294967296) |main_#t~ret4|) (not (< main_~i~1 100000)) (< v_prenex_2959 0) (<= (mod (+ (div v_prenex_2959 100000) 1) 4294967296) 2147483647) (not (= 0 (mod v_prenex_2959 100000)))) (and (= (+ (mod (+ (div v_prenex_2959 100000) 1) 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 100000)) (< v_prenex_2959 0) (not (= 0 (mod v_prenex_2959 100000))) (not (<= (mod (+ (div v_prenex_2959 100000) 1) 4294967296) 2147483647))) (and (not (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 100000) 4294967296) 2147483647)) (not (< main_~i~1 100000)) (not (< v_mapavg_~ret~0_BEFORE_RETURN_235 0)) (= (+ (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 100000) 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 100000) 4294967296) 2147483647) (= |main_#t~ret4| (mod (div v_mapavg_~ret~0_BEFORE_RETURN_235 100000) 4294967296)) (not (< main_~i~1 100000)) (= 0 (mod v_mapavg_~ret~0_BEFORE_RETURN_235 100000)))))) [2019-10-06 23:00:45,067 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 453#true [2019-10-06 23:00:45,067 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 327#(or (not (= main_~ret~1 main_~ret2~0)) (not (= main_~ret~1 main_~ret5~0))) [2019-10-06 23:00:45,067 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 607#true [2019-10-06 23:00:45,067 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 643#true [2019-10-06 23:00:48,945 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:00:48,946 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [235, 235, 235, 11] total 479 [2019-10-06 23:00:48,947 INFO L442 AbstractCegarLoop]: Interpolant automaton has 479 states [2019-10-06 23:00:48,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 479 interpolants. [2019-10-06 23:00:48,962 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=109771, Invalid=119190, Unknown=1, NotChecked=0, Total=228962 [2019-10-06 23:00:48,963 INFO L87 Difference]: Start difference. First operand 265 states and 269 transitions. Second operand 479 states.