java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/max10-1.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:23:56,082 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:23:56,084 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:23:56,103 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:23:56,103 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:23:56,105 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:23:56,107 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:23:56,121 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:23:56,122 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:23:56,124 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:23:56,125 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:23:56,127 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:23:56,127 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:23:56,131 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:23:56,134 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:23:56,136 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:23:56,137 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:23:56,141 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:23:56,142 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:23:56,148 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:23:56,153 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:23:56,156 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:23:56,159 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:23:56,160 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:23:56,164 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-10-07 15:23:56,164 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-10-07 15:23:56,165 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-10-07 15:23:56,167 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-10-07 15:23:56,168 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-10-07 15:23:56,169 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-10-07 15:23:56,169 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-07 15:23:56,172 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-07 15:23:56,173 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-07 15:23:56,174 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-07 15:23:56,175 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-07 15:23:56,176 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-07 15:23:56,176 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-07 15:23:56,177 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-07 15:23:56,177 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:23:56,178 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:23:56,179 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:23:56,180 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:23:56,199 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:23:56,199 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:23:56,201 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:23:56,201 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:23:56,201 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:23:56,201 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:23:56,202 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:23:56,202 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:23:56,202 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:23:56,202 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:23:56,203 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:23:56,204 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:23:56,204 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:23:56,204 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:23:56,205 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:23:56,205 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:23:56,205 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:23:56,205 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:23:56,205 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:23:56,206 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:23:56,206 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:23:56,206 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:23:56,206 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:23:56,206 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:23:56,207 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:23:56,207 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:23:56,207 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:23:56,207 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:23:56,207 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:23:56,495 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:23:56,508 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:23:56,512 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:23:56,513 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:23:56,513 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:23:56,514 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/max10-1.i [2019-10-07 15:23:56,577 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ad540b0b8/7c15e2be77a74763bcffb7b891a17be3/FLAGfa94e4873 [2019-10-07 15:23:57,079 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:23:57,081 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/max10-1.i [2019-10-07 15:23:57,088 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ad540b0b8/7c15e2be77a74763bcffb7b891a17be3/FLAGfa94e4873 [2019-10-07 15:23:57,459 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ad540b0b8/7c15e2be77a74763bcffb7b891a17be3 [2019-10-07 15:23:57,469 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:23:57,471 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:23:57,472 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:23:57,472 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:23:57,476 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:23:57,477 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:23:57" (1/1) ... [2019-10-07 15:23:57,480 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@76f51de0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:57, skipping insertion in model container [2019-10-07 15:23:57,480 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:23:57" (1/1) ... [2019-10-07 15:23:57,488 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:23:57,506 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:23:57,731 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:23:57,741 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:23:57,768 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:23:57,784 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:23:57,784 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:57 WrapperNode [2019-10-07 15:23:57,784 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:23:57,785 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:23:57,785 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:23:57,785 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:23:57,895 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:57" (1/1) ... [2019-10-07 15:23:57,896 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:57" (1/1) ... [2019-10-07 15:23:57,906 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:57" (1/1) ... [2019-10-07 15:23:57,908 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:57" (1/1) ... [2019-10-07 15:23:57,928 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:57" (1/1) ... [2019-10-07 15:23:57,933 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:57" (1/1) ... [2019-10-07 15:23:57,935 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:57" (1/1) ... [2019-10-07 15:23:57,937 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:23:57,938 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:23:57,938 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:23:57,938 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:23:57,939 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:57" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:23:58,001 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:23:58,001 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:23:58,002 INFO L138 BoogieDeclarations]: Found implementation of procedure max [2019-10-07 15:23:58,002 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:23:58,002 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:23:58,002 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:23:58,002 INFO L130 BoogieDeclarations]: Found specification of procedure max [2019-10-07 15:23:58,003 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:23:58,003 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:23:58,003 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:23:58,003 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:23:58,003 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:23:58,003 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:23:58,004 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:23:58,429 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:23:58,429 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:23:58,431 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:23:58 BoogieIcfgContainer [2019-10-07 15:23:58,431 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:23:58,432 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:23:58,432 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:23:58,435 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:23:58,436 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:23:57" (1/3) ... [2019-10-07 15:23:58,437 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@28ed3b57 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:23:58, skipping insertion in model container [2019-10-07 15:23:58,437 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:23:57" (2/3) ... [2019-10-07 15:23:58,437 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@28ed3b57 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:23:58, skipping insertion in model container [2019-10-07 15:23:58,438 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:23:58" (3/3) ... [2019-10-07 15:23:58,439 INFO L109 eAbstractionObserver]: Analyzing ICFG max10-1.i [2019-10-07 15:23:58,450 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:23:58,468 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:23:58,479 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:23:58,502 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:23:58,502 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:23:58,502 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:23:58,503 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:23:58,503 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:23:58,503 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:23:58,503 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:23:58,503 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:23:58,521 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:23:58,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:23:58,527 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:58,528 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:58,530 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:58,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:58,535 INFO L82 PathProgramCache]: Analyzing trace with hash 855740909, now seen corresponding path program 1 times [2019-10-07 15:23:58,542 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:58,542 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:58,542 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:58,542 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:58,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:58,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:58,724 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:23:58,725 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:58,726 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:23:58,726 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:23:58,730 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:58,742 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:58,743 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:58,745 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:23:58,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:58,785 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:23:58,786 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:58,787 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:23:58,787 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:58,795 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:23:58,795 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:23:58,799 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:58,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:23:58,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:23:58,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:23:58,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:23:58,841 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:23:58,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:58,842 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:23:58,842 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:58,842 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:23:58,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:23:58,844 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:58,845 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:58,845 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:58,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:58,846 INFO L82 PathProgramCache]: Analyzing trace with hash -1075349738, now seen corresponding path program 1 times [2019-10-07 15:23:58,846 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:58,846 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:58,847 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:58,847 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:58,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:58,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:58,920 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:58,921 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:58,921 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:23:58,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:58,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:58,995 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:23:59,003 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:23:59,039 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:59,039 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:23:59,096 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:23:59,096 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:23:59,097 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:23:59,098 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:59,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:59,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:23:59,099 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:23:59,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:59,112 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:23:59,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:59,113 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:23:59,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:59,114 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:23:59,114 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:23:59,115 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:23:59,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:23:59,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:23:59,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:23:59,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:23:59,122 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:23:59,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:59,123 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:23:59,123 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:59,123 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:23:59,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:23:59,124 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:59,124 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:59,329 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:59,329 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:59,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:59,330 INFO L82 PathProgramCache]: Analyzing trace with hash 447698074, now seen corresponding path program 1 times [2019-10-07 15:23:59,331 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:59,331 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:59,332 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:59,332 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:59,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:59,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:59,435 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:59,435 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:59,435 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:23:59,436 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:23:59,437 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:23:59,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:23:59,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:59,437 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:23:59,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:23:59,448 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:23:59,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:23:59,449 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:23:59,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:23:59,451 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:23:59,451 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:23:59,451 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:23:59,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:23:59,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:23:59,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:23:59,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:23:59,458 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:23:59,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:23:59,460 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:23:59,460 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:23:59,460 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:23:59,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:23:59,461 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:23:59,462 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:23:59,462 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:23:59,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:23:59,462 INFO L82 PathProgramCache]: Analyzing trace with hash -69054062, now seen corresponding path program 1 times [2019-10-07 15:23:59,463 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:23:59,463 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:59,463 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:59,463 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:23:59,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:23:59,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:59,585 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:59,586 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:23:59,586 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:23:59,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:23:59,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:23:59,680 INFO L256 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:23:59,683 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:23:59,695 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:59,695 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:23:59,732 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:23:59,732 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:23:59,780 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:23:59,780 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:23:59,786 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:23:59,794 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:23:59,794 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:23:59,935 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:01,914 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:01,975 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:01,980 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:01,980 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:01,981 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 640#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:01,981 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 636#(and (not (< max_~i~0 10)) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|) (<= 10 max_~i~0)) [2019-10-07 15:24:01,981 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 467#true [2019-10-07 15:24:01,981 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 510#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:24:01,982 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 631#(<= 0 max_~i~0) [2019-10-07 15:24:01,982 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:01,983 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:01,983 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 108#(or (exists ((v_max_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296)) (not (< main_~i~1 10))) (and (= (+ (mod v_prenex_1 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 10)) (not (<= (mod v_prenex_1 4294967296) 2147483647))))) (exists ((v_prenex_2 Int) (v_max_~ret~0_BEFORE_RETURN_2 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647) (not (< main_~i~1 10)) (= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) |main_#t~ret6|)) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 10)))))) [2019-10-07 15:24:01,983 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 368#true [2019-10-07 15:24:01,983 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 645#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:01,984 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:01,984 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 301#true [2019-10-07 15:24:01,984 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 589#true [2019-10-07 15:24:01,984 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 575#true [2019-10-07 15:24:01,984 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 548#true [2019-10-07 15:24:01,985 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 222#(or (and (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_max_~ret~0_BEFORE_RETURN_5 Int) (v_max_~ret~0_BEFORE_RETURN_6 Int)) (or (and (not (<= (mod v_prenex_29 4294967296) 2147483647)) (not (< main_~i~2 9)) (= main_~ret5~0 (+ (mod v_prenex_29 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (<= (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647)) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_max_~ret~0_BEFORE_RETURN_5 Int) (v_max_~ret~0_BEFORE_RETURN_6 Int)) (or (and (not (<= (mod v_prenex_29 4294967296) 2147483647)) (not (< main_~i~2 9)) (= main_~ret5~0 (+ (mod v_prenex_29 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (<= (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647)) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)))))) [2019-10-07 15:24:01,986 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:24:01,987 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 580#(exists ((v_prenex_2 Int) (v_max_~ret~0_BEFORE_RETURN_1 Int) (v_max_~ret~0_BEFORE_RETURN_2 Int) (v_prenex_1 Int)) (or (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) main_~ret~1) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (<= main_~ret~1 2147483647) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (not (< main_~i~1 10)) (not (<= (mod v_prenex_1 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:01,987 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:02,392 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:02,392 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:24:02,394 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-07 15:24:02,394 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-07 15:24:02,400 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-07 15:24:02,400 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-07 15:24:03,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:03,113 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:24:03,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-07 15:24:03,113 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-07 15:24:03,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:03,114 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:24:03,115 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:24:03,116 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 101 GetRequests, 73 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 192 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=139, Invalid=731, Unknown=0, NotChecked=0, Total=870 [2019-10-07 15:24:03,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:24:03,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:24:03,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:24:03,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:24:03,122 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:24:03,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:03,122 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:24:03,123 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-07 15:24:03,123 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:24:03,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:24:03,124 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:03,124 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:03,324 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:03,325 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:03,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:03,326 INFO L82 PathProgramCache]: Analyzing trace with hash -493974743, now seen corresponding path program 2 times [2019-10-07 15:24:03,326 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:03,327 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:03,327 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:03,327 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:03,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:03,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:03,445 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:03,445 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:03,445 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:03,446 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:03,522 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:24:03,524 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:03,529 INFO L256 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:24:03,533 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:03,568 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:03,568 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:03,599 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:03,599 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:03,603 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:03,603 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:03,604 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:03,604 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:03,604 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:03,637 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:05,184 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:05,231 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:05,248 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:05,248 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:05,248 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:05,249 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 10)) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|) (<= 10 max_~i~0)) [2019-10-07 15:24:05,249 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:05,249 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:24:05,249 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:05,250 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:05,255 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:05,256 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_196 Int) (v_max_~ret~0_BEFORE_RETURN_28 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296)) (not (< main_~i~1 10))) (and (not (<= (mod v_prenex_196 4294967296) 2147483647)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 10))))) (exists ((v_prenex_195 Int) (v_max_~ret~0_BEFORE_RETURN_27 Int)) (or (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 10))) (and (= (mod v_prenex_195 4294967296) |main_#t~ret6|) (<= (mod v_prenex_195 4294967296) 2147483647) (not (< main_~i~1 10)))))) [2019-10-07 15:24:05,256 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:05,256 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:05,256 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:05,257 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:05,257 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:05,257 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:05,258 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:05,260 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_prenex_224 Int) (v_max_~ret~0_BEFORE_RETURN_32 Int) (v_max_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (= main_~ret5~0 (mod v_prenex_224 4294967296))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_224 Int) (v_max_~ret~0_BEFORE_RETURN_32 Int) (v_max_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (= main_~ret5~0 (mod v_prenex_224 4294967296))))))) [2019-10-07 15:24:05,261 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:24:05,261 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_196 Int) (v_prenex_195 Int) (v_max_~ret~0_BEFORE_RETURN_28 Int) (v_max_~ret~0_BEFORE_RETURN_27 Int)) (or (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296)) (<= main_~ret~1 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_195 4294967296) main_~ret~1) (<= (mod v_prenex_195 4294967296) 2147483647) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:05,261 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:05,688 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:05,689 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:24:05,692 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-07 15:24:05,692 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-07 15:24:05,693 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-07 15:24:05,693 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-07 15:24:06,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:06,687 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:24:06,688 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:24:06,688 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-07 15:24:06,689 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:06,689 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:24:06,690 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:24:06,691 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-07 15:24:06,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:24:06,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:24:06,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:24:06,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:24:06,704 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:24:06,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:06,704 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:24:06,704 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-07 15:24:06,705 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:24:06,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:24:06,706 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:06,706 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:06,910 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:06,910 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:06,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:06,911 INFO L82 PathProgramCache]: Analyzing trace with hash 132820922, now seen corresponding path program 3 times [2019-10-07 15:24:06,912 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:06,912 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:06,912 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:06,912 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:06,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:06,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:07,038 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-10-07 15:24:07,039 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:07,039 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:07,039 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:07,159 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:24:07,160 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:07,161 INFO L256 TraceCheckSpWp]: Trace formula consists of 199 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:24:07,167 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:07,182 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-10-07 15:24:07,184 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:07,249 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 62 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-10-07 15:24:07,249 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:07,251 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:07,251 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:07,252 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:07,252 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:07,252 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:07,274 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:08,959 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:08,996 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:09,000 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:09,001 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:09,001 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:09,001 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 10)) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|) (<= 10 max_~i~0)) [2019-10-07 15:24:09,002 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:09,002 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:24:09,002 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:09,003 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:09,003 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:09,003 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_389 Int) (v_max_~ret~0_BEFORE_RETURN_53 Int)) (or (and (<= (mod v_prenex_389 4294967296) 2147483647) (= |main_#t~ret6| (mod v_prenex_389 4294967296)) (not (< main_~i~1 10))) (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 10)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647))))) (exists ((v_max_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (not (< main_~i~1 10))) (and (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296)) (not (< main_~i~1 10)) (<= (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647))))) [2019-10-07 15:24:09,004 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:09,004 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:09,004 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:09,005 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:09,005 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:09,005 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:09,006 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:09,006 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_max_~ret~0_BEFORE_RETURN_58 Int)) (or (and (= main_~ret5~0 (mod v_prenex_418 4294967296)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (<= (mod v_prenex_418 4294967296) 2147483647)) (and (not (< main_~i~2 9)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_prenex_417 4294967296) (- 4294967296))) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (not (<= (mod v_prenex_417 4294967296) 2147483647))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647) (not (< main_~i~2 9)) (= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0))))) (and (exists ((v_max_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_max_~ret~0_BEFORE_RETURN_58 Int)) (or (and (= main_~ret5~0 (mod v_prenex_418 4294967296)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (<= (mod v_prenex_418 4294967296) 2147483647)) (and (not (< main_~i~2 9)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_prenex_417 4294967296) (- 4294967296))) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (not (<= (mod v_prenex_417 4294967296) 2147483647))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647) (not (< main_~i~2 9)) (= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:24:09,006 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:24:09,007 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_389 Int) (v_max_~ret~0_BEFORE_RETURN_54 Int) (v_max_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_390 Int)) (or (and (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (mod v_prenex_389 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296)) (<= (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296))) (not (< main_~i~1 10)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:09,007 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:09,537 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:09,537 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 23 [2019-10-07 15:24:09,540 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-10-07 15:24:09,540 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-10-07 15:24:09,541 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=108, Invalid=444, Unknown=0, NotChecked=0, Total=552 [2019-10-07 15:24:09,542 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 24 states. [2019-10-07 15:24:10,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:10,674 INFO L93 Difference]: Finished difference Result 52 states and 67 transitions. [2019-10-07 15:24:10,674 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-10-07 15:24:10,675 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 42 [2019-10-07 15:24:10,675 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:10,676 INFO L225 Difference]: With dead ends: 52 [2019-10-07 15:24:10,676 INFO L226 Difference]: Without dead ends: 35 [2019-10-07 15:24:10,677 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 110 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 428 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=353, Invalid=1369, Unknown=0, NotChecked=0, Total=1722 [2019-10-07 15:24:10,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2019-10-07 15:24:10,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 35. [2019-10-07 15:24:10,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35 states. [2019-10-07 15:24:10,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 39 transitions. [2019-10-07 15:24:10,685 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 39 transitions. Word has length 42 [2019-10-07 15:24:10,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:10,685 INFO L462 AbstractCegarLoop]: Abstraction has 35 states and 39 transitions. [2019-10-07 15:24:10,685 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-10-07 15:24:10,685 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 39 transitions. [2019-10-07 15:24:10,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-10-07 15:24:10,687 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:10,687 INFO L385 BasicCegarLoop]: trace histogram [30, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:10,896 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:10,897 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:10,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:10,898 INFO L82 PathProgramCache]: Analyzing trace with hash 238611642, now seen corresponding path program 4 times [2019-10-07 15:24:10,898 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:10,898 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:10,899 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:10,899 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:10,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:10,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:11,032 INFO L134 CoverageAnalysis]: Checked inductivity of 550 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2019-10-07 15:24:11,033 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:11,033 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:11,033 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:11,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:11,178 INFO L256 TraceCheckSpWp]: Trace formula consists of 271 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:24:11,182 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:11,227 INFO L134 CoverageAnalysis]: Checked inductivity of 550 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 535 trivial. 0 not checked. [2019-10-07 15:24:11,227 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:11,305 INFO L134 CoverageAnalysis]: Checked inductivity of 550 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 535 trivial. 0 not checked. [2019-10-07 15:24:11,305 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:11,307 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:11,307 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:11,308 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:11,308 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:11,308 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:11,361 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:12,680 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:12,702 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:12,731 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:12,731 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:12,732 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 640#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:12,732 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 636#(and (not (< max_~i~0 10)) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|) (<= 10 max_~i~0)) [2019-10-07 15:24:12,732 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:12,732 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:24:12,733 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 631#(<= 0 max_~i~0) [2019-10-07 15:24:12,733 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:12,733 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:12,733 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_max_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_583 Int)) (or (and (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_583 4294967296) 2147483647)) (not (< main_~i~1 10))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) |main_#t~ret6|) (not (< main_~i~1 10))))) (exists ((v_prenex_584 Int) (v_max_~ret~0_BEFORE_RETURN_80 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) |main_#t~ret6|) (not (< main_~i~1 10))) (and (= (+ (mod v_prenex_584 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_584 4294967296) 2147483647)) (not (< main_~i~1 10)))))) [2019-10-07 15:24:12,734 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 645#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:12,734 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:12,734 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:12,734 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:12,734 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:12,734 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:12,735 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_max_~ret~0_BEFORE_RETURN_84 Int) (v_max_~ret~0_BEFORE_RETURN_83 Int)) (or (and (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296))) (and (<= (mod v_prenex_611 4294967296) 2147483647) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (not (<= (mod v_prenex_612 4294967296) 2147483647))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0))))) (and (not (= main_~ret~1 main_~ret5~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_max_~ret~0_BEFORE_RETURN_84 Int) (v_max_~ret~0_BEFORE_RETURN_83 Int)) (or (and (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296))) (and (<= (mod v_prenex_611 4294967296) 2147483647) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (not (<= (mod v_prenex_612 4294967296) 2147483647))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)))))) [2019-10-07 15:24:12,735 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:12,735 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:24:12,736 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_max_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_583 Int) (v_prenex_584 Int) (v_max_~ret~0_BEFORE_RETURN_80 Int)) (or (and (<= main_~ret~1 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) main_~ret~1) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_584 4294967296) 2147483647)) (not (< main_~i~1 10)) (= main_~ret~1 (+ (mod v_prenex_584 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_583 4294967296) 2147483647)) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:12,736 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:13,099 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:13,099 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 8, 8, 11] total 24 [2019-10-07 15:24:13,100 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-10-07 15:24:13,101 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-10-07 15:24:13,101 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=500, Unknown=0, NotChecked=0, Total=600 [2019-10-07 15:24:13,102 INFO L87 Difference]: Start difference. First operand 35 states and 39 transitions. Second operand 25 states. [2019-10-07 15:24:14,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:14,172 INFO L93 Difference]: Finished difference Result 65 states and 78 transitions. [2019-10-07 15:24:14,172 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-07 15:24:14,172 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 60 [2019-10-07 15:24:14,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:14,173 INFO L225 Difference]: With dead ends: 65 [2019-10-07 15:24:14,173 INFO L226 Difference]: Without dead ends: 41 [2019-10-07 15:24:14,175 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 204 GetRequests, 159 SyntacticMatches, 2 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 457 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=298, Invalid=1682, Unknown=0, NotChecked=0, Total=1980 [2019-10-07 15:24:14,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2019-10-07 15:24:14,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 41. [2019-10-07 15:24:14,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2019-10-07 15:24:14,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 45 transitions. [2019-10-07 15:24:14,183 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 45 transitions. Word has length 60 [2019-10-07 15:24:14,184 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:14,184 INFO L462 AbstractCegarLoop]: Abstraction has 41 states and 45 transitions. [2019-10-07 15:24:14,184 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-10-07 15:24:14,184 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 45 transitions. [2019-10-07 15:24:14,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-10-07 15:24:14,185 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:14,185 INFO L385 BasicCegarLoop]: trace histogram [30, 10, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:14,389 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:14,390 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:14,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:14,390 INFO L82 PathProgramCache]: Analyzing trace with hash -24325491, now seen corresponding path program 5 times [2019-10-07 15:24:14,391 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:14,391 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:14,391 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:14,391 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:14,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:14,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:14,603 INFO L134 CoverageAnalysis]: Checked inductivity of 592 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-10-07 15:24:14,604 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:14,604 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:14,604 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:14,776 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:24:14,777 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:14,778 INFO L256 TraceCheckSpWp]: Trace formula consists of 147 conjuncts, 4 conjunts are in the unsatisfiable core [2019-10-07 15:24:14,781 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:14,796 INFO L134 CoverageAnalysis]: Checked inductivity of 592 backedges. 246 proven. 3 refuted. 0 times theorem prover too weak. 343 trivial. 0 not checked. [2019-10-07 15:24:14,796 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:14,832 INFO L134 CoverageAnalysis]: Checked inductivity of 592 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-10-07 15:24:14,833 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:14,835 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:14,835 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:14,836 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:14,836 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:14,836 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:14,854 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:16,263 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:16,280 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:16,283 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:16,283 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:16,283 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 624#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:16,283 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 620#(and (not (< max_~i~0 10)) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|) (<= 10 max_~i~0)) [2019-10-07 15:24:16,284 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 467#true [2019-10-07 15:24:16,284 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 510#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:24:16,284 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 615#(<= 0 max_~i~0) [2019-10-07 15:24:16,284 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:16,284 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:24:16,285 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 108#(or (exists ((v_prenex_777 Int) (v_max_~ret~0_BEFORE_RETURN_105 Int)) (or (and (not (<= (mod v_prenex_777 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_prenex_777 4294967296) (- 4294967296))) (not (< main_~i~1 10))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) |main_#t~ret6|) (not (< main_~i~1 10))))) (exists ((v_max_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (= |main_#t~ret6| (mod v_prenex_778 4294967296)) (not (< main_~i~1 10)) (<= (mod v_prenex_778 4294967296) 2147483647)) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296))) (not (< main_~i~1 10)))))) [2019-10-07 15:24:16,285 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 629#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:16,285 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 368#true [2019-10-07 15:24:16,285 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:16,285 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 301#true [2019-10-07 15:24:16,285 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 589#true [2019-10-07 15:24:16,286 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 575#true [2019-10-07 15:24:16,286 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 222#(or (and (exists ((v_max_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_max_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= main_~ret5~0 (mod v_prenex_806 4294967296)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (not (< main_~i~2 9)) (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) main_~ret5~0) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_max_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= main_~ret5~0 (mod v_prenex_806 4294967296)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (not (< main_~i~2 9)) (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) main_~ret5~0) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)))))) [2019-10-07 15:24:16,286 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 548#true [2019-10-07 15:24:16,286 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:24:16,287 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 580#(exists ((v_prenex_777 Int) (v_max_~ret~0_BEFORE_RETURN_105 Int) (v_max_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_prenex_777 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_777 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) main_~ret~1) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:16,287 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:16,800 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:16,801 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 11] total 19 [2019-10-07 15:24:16,802 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-10-07 15:24:16,802 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-10-07 15:24:16,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2019-10-07 15:24:16,803 INFO L87 Difference]: Start difference. First operand 41 states and 45 transitions. Second operand 20 states. [2019-10-07 15:24:17,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:17,554 INFO L93 Difference]: Finished difference Result 63 states and 71 transitions. [2019-10-07 15:24:17,554 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-10-07 15:24:17,555 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 66 [2019-10-07 15:24:17,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:17,556 INFO L225 Difference]: With dead ends: 63 [2019-10-07 15:24:17,556 INFO L226 Difference]: Without dead ends: 45 [2019-10-07 15:24:17,557 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 185 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=186, Invalid=936, Unknown=0, NotChecked=0, Total=1122 [2019-10-07 15:24:17,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2019-10-07 15:24:17,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2019-10-07 15:24:17,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2019-10-07 15:24:17,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 49 transitions. [2019-10-07 15:24:17,565 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 49 transitions. Word has length 66 [2019-10-07 15:24:17,565 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:17,565 INFO L462 AbstractCegarLoop]: Abstraction has 45 states and 49 transitions. [2019-10-07 15:24:17,565 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-10-07 15:24:17,565 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 49 transitions. [2019-10-07 15:24:17,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-10-07 15:24:17,567 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:17,567 INFO L385 BasicCegarLoop]: trace histogram [30, 10, 6, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:17,770 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:17,771 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:17,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:17,772 INFO L82 PathProgramCache]: Analyzing trace with hash -1814718451, now seen corresponding path program 6 times [2019-10-07 15:24:17,772 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:17,772 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:17,773 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:17,773 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:17,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:17,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:17,983 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-10-07 15:24:17,983 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:17,984 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:17,984 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:18,202 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:24:18,202 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:18,204 INFO L256 TraceCheckSpWp]: Trace formula consists of 321 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-07 15:24:18,210 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:18,225 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 246 proven. 21 refuted. 0 times theorem prover too weak. 343 trivial. 0 not checked. [2019-10-07 15:24:18,225 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:18,319 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-10-07 15:24:18,320 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:18,321 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:18,322 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:18,322 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:18,322 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:18,323 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:18,337 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:19,564 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:19,585 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:19,588 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:19,588 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:19,588 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:19,589 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 10)) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|) (<= 10 max_~i~0)) [2019-10-07 15:24:19,589 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:19,589 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 9)) (<= 9 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) [2019-10-07 15:24:19,589 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:19,589 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:19,589 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:19,590 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_972 Int) (v_max_~ret~0_BEFORE_RETURN_132 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296)) (not (< main_~i~1 10))) (and (not (<= (mod v_prenex_972 4294967296) 2147483647)) (= (+ (mod v_prenex_972 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 10))))) (exists ((v_prenex_971 Int) (v_max_~ret~0_BEFORE_RETURN_131 Int)) (or (and (<= (mod v_prenex_971 4294967296) 2147483647) (= (mod v_prenex_971 4294967296) |main_#t~ret6|) (not (< main_~i~1 10))) (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 10)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647)))))) [2019-10-07 15:24:19,590 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:19,590 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:19,590 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:19,590 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:19,590 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:19,591 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:19,591 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_prenex_1000 Int) (v_max_~ret~0_BEFORE_RETURN_135 Int) (v_prenex_999 Int) (v_max_~ret~0_BEFORE_RETURN_136 Int)) (or (and (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (not (<= (mod v_prenex_1000 4294967296) 2147483647))) (and (= (mod v_prenex_999 4294967296) main_~ret5~0) (not (< main_~i~2 9)) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1000 Int) (v_max_~ret~0_BEFORE_RETURN_135 Int) (v_prenex_999 Int) (v_max_~ret~0_BEFORE_RETURN_136 Int)) (or (and (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0) (not (<= (mod v_prenex_1000 4294967296) 2147483647))) (and (= (mod v_prenex_999 4294967296) main_~ret5~0) (not (< main_~i~2 9)) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296)) (not (< main_~i~2 9)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 36)) main_~temp~0)))))) [2019-10-07 15:24:19,591 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:19,591 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 10 main_~i~1) (not (< main_~i~1 10))) [2019-10-07 15:24:19,591 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_max_~ret~0_BEFORE_RETURN_131 Int) (v_max_~ret~0_BEFORE_RETURN_132 Int)) (or (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296)) (<= main_~ret~1 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_prenex_971 4294967296) 2147483647) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (< main_~i~1 10)) (= main_~ret~1 (mod v_prenex_971 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647)) (not (< main_~i~1 10)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:19,592 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:19,972 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:19,972 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 11] total 22 [2019-10-07 15:24:19,974 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-10-07 15:24:19,974 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-10-07 15:24:19,974 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=411, Unknown=0, NotChecked=0, Total=506 [2019-10-07 15:24:19,975 INFO L87 Difference]: Start difference. First operand 45 states and 49 transitions. Second operand 23 states. [2019-10-07 15:24:22,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:22,828 INFO L93 Difference]: Finished difference Result 66 states and 73 transitions. [2019-10-07 15:24:22,828 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:24:22,829 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 70 [2019-10-07 15:24:22,829 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:22,830 INFO L225 Difference]: With dead ends: 66 [2019-10-07 15:24:22,830 INFO L226 Difference]: Without dead ends: 48 [2019-10-07 15:24:22,832 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 236 GetRequests, 193 SyntacticMatches, 5 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 361 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=276, Invalid=1284, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:24:22,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2019-10-07 15:24:22,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2019-10-07 15:24:22,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2019-10-07 15:24:22,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 52 transitions. [2019-10-07 15:24:22,841 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 52 transitions. Word has length 70 [2019-10-07 15:24:22,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:22,842 INFO L462 AbstractCegarLoop]: Abstraction has 48 states and 52 transitions. [2019-10-07 15:24:22,842 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-10-07 15:24:22,842 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 52 transitions. [2019-10-07 15:24:22,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-10-07 15:24:22,844 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:22,844 INFO L385 BasicCegarLoop]: trace histogram [30, 10, 9, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:23,057 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:23,058 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:23,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:23,058 INFO L82 PathProgramCache]: Analyzing trace with hash -1614484445, now seen corresponding path program 7 times [2019-10-07 15:24:23,058 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:23,058 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:23,059 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:23,059 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:23,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:44,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat