java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/max20-1.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:24:08,118 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:24:08,121 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:24:08,134 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:24:08,134 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:24:08,135 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:24:08,137 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:24:08,138 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:24:08,140 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:24:08,141 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:24:08,142 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:24:08,143 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:24:08,143 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:24:08,144 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:24:08,145 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:24:08,146 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:24:08,147 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:24:08,148 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:24:08,150 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:24:08,152 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:24:08,153 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:24:08,154 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:24:08,156 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:24:08,156 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:24:08,159 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 15:24:08,166 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:24:08,167 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:24:08,168 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:24:08,168 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:24:08,184 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:24:08,185 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:24:08,186 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:24:08,186 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:24:08,186 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:24:08,187 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:24:08,187 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:24:08,187 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:24:08,187 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:24:08,187 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:24:08,187 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:24:08,188 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:24:08,188 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:24:08,188 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:24:08,188 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:24:08,188 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:24:08,189 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:24:08,189 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:24:08,189 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:24:08,189 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:24:08,189 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:24:08,190 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:24:08,190 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:24:08,190 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:24:08,190 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:24:08,190 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:24:08,191 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:24:08,191 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:24:08,191 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:24:08,474 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:24:08,487 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:24:08,490 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:24:08,491 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:24:08,492 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:24:08,493 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/max20-1.i [2019-10-07 15:24:08,555 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/253ba1369/eb0005b7e5894258a1f6f757d58d38eb/FLAGd2dd18422 [2019-10-07 15:24:08,994 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:24:08,997 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/max20-1.i [2019-10-07 15:24:09,004 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/253ba1369/eb0005b7e5894258a1f6f757d58d38eb/FLAGd2dd18422 [2019-10-07 15:24:09,380 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/253ba1369/eb0005b7e5894258a1f6f757d58d38eb [2019-10-07 15:24:09,390 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:24:09,392 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:24:09,393 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:24:09,393 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:24:09,397 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:24:09,398 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:24:09" (1/1) ... [2019-10-07 15:24:09,401 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3e7f8ae9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:09, skipping insertion in model container [2019-10-07 15:24:09,401 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:24:09" (1/1) ... [2019-10-07 15:24:09,409 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:24:09,427 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:24:09,652 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:24:09,660 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:24:09,680 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:24:09,693 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:24:09,694 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:09 WrapperNode [2019-10-07 15:24:09,694 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:24:09,694 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:24:09,695 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:24:09,695 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:24:09,785 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:09" (1/1) ... [2019-10-07 15:24:09,785 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:09" (1/1) ... [2019-10-07 15:24:09,795 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:09" (1/1) ... [2019-10-07 15:24:09,797 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:09" (1/1) ... [2019-10-07 15:24:09,812 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:09" (1/1) ... [2019-10-07 15:24:09,818 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:09" (1/1) ... [2019-10-07 15:24:09,820 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:09" (1/1) ... [2019-10-07 15:24:09,822 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:24:09,823 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:24:09,823 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:24:09,823 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:24:09,824 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:09" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:24:09,891 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:24:09,891 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:24:09,891 INFO L138 BoogieDeclarations]: Found implementation of procedure max [2019-10-07 15:24:09,892 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:24:09,892 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:24:09,892 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:24:09,893 INFO L130 BoogieDeclarations]: Found specification of procedure max [2019-10-07 15:24:09,893 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:24:09,893 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:24:09,893 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:24:09,893 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:24:09,894 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:24:09,894 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:24:09,894 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:24:10,306 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:24:10,306 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:24:10,308 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:24:10 BoogieIcfgContainer [2019-10-07 15:24:10,308 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:24:10,309 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:24:10,309 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:24:10,312 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:24:10,313 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:24:09" (1/3) ... [2019-10-07 15:24:10,313 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@35dd0dd8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:24:10, skipping insertion in model container [2019-10-07 15:24:10,314 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:09" (2/3) ... [2019-10-07 15:24:10,314 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@35dd0dd8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:24:10, skipping insertion in model container [2019-10-07 15:24:10,314 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:24:10" (3/3) ... [2019-10-07 15:24:10,316 INFO L109 eAbstractionObserver]: Analyzing ICFG max20-1.i [2019-10-07 15:24:10,325 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:24:10,333 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:24:10,345 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:24:10,370 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:24:10,370 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:24:10,370 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:24:10,370 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:24:10,370 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:24:10,371 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:24:10,371 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:24:10,371 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:24:10,386 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:24:10,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:24:10,392 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:10,393 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:10,395 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:10,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:10,399 INFO L82 PathProgramCache]: Analyzing trace with hash 855740909, now seen corresponding path program 1 times [2019-10-07 15:24:10,406 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:10,406 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:10,407 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:10,407 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:10,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:10,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:10,571 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:24:10,571 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:10,572 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:24:10,572 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:24:10,577 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:24:10,591 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:24:10,592 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:24:10,595 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:24:10,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:10,635 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:24:10,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:24:10,638 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:24:10,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:10,651 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:24:10,651 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:24:10,655 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:24:10,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:24:10,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:24:10,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:24:10,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:24:10,709 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:24:10,710 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:10,710 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:24:10,710 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:24:10,710 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:24:10,712 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:24:10,713 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:10,713 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:10,714 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:10,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:10,715 INFO L82 PathProgramCache]: Analyzing trace with hash -1075349738, now seen corresponding path program 1 times [2019-10-07 15:24:10,715 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:10,715 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:10,716 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:10,716 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:10,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:10,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:10,826 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:24:10,826 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:10,827 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:10,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:10,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:10,934 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:24:10,945 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:10,983 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:24:10,984 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:11,029 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:24:11,030 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:24:11,031 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:24:11,033 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:24:11,033 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:24:11,033 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:24:11,034 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:24:11,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:11,050 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:24:11,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:24:11,051 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:24:11,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:11,052 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:24:11,052 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:24:11,054 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:24:11,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:24:11,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:24:11,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:24:11,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:24:11,069 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:24:11,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:11,070 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:24:11,070 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:24:11,071 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:24:11,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:24:11,074 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:11,074 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:11,278 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:11,278 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:11,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:11,280 INFO L82 PathProgramCache]: Analyzing trace with hash 447698074, now seen corresponding path program 1 times [2019-10-07 15:24:11,280 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:11,281 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:11,281 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:11,281 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:11,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:11,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:11,360 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:11,360 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:11,361 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:24:11,361 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:24:11,361 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:24:11,362 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:24:11,362 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:24:11,363 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:24:11,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:11,379 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:24:11,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:24:11,381 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:24:11,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:11,382 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:24:11,382 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:24:11,383 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:24:11,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:24:11,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:24:11,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:24:11,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:24:11,389 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:24:11,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:11,391 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:24:11,391 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:24:11,392 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:24:11,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:24:11,393 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:11,393 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:11,393 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:11,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:11,394 INFO L82 PathProgramCache]: Analyzing trace with hash -69054062, now seen corresponding path program 1 times [2019-10-07 15:24:11,394 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:11,394 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:11,394 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:11,395 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:11,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:11,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:11,471 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:11,471 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:11,471 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:11,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:11,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:11,540 INFO L256 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:24:11,542 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:11,569 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:11,569 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:11,602 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:11,602 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:11,627 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:11,628 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:11,634 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:11,642 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:11,643 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:11,804 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:13,720 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:13,777 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:13,783 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:13,783 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:13,784 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:13,784 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 20)) (<= 20 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:13,784 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:13,784 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:24:13,785 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:13,785 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:13,785 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:13,786 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_max_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (not (< main_~i~1 20)) (= (+ (mod v_prenex_1 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 20)) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296))))) (exists ((v_prenex_2 Int) (v_max_~ret~0_BEFORE_RETURN_2 Int)) (or (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 20))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647) (not (< main_~i~1 20)) (= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) |main_#t~ret6|))))) [2019-10-07 15:24:13,786 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:13,786 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:13,787 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:13,787 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:13,787 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:13,788 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:13,788 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:13,788 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:24:13,791 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_2 Int) (v_max_~ret~0_BEFORE_RETURN_1 Int) (v_max_~ret~0_BEFORE_RETURN_2 Int) (v_prenex_1 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:13,791 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_max_~ret~0_BEFORE_RETURN_5 Int) (v_max_~ret~0_BEFORE_RETURN_6 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) main_~ret5~0) (not (< main_~i~2 19))) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647)) (and (not (<= (mod v_prenex_29 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_prenex_29 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)))))) (and (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_max_~ret~0_BEFORE_RETURN_5 Int) (v_max_~ret~0_BEFORE_RETURN_6 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) main_~ret5~0) (not (< main_~i~2 19))) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647)) (and (not (<= (mod v_prenex_29 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_prenex_29 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:24:13,792 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:14,230 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:14,231 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:24:14,233 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-07 15:24:14,234 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-07 15:24:14,235 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-07 15:24:14,235 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-07 15:24:16,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:16,079 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:24:16,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-07 15:24:16,079 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-07 15:24:16,080 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:16,080 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:24:16,080 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:24:16,081 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=133, Invalid=737, Unknown=0, NotChecked=0, Total=870 [2019-10-07 15:24:16,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:24:16,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:24:16,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:24:16,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:24:16,088 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:24:16,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:16,088 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:24:16,089 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-07 15:24:16,089 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:24:16,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:24:16,090 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:16,090 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:16,294 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:16,295 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:16,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:16,295 INFO L82 PathProgramCache]: Analyzing trace with hash -493974743, now seen corresponding path program 2 times [2019-10-07 15:24:16,296 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:16,296 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:16,297 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:16,297 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:16,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:16,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:16,427 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:16,427 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:16,428 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:16,428 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:16,513 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:24:16,513 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:16,517 INFO L256 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:24:16,521 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:16,547 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:16,547 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:16,582 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:16,583 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:16,587 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:16,588 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:16,589 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:16,589 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:16,589 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:16,622 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:18,040 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:18,069 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:18,073 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:18,073 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:18,073 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:18,073 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 20)) (<= 20 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:18,074 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:18,080 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:24:18,081 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:18,081 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:18,081 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:18,081 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_195 Int) (v_max_~ret~0_BEFORE_RETURN_27 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (not (< main_~i~1 20)) (= (mod v_prenex_195 4294967296) |main_#t~ret6|) (<= (mod v_prenex_195 4294967296) 2147483647)))) (exists ((v_prenex_196 Int) (v_max_~ret~0_BEFORE_RETURN_28 Int)) (or (and (not (< main_~i~1 20)) (<= (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296))) (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret6|))))) [2019-10-07 15:24:18,081 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:18,082 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:18,082 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:18,082 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:18,082 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:18,082 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:18,083 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:18,083 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:24:18,085 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_196 Int) (v_prenex_195 Int) (v_max_~ret~0_BEFORE_RETURN_28 Int) (v_max_~ret~0_BEFORE_RETURN_27 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 20)) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296)) (<= main_~ret~1 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_195 4294967296) main_~ret~1) (<= (mod v_prenex_195 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:18,085 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_prenex_224 Int) (v_max_~ret~0_BEFORE_RETURN_32 Int) (v_max_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_prenex_224 4294967296))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_224 Int) (v_max_~ret~0_BEFORE_RETURN_32 Int) (v_max_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_prenex_224 4294967296))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))))) [2019-10-07 15:24:18,086 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:18,446 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:18,446 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:24:18,448 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-07 15:24:18,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-07 15:24:18,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-07 15:24:18,449 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-07 15:24:19,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:19,399 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:24:19,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:24:19,399 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-07 15:24:19,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:19,400 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:24:19,400 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:24:19,401 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-07 15:24:19,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:24:19,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:24:19,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:24:19,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:24:19,407 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:24:19,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:19,408 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:24:19,408 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-07 15:24:19,408 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:24:19,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:24:19,409 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:19,409 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:19,612 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:19,613 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:19,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:19,614 INFO L82 PathProgramCache]: Analyzing trace with hash 132820922, now seen corresponding path program 3 times [2019-10-07 15:24:19,614 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:19,614 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:19,614 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:19,615 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:19,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:19,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:19,723 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-10-07 15:24:19,724 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:19,724 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:19,724 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:19,834 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:24:19,834 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:19,836 INFO L256 TraceCheckSpWp]: Trace formula consists of 199 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:24:19,839 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:19,897 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:19,897 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:19,993 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:19,994 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:19,995 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:19,995 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:19,996 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:19,996 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:19,996 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:20,015 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:21,583 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:21,610 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:21,613 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:21,613 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:21,613 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:21,613 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 20)) (<= 20 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:21,614 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:21,614 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:24:21,614 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:21,614 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:21,614 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:21,614 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_389 Int) (v_max_~ret~0_BEFORE_RETURN_53 Int)) (or (and (not (< main_~i~1 20)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (<= (mod v_prenex_389 4294967296) 2147483647) (= |main_#t~ret6| (mod v_prenex_389 4294967296))))) (exists ((v_max_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 20)) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_390 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296)) (<= (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647))))) [2019-10-07 15:24:21,615 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:21,615 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:21,615 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:21,615 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:21,615 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:21,616 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:21,616 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:21,616 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:24:21,616 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(or (exists ((v_prenex_389 Int) (v_max_~ret~0_BEFORE_RETURN_54 Int) (v_max_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (mod v_prenex_389 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296)) (<= (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_prenex_389 Int) (v_max_~ret~0_BEFORE_RETURN_54 Int) (v_max_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (mod v_prenex_389 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296)) (<= (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:24:21,617 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_max_~ret~0_BEFORE_RETURN_58 Int)) (or (and (= main_~ret5~0 (+ (mod v_prenex_417 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_417 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (mod v_prenex_418 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_prenex_418 4294967296) 2147483647))))) (and (exists ((v_max_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_max_~ret~0_BEFORE_RETURN_58 Int)) (or (and (= main_~ret5~0 (+ (mod v_prenex_417 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_417 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (mod v_prenex_418 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_prenex_418 4294967296) 2147483647)))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:24:21,617 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:22,065 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:22,066 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8, 8, 11] total 29 [2019-10-07 15:24:22,067 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2019-10-07 15:24:22,067 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2019-10-07 15:24:22,068 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=729, Unknown=0, NotChecked=0, Total=870 [2019-10-07 15:24:22,068 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 30 states. [2019-10-07 15:24:23,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:23,288 INFO L93 Difference]: Finished difference Result 55 states and 73 transitions. [2019-10-07 15:24:23,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-10-07 15:24:23,288 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 42 [2019-10-07 15:24:23,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:23,289 INFO L225 Difference]: With dead ends: 55 [2019-10-07 15:24:23,290 INFO L226 Difference]: Without dead ends: 37 [2019-10-07 15:24:23,291 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 104 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 727 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=445, Invalid=2525, Unknown=0, NotChecked=0, Total=2970 [2019-10-07 15:24:23,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2019-10-07 15:24:23,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 37. [2019-10-07 15:24:23,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2019-10-07 15:24:23,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 41 transitions. [2019-10-07 15:24:23,299 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 41 transitions. Word has length 42 [2019-10-07 15:24:23,299 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:23,299 INFO L462 AbstractCegarLoop]: Abstraction has 37 states and 41 transitions. [2019-10-07 15:24:23,300 INFO L463 AbstractCegarLoop]: Interpolant automaton has 30 states. [2019-10-07 15:24:23,300 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 41 transitions. [2019-10-07 15:24:23,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-10-07 15:24:23,301 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:23,302 INFO L385 BasicCegarLoop]: trace histogram [15, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:23,506 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:23,507 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:23,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:23,507 INFO L82 PathProgramCache]: Analyzing trace with hash -431924951, now seen corresponding path program 4 times [2019-10-07 15:24:23,508 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:23,508 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:23,508 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:23,508 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:23,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:23,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:23,613 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 37 proven. 52 refuted. 0 times theorem prover too weak. 149 trivial. 0 not checked. [2019-10-07 15:24:23,613 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:23,613 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:23,613 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:23,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:23,799 INFO L256 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:24:23,807 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:23,992 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2019-10-07 15:24:23,992 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:24,227 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2019-10-07 15:24:24,227 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:24,229 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:24,229 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:24,230 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:24,230 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:24,230 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:24,247 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:25,517 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:25,549 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:25,551 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:25,552 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:25,552 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:25,552 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 20)) (<= 20 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:25,552 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:25,552 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:24:25,552 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:25,552 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:25,552 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:25,553 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_max_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_583 Int)) (or (and (not (< main_~i~1 20)) (<= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) |main_#t~ret6|)) (and (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 20)) (not (<= (mod v_prenex_583 4294967296) 2147483647))))) (exists ((v_prenex_584 Int) (v_max_~ret~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 20)) (<= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) |main_#t~ret6|)) (and (not (< main_~i~1 20)) (= (+ (mod v_prenex_584 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_584 4294967296) 2147483647)))))) [2019-10-07 15:24:25,553 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:25,553 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:25,553 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:25,553 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:25,553 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:25,553 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:25,553 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:25,554 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:24:25,554 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_max_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_583 Int) (v_prenex_584 Int) (v_max_~ret~0_BEFORE_RETURN_80 Int)) (or (and (= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) main_~ret~1) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_584 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_prenex_584 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_583 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:25,554 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_max_~ret~0_BEFORE_RETURN_84 Int) (v_max_~ret~0_BEFORE_RETURN_83 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296))) (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (not (<= (mod v_prenex_612 4294967296) 2147483647))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_611 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_prenex_611 4294967296))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_max_~ret~0_BEFORE_RETURN_84 Int) (v_max_~ret~0_BEFORE_RETURN_83 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296))) (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (not (<= (mod v_prenex_612 4294967296) 2147483647))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_611 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_prenex_611 4294967296))))))) [2019-10-07 15:24:25,554 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:26,000 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:26,000 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 15, 15, 11] total 38 [2019-10-07 15:24:26,001 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2019-10-07 15:24:26,001 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-10-07 15:24:26,002 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=288, Invalid=1194, Unknown=0, NotChecked=0, Total=1482 [2019-10-07 15:24:26,003 INFO L87 Difference]: Start difference. First operand 37 states and 41 transitions. Second operand 39 states. [2019-10-07 15:24:31,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:31,666 INFO L93 Difference]: Finished difference Result 65 states and 84 transitions. [2019-10-07 15:24:31,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-07 15:24:31,666 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 52 [2019-10-07 15:24:31,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:31,667 INFO L225 Difference]: With dead ends: 65 [2019-10-07 15:24:31,667 INFO L226 Difference]: Without dead ends: 46 [2019-10-07 15:24:31,670 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 121 SyntacticMatches, 6 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1293 ImplicationChecksByTransitivity, 6.1s TimeCoverageRelationStatistics Valid=892, Invalid=4362, Unknown=2, NotChecked=0, Total=5256 [2019-10-07 15:24:31,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2019-10-07 15:24:31,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 46. [2019-10-07 15:24:31,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2019-10-07 15:24:31,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 50 transitions. [2019-10-07 15:24:31,679 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 50 transitions. Word has length 52 [2019-10-07 15:24:31,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:31,680 INFO L462 AbstractCegarLoop]: Abstraction has 46 states and 50 transitions. [2019-10-07 15:24:31,680 INFO L463 AbstractCegarLoop]: Interpolant automaton has 39 states. [2019-10-07 15:24:31,680 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 50 transitions. [2019-10-07 15:24:31,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-07 15:24:31,681 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:31,681 INFO L385 BasicCegarLoop]: trace histogram [20, 18, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:31,885 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:31,886 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:31,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:31,886 INFO L82 PathProgramCache]: Analyzing trace with hash -1554765565, now seen corresponding path program 5 times [2019-10-07 15:24:31,886 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:31,887 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:31,887 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:31,887 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:31,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:31,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:32,044 INFO L134 CoverageAnalysis]: Checked inductivity of 427 backedges. 100 proven. 21 refuted. 0 times theorem prover too weak. 306 trivial. 0 not checked. [2019-10-07 15:24:32,044 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:32,044 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:32,044 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:32,213 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:24:32,213 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:32,217 INFO L256 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:24:32,219 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:32,239 INFO L134 CoverageAnalysis]: Checked inductivity of 427 backedges. 102 proven. 1 refuted. 0 times theorem prover too weak. 324 trivial. 0 not checked. [2019-10-07 15:24:32,239 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:32,271 INFO L134 CoverageAnalysis]: Checked inductivity of 427 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 426 trivial. 0 not checked. [2019-10-07 15:24:32,272 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:32,274 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:32,274 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:32,274 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:32,274 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:32,275 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:32,297 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:33,560 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:33,586 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:33,593 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:33,594 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:33,594 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:33,594 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 20)) (<= 20 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:33,594 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:33,594 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:24:33,594 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:33,595 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:33,595 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:24:33,595 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_max_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (< main_~i~1 20)) (= |main_#t~ret6| (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647)) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (not (< main_~i~1 20)) (= |main_#t~ret6| (+ (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296)))))) (exists ((v_max_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_777 Int)) (or (and (not (< main_~i~1 20)) (<= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) |main_#t~ret6|)) (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_777 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_prenex_777 4294967296) (- 4294967296))))))) [2019-10-07 15:24:33,595 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:33,595 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:33,596 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:33,596 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:33,596 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:33,596 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:33,596 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:33,596 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:24:33,597 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_777 Int) (v_max_~ret~0_BEFORE_RETURN_105 Int) (v_max_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_777 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_777 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:33,597 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_max_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_prenex_805 Int) (v_max_~ret~0_BEFORE_RETURN_110 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_prenex_805 Int) (v_max_~ret~0_BEFORE_RETURN_110 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))))) [2019-10-07 15:24:33,597 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:33,958 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:33,959 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 4, 4, 11] total 23 [2019-10-07 15:24:33,960 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-10-07 15:24:33,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-10-07 15:24:33,961 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=472, Unknown=0, NotChecked=0, Total=552 [2019-10-07 15:24:33,961 INFO L87 Difference]: Start difference. First operand 46 states and 50 transitions. Second operand 24 states. [2019-10-07 15:24:35,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:35,003 INFO L93 Difference]: Finished difference Result 69 states and 82 transitions. [2019-10-07 15:24:35,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-10-07 15:24:35,003 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 63 [2019-10-07 15:24:35,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:35,004 INFO L225 Difference]: With dead ends: 69 [2019-10-07 15:24:35,004 INFO L226 Difference]: Without dead ends: 50 [2019-10-07 15:24:35,005 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 216 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 362 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=282, Invalid=1524, Unknown=0, NotChecked=0, Total=1806 [2019-10-07 15:24:35,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-07 15:24:35,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-07 15:24:35,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-07 15:24:35,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-07 15:24:35,013 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 63 [2019-10-07 15:24:35,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:35,014 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-07 15:24:35,014 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-10-07 15:24:35,014 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-07 15:24:35,015 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-10-07 15:24:35,015 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:35,015 INFO L385 BasicCegarLoop]: trace histogram [21, 20, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:35,219 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:35,219 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:35,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:35,220 INFO L82 PathProgramCache]: Analyzing trace with hash 654654435, now seen corresponding path program 6 times [2019-10-07 15:24:35,220 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:35,220 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:35,221 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:35,221 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:35,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:35,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:35,339 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 0 proven. 158 refuted. 0 times theorem prover too weak. 344 trivial. 0 not checked. [2019-10-07 15:24:35,340 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:35,340 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:35,340 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:35,538 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:24:35,538 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:35,539 INFO L256 TraceCheckSpWp]: Trace formula consists of 337 conjuncts, 9 conjunts are in the unsatisfiable core [2019-10-07 15:24:35,542 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:35,559 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 130 proven. 28 refuted. 0 times theorem prover too weak. 344 trivial. 0 not checked. [2019-10-07 15:24:35,559 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:35,698 INFO L134 CoverageAnalysis]: Checked inductivity of 502 backedges. 0 proven. 158 refuted. 0 times theorem prover too weak. 344 trivial. 0 not checked. [2019-10-07 15:24:35,699 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:35,703 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:35,704 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:35,704 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:35,705 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:35,705 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:35,723 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:36,991 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:37,012 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:37,014 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:37,015 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:37,015 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:37,015 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 20)) (<= 20 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:37,015 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:37,015 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:24:37,016 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:37,016 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:37,016 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:37,016 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_972 Int) (v_max_~ret~0_BEFORE_RETURN_132 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (= (+ (mod v_prenex_972 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (not (< main_~i~1 20)) (<= (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296))))) (exists ((v_prenex_971 Int) (v_max_~ret~0_BEFORE_RETURN_131 Int)) (or (and (not (< main_~i~1 20)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647))) (and (<= (mod v_prenex_971 4294967296) 2147483647) (not (< main_~i~1 20)) (= (mod v_prenex_971 4294967296) |main_#t~ret6|))))) [2019-10-07 15:24:37,016 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:37,017 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:37,017 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:37,017 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:37,017 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:37,017 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:37,017 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:37,018 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:24:37,018 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_max_~ret~0_BEFORE_RETURN_131 Int) (v_max_~ret~0_BEFORE_RETURN_132 Int)) (or (and (<= (mod v_prenex_971 4294967296) 2147483647) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_971 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:37,018 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1000 Int) (v_max_~ret~0_BEFORE_RETURN_135 Int) (v_max_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_999 Int)) (or (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (not (< main_~i~2 19))) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1000 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)))))) (and (exists ((v_prenex_1000 Int) (v_max_~ret~0_BEFORE_RETURN_135 Int) (v_max_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_999 Int)) (or (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (not (< main_~i~2 19))) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1000 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:24:37,018 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:37,362 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:37,362 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 11] total 29 [2019-10-07 15:24:37,363 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2019-10-07 15:24:37,364 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2019-10-07 15:24:37,364 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=201, Invalid=669, Unknown=0, NotChecked=0, Total=870 [2019-10-07 15:24:37,365 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 30 states. [2019-10-07 15:24:38,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:38,720 INFO L93 Difference]: Finished difference Result 82 states and 100 transitions. [2019-10-07 15:24:38,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-10-07 15:24:38,720 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 69 [2019-10-07 15:24:38,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:38,722 INFO L225 Difference]: With dead ends: 82 [2019-10-07 15:24:38,722 INFO L226 Difference]: Without dead ends: 59 [2019-10-07 15:24:38,724 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 242 GetRequests, 190 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 713 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=656, Invalid=2206, Unknown=0, NotChecked=0, Total=2862 [2019-10-07 15:24:38,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2019-10-07 15:24:38,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2019-10-07 15:24:38,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2019-10-07 15:24:38,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 63 transitions. [2019-10-07 15:24:38,733 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 63 transitions. Word has length 69 [2019-10-07 15:24:38,734 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:38,734 INFO L462 AbstractCegarLoop]: Abstraction has 59 states and 63 transitions. [2019-10-07 15:24:38,734 INFO L463 AbstractCegarLoop]: Interpolant automaton has 30 states. [2019-10-07 15:24:38,734 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 63 transitions. [2019-10-07 15:24:38,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-07 15:24:38,736 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:38,736 INFO L385 BasicCegarLoop]: trace histogram [48, 20, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:38,940 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:38,941 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:38,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:38,941 INFO L82 PathProgramCache]: Analyzing trace with hash -953193299, now seen corresponding path program 7 times [2019-10-07 15:24:38,942 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:38,942 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:38,942 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:38,943 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:38,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:39,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:39,252 INFO L134 CoverageAnalysis]: Checked inductivity of 1501 backedges. 580 proven. 136 refuted. 0 times theorem prover too weak. 785 trivial. 0 not checked. [2019-10-07 15:24:39,252 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:39,253 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:39,253 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:39,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:39,521 INFO L256 TraceCheckSpWp]: Trace formula consists of 445 conjuncts, 18 conjunts are in the unsatisfiable core [2019-10-07 15:24:39,525 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:39,545 INFO L134 CoverageAnalysis]: Checked inductivity of 1501 backedges. 580 proven. 136 refuted. 0 times theorem prover too weak. 785 trivial. 0 not checked. [2019-10-07 15:24:39,545 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:39,811 INFO L134 CoverageAnalysis]: Checked inductivity of 1501 backedges. 0 proven. 716 refuted. 0 times theorem prover too weak. 785 trivial. 0 not checked. [2019-10-07 15:24:39,811 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:39,813 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:39,813 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:39,814 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:39,814 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:39,814 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:39,831 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:41,102 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:41,123 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:41,125 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:41,125 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:41,125 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:41,125 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 20)) (<= 20 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:41,126 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:41,126 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:24:41,126 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:41,126 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:41,126 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:41,126 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_1166 Int) (v_max_~ret~0_BEFORE_RETURN_158 Int)) (or (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 20)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (<= (mod v_prenex_1166 4294967296) 2147483647) (= (mod v_prenex_1166 4294967296) |main_#t~ret6|)))) (exists ((v_prenex_1165 Int) (v_max_~ret~0_BEFORE_RETURN_157 Int)) (or (and (<= (mod v_prenex_1165 4294967296) 2147483647) (= |main_#t~ret6| (mod v_prenex_1165 4294967296)) (not (< main_~i~1 20))) (and (not (< main_~i~1 20)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_max_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296))))))) [2019-10-07 15:24:41,127 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:41,127 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:41,127 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:41,127 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:41,128 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:41,128 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:41,128 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:41,128 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:24:41,129 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_1166 Int) (v_prenex_1165 Int) (v_max_~ret~0_BEFORE_RETURN_157 Int) (v_max_~ret~0_BEFORE_RETURN_158 Int)) (or (and (<= (mod v_prenex_1165 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_1165 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1166 4294967296)) (not (< main_~i~1 20)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:41,129 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_161 Int) (v_max_~ret~0_BEFORE_RETURN_162 Int) (v_prenex_1194 Int) (v_prenex_1193 Int)) (or (and (= (mod v_max_~ret~0_BEFORE_RETURN_161 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_max_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (not (< main_~i~2 19))) (and (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0))))) (and (exists ((v_max_~ret~0_BEFORE_RETURN_161 Int) (v_max_~ret~0_BEFORE_RETURN_162 Int) (v_prenex_1194 Int) (v_prenex_1193 Int)) (or (and (= (mod v_max_~ret~0_BEFORE_RETURN_161 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_max_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (not (< main_~i~2 19))) (and (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0)))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:24:41,129 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:41,511 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:41,512 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 11] total 33 [2019-10-07 15:24:41,513 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2019-10-07 15:24:41,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-10-07 15:24:41,514 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=283, Invalid=839, Unknown=0, NotChecked=0, Total=1122 [2019-10-07 15:24:41,514 INFO L87 Difference]: Start difference. First operand 59 states and 63 transitions. Second operand 34 states. [2019-10-07 15:24:43,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:43,247 INFO L93 Difference]: Finished difference Result 95 states and 108 transitions. [2019-10-07 15:24:43,247 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-10-07 15:24:43,247 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 96 [2019-10-07 15:24:43,248 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:43,249 INFO L225 Difference]: With dead ends: 95 [2019-10-07 15:24:43,249 INFO L226 Difference]: Without dead ends: 63 [2019-10-07 15:24:43,251 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 334 GetRequests, 260 SyntacticMatches, 14 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 921 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=918, Invalid=2864, Unknown=0, NotChecked=0, Total=3782 [2019-10-07 15:24:43,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2019-10-07 15:24:43,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2019-10-07 15:24:43,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2019-10-07 15:24:43,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 67 transitions. [2019-10-07 15:24:43,261 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 67 transitions. Word has length 96 [2019-10-07 15:24:43,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:43,261 INFO L462 AbstractCegarLoop]: Abstraction has 63 states and 67 transitions. [2019-10-07 15:24:43,261 INFO L463 AbstractCegarLoop]: Interpolant automaton has 34 states. [2019-10-07 15:24:43,261 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 67 transitions. [2019-10-07 15:24:43,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2019-10-07 15:24:43,263 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:43,263 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:43,469 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:43,469 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:43,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:43,470 INFO L82 PathProgramCache]: Analyzing trace with hash 1762274093, now seen corresponding path program 8 times [2019-10-07 15:24:43,470 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:43,470 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:43,470 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:43,470 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:43,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:43,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:43,676 INFO L134 CoverageAnalysis]: Checked inductivity of 2179 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:24:43,676 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:43,677 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:43,677 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:43,954 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2019-10-07 15:24:43,955 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:43,956 INFO L256 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:24:43,960 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:43,979 INFO L134 CoverageAnalysis]: Checked inductivity of 2179 backedges. 886 proven. 10 refuted. 0 times theorem prover too weak. 1283 trivial. 0 not checked. [2019-10-07 15:24:43,979 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:44,040 INFO L134 CoverageAnalysis]: Checked inductivity of 2179 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:24:44,041 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:44,042 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:44,042 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:44,043 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:44,043 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:44,043 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:44,057 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:45,236 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:45,262 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:45,265 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:45,265 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:45,265 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:45,266 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 20)) (<= 20 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:45,266 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:45,266 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:24:45,266 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:45,266 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:45,266 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:45,267 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_1359 Int) (v_max_~ret~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 20)) (<= (mod v_max_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_183 4294967296) |main_#t~ret6|)) (and (not (<= (mod v_prenex_1359 4294967296) 2147483647)) (not (< main_~i~1 20)) (= |main_#t~ret6| (+ (mod v_prenex_1359 4294967296) (- 4294967296)))))) (exists ((v_max_~ret~0_BEFORE_RETURN_184 Int) (v_prenex_1360 Int)) (or (and (not (< main_~i~1 20)) (<= (mod v_max_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_184 4294967296) |main_#t~ret6|)) (and (not (< main_~i~1 20)) (= |main_#t~ret6| (+ (mod v_prenex_1360 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1360 4294967296) 2147483647)))))) [2019-10-07 15:24:45,267 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:45,267 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:45,267 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:45,267 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:45,267 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:45,268 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:45,268 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:45,268 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:24:45,268 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_1359 Int) (v_max_~ret~0_BEFORE_RETURN_183 Int) (v_max_~ret~0_BEFORE_RETURN_184 Int) (v_prenex_1360 Int)) (or (and (not (<= (mod v_prenex_1359 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_1359 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_183 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_184 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_1360 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:45,268 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_max_~ret~0_BEFORE_RETURN_187 Int) (v_max_~ret~0_BEFORE_RETURN_188 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (not (< main_~i~2 19)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296)))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_188 4294967296))) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)))))) (and (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_max_~ret~0_BEFORE_RETURN_187 Int) (v_max_~ret~0_BEFORE_RETURN_188 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (not (< main_~i~2 19)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296)))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_188 4294967296))) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:24:45,269 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:45,621 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:45,621 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 23 [2019-10-07 15:24:45,622 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-10-07 15:24:45,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-10-07 15:24:45,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=445, Unknown=0, NotChecked=0, Total=552 [2019-10-07 15:24:45,623 INFO L87 Difference]: Start difference. First operand 63 states and 67 transitions. Second operand 24 states. [2019-10-07 15:24:46,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:46,476 INFO L93 Difference]: Finished difference Result 97 states and 107 transitions. [2019-10-07 15:24:46,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-10-07 15:24:46,476 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 108 [2019-10-07 15:24:46,477 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:46,478 INFO L225 Difference]: With dead ends: 97 [2019-10-07 15:24:46,478 INFO L226 Difference]: Without dead ends: 69 [2019-10-07 15:24:46,479 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 349 GetRequests, 309 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 426 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=312, Invalid=1410, Unknown=0, NotChecked=0, Total=1722 [2019-10-07 15:24:46,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2019-10-07 15:24:46,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2019-10-07 15:24:46,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2019-10-07 15:24:46,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 73 transitions. [2019-10-07 15:24:46,490 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 73 transitions. Word has length 108 [2019-10-07 15:24:46,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:46,490 INFO L462 AbstractCegarLoop]: Abstraction has 69 states and 73 transitions. [2019-10-07 15:24:46,491 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-10-07 15:24:46,491 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 73 transitions. [2019-10-07 15:24:46,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2019-10-07 15:24:46,492 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:46,492 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 10, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:46,693 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:46,693 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:46,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:46,694 INFO L82 PathProgramCache]: Analyzing trace with hash -128228499, now seen corresponding path program 9 times [2019-10-07 15:24:46,694 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:46,694 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:46,695 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:46,695 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:46,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:46,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:47,150 INFO L134 CoverageAnalysis]: Checked inductivity of 2224 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:24:47,151 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:47,152 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:47,152 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:47,505 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:24:47,505 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:47,508 INFO L256 TraceCheckSpWp]: Trace formula consists of 517 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-07 15:24:47,513 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:47,532 INFO L134 CoverageAnalysis]: Checked inductivity of 2224 backedges. 886 proven. 55 refuted. 0 times theorem prover too weak. 1283 trivial. 0 not checked. [2019-10-07 15:24:47,533 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:47,708 INFO L134 CoverageAnalysis]: Checked inductivity of 2224 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:24:47,708 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:47,709 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:47,709 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:47,710 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:47,710 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:47,710 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:47,725 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:48,994 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:49,023 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:49,025 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:49,026 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:49,026 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:49,026 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 20)) (<= 20 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:49,026 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:49,026 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:24:49,026 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:49,027 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:49,027 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:24:49,027 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_1553 Int) (v_max_~ret~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 20)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= (mod v_prenex_1553 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1553 4294967296) 2147483647)))) (exists ((v_prenex_1554 Int) (v_max_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (< main_~i~1 20)) (= (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296) |main_#t~ret6|) (<= (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (= |main_#t~ret6| (+ (mod v_prenex_1554 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)))))) [2019-10-07 15:24:49,027 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:49,027 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:49,028 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:49,028 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:49,028 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:49,028 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:49,028 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:49,028 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:24:49,029 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(or (exists ((v_prenex_1554 Int) (v_prenex_1553 Int) (v_max_~ret~0_BEFORE_RETURN_209 Int) (v_max_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_1553 4294967296)) (<= (mod v_prenex_1553 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_prenex_1554 Int) (v_prenex_1553 Int) (v_max_~ret~0_BEFORE_RETURN_209 Int) (v_max_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1553 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_1553 4294967296)) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:24:49,029 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_max_~ret~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int) (v_max_~ret~0_BEFORE_RETURN_213 Int)) (or (and (<= (mod v_prenex_1582 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_214 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_max_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_213 4294967296) main_~ret5~0)) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int) (v_max_~ret~0_BEFORE_RETURN_213 Int)) (or (and (<= (mod v_prenex_1582 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_214 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_max_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_213 4294967296) main_~ret5~0)) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))))) [2019-10-07 15:24:49,029 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:49,464 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:49,464 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 11] total 32 [2019-10-07 15:24:49,465 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-10-07 15:24:49,466 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-10-07 15:24:49,466 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=260, Invalid=796, Unknown=0, NotChecked=0, Total=1056 [2019-10-07 15:24:49,466 INFO L87 Difference]: Start difference. First operand 69 states and 73 transitions. Second operand 33 states. [2019-10-07 15:24:52,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:52,795 INFO L93 Difference]: Finished difference Result 106 states and 119 transitions. [2019-10-07 15:24:52,795 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-10-07 15:24:52,795 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 114 [2019-10-07 15:24:52,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:52,797 INFO L225 Difference]: With dead ends: 106 [2019-10-07 15:24:52,797 INFO L226 Difference]: Without dead ends: 78 [2019-10-07 15:24:52,798 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 382 GetRequests, 321 SyntacticMatches, 3 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 864 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=771, Invalid=2769, Unknown=0, NotChecked=0, Total=3540 [2019-10-07 15:24:52,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2019-10-07 15:24:52,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 78. [2019-10-07 15:24:52,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2019-10-07 15:24:52,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 82 transitions. [2019-10-07 15:24:52,809 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 82 transitions. Word has length 114 [2019-10-07 15:24:52,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:52,809 INFO L462 AbstractCegarLoop]: Abstraction has 78 states and 82 transitions. [2019-10-07 15:24:52,809 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-10-07 15:24:52,810 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 82 transitions. [2019-10-07 15:24:52,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2019-10-07 15:24:52,811 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:52,811 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 19, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:53,016 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:53,017 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:53,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:53,017 INFO L82 PathProgramCache]: Analyzing trace with hash 1922274819, now seen corresponding path program 10 times [2019-10-07 15:24:53,018 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:53,018 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:53,018 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:53,018 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:53,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:29:34,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat