java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/max40-1.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:24:24,002 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:24:24,004 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:24:24,024 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:24:24,024 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:24:24,026 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:24:24,028 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:24:24,041 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:24:24,043 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:24:24,044 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:24:24,045 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:24:24,047 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:24:24,047 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:24:24,051 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:24:24,054 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:24:24,055 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:24:24,057 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:24:24,059 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:24:24,061 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:24:24,068 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:24:24,072 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:24:24,075 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:24:24,076 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:24:24,079 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:24:24,082 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 15:24:24,094 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:24:24,095 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:24:24,096 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:24:24,096 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:24:24,110 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:24:24,110 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:24:24,111 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:24:24,111 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:24:24,112 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:24:24,112 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:24:24,112 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:24:24,112 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:24:24,112 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:24:24,113 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:24:24,113 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:24:24,113 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:24:24,113 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:24:24,113 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:24:24,114 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:24:24,114 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:24:24,114 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:24:24,114 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:24:24,114 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:24:24,115 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:24:24,115 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:24:24,115 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:24:24,115 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:24:24,115 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:24:24,116 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:24:24,116 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:24:24,116 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:24:24,116 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:24:24,116 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:24:24,398 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:24:24,422 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:24:24,426 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:24:24,428 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:24:24,428 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:24:24,429 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/max40-1.i [2019-10-07 15:24:24,504 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0d8d81162/ea24926b302c4ad0b356e9e0df17e546/FLAG40365a492 [2019-10-07 15:24:24,997 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:24:24,999 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/max40-1.i [2019-10-07 15:24:25,006 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0d8d81162/ea24926b302c4ad0b356e9e0df17e546/FLAG40365a492 [2019-10-07 15:24:25,414 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0d8d81162/ea24926b302c4ad0b356e9e0df17e546 [2019-10-07 15:24:25,426 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:24:25,428 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:24:25,428 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:24:25,429 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:24:25,431 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:24:25,432 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:24:25" (1/1) ... [2019-10-07 15:24:25,434 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4b70fdbb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:25, skipping insertion in model container [2019-10-07 15:24:25,434 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:24:25" (1/1) ... [2019-10-07 15:24:25,442 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:24:25,458 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:24:25,623 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:24:25,632 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:24:25,652 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:24:25,668 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:24:25,668 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:25 WrapperNode [2019-10-07 15:24:25,668 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:24:25,669 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:24:25,669 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:24:25,669 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:24:25,765 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:25" (1/1) ... [2019-10-07 15:24:25,765 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:25" (1/1) ... [2019-10-07 15:24:25,773 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:25" (1/1) ... [2019-10-07 15:24:25,774 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:25" (1/1) ... [2019-10-07 15:24:25,784 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:25" (1/1) ... [2019-10-07 15:24:25,790 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:25" (1/1) ... [2019-10-07 15:24:25,791 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:25" (1/1) ... [2019-10-07 15:24:25,795 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:24:25,795 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:24:25,796 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:24:25,796 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:24:25,797 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:25" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:24:25,853 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:24:25,854 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:24:25,854 INFO L138 BoogieDeclarations]: Found implementation of procedure max [2019-10-07 15:24:25,854 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:24:25,854 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:24:25,854 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:24:25,854 INFO L130 BoogieDeclarations]: Found specification of procedure max [2019-10-07 15:24:25,855 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:24:25,855 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:24:25,855 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:24:25,855 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:24:25,855 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:24:25,855 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:24:25,856 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:24:26,283 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:24:26,284 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:24:26,285 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:24:26 BoogieIcfgContainer [2019-10-07 15:24:26,286 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:24:26,287 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:24:26,287 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:24:26,290 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:24:26,290 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:24:25" (1/3) ... [2019-10-07 15:24:26,291 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7b4ad807 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:24:26, skipping insertion in model container [2019-10-07 15:24:26,291 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:24:25" (2/3) ... [2019-10-07 15:24:26,292 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7b4ad807 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:24:26, skipping insertion in model container [2019-10-07 15:24:26,292 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:24:26" (3/3) ... [2019-10-07 15:24:26,294 INFO L109 eAbstractionObserver]: Analyzing ICFG max40-1.i [2019-10-07 15:24:26,304 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:24:26,312 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:24:26,323 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:24:26,346 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:24:26,346 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:24:26,346 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:24:26,347 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:24:26,347 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:24:26,347 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:24:26,347 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:24:26,347 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:24:26,365 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:24:26,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:24:26,371 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:26,372 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:26,374 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:26,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:26,378 INFO L82 PathProgramCache]: Analyzing trace with hash 855740909, now seen corresponding path program 1 times [2019-10-07 15:24:26,385 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:26,385 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:26,385 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:26,386 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:26,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:26,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:26,558 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:24:26,559 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:26,560 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:24:26,560 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:24:26,564 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:24:26,578 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:24:26,579 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:24:26,581 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:24:26,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:26,620 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:24:26,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:24:26,622 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:24:26,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:26,630 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:24:26,630 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:24:26,634 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:24:26,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:24:26,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:24:26,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:24:26,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:24:26,675 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:24:26,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:26,675 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:24:26,676 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:24:26,676 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:24:26,678 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:24:26,678 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:26,678 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:26,679 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:26,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:26,680 INFO L82 PathProgramCache]: Analyzing trace with hash -1075349738, now seen corresponding path program 1 times [2019-10-07 15:24:26,680 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:26,680 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:26,680 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:26,681 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:26,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:26,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:26,768 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:24:26,768 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:26,768 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:26,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:26,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:26,839 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:24:26,846 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:26,873 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:24:26,874 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:26,907 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:24:26,908 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:24:26,908 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:24:26,910 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:24:26,910 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:24:26,911 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:24:26,911 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:24:26,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:26,921 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:24:26,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:24:26,922 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:24:26,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:26,923 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:24:26,923 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:24:26,924 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:24:26,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:24:26,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:24:26,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:24:26,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:24:26,930 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:24:26,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:26,931 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:24:26,931 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:24:26,931 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:24:26,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:24:26,932 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:26,932 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:27,136 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:27,137 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:27,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:27,138 INFO L82 PathProgramCache]: Analyzing trace with hash 447698074, now seen corresponding path program 1 times [2019-10-07 15:24:27,138 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:27,139 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:27,139 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:27,139 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:27,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:27,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:27,265 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:27,265 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:27,266 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:24:27,266 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:24:27,266 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:24:27,267 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:24:27,267 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:24:27,268 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:24:27,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:27,279 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:24:27,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:24:27,280 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:24:27,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:27,281 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:24:27,281 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:24:27,282 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:24:27,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:24:27,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:24:27,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:24:27,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:24:27,288 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:24:27,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:27,290 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:24:27,291 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:24:27,291 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:24:27,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:24:27,292 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:27,292 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:27,292 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:27,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:27,293 INFO L82 PathProgramCache]: Analyzing trace with hash -69054062, now seen corresponding path program 1 times [2019-10-07 15:24:27,293 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:27,293 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:27,294 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:27,294 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:27,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:27,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:27,398 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:27,398 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:27,399 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:27,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:27,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:27,479 INFO L256 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:24:27,482 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:27,494 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:27,494 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:27,547 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:27,547 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:27,593 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:27,594 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:27,605 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:27,614 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:27,614 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:27,807 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:29,935 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:30,008 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:30,012 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:30,012 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:30,013 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 640#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:30,013 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 636#(and (not (< max_~i~0 40)) (<= 40 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:30,013 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 467#true [2019-10-07 15:24:30,014 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 222#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_max_~ret~0_BEFORE_RETURN_5 Int) (v_prenex_30 Int) (v_max_~ret~0_BEFORE_RETURN_6 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_29 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_29 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_prenex_29 Int) (v_max_~ret~0_BEFORE_RETURN_5 Int) (v_prenex_30 Int) (v_max_~ret~0_BEFORE_RETURN_6 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_29 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_29 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:24:30,014 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 510#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:24:30,014 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 631#(<= 0 max_~i~0) [2019-10-07 15:24:30,014 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:30,015 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:30,015 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 108#(or (exists ((v_max_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (not (< main_~i~1 40)) (= (+ (mod v_prenex_1 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 40)) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296))))) (exists ((v_prenex_2 Int) (v_max_~ret~0_BEFORE_RETURN_2 Int)) (or (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 40))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) |main_#t~ret6|))))) [2019-10-07 15:24:30,015 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 368#true [2019-10-07 15:24:30,015 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 645#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:30,016 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:30,016 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 301#true [2019-10-07 15:24:30,016 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 589#true [2019-10-07 15:24:30,016 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 575#true [2019-10-07 15:24:30,016 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 548#true [2019-10-07 15:24:30,018 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:24:30,018 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 580#(exists ((v_max_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_2 Int) (v_max_~ret~0_BEFORE_RETURN_2 Int) (v_prenex_1 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:30,019 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:30,390 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:30,391 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:24:30,392 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-07 15:24:30,393 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-07 15:24:30,395 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-07 15:24:30,395 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-07 15:24:31,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:31,067 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:24:31,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-07 15:24:31,068 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-07 15:24:31,068 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:31,072 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:24:31,072 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:24:31,073 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 101 GetRequests, 73 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 192 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=139, Invalid=731, Unknown=0, NotChecked=0, Total=870 [2019-10-07 15:24:31,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:24:31,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:24:31,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:24:31,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:24:31,085 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:24:31,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:31,085 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:24:31,086 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-07 15:24:31,086 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:24:31,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:24:31,087 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:31,087 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:31,292 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:31,293 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:31,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:31,293 INFO L82 PathProgramCache]: Analyzing trace with hash -493974743, now seen corresponding path program 2 times [2019-10-07 15:24:31,294 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:31,294 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:31,294 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:31,294 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:31,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:31,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:31,413 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:24:31,413 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:31,414 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:31,414 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:31,491 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:24:31,491 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:31,493 INFO L256 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:24:31,498 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:31,517 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:31,517 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:31,556 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:24:31,557 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:31,558 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:31,559 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:31,559 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:31,560 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:31,560 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:31,581 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:33,151 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:33,179 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:33,182 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:33,182 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:33,183 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:33,183 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 40)) (<= 40 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:33,183 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:33,183 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_224 Int) (v_max_~ret~0_BEFORE_RETURN_32 Int) (v_max_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_prenex_224 Int) (v_max_~ret~0_BEFORE_RETURN_32 Int) (v_max_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:24:33,184 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:24:33,184 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:33,184 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:33,184 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:33,184 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_195 Int) (v_max_~ret~0_BEFORE_RETURN_27 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (= (mod v_prenex_195 4294967296) |main_#t~ret6|) (not (< main_~i~1 40)) (<= (mod v_prenex_195 4294967296) 2147483647)))) (exists ((v_prenex_196 Int) (v_max_~ret~0_BEFORE_RETURN_28 Int)) (or (and (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296))) (and (not (<= (mod v_prenex_196 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret6|))))) [2019-10-07 15:24:33,185 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:33,185 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:33,185 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:33,185 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:33,185 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:33,185 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:33,186 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:33,186 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:24:33,186 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_196 Int) (v_prenex_195 Int) (v_max_~ret~0_BEFORE_RETURN_28 Int) (v_max_~ret~0_BEFORE_RETURN_27 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_195 4294967296) main_~ret~1) (<= (mod v_prenex_195 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:33,186 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:33,529 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:33,530 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:24:33,531 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-07 15:24:33,532 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-07 15:24:33,532 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-07 15:24:33,532 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-07 15:24:34,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:34,530 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:24:34,530 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:24:34,531 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-07 15:24:34,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:34,532 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:24:34,532 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:24:34,533 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-07 15:24:34,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:24:34,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:24:34,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:24:34,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:24:34,540 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:24:34,540 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:34,541 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:24:34,541 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-07 15:24:34,541 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:24:34,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:24:34,542 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:34,542 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:34,753 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:34,755 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:34,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:34,756 INFO L82 PathProgramCache]: Analyzing trace with hash 132820922, now seen corresponding path program 3 times [2019-10-07 15:24:34,756 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:34,756 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:34,756 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:34,756 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:34,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:34,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:34,856 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:34,856 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:34,856 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:34,856 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:34,966 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:24:34,967 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:34,968 INFO L256 TraceCheckSpWp]: Trace formula consists of 199 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:24:34,971 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:34,986 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:34,987 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:35,061 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:35,062 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:35,063 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:35,064 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:35,064 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:35,065 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:35,065 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:35,097 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:36,995 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:37,036 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:37,041 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:37,042 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:37,042 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:37,043 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 40)) (<= 40 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:37,043 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:37,043 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_max_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_max_~ret~0_BEFORE_RETURN_58 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_prenex_418 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_418 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_prenex_417 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_417 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_max_~ret~0_BEFORE_RETURN_58 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_prenex_418 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_418 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_prenex_417 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_417 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:24:37,044 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:24:37,044 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:37,044 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:37,045 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:37,045 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_389 Int) (v_max_~ret~0_BEFORE_RETURN_53 Int)) (or (and (not (< main_~i~1 40)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (<= (mod v_prenex_389 4294967296) 2147483647) (= |main_#t~ret6| (mod v_prenex_389 4294967296))))) (exists ((v_max_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 40)) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296)) (<= (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647)) (and (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 40)) (not (<= (mod v_prenex_390 4294967296) 2147483647)))))) [2019-10-07 15:24:37,045 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:37,046 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:37,046 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:37,046 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:37,047 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:37,047 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:37,047 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:37,047 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:24:37,048 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_389 Int) (v_max_~ret~0_BEFORE_RETURN_54 Int) (v_max_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_390 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296)) (<= (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_389 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:37,048 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:39,586 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:39,587 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-07 15:24:39,588 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-07 15:24:39,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-07 15:24:39,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=515, Unknown=1, NotChecked=0, Total=650 [2019-10-07 15:24:39,589 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-07 15:24:40,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:40,478 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-07 15:24:40,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-07 15:24:40,479 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-07 15:24:40,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:40,480 INFO L225 Difference]: With dead ends: 54 [2019-10-07 15:24:40,480 INFO L226 Difference]: Without dead ends: 36 [2019-10-07 15:24:40,482 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=369, Invalid=1700, Unknown=1, NotChecked=0, Total=2070 [2019-10-07 15:24:40,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-07 15:24:40,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-07 15:24:40,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-07 15:24:40,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-07 15:24:40,490 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-07 15:24:40,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:40,490 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-07 15:24:40,490 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-07 15:24:40,490 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-07 15:24:40,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-07 15:24:40,491 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:40,492 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:40,696 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:40,696 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:40,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:40,697 INFO L82 PathProgramCache]: Analyzing trace with hash 944007491, now seen corresponding path program 4 times [2019-10-07 15:24:40,697 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:40,698 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:40,698 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:40,698 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:40,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:40,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:40,857 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:40,857 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:40,857 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:40,857 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:41,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:41,028 INFO L256 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:24:41,031 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:41,047 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:41,047 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:41,405 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:41,406 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:41,408 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:41,409 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:41,409 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:41,410 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:41,410 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:41,430 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:42,655 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:42,679 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:42,681 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:42,682 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:42,682 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:42,682 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 40)) (<= 40 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:42,682 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:42,682 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_max_~ret~0_BEFORE_RETURN_84 Int) (v_max_~ret~0_BEFORE_RETURN_83 Int)) (or (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_611 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_max_~ret~0_BEFORE_RETURN_84 Int) (v_max_~ret~0_BEFORE_RETURN_83 Int)) (or (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_611 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:24:42,683 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:24:42,683 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:24:42,683 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:42,683 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:42,683 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_max_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_583 Int)) (or (and (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) |main_#t~ret6|)) (and (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 40)) (not (<= (mod v_prenex_583 4294967296) 2147483647))))) (exists ((v_prenex_584 Int) (v_max_~ret~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) |main_#t~ret6|)) (and (not (< main_~i~1 40)) (= (+ (mod v_prenex_584 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_584 4294967296) 2147483647)))))) [2019-10-07 15:24:42,684 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:42,684 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:42,684 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:42,684 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:42,684 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:42,684 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:42,685 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:42,685 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:24:42,685 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_max_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_583 Int) (v_prenex_584 Int) (v_max_~ret~0_BEFORE_RETURN_80 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_583 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_584 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_prenex_584 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:42,685 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:43,060 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:43,060 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-07 15:24:43,061 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-07 15:24:43,062 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-07 15:24:43,063 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:24:43,063 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 40 states. [2019-10-07 15:24:44,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:44,622 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-07 15:24:44,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-07 15:24:44,623 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 49 [2019-10-07 15:24:44,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:44,624 INFO L225 Difference]: With dead ends: 68 [2019-10-07 15:24:44,624 INFO L226 Difference]: Without dead ends: 50 [2019-10-07 15:24:44,626 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:24:44,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-07 15:24:44,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-07 15:24:44,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-07 15:24:44,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-07 15:24:44,635 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-07 15:24:44,635 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:44,635 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-07 15:24:44,636 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-07 15:24:44,636 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-07 15:24:44,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-07 15:24:44,637 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:44,638 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:44,843 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:44,844 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:44,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:44,845 INFO L82 PathProgramCache]: Analyzing trace with hash -1182307997, now seen corresponding path program 5 times [2019-10-07 15:24:44,845 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:44,845 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:44,845 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:44,846 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:44,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:44,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:45,276 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:24:45,276 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:45,277 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:45,277 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:45,450 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:24:45,450 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:45,451 INFO L256 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:24:45,454 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:45,514 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-07 15:24:45,514 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:45,567 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-07 15:24:45,567 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:45,569 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:45,569 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:45,569 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:45,569 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:45,570 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:45,599 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:46,856 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:46,874 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:46,877 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:46,877 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:46,877 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 640#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:46,877 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 636#(and (not (< max_~i~0 40)) (<= 40 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:46,878 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:46,878 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_max_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_prenex_805 Int) (v_max_~ret~0_BEFORE_RETURN_110 Int)) (or (and (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_prenex_805 Int) (v_max_~ret~0_BEFORE_RETURN_110 Int)) (or (and (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:24:46,878 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:24:46,878 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 631#(<= 0 max_~i~0) [2019-10-07 15:24:46,878 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:46,879 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:24:46,879 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_max_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (not (< main_~i~1 40)) (= |main_#t~ret6| (+ (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296)))) (and (not (< main_~i~1 40)) (= |main_#t~ret6| (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647)))) (exists ((v_prenex_777 Int) (v_max_~ret~0_BEFORE_RETURN_105 Int)) (or (and (not (<= (mod v_prenex_777 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_prenex_777 4294967296) (- 4294967296))) (not (< main_~i~1 40))) (and (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) |main_#t~ret6|))))) [2019-10-07 15:24:46,879 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 645#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:46,879 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:46,879 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:46,879 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:46,880 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:46,880 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:46,880 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:46,880 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:24:46,880 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_max_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_777 Int) (v_max_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_777 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (+ (mod v_prenex_777 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:46,881 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:47,434 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:47,434 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-07 15:24:47,435 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-07 15:24:47,436 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-07 15:24:47,436 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-07 15:24:47,437 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 44 states. [2019-10-07 15:24:51,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:51,550 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-07 15:24:51,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-07 15:24:51,550 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 63 [2019-10-07 15:24:51,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:51,551 INFO L225 Difference]: With dead ends: 72 [2019-10-07 15:24:51,551 INFO L226 Difference]: Without dead ends: 54 [2019-10-07 15:24:51,553 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1350 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1349, Invalid=5457, Unknown=0, NotChecked=0, Total=6806 [2019-10-07 15:24:51,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-07 15:24:51,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-07 15:24:51,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-07 15:24:51,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-07 15:24:51,563 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-07 15:24:51,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:51,563 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-07 15:24:51,563 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-07 15:24:51,564 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-07 15:24:51,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-07 15:24:51,565 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:51,565 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:51,772 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:51,772 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:51,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:51,773 INFO L82 PathProgramCache]: Analyzing trace with hash 2129164918, now seen corresponding path program 6 times [2019-10-07 15:24:51,773 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:51,773 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:51,774 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:51,774 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:51,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:51,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:52,238 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:24:52,239 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:52,239 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:52,239 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:52,459 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:24:52,460 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:24:52,461 INFO L256 TraceCheckSpWp]: Trace formula consists of 343 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-07 15:24:52,464 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:52,480 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:24:52,481 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:53,115 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:24:53,115 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:53,117 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:53,117 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:53,118 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:53,118 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:53,118 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:53,131 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:54,315 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:54,329 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:54,331 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:54,332 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:54,332 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 640#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:54,332 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 636#(and (not (< max_~i~0 40)) (<= 40 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:54,332 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:24:54,333 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1000 Int) (v_max_~ret~0_BEFORE_RETURN_135 Int) (v_max_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_999 Int)) (or (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1000 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_prenex_1000 Int) (v_max_~ret~0_BEFORE_RETURN_135 Int) (v_max_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_999 Int)) (or (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1000 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:24:54,333 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:24:54,333 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 631#(<= 0 max_~i~0) [2019-10-07 15:24:54,333 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:54,333 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:54,333 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_972 Int) (v_max_~ret~0_BEFORE_RETURN_132 Int)) (or (and (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296))) (and (not (< main_~i~1 40)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (= (+ (mod v_prenex_972 4294967296) (- 4294967296)) |main_#t~ret6|)))) (exists ((v_prenex_971 Int) (v_max_~ret~0_BEFORE_RETURN_131 Int)) (or (and (<= (mod v_prenex_971 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_971 4294967296) |main_#t~ret6|)) (and (not (< main_~i~1 40)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647)))))) [2019-10-07 15:24:54,334 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 645#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:54,334 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:24:54,334 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:54,334 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:24:54,334 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:24:54,334 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:24:54,335 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:24:54,335 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:24:54,335 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_max_~ret~0_BEFORE_RETURN_131 Int) (v_max_~ret~0_BEFORE_RETURN_132 Int)) (or (and (<= (mod v_prenex_971 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_971 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:54,335 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:54,979 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:54,979 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 53 [2019-10-07 15:24:54,980 INFO L442 AbstractCegarLoop]: Interpolant automaton has 54 states [2019-10-07 15:24:54,980 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2019-10-07 15:24:54,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=932, Invalid=1930, Unknown=0, NotChecked=0, Total=2862 [2019-10-07 15:24:54,982 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 54 states. [2019-10-07 15:24:57,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:24:57,349 INFO L93 Difference]: Finished difference Result 88 states and 108 transitions. [2019-10-07 15:24:57,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-10-07 15:24:57,349 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 67 [2019-10-07 15:24:57,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:24:57,350 INFO L225 Difference]: With dead ends: 88 [2019-10-07 15:24:57,350 INFO L226 Difference]: Without dead ends: 67 [2019-10-07 15:24:57,354 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 281 GetRequests, 165 SyntacticMatches, 16 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2497 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=2707, Invalid=7595, Unknown=0, NotChecked=0, Total=10302 [2019-10-07 15:24:57,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2019-10-07 15:24:57,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2019-10-07 15:24:57,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2019-10-07 15:24:57,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 71 transitions. [2019-10-07 15:24:57,362 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 71 transitions. Word has length 67 [2019-10-07 15:24:57,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:24:57,362 INFO L462 AbstractCegarLoop]: Abstraction has 67 states and 71 transitions. [2019-10-07 15:24:57,363 INFO L463 AbstractCegarLoop]: Interpolant automaton has 54 states. [2019-10-07 15:24:57,363 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 71 transitions. [2019-10-07 15:24:57,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2019-10-07 15:24:57,364 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:24:57,364 INFO L385 BasicCegarLoop]: trace histogram [40, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:24:57,574 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:57,574 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:24:57,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:24:57,575 INFO L82 PathProgramCache]: Analyzing trace with hash 1006701, now seen corresponding path program 7 times [2019-10-07 15:24:57,575 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:24:57,575 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:57,575 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:57,575 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:24:57,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:24:57,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:57,739 INFO L134 CoverageAnalysis]: Checked inductivity of 941 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 931 trivial. 0 not checked. [2019-10-07 15:24:57,740 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:24:57,740 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:24:57,740 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:24:58,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:24:58,007 INFO L256 TraceCheckSpWp]: Trace formula consists of 421 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:24:58,010 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:24:58,055 INFO L134 CoverageAnalysis]: Checked inductivity of 941 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 879 trivial. 0 not checked. [2019-10-07 15:24:58,055 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:24:58,131 INFO L134 CoverageAnalysis]: Checked inductivity of 941 backedges. 0 proven. 62 refuted. 0 times theorem prover too weak. 879 trivial. 0 not checked. [2019-10-07 15:24:58,132 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:24:58,134 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:24:58,135 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:24:58,135 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:24:58,136 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:24:58,136 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:24:58,151 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:24:59,348 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:24:59,367 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:24:59,370 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:24:59,371 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:24:59,371 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 640#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:24:59,371 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 636#(and (not (< max_~i~0 40)) (<= 40 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:24:59,371 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 467#true [2019-10-07 15:24:59,371 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 222#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_161 Int) (v_max_~ret~0_BEFORE_RETURN_162 Int) (v_prenex_1194 Int) (v_prenex_1193 Int)) (or (and (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_max_~ret~0_BEFORE_RETURN_161 4294967296) main_~ret5~0) (<= (mod v_max_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_max_~ret~0_BEFORE_RETURN_161 Int) (v_max_~ret~0_BEFORE_RETURN_162 Int) (v_prenex_1194 Int) (v_prenex_1193 Int)) (or (and (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_max_~ret~0_BEFORE_RETURN_161 4294967296) main_~ret5~0) (<= (mod v_max_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:24:59,372 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 510#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:24:59,372 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 631#(<= 0 max_~i~0) [2019-10-07 15:24:59,372 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:59,372 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:59,372 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 108#(or (exists ((v_prenex_1165 Int) (v_max_~ret~0_BEFORE_RETURN_157 Int)) (or (and (<= (mod v_prenex_1165 4294967296) 2147483647) (= |main_#t~ret6| (mod v_prenex_1165 4294967296)) (not (< main_~i~1 40))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (not (< main_~i~1 40)) (= |main_#t~ret6| (+ (mod v_max_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296)))))) (exists ((v_prenex_1166 Int) (v_max_~ret~0_BEFORE_RETURN_158 Int)) (or (and (<= (mod v_prenex_1166 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_1166 4294967296) |main_#t~ret6|)) (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 40)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)))))) [2019-10-07 15:24:59,372 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 645#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:24:59,372 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 368#true [2019-10-07 15:24:59,373 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:24:59,373 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 301#true [2019-10-07 15:24:59,373 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 589#true [2019-10-07 15:24:59,373 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 575#true [2019-10-07 15:24:59,373 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 548#true [2019-10-07 15:24:59,373 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:24:59,374 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 580#(exists ((v_prenex_1166 Int) (v_prenex_1165 Int) (v_max_~ret~0_BEFORE_RETURN_157 Int) (v_max_~ret~0_BEFORE_RETURN_158 Int)) (or (and (= main_~ret~1 (mod v_prenex_1166 4294967296)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_prenex_1165 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_1165 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:24:59,374 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:24:59,739 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:24:59,740 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 27 [2019-10-07 15:24:59,741 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-10-07 15:24:59,742 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-10-07 15:24:59,742 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=641, Unknown=0, NotChecked=0, Total=756 [2019-10-07 15:24:59,742 INFO L87 Difference]: Start difference. First operand 67 states and 71 transitions. Second operand 28 states. [2019-10-07 15:25:02,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:02,364 INFO L93 Difference]: Finished difference Result 94 states and 110 transitions. [2019-10-07 15:25:02,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-10-07 15:25:02,365 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 80 [2019-10-07 15:25:02,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:02,366 INFO L225 Difference]: With dead ends: 94 [2019-10-07 15:25:02,366 INFO L226 Difference]: Without dead ends: 74 [2019-10-07 15:25:02,368 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 270 GetRequests, 221 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 581 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=409, Invalid=2141, Unknown=0, NotChecked=0, Total=2550 [2019-10-07 15:25:02,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2019-10-07 15:25:02,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 74. [2019-10-07 15:25:02,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2019-10-07 15:25:02,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 78 transitions. [2019-10-07 15:25:02,379 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 78 transitions. Word has length 80 [2019-10-07 15:25:02,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:02,379 INFO L462 AbstractCegarLoop]: Abstraction has 74 states and 78 transitions. [2019-10-07 15:25:02,380 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-10-07 15:25:02,380 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 78 transitions. [2019-10-07 15:25:02,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2019-10-07 15:25:02,381 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:02,381 INFO L385 BasicCegarLoop]: trace histogram [40, 30, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:02,585 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:02,586 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:02,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:02,586 INFO L82 PathProgramCache]: Analyzing trace with hash 1446406339, now seen corresponding path program 8 times [2019-10-07 15:25:02,587 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:02,587 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:02,587 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:02,587 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:02,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:02,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:02,815 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 122 proven. 177 refuted. 0 times theorem prover too weak. 1070 trivial. 0 not checked. [2019-10-07 15:25:02,815 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:02,815 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:02,815 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:03,089 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-10-07 15:25:03,090 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:25:03,091 INFO L256 TraceCheckSpWp]: Trace formula consists of 215 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:25:03,094 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:03,169 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 246 proven. 15 refuted. 0 times theorem prover too weak. 1108 trivial. 0 not checked. [2019-10-07 15:25:03,169 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:03,324 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 1354 trivial. 0 not checked. [2019-10-07 15:25:03,324 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:03,325 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:03,326 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:03,326 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:03,326 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:03,327 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:03,344 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:04,452 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:25:04,474 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:04,476 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:04,476 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:04,476 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 624#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:04,477 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 620#(and (not (< max_~i~0 40)) (<= 40 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:25:04,477 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 467#true [2019-10-07 15:25:04,477 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 222#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_max_~ret~0_BEFORE_RETURN_187 Int) (v_max_~ret~0_BEFORE_RETURN_188 Int)) (or (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_188 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (not (= main_~ret~1 main_~ret5~0)) (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_max_~ret~0_BEFORE_RETURN_187 Int) (v_max_~ret~0_BEFORE_RETURN_188 Int)) (or (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_188 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:25:04,477 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 510#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:25:04,477 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 615#(<= 0 max_~i~0) [2019-10-07 15:25:04,478 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:04,478 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:04,478 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 108#(or (exists ((v_max_~ret~0_BEFORE_RETURN_184 Int) (v_prenex_1360 Int)) (or (and (not (< main_~i~1 40)) (= |main_#t~ret6| (+ (mod v_prenex_1360 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1360 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_184 4294967296) |main_#t~ret6|)))) (exists ((v_prenex_1359 Int) (v_max_~ret~0_BEFORE_RETURN_183 Int)) (or (and (not (<= (mod v_prenex_1359 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_prenex_1359 4294967296) (- 4294967296))) (not (< main_~i~1 40))) (and (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_183 4294967296) |main_#t~ret6|))))) [2019-10-07 15:25:04,478 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 368#true [2019-10-07 15:25:04,478 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 629#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:04,478 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:04,479 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 301#true [2019-10-07 15:25:04,479 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 589#true [2019-10-07 15:25:04,479 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 575#true [2019-10-07 15:25:04,479 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 548#true [2019-10-07 15:25:04,479 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:25:04,479 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 580#(exists ((v_prenex_1359 Int) (v_max_~ret~0_BEFORE_RETURN_183 Int) (v_max_~ret~0_BEFORE_RETURN_184 Int) (v_prenex_1360 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_1360 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_1359 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (+ (mod v_prenex_1359 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_183 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_184 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:25:04,480 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:04,864 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:04,864 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 8, 8, 11] total 35 [2019-10-07 15:25:04,866 INFO L442 AbstractCegarLoop]: Interpolant automaton has 36 states [2019-10-07 15:25:04,866 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2019-10-07 15:25:04,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=198, Invalid=1062, Unknown=0, NotChecked=0, Total=1260 [2019-10-07 15:25:04,867 INFO L87 Difference]: Start difference. First operand 74 states and 78 transitions. Second operand 36 states. [2019-10-07 15:25:08,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:08,567 INFO L93 Difference]: Finished difference Result 109 states and 126 transitions. [2019-10-07 15:25:08,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-10-07 15:25:08,568 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 99 [2019-10-07 15:25:08,568 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:08,569 INFO L225 Difference]: With dead ends: 109 [2019-10-07 15:25:08,569 INFO L226 Difference]: Without dead ends: 82 [2019-10-07 15:25:08,571 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 341 GetRequests, 276 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1030 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=676, Invalid=3746, Unknown=0, NotChecked=0, Total=4422 [2019-10-07 15:25:08,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2019-10-07 15:25:08,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 82. [2019-10-07 15:25:08,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2019-10-07 15:25:08,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 86 transitions. [2019-10-07 15:25:08,580 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 86 transitions. Word has length 99 [2019-10-07 15:25:08,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:08,580 INFO L462 AbstractCegarLoop]: Abstraction has 82 states and 86 transitions. [2019-10-07 15:25:08,580 INFO L463 AbstractCegarLoop]: Interpolant automaton has 36 states. [2019-10-07 15:25:08,581 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 86 transitions. [2019-10-07 15:25:08,582 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2019-10-07 15:25:08,582 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:08,582 INFO L385 BasicCegarLoop]: trace histogram [40, 33, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:08,786 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:08,787 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:08,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:08,787 INFO L82 PathProgramCache]: Analyzing trace with hash 1688017699, now seen corresponding path program 9 times [2019-10-07 15:25:08,788 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:08,788 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:08,788 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:08,789 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:08,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:08,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:08,982 INFO L134 CoverageAnalysis]: Checked inductivity of 1534 backedges. 145 proven. 211 refuted. 0 times theorem prover too weak. 1178 trivial. 0 not checked. [2019-10-07 15:25:08,983 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:08,983 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:08,984 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:09,281 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:25:09,281 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:25:09,284 INFO L256 TraceCheckSpWp]: Trace formula consists of 537 conjuncts, 13 conjunts are in the unsatisfiable core [2019-10-07 15:25:09,289 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:09,312 INFO L134 CoverageAnalysis]: Checked inductivity of 1534 backedges. 290 proven. 66 refuted. 0 times theorem prover too weak. 1178 trivial. 0 not checked. [2019-10-07 15:25:09,312 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:09,590 INFO L134 CoverageAnalysis]: Checked inductivity of 1534 backedges. 0 proven. 356 refuted. 0 times theorem prover too weak. 1178 trivial. 0 not checked. [2019-10-07 15:25:09,591 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:09,600 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:09,600 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:09,601 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:09,601 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:09,602 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:09,648 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:10,735 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:25:10,759 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:10,764 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:10,764 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:10,764 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 640#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:10,764 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 636#(and (not (< max_~i~0 40)) (<= 40 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:25:10,765 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 467#true [2019-10-07 15:25:10,765 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 222#(or (and (exists ((v_max_~ret~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int) (v_max_~ret~0_BEFORE_RETURN_213 Int)) (or (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_214 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1582 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_213 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int) (v_max_~ret~0_BEFORE_RETURN_213 Int)) (or (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_214 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1582 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_213 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:25:10,765 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 510#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:25:10,765 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 631#(<= 0 max_~i~0) [2019-10-07 15:25:10,765 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:10,765 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:25:10,766 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 108#(or (exists ((v_prenex_1553 Int) (v_max_~ret~0_BEFORE_RETURN_209 Int)) (or (and (= (mod v_prenex_1553 4294967296) |main_#t~ret6|) (not (< main_~i~1 40)) (<= (mod v_prenex_1553 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647))))) (exists ((v_prenex_1554 Int) (v_max_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (< main_~i~1 40)) (= (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296) |main_#t~ret6|) (<= (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (= |main_#t~ret6| (+ (mod v_prenex_1554 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)))))) [2019-10-07 15:25:10,766 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 368#true [2019-10-07 15:25:10,766 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 645#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:10,766 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:10,766 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 301#true [2019-10-07 15:25:10,766 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 589#true [2019-10-07 15:25:10,766 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 575#true [2019-10-07 15:25:10,767 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 548#true [2019-10-07 15:25:10,767 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:25:10,767 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 580#(exists ((v_prenex_1554 Int) (v_prenex_1553 Int) (v_max_~ret~0_BEFORE_RETURN_209 Int) (v_max_~ret~0_BEFORE_RETURN_210 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_1553 4294967296)) (<= (mod v_prenex_1553 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:25:10,767 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:11,096 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:11,096 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 11] total 37 [2019-10-07 15:25:11,098 INFO L442 AbstractCegarLoop]: Interpolant automaton has 38 states [2019-10-07 15:25:11,098 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2019-10-07 15:25:11,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=381, Invalid=1025, Unknown=0, NotChecked=0, Total=1406 [2019-10-07 15:25:11,099 INFO L87 Difference]: Start difference. First operand 82 states and 86 transitions. Second operand 38 states. [2019-10-07 15:25:12,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:12,878 INFO L93 Difference]: Finished difference Result 130 states and 152 transitions. [2019-10-07 15:25:12,878 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-10-07 15:25:12,878 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 109 [2019-10-07 15:25:12,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:12,880 INFO L225 Difference]: With dead ends: 130 [2019-10-07 15:25:12,880 INFO L226 Difference]: Without dead ends: 95 [2019-10-07 15:25:12,882 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 373 GetRequests, 305 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1163 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1228, Invalid=3602, Unknown=0, NotChecked=0, Total=4830 [2019-10-07 15:25:12,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2019-10-07 15:25:12,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2019-10-07 15:25:12,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2019-10-07 15:25:12,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 99 transitions. [2019-10-07 15:25:12,893 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 99 transitions. Word has length 109 [2019-10-07 15:25:12,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:12,894 INFO L462 AbstractCegarLoop]: Abstraction has 95 states and 99 transitions. [2019-10-07 15:25:12,894 INFO L463 AbstractCegarLoop]: Interpolant automaton has 38 states. [2019-10-07 15:25:12,894 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 99 transitions. [2019-10-07 15:25:12,895 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2019-10-07 15:25:12,896 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:12,896 INFO L385 BasicCegarLoop]: trace histogram [72, 40, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:13,097 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:13,099 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:13,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:13,099 INFO L82 PathProgramCache]: Analyzing trace with hash 202252269, now seen corresponding path program 10 times [2019-10-07 15:25:13,100 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:13,100 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:13,100 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:13,100 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:13,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:13,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:13,703 INFO L134 CoverageAnalysis]: Checked inductivity of 3679 backedges. 1252 proven. 300 refuted. 0 times theorem prover too weak. 2127 trivial. 0 not checked. [2019-10-07 15:25:13,704 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:13,704 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:13,704 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:14,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:14,050 INFO L256 TraceCheckSpWp]: Trace formula consists of 693 conjuncts, 26 conjunts are in the unsatisfiable core [2019-10-07 15:25:14,054 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:14,106 INFO L134 CoverageAnalysis]: Checked inductivity of 3679 backedges. 1252 proven. 300 refuted. 0 times theorem prover too weak. 2127 trivial. 0 not checked. [2019-10-07 15:25:14,106 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:14,649 INFO L134 CoverageAnalysis]: Checked inductivity of 3679 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 2127 trivial. 0 not checked. [2019-10-07 15:25:14,649 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:14,651 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:14,651 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:14,651 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:14,651 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:14,652 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:14,665 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:15,810 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:25:15,827 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:15,830 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:15,830 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:15,831 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 640#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:15,831 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 636#(and (not (< max_~i~0 40)) (<= 40 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:25:15,831 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 467#true [2019-10-07 15:25:15,831 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 222#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1776 Int) (v_max_~ret~0_BEFORE_RETURN_239 Int) (v_prenex_1775 Int) (v_max_~ret~0_BEFORE_RETURN_240 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_239 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_239 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1776 4294967296) 2147483647)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1776 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_240 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_240 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_1775 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1775 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_prenex_1776 Int) (v_max_~ret~0_BEFORE_RETURN_239 Int) (v_prenex_1775 Int) (v_max_~ret~0_BEFORE_RETURN_240 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_239 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_239 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1776 4294967296) 2147483647)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1776 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_240 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_240 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_1775 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1775 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:25:15,831 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 510#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:25:15,831 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 631#(<= 0 max_~i~0) [2019-10-07 15:25:15,831 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:15,831 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:15,832 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 108#(or (exists ((v_prenex_1747 Int) (v_max_~ret~0_BEFORE_RETURN_235 Int)) (or (and (not (<= (mod v_prenex_1747 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod v_prenex_1747 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (= (mod v_max_~ret~0_BEFORE_RETURN_235 4294967296) |main_#t~ret6|) (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_235 4294967296) 2147483647)))) (exists ((v_max_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int)) (or (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_236 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_236 4294967296) 2147483647)) (not (< main_~i~1 40))) (and (not (< main_~i~1 40)) (<= (mod v_prenex_1748 4294967296) 2147483647) (= (mod v_prenex_1748 4294967296) |main_#t~ret6|))))) [2019-10-07 15:25:15,832 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 368#true [2019-10-07 15:25:15,832 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 645#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:15,832 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:15,832 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 301#true [2019-10-07 15:25:15,832 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 589#true [2019-10-07 15:25:15,832 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 575#true [2019-10-07 15:25:15,832 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 548#true [2019-10-07 15:25:15,832 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:25:15,833 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 580#(exists ((v_max_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int) (v_prenex_1747 Int) (v_max_~ret~0_BEFORE_RETURN_235 Int)) (or (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_236 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_236 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (= (mod v_prenex_1748 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1748 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_max_~ret~0_BEFORE_RETURN_235 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_235 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_1747 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_prenex_1747 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:25:15,833 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:16,275 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:16,275 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 11] total 53 [2019-10-07 15:25:16,276 INFO L442 AbstractCegarLoop]: Interpolant automaton has 54 states [2019-10-07 15:25:16,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2019-10-07 15:25:16,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=933, Invalid=1929, Unknown=0, NotChecked=0, Total=2862 [2019-10-07 15:25:16,278 INFO L87 Difference]: Start difference. First operand 95 states and 99 transitions. Second operand 54 states. [2019-10-07 15:25:21,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:21,428 INFO L93 Difference]: Finished difference Result 159 states and 184 transitions. [2019-10-07 15:25:21,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-10-07 15:25:21,428 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 148 [2019-10-07 15:25:21,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:21,430 INFO L225 Difference]: With dead ends: 159 [2019-10-07 15:25:21,430 INFO L226 Difference]: Without dead ends: 111 [2019-10-07 15:25:21,434 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 518 GetRequests, 408 SyntacticMatches, 10 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2343 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=2948, Invalid=7354, Unknown=0, NotChecked=0, Total=10302 [2019-10-07 15:25:21,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2019-10-07 15:25:21,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2019-10-07 15:25:21,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2019-10-07 15:25:21,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 115 transitions. [2019-10-07 15:25:21,446 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 115 transitions. Word has length 148 [2019-10-07 15:25:21,446 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:21,447 INFO L462 AbstractCegarLoop]: Abstraction has 111 states and 115 transitions. [2019-10-07 15:25:21,447 INFO L463 AbstractCegarLoop]: Interpolant automaton has 54 states. [2019-10-07 15:25:21,447 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 115 transitions. [2019-10-07 15:25:21,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 197 [2019-10-07 15:25:21,449 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:21,449 INFO L385 BasicCegarLoop]: trace histogram [120, 40, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:21,654 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:21,655 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:21,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:21,655 INFO L82 PathProgramCache]: Analyzing trace with hash -169797139, now seen corresponding path program 11 times [2019-10-07 15:25:21,656 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:21,656 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:21,656 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:21,656 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:21,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:22,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:23,006 INFO L134 CoverageAnalysis]: Checked inductivity of 8407 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:25:23,007 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:23,007 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:23,007 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:23,556 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2019-10-07 15:25:23,557 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:25:23,560 INFO L256 TraceCheckSpWp]: Trace formula consists of 327 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:25:23,564 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:23,610 INFO L134 CoverageAnalysis]: Checked inductivity of 8407 backedges. 3366 proven. 78 refuted. 0 times theorem prover too weak. 4963 trivial. 0 not checked. [2019-10-07 15:25:23,610 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:23,850 INFO L134 CoverageAnalysis]: Checked inductivity of 8407 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:25:23,851 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:23,852 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:23,852 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:23,852 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:23,852 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:23,852 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:23,864 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:24,989 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:25:25,002 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:25,003 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:25,003 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:25,004 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 640#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:25,004 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 636#(and (not (< max_~i~0 40)) (<= 40 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:25:25,004 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:25:25,004 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1970 Int) (v_max_~ret~0_BEFORE_RETURN_265 Int) (v_prenex_1969 Int) (v_max_~ret~0_BEFORE_RETURN_266 Int)) (or (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_265 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_265 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_266 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_266 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_prenex_1969 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1969 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_prenex_1970 Int) (v_max_~ret~0_BEFORE_RETURN_265 Int) (v_prenex_1969 Int) (v_max_~ret~0_BEFORE_RETURN_266 Int)) (or (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_265 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_265 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_266 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_266 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_prenex_1969 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1969 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:25:25,004 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:25:25,004 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 631#(<= 0 max_~i~0) [2019-10-07 15:25:25,004 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:25,005 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:25,005 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_1941 Int) (v_max_~ret~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 40)) (= (mod v_prenex_1941 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1941 4294967296) 2147483647)) (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_261 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 40)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647))))) (exists ((v_prenex_1942 Int) (v_max_~ret~0_BEFORE_RETURN_262 Int)) (or (and (not (< main_~i~1 40)) (= (mod v_max_~ret~0_BEFORE_RETURN_262 4294967296) |main_#t~ret6|) (<= (mod v_max_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (= (+ (mod v_prenex_1942 4294967296) (- 4294967296)) |main_#t~ret6|))))) [2019-10-07 15:25:25,005 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 645#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:25,005 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:25:25,005 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:25,005 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:25:25,005 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:25:25,006 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:25:25,006 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:25:25,006 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:25:25,007 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(or (exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_max_~ret~0_BEFORE_RETURN_261 Int) (v_max_~ret~0_BEFORE_RETURN_262 Int)) (or (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_262 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_261 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_1941 4294967296)) (<= (mod v_prenex_1941 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_1942 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_max_~ret~0_BEFORE_RETURN_261 Int) (v_max_~ret~0_BEFORE_RETURN_262 Int)) (or (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_262 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_1941 4294967296)) (<= (mod v_prenex_1941 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_261 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_1942 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:25:25,007 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:25,344 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:25,344 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-07 15:25:25,345 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-07 15:25:25,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-07 15:25:25,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:25:25,347 INFO L87 Difference]: Start difference. First operand 111 states and 115 transitions. Second operand 40 states. [2019-10-07 15:25:28,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:28,799 INFO L93 Difference]: Finished difference Result 173 states and 191 transitions. [2019-10-07 15:25:28,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-07 15:25:28,800 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 196 [2019-10-07 15:25:28,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:28,802 INFO L225 Difference]: With dead ends: 173 [2019-10-07 15:25:28,802 INFO L226 Difference]: Without dead ends: 125 [2019-10-07 15:25:28,804 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 637 GetRequests, 565 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1286 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=1296, Invalid=4106, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:25:28,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2019-10-07 15:25:28,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 125. [2019-10-07 15:25:28,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2019-10-07 15:25:28,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 129 transitions. [2019-10-07 15:25:28,817 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 129 transitions. Word has length 196 [2019-10-07 15:25:28,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:28,818 INFO L462 AbstractCegarLoop]: Abstraction has 125 states and 129 transitions. [2019-10-07 15:25:28,818 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-07 15:25:28,818 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 129 transitions. [2019-10-07 15:25:28,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 211 [2019-10-07 15:25:28,820 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:28,820 INFO L385 BasicCegarLoop]: trace histogram [120, 40, 26, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:29,025 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:29,026 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:29,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:29,027 INFO L82 PathProgramCache]: Analyzing trace with hash 2105068845, now seen corresponding path program 12 times [2019-10-07 15:25:29,027 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:29,027 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:29,028 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:29,028 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:29,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:29,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:29,862 INFO L134 CoverageAnalysis]: Checked inductivity of 8680 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:25:29,862 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:29,862 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:29,862 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:30,291 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:25:30,291 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:25:30,294 INFO L256 TraceCheckSpWp]: Trace formula consists of 941 conjuncts, 28 conjunts are in the unsatisfiable core [2019-10-07 15:25:30,300 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:30,328 INFO L134 CoverageAnalysis]: Checked inductivity of 8680 backedges. 3366 proven. 351 refuted. 0 times theorem prover too weak. 4963 trivial. 0 not checked. [2019-10-07 15:25:30,328 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:30,974 INFO L134 CoverageAnalysis]: Checked inductivity of 8680 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:25:30,974 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:30,975 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:30,975 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:30,976 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:30,976 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:30,976 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:30,996 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:32,096 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:25:32,117 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:32,119 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:32,119 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:32,119 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 640#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:32,119 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 636#(and (not (< max_~i~0 40)) (<= 40 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:25:32,119 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:25:32,119 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_max_~ret~0_BEFORE_RETURN_291 Int) (v_max_~ret~0_BEFORE_RETURN_292 Int) (v_prenex_2163 Int) (v_prenex_2164 Int)) (or (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_291 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_291 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_prenex_2163 4294967296)) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2163 4294967296) 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_prenex_2164 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_2164 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_292 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_292 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_291 Int) (v_max_~ret~0_BEFORE_RETURN_292 Int) (v_prenex_2163 Int) (v_prenex_2164 Int)) (or (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_291 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_291 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_prenex_2163 4294967296)) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2163 4294967296) 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_prenex_2164 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_2164 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_292 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_292 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:25:32,120 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:25:32,120 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 631#(<= 0 max_~i~0) [2019-10-07 15:25:32,120 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:32,120 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:32,120 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_2135 Int) (v_max_~ret~0_BEFORE_RETURN_287 Int)) (or (and (not (< main_~i~1 40)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_287 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_287 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (<= (mod v_prenex_2135 4294967296) 2147483647) (= |main_#t~ret6| (mod v_prenex_2135 4294967296))))) (exists ((v_prenex_2136 Int) (v_max_~ret~0_BEFORE_RETURN_288 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_288 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_288 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (= |main_#t~ret6| (mod v_prenex_2136 4294967296)) (not (< main_~i~1 40)) (<= (mod v_prenex_2136 4294967296) 2147483647))))) [2019-10-07 15:25:32,120 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 645#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:32,120 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:25:32,120 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:32,121 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:25:32,121 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:25:32,121 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:25:32,121 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:25:32,121 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:25:32,121 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_2135 Int) (v_prenex_2136 Int) (v_max_~ret~0_BEFORE_RETURN_287 Int) (v_max_~ret~0_BEFORE_RETURN_288 Int)) (or (and (= (mod v_prenex_2135 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_prenex_2135 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_288 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_288 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_287 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_287 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_2136 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_prenex_2136 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:25:32,121 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:32,615 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:32,615 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 11] total 52 [2019-10-07 15:25:32,616 INFO L442 AbstractCegarLoop]: Interpolant automaton has 53 states [2019-10-07 15:25:32,617 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2019-10-07 15:25:32,618 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=890, Invalid=1866, Unknown=0, NotChecked=0, Total=2756 [2019-10-07 15:25:32,618 INFO L87 Difference]: Start difference. First operand 125 states and 129 transitions. Second operand 53 states. [2019-10-07 15:25:35,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:35,177 INFO L93 Difference]: Finished difference Result 186 states and 203 transitions. [2019-10-07 15:25:35,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2019-10-07 15:25:35,177 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 210 [2019-10-07 15:25:35,178 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:35,179 INFO L225 Difference]: With dead ends: 186 [2019-10-07 15:25:35,179 INFO L226 Difference]: Without dead ends: 138 [2019-10-07 15:25:35,181 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 706 GetRequests, 593 SyntacticMatches, 15 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2286 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=2661, Invalid=7239, Unknown=0, NotChecked=0, Total=9900 [2019-10-07 15:25:35,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2019-10-07 15:25:35,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2019-10-07 15:25:35,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2019-10-07 15:25:35,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 142 transitions. [2019-10-07 15:25:35,192 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 142 transitions. Word has length 210 [2019-10-07 15:25:35,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:35,193 INFO L462 AbstractCegarLoop]: Abstraction has 138 states and 142 transitions. [2019-10-07 15:25:35,193 INFO L463 AbstractCegarLoop]: Interpolant automaton has 53 states. [2019-10-07 15:25:35,193 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 142 transitions. [2019-10-07 15:25:35,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 224 [2019-10-07 15:25:35,196 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:35,196 INFO L385 BasicCegarLoop]: trace histogram [120, 40, 39, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:35,401 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:35,402 INFO L410 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:35,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:35,402 INFO L82 PathProgramCache]: Analyzing trace with hash 636109251, now seen corresponding path program 13 times [2019-10-07 15:25:35,402 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:35,403 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:35,403 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:35,403 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:35,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY