java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/max60-2.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:25:23,124 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:25:23,127 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:25:23,146 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:25:23,146 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:25:23,148 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:25:23,150 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:25:23,159 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:25:23,165 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:25:23,168 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:25:23,169 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:25:23,170 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:25:23,171 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:25:23,172 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:25:23,175 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:25:23,176 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:25:23,178 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:25:23,178 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:25:23,180 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:25:23,185 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:25:23,189 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:25:23,192 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:25:23,194 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:25:23,195 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:25:23,197 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 15:25:23,208 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:25:23,209 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:25:23,210 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:25:23,211 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:25:23,243 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:25:23,245 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:25:23,247 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:25:23,247 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:25:23,247 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:25:23,247 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:25:23,247 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:25:23,248 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:25:23,248 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:25:23,248 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:25:23,249 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:25:23,249 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:25:23,250 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:25:23,250 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:25:23,250 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:25:23,250 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:25:23,250 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:25:23,251 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:25:23,251 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:25:23,251 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:25:23,251 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:25:23,251 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:25:23,252 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:25:23,252 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:25:23,252 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:25:23,253 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:25:23,253 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:25:23,254 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:25:23,254 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:25:23,564 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:25:23,585 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:25:23,589 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:25:23,590 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:25:23,591 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:25:23,592 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/max60-2.i [2019-10-07 15:25:23,665 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/9443a624d/328b442234e94681872c292e9d8e23b2/FLAG99d3f2eef [2019-10-07 15:25:24,123 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:25:24,124 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/max60-2.i [2019-10-07 15:25:24,130 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/9443a624d/328b442234e94681872c292e9d8e23b2/FLAG99d3f2eef [2019-10-07 15:25:24,561 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/9443a624d/328b442234e94681872c292e9d8e23b2 [2019-10-07 15:25:24,572 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:25:24,574 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:25:24,579 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:25:24,579 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:25:24,582 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:25:24,583 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:25:24" (1/1) ... [2019-10-07 15:25:24,586 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7d3c52bf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:25:24, skipping insertion in model container [2019-10-07 15:25:24,586 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:25:24" (1/1) ... [2019-10-07 15:25:24,595 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:25:24,615 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:25:24,842 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:25:24,851 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:25:24,874 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:25:24,890 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:25:24,891 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:25:24 WrapperNode [2019-10-07 15:25:24,891 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:25:24,892 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:25:24,892 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:25:24,892 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:25:24,986 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:25:24" (1/1) ... [2019-10-07 15:25:24,986 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:25:24" (1/1) ... [2019-10-07 15:25:24,995 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:25:24" (1/1) ... [2019-10-07 15:25:24,995 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:25:24" (1/1) ... [2019-10-07 15:25:25,003 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:25:24" (1/1) ... [2019-10-07 15:25:25,009 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:25:24" (1/1) ... [2019-10-07 15:25:25,010 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:25:24" (1/1) ... [2019-10-07 15:25:25,013 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:25:25,013 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:25:25,013 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:25:25,014 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:25:25,014 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:25:24" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:25:25,073 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:25:25,074 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:25:25,074 INFO L138 BoogieDeclarations]: Found implementation of procedure max [2019-10-07 15:25:25,074 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:25:25,074 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:25:25,074 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:25:25,074 INFO L130 BoogieDeclarations]: Found specification of procedure max [2019-10-07 15:25:25,075 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:25:25,075 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:25:25,075 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:25:25,075 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:25:25,075 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:25:25,075 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:25:25,076 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:25:25,497 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:25:25,497 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:25:25,499 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:25:25 BoogieIcfgContainer [2019-10-07 15:25:25,499 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:25:25,500 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:25:25,500 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:25:25,503 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:25:25,503 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:25:24" (1/3) ... [2019-10-07 15:25:25,504 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@443d4deb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:25:25, skipping insertion in model container [2019-10-07 15:25:25,504 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:25:24" (2/3) ... [2019-10-07 15:25:25,505 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@443d4deb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:25:25, skipping insertion in model container [2019-10-07 15:25:25,505 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:25:25" (3/3) ... [2019-10-07 15:25:25,507 INFO L109 eAbstractionObserver]: Analyzing ICFG max60-2.i [2019-10-07 15:25:25,516 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:25:25,524 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:25:25,534 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:25:25,559 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:25:25,560 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:25:25,560 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:25:25,560 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:25:25,560 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:25:25,561 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:25:25,561 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:25:25,561 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:25:25,577 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:25:25,582 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:25:25,582 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:25,583 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:25,585 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:25,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:25,590 INFO L82 PathProgramCache]: Analyzing trace with hash 855740909, now seen corresponding path program 1 times [2019-10-07 15:25:25,597 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:25,597 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:25,597 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:25,597 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:25,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:25,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:25,770 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:25:25,771 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:25,772 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:25:25,772 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:25:25,776 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:25:25,786 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:25:25,787 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:25:25,789 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:25:25,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:25,819 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:25:25,820 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:25:25,821 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:25:25,821 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:25,828 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:25:25,829 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:25:25,832 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:25:25,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:25:25,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:25:25,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:25:25,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:25:25,870 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:25:25,870 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:25,871 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:25:25,871 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:25:25,871 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:25:25,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:25:25,873 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:25,873 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:25,874 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:25,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:25,874 INFO L82 PathProgramCache]: Analyzing trace with hash -1075349738, now seen corresponding path program 1 times [2019-10-07 15:25:25,875 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:25,875 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:25,875 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:25,875 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:25,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:25,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:25,963 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:25:25,964 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:25,965 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:25,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:26,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:26,077 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:25:26,088 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:26,134 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:25:26,134 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:26,173 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:25:26,174 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:25:26,174 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:25:26,176 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:25:26,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:25:26,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:25:26,177 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:25:26,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:26,196 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:25:26,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:25:26,197 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:25:26,198 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:26,199 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:25:26,199 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:25:26,200 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:25:26,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:25:26,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:25:26,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:25:26,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:25:26,214 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:25:26,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:26,215 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:25:26,215 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:25:26,216 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:25:26,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:25:26,219 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:26,220 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:26,427 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:26,428 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:26,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:26,429 INFO L82 PathProgramCache]: Analyzing trace with hash 447698074, now seen corresponding path program 1 times [2019-10-07 15:25:26,429 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:26,430 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:26,430 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:26,430 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:26,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:26,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:26,552 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:25:26,553 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:26,553 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:25:26,553 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:25:26,555 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:25:26,555 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:25:26,555 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:25:26,556 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:25:26,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:26,571 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:25:26,571 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:25:26,571 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:25:26,572 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:26,573 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:25:26,573 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:25:26,574 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:25:26,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:25:26,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:25:26,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:25:26,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:25:26,580 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:25:26,581 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:26,582 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:25:26,582 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:25:26,582 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:25:26,583 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:25:26,583 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:26,583 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:26,584 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:26,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:26,584 INFO L82 PathProgramCache]: Analyzing trace with hash -69054062, now seen corresponding path program 1 times [2019-10-07 15:25:26,585 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:26,585 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:26,585 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:26,585 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:26,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:26,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:26,710 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:25:26,711 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:26,711 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:26,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:26,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:26,805 INFO L256 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:25:26,809 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:26,823 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:25:26,824 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:26,873 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:25:26,874 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:26,916 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:26,916 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:26,925 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:26,938 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:26,938 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:27,081 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:29,102 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:25:29,157 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:29,161 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:29,162 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:29,162 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:29,162 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_prenex_29 Int) (v_max_~ret~0_BEFORE_RETURN_5 Int) (v_prenex_30 Int) (v_max_~ret~0_BEFORE_RETURN_6 Int)) (or (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296)) (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_29 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_29 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_max_~ret~0_BEFORE_RETURN_5 Int) (v_prenex_30 Int) (v_max_~ret~0_BEFORE_RETURN_6 Int)) (or (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296)) (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_max_~ret~0_BEFORE_RETURN_5 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_29 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_29 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:25:29,163 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:25:29,163 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:25:29,163 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:25:29,163 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:25:29,164 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:29,164 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:29,164 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_2 Int) (v_max_~ret~0_BEFORE_RETURN_2 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) |main_#t~ret6|)) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60))))) (exists ((v_max_~ret~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (= (+ (mod v_prenex_1 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296)))))) [2019-10-07 15:25:29,164 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:25:29,165 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:29,165 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:29,165 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:25:29,165 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:25:29,165 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:25:29,166 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:25:29,166 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:25:29,166 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_2 Int) (v_max_~ret~0_BEFORE_RETURN_1 Int) (v_max_~ret~0_BEFORE_RETURN_2 Int) (v_prenex_1 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_2 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_1 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:25:29,166 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:29,528 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:29,528 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:25:29,531 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-07 15:25:29,531 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-07 15:25:29,532 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-07 15:25:29,533 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-07 15:25:30,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:30,813 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:25:30,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-07 15:25:30,813 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-07 15:25:30,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:30,814 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:25:30,814 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:25:30,815 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=133, Invalid=737, Unknown=0, NotChecked=0, Total=870 [2019-10-07 15:25:30,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:25:30,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:25:30,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:25:30,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:25:30,822 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:25:30,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:30,822 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:25:30,822 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-07 15:25:30,823 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:25:30,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:25:30,824 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:30,824 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:31,024 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:31,025 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:31,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:31,025 INFO L82 PathProgramCache]: Analyzing trace with hash -493974743, now seen corresponding path program 2 times [2019-10-07 15:25:31,026 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:31,026 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:31,026 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:31,026 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:31,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:31,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:31,136 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:25:31,137 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:31,137 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:31,137 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:31,216 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:25:31,217 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:25:31,222 INFO L256 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:25:31,226 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:31,261 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:25:31,262 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:31,297 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:25:31,297 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:31,301 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:31,302 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:31,302 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:31,303 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:31,303 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:31,340 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:32,903 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:25:32,938 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:32,942 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:32,942 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:32,942 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:32,943 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_224 Int) (v_max_~ret~0_BEFORE_RETURN_32 Int) (v_max_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_prenex_224 Int) (v_max_~ret~0_BEFORE_RETURN_32 Int) (v_max_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:25:32,943 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:25:32,943 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:25:32,943 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:25:32,943 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:25:32,944 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:32,944 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:32,944 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_195 Int) (v_max_~ret~0_BEFORE_RETURN_27 Int)) (or (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (= (mod v_prenex_195 4294967296) |main_#t~ret6|) (not (< main_~i~1 60)) (<= (mod v_prenex_195 4294967296) 2147483647)))) (exists ((v_prenex_196 Int) (v_max_~ret~0_BEFORE_RETURN_28 Int)) (or (and (not (<= (mod v_prenex_196 4294967296) 2147483647)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296)))))) [2019-10-07 15:25:32,944 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:25:32,945 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:32,945 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:32,945 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:25:32,945 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:25:32,945 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:25:32,946 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:25:32,946 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:25:32,946 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_196 Int) (v_prenex_195 Int) (v_max_~ret~0_BEFORE_RETURN_28 Int) (v_max_~ret~0_BEFORE_RETURN_27 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_195 4294967296) main_~ret~1) (<= (mod v_prenex_195 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296)) (<= main_~ret~1 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:25:32,946 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:33,311 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:33,311 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:25:33,312 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-07 15:25:33,313 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-07 15:25:33,313 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-07 15:25:33,313 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-07 15:25:34,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:34,308 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:25:34,309 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:25:34,309 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-07 15:25:34,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:34,310 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:25:34,310 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:25:34,311 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-07 15:25:34,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:25:34,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:25:34,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:25:34,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:25:34,318 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:25:34,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:34,318 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:25:34,319 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-07 15:25:34,319 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:25:34,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:25:34,320 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:34,320 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:34,523 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:34,524 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:34,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:34,525 INFO L82 PathProgramCache]: Analyzing trace with hash 132820922, now seen corresponding path program 3 times [2019-10-07 15:25:34,525 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:34,525 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:34,525 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:34,526 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:34,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:34,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:34,640 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:34,641 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:34,641 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:34,641 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:34,764 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:25:34,765 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:25:34,766 INFO L256 TraceCheckSpWp]: Trace formula consists of 199 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:25:34,770 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:34,791 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:34,791 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:34,906 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:34,906 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:34,908 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:34,912 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:34,912 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:34,912 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:34,913 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:34,932 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:36,260 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:25:36,291 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:36,295 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:36,295 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:36,296 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:36,296 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_max_~ret~0_BEFORE_RETURN_58 Int)) (or (and (not (< main_~i~2 59)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_418 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_418 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647) (not (< main_~i~2 59)) (= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_prenex_417 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_417 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_max_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_max_~ret~0_BEFORE_RETURN_58 Int)) (or (and (not (< main_~i~2 59)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_418 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_418 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647) (not (< main_~i~2 59)) (= (mod v_max_~ret~0_BEFORE_RETURN_57 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_prenex_417 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_417 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:25:36,296 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:25:36,297 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:25:36,297 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:25:36,297 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:25:36,297 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:36,297 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:36,298 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_389 Int) (v_max_~ret~0_BEFORE_RETURN_53 Int)) (or (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647))) (and (not (< main_~i~1 60)) (<= (mod v_prenex_389 4294967296) 2147483647) (= |main_#t~ret6| (mod v_prenex_389 4294967296))))) (exists ((v_max_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_prenex_390 4294967296) 2147483647))) (and (not (< main_~i~1 60)) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296)) (<= (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647))))) [2019-10-07 15:25:36,298 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:25:36,298 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:36,298 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:36,298 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:25:36,298 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:25:36,299 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:25:36,299 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:25:36,299 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:25:36,299 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(or (exists ((v_prenex_389 Int) (v_max_~ret~0_BEFORE_RETURN_54 Int) (v_max_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_390 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296)) (<= (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (mod v_prenex_389 4294967296) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_prenex_389 Int) (v_max_~ret~0_BEFORE_RETURN_54 Int) (v_max_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_390 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296)) (<= (mod v_max_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (mod v_prenex_389 4294967296) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:25:36,299 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:36,809 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:36,810 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-07 15:25:36,811 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-07 15:25:36,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-07 15:25:36,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-07 15:25:36,815 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-07 15:25:38,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:38,087 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-07 15:25:38,087 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-07 15:25:38,087 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-07 15:25:38,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:38,088 INFO L225 Difference]: With dead ends: 54 [2019-10-07 15:25:38,089 INFO L226 Difference]: Without dead ends: 36 [2019-10-07 15:25:38,090 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-07 15:25:38,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-07 15:25:38,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-07 15:25:38,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-07 15:25:38,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-07 15:25:38,098 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-07 15:25:38,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:38,098 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-07 15:25:38,098 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-07 15:25:38,098 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-07 15:25:38,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-07 15:25:38,100 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:38,100 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:38,311 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:38,312 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:38,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:38,312 INFO L82 PathProgramCache]: Analyzing trace with hash 944007491, now seen corresponding path program 4 times [2019-10-07 15:25:38,313 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:38,313 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:38,313 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:38,313 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:38,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:38,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:38,509 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:38,509 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:38,509 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:38,509 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:38,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:38,645 INFO L256 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:25:38,648 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:38,663 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:38,664 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:38,912 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:38,912 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:38,913 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:38,914 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:38,914 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:38,914 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:38,915 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:38,943 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:40,118 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:25:40,140 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:40,144 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:40,144 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:40,144 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:40,145 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_max_~ret~0_BEFORE_RETURN_84 Int) (v_max_~ret~0_BEFORE_RETURN_83 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_611 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_max_~ret~0_BEFORE_RETURN_84 Int) (v_max_~ret~0_BEFORE_RETURN_83 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_611 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_84 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:25:40,145 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:25:40,145 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:25:40,145 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:25:40,146 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:25:40,146 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:40,146 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:40,146 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_584 Int) (v_max_~ret~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 60)) (<= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) |main_#t~ret6|)) (and (= (+ (mod v_prenex_584 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_prenex_584 4294967296) 2147483647))))) (exists ((v_max_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_583 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) |main_#t~ret6|) (not (< main_~i~1 60))) (and (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_prenex_583 4294967296) 2147483647)))))) [2019-10-07 15:25:40,146 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:40,147 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:25:40,147 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:40,147 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:25:40,147 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:25:40,147 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:25:40,148 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:25:40,148 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:25:40,148 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_max_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_583 Int) (v_prenex_584 Int) (v_max_~ret~0_BEFORE_RETURN_80 Int)) (or (and (= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_79 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_583 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_584 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_prenex_584 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:25:40,148 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:40,624 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:40,625 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-07 15:25:40,626 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-07 15:25:40,626 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-07 15:25:40,627 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:25:40,627 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 40 states. [2019-10-07 15:25:42,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:42,134 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-07 15:25:42,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-07 15:25:42,134 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 49 [2019-10-07 15:25:42,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:42,135 INFO L225 Difference]: With dead ends: 68 [2019-10-07 15:25:42,135 INFO L226 Difference]: Without dead ends: 50 [2019-10-07 15:25:42,139 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:25:42,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-07 15:25:42,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-07 15:25:42,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-07 15:25:42,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-07 15:25:42,147 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-07 15:25:42,147 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:42,147 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-07 15:25:42,148 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-07 15:25:42,148 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-07 15:25:42,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-07 15:25:42,149 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:42,149 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:42,351 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:42,352 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:42,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:42,353 INFO L82 PathProgramCache]: Analyzing trace with hash -1182307997, now seen corresponding path program 5 times [2019-10-07 15:25:42,353 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:42,353 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:42,354 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:42,354 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:42,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:42,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:42,782 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:25:42,782 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:42,782 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:42,782 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:42,964 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:25:42,964 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:25:42,965 INFO L256 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:25:42,968 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:43,007 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-07 15:25:43,008 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:43,051 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-07 15:25:43,051 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:43,053 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:43,053 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:43,053 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:43,053 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:43,054 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:43,081 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:44,459 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:25:44,479 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:44,481 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:44,481 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:44,481 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:44,482 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_max_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_max_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (not (< main_~i~2 59)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_max_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (not (< main_~i~2 59)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:25:44,482 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:25:44,482 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:25:44,482 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:25:44,483 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:25:44,483 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:44,483 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:25:44,483 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_max_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (not (< main_~i~1 60)) (= |main_#t~ret6| (+ (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296)))) (and (not (< main_~i~1 60)) (= |main_#t~ret6| (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647)))) (exists ((v_max_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_777 Int)) (or (and (not (< main_~i~1 60)) (<= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) |main_#t~ret6|)) (and (not (<= (mod v_prenex_777 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_prenex_777 4294967296) (- 4294967296))) (not (< main_~i~1 60)))))) [2019-10-07 15:25:44,483 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:44,483 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:25:44,484 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:44,484 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:25:44,484 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:25:44,484 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:25:44,484 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:25:44,484 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:25:44,485 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_max_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_777 Int) (v_max_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_105 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_777 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_777 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:25:44,485 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:44,958 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:44,959 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-07 15:25:44,960 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-07 15:25:44,961 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-07 15:25:44,962 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-07 15:25:44,962 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 44 states. [2019-10-07 15:25:46,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:46,947 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-07 15:25:46,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-07 15:25:46,948 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 63 [2019-10-07 15:25:46,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:46,950 INFO L225 Difference]: With dead ends: 72 [2019-10-07 15:25:46,950 INFO L226 Difference]: Without dead ends: 54 [2019-10-07 15:25:46,952 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1350 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1349, Invalid=5457, Unknown=0, NotChecked=0, Total=6806 [2019-10-07 15:25:46,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-07 15:25:46,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-07 15:25:46,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-07 15:25:46,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-07 15:25:46,961 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-07 15:25:46,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:46,961 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-07 15:25:46,961 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-07 15:25:46,961 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-07 15:25:46,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-07 15:25:46,962 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:46,962 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:47,166 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:47,166 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:47,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:47,167 INFO L82 PathProgramCache]: Analyzing trace with hash 2129164918, now seen corresponding path program 6 times [2019-10-07 15:25:47,167 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:47,167 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:47,167 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:47,168 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:47,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:47,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:47,579 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:25:47,579 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:47,579 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:47,579 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:47,802 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:25:47,802 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:25:47,805 INFO L256 TraceCheckSpWp]: Trace formula consists of 343 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-07 15:25:47,808 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:47,833 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:25:47,834 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:48,852 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:25:48,853 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:48,855 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:48,855 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:48,855 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:48,855 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:48,856 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:48,871 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:25:50,037 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:25:50,062 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:25:50,064 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:25:50,065 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:25:50,065 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:25:50,065 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_prenex_1000 Int) (v_max_~ret~0_BEFORE_RETURN_135 Int) (v_prenex_999 Int) (v_max_~ret~0_BEFORE_RETURN_136 Int)) (or (and (not (< main_~i~2 59)) (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1000 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1000 Int) (v_max_~ret~0_BEFORE_RETURN_135 Int) (v_prenex_999 Int) (v_max_~ret~0_BEFORE_RETURN_136 Int)) (or (and (not (< main_~i~2 59)) (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1000 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:25:50,065 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:25:50,066 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:25:50,066 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:25:50,066 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:25:50,066 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:50,066 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:50,067 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_972 Int) (v_max_~ret~0_BEFORE_RETURN_132 Int)) (or (and (not (<= (mod v_prenex_972 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_prenex_972 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (not (< main_~i~1 60)) (<= (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296))))) (exists ((v_prenex_971 Int) (v_max_~ret~0_BEFORE_RETURN_131 Int)) (or (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647))) (and (<= (mod v_prenex_971 4294967296) 2147483647) (= (mod v_prenex_971 4294967296) |main_#t~ret6|) (not (< main_~i~1 60)))))) [2019-10-07 15:25:50,067 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:25:50,067 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:25:50,067 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:25:50,067 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:25:50,067 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:25:50,068 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:25:50,068 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:25:50,068 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:25:50,068 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_max_~ret~0_BEFORE_RETURN_131 Int) (v_max_~ret~0_BEFORE_RETURN_132 Int)) (or (and (<= (mod v_prenex_971 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_971 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~ret~1 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (<= (mod v_max_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:25:50,068 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:25:50,604 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:25:50,605 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-07 15:25:50,606 INFO L442 AbstractCegarLoop]: Interpolant automaton has 70 states [2019-10-07 15:25:50,607 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2019-10-07 15:25:50,609 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1740, Invalid=3090, Unknown=0, NotChecked=0, Total=4830 [2019-10-07 15:25:50,609 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 70 states. [2019-10-07 15:25:55,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:25:55,903 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-07 15:25:55,903 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2019-10-07 15:25:55,903 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 67 [2019-10-07 15:25:55,904 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:25:55,905 INFO L225 Difference]: With dead ends: 104 [2019-10-07 15:25:55,905 INFO L226 Difference]: Without dead ends: 83 [2019-10-07 15:25:55,909 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3929 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=5099, Invalid=12723, Unknown=0, NotChecked=0, Total=17822 [2019-10-07 15:25:55,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-07 15:25:55,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-07 15:25:55,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-07 15:25:55,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-07 15:25:55,920 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-07 15:25:55,920 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:25:55,921 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-07 15:25:55,921 INFO L463 AbstractCegarLoop]: Interpolant automaton has 70 states. [2019-10-07 15:25:55,921 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-07 15:25:55,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-07 15:25:55,922 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:25:55,922 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:25:56,126 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:56,127 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:25:56,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:25:56,128 INFO L82 PathProgramCache]: Analyzing trace with hash -332421779, now seen corresponding path program 7 times [2019-10-07 15:25:56,128 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:25:56,128 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:56,129 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:56,129 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:25:56,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:25:56,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:57,581 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:25:57,582 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:25:57,582 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:25:57,582 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:25:57,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:25:57,853 INFO L256 TraceCheckSpWp]: Trace formula consists of 517 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-07 15:25:57,858 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:25:57,885 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:25:57,885 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:25:59,568 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:25:59,568 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:25:59,570 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:25:59,570 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:25:59,571 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:25:59,571 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:25:59,571 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:25:59,589 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:00,840 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:26:00,859 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:00,861 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:00,861 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:00,861 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:00,862 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_161 Int) (v_max_~ret~0_BEFORE_RETURN_162 Int) (v_prenex_1194 Int) (v_prenex_1193 Int)) (or (and (not (< main_~i~2 59)) (= (mod v_max_~ret~0_BEFORE_RETURN_161 4294967296) main_~ret5~0) (<= (mod v_max_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_max_~ret~0_BEFORE_RETURN_161 Int) (v_max_~ret~0_BEFORE_RETURN_162 Int) (v_prenex_1194 Int) (v_prenex_1193 Int)) (or (and (not (< main_~i~2 59)) (= (mod v_max_~ret~0_BEFORE_RETURN_161 4294967296) main_~ret5~0) (<= (mod v_max_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:26:00,862 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:26:00,862 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:26:00,862 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:26:00,862 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:26:00,863 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:00,863 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:00,863 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_1165 Int) (v_max_~ret~0_BEFORE_RETURN_157 Int)) (or (and (<= (mod v_prenex_1165 4294967296) 2147483647) (= |main_#t~ret6| (mod v_prenex_1165 4294967296)) (not (< main_~i~1 60))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_max_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296))) (not (< main_~i~1 60))))) (exists ((v_prenex_1166 Int) (v_max_~ret~0_BEFORE_RETURN_158 Int)) (or (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647))) (and (<= (mod v_prenex_1166 4294967296) 2147483647) (= (mod v_prenex_1166 4294967296) |main_#t~ret6|) (not (< main_~i~1 60)))))) [2019-10-07 15:26:00,863 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:26:00,863 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:00,863 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:00,864 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:26:00,864 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:26:00,864 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:26:00,864 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:26:00,864 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:26:00,864 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_1166 Int) (v_prenex_1165 Int) (v_max_~ret~0_BEFORE_RETURN_157 Int) (v_max_~ret~0_BEFORE_RETURN_158 Int)) (or (and (<= (mod v_prenex_1165 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_1165 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1166 4294967296)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:26:00,865 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:01,624 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:01,625 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 73 [2019-10-07 15:26:01,629 INFO L442 AbstractCegarLoop]: Interpolant automaton has 74 states [2019-10-07 15:26:01,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2019-10-07 15:26:01,632 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1982, Invalid=3420, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:26:01,632 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 74 states. [2019-10-07 15:26:07,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:26:07,632 INFO L93 Difference]: Finished difference Result 108 states and 119 transitions. [2019-10-07 15:26:07,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2019-10-07 15:26:07,632 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 96 [2019-10-07 15:26:07,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:26:07,633 INFO L225 Difference]: With dead ends: 108 [2019-10-07 15:26:07,634 INFO L226 Difference]: Without dead ends: 87 [2019-10-07 15:26:07,639 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 417 GetRequests, 223 SyntacticMatches, 54 SemanticMatches, 140 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5139 ImplicationChecksByTransitivity, 7.2s TimeCoverageRelationStatistics Valid=5817, Invalid=14205, Unknown=0, NotChecked=0, Total=20022 [2019-10-07 15:26:07,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2019-10-07 15:26:07,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2019-10-07 15:26:07,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2019-10-07 15:26:07,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 91 transitions. [2019-10-07 15:26:07,651 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 91 transitions. Word has length 96 [2019-10-07 15:26:07,651 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:26:07,651 INFO L462 AbstractCegarLoop]: Abstraction has 87 states and 91 transitions. [2019-10-07 15:26:07,651 INFO L463 AbstractCegarLoop]: Interpolant automaton has 74 states. [2019-10-07 15:26:07,651 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 91 transitions. [2019-10-07 15:26:07,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2019-10-07 15:26:07,653 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:26:07,653 INFO L385 BasicCegarLoop]: trace histogram [60, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:26:07,857 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:07,857 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:26:07,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:26:07,858 INFO L82 PathProgramCache]: Analyzing trace with hash 1935402925, now seen corresponding path program 8 times [2019-10-07 15:26:07,858 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:26:07,858 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:07,859 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:07,859 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:07,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:26:07,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:07,993 INFO L134 CoverageAnalysis]: Checked inductivity of 1951 backedges. 0 proven. 62 refuted. 0 times theorem prover too weak. 1889 trivial. 0 not checked. [2019-10-07 15:26:07,993 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:07,993 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:26:07,994 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:08,232 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:26:08,232 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:26:08,233 INFO L256 TraceCheckSpWp]: Trace formula consists of 147 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:26:08,236 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:26:08,259 INFO L134 CoverageAnalysis]: Checked inductivity of 1951 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 1889 trivial. 0 not checked. [2019-10-07 15:26:08,286 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:26:08,352 INFO L134 CoverageAnalysis]: Checked inductivity of 1951 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 1889 trivial. 0 not checked. [2019-10-07 15:26:08,352 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:26:08,354 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:26:08,354 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:26:08,354 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:26:08,354 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:26:08,355 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:26:08,372 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:09,580 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:26:09,611 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:09,613 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:09,613 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:09,613 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:09,614 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_max_~ret~0_BEFORE_RETURN_187 Int) (v_max_~ret~0_BEFORE_RETURN_188 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_prenex_1387 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_188 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret2~0))) (and (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_max_~ret~0_BEFORE_RETURN_187 Int) (v_max_~ret~0_BEFORE_RETURN_188 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_prenex_1387 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_188 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:26:09,614 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:26:09,614 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:26:09,614 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:26:09,614 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:26:09,614 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:09,614 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:09,614 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_1359 Int) (v_max_~ret~0_BEFORE_RETURN_183 Int)) (or (and (not (<= (mod v_prenex_1359 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_prenex_1359 4294967296) (- 4294967296))) (not (< main_~i~1 60))) (and (not (< main_~i~1 60)) (<= (mod v_max_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_183 4294967296) |main_#t~ret6|)))) (exists ((v_max_~ret~0_BEFORE_RETURN_184 Int) (v_prenex_1360 Int)) (or (and (not (< main_~i~1 60)) (= |main_#t~ret6| (+ (mod v_prenex_1360 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1360 4294967296) 2147483647))) (and (not (< main_~i~1 60)) (<= (mod v_max_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_184 4294967296) |main_#t~ret6|))))) [2019-10-07 15:26:09,615 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:26:09,615 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:09,615 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:09,615 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:26:09,615 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:26:09,615 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:26:09,615 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:26:09,615 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:26:09,615 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_1359 Int) (v_max_~ret~0_BEFORE_RETURN_183 Int) (v_max_~ret~0_BEFORE_RETURN_184 Int) (v_prenex_1360 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (<= (mod v_max_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_184 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_1360 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_1359 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~ret~1 (+ (mod v_prenex_1359 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_183 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:26:09,616 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:09,913 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:09,913 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 23 [2019-10-07 15:26:09,914 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-10-07 15:26:09,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-10-07 15:26:09,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=108, Invalid=444, Unknown=0, NotChecked=0, Total=552 [2019-10-07 15:26:09,915 INFO L87 Difference]: Start difference. First operand 87 states and 91 transitions. Second operand 24 states. [2019-10-07 15:26:10,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:26:10,823 INFO L93 Difference]: Finished difference Result 113 states and 128 transitions. [2019-10-07 15:26:10,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-10-07 15:26:10,823 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 100 [2019-10-07 15:26:10,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:26:10,825 INFO L225 Difference]: With dead ends: 113 [2019-10-07 15:26:10,825 INFO L226 Difference]: Without dead ends: 93 [2019-10-07 15:26:10,826 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 324 GetRequests, 284 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 428 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=353, Invalid=1369, Unknown=0, NotChecked=0, Total=1722 [2019-10-07 15:26:10,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2019-10-07 15:26:10,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2019-10-07 15:26:10,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2019-10-07 15:26:10,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 97 transitions. [2019-10-07 15:26:10,838 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 97 transitions. Word has length 100 [2019-10-07 15:26:10,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:26:10,839 INFO L462 AbstractCegarLoop]: Abstraction has 93 states and 97 transitions. [2019-10-07 15:26:10,839 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-10-07 15:26:10,839 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 97 transitions. [2019-10-07 15:26:10,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2019-10-07 15:26:10,840 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:26:10,840 INFO L385 BasicCegarLoop]: trace histogram [60, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:26:11,044 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:11,045 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:26:11,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:26:11,046 INFO L82 PathProgramCache]: Analyzing trace with hash -188408467, now seen corresponding path program 9 times [2019-10-07 15:26:11,046 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:26:11,046 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:11,046 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:11,047 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:11,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:26:11,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:11,368 INFO L134 CoverageAnalysis]: Checked inductivity of 2374 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 2364 trivial. 0 not checked. [2019-10-07 15:26:11,368 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:11,368 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:26:11,369 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:11,698 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:26:11,699 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:26:11,702 INFO L256 TraceCheckSpWp]: Trace formula consists of 613 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-07 15:26:11,705 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:26:11,832 INFO L134 CoverageAnalysis]: Checked inductivity of 2374 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 2075 trivial. 0 not checked. [2019-10-07 15:26:11,832 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:26:12,072 INFO L134 CoverageAnalysis]: Checked inductivity of 2374 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 2075 trivial. 0 not checked. [2019-10-07 15:26:12,072 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:26:12,073 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:26:12,074 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:26:12,074 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:26:12,074 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:26:12,074 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:26:12,087 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:13,407 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:26:13,433 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:13,436 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:13,436 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:13,436 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:13,437 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_max_~ret~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int) (v_max_~ret~0_BEFORE_RETURN_213 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_214 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_213 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (<= (mod v_prenex_1582 4294967296) 2147483647) (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 59)) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int) (v_max_~ret~0_BEFORE_RETURN_213 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_214 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_213 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (<= (mod v_prenex_1582 4294967296) 2147483647) (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 59)) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:26:13,437 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:26:13,437 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:26:13,437 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:26:13,437 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:26:13,437 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:13,438 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:26:13,438 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_1553 Int) (v_max_~ret~0_BEFORE_RETURN_209 Int)) (or (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647))) (and (= (mod v_prenex_1553 4294967296) |main_#t~ret6|) (not (< main_~i~1 60)) (<= (mod v_prenex_1553 4294967296) 2147483647)))) (exists ((v_prenex_1554 Int) (v_max_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (< main_~i~1 60)) (= (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296) |main_#t~ret6|) (<= (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (and (= |main_#t~ret6| (+ (mod v_prenex_1554 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (not (<= (mod v_prenex_1554 4294967296) 2147483647)))))) [2019-10-07 15:26:13,438 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:26:13,438 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:13,438 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:13,439 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:26:13,439 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:26:13,439 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:26:13,439 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:26:13,439 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:26:13,440 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_1554 Int) (v_prenex_1553 Int) (v_max_~ret~0_BEFORE_RETURN_209 Int) (v_max_~ret~0_BEFORE_RETURN_210 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_1553 4294967296)) (<= (mod v_prenex_1553 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:26:13,440 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:13,887 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:13,888 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 13, 13, 11] total 39 [2019-10-07 15:26:13,889 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-07 15:26:13,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-07 15:26:13,889 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=1235, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:26:13,889 INFO L87 Difference]: Start difference. First operand 93 states and 97 transitions. Second operand 40 states. [2019-10-07 15:26:17,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:26:17,781 INFO L93 Difference]: Finished difference Result 132 states and 154 transitions. [2019-10-07 15:26:17,781 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-10-07 15:26:17,781 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 118 [2019-10-07 15:26:17,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:26:17,783 INFO L225 Difference]: With dead ends: 132 [2019-10-07 15:26:17,783 INFO L226 Difference]: Without dead ends: 106 [2019-10-07 15:26:17,784 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 396 GetRequests, 323 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1298 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1111, Invalid=4439, Unknown=0, NotChecked=0, Total=5550 [2019-10-07 15:26:17,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2019-10-07 15:26:17,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 106. [2019-10-07 15:26:17,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2019-10-07 15:26:17,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 110 transitions. [2019-10-07 15:26:17,797 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 110 transitions. Word has length 118 [2019-10-07 15:26:17,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:26:17,797 INFO L462 AbstractCegarLoop]: Abstraction has 106 states and 110 transitions. [2019-10-07 15:26:17,797 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-07 15:26:17,797 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 110 transitions. [2019-10-07 15:26:17,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2019-10-07 15:26:17,799 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:26:17,799 INFO L385 BasicCegarLoop]: trace histogram [66, 60, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:26:18,005 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:18,006 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:26:18,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:26:18,007 INFO L82 PathProgramCache]: Analyzing trace with hash 892034819, now seen corresponding path program 10 times [2019-10-07 15:26:18,007 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:26:18,007 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:18,007 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:18,008 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:18,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:26:18,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:18,383 INFO L134 CoverageAnalysis]: Checked inductivity of 4197 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 4182 trivial. 0 not checked. [2019-10-07 15:26:18,384 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:18,384 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:26:18,384 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:18,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:18,755 INFO L256 TraceCheckSpWp]: Trace formula consists of 761 conjuncts, 24 conjunts are in the unsatisfiable core [2019-10-07 15:26:18,759 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:26:19,059 INFO L134 CoverageAnalysis]: Checked inductivity of 4197 backedges. 1060 proven. 253 refuted. 0 times theorem prover too weak. 2884 trivial. 0 not checked. [2019-10-07 15:26:19,060 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:26:19,737 INFO L134 CoverageAnalysis]: Checked inductivity of 4197 backedges. 0 proven. 1313 refuted. 0 times theorem prover too weak. 2884 trivial. 0 not checked. [2019-10-07 15:26:19,737 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:26:19,738 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:26:19,738 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:26:19,739 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:26:19,739 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:26:19,739 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:26:19,756 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:20,974 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:26:21,005 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:21,007 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:21,008 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:21,008 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:21,008 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1776 Int) (v_max_~ret~0_BEFORE_RETURN_239 Int) (v_prenex_1775 Int) (v_max_~ret~0_BEFORE_RETURN_240 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1776 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1776 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_max_~ret~0_BEFORE_RETURN_239 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_239 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_1775 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1775 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_240 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_240 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_prenex_1776 Int) (v_max_~ret~0_BEFORE_RETURN_239 Int) (v_prenex_1775 Int) (v_max_~ret~0_BEFORE_RETURN_240 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1776 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1776 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_max_~ret~0_BEFORE_RETURN_239 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_239 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_1775 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1775 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_240 4294967296) 2147483647) (= (mod v_max_~ret~0_BEFORE_RETURN_240 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:26:21,008 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:26:21,008 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:26:21,009 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:26:21,009 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:26:21,009 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:21,009 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:21,009 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_1747 Int) (v_max_~ret~0_BEFORE_RETURN_235 Int)) (or (and (= (mod v_max_~ret~0_BEFORE_RETURN_235 4294967296) |main_#t~ret6|) (<= (mod v_max_~ret~0_BEFORE_RETURN_235 4294967296) 2147483647) (not (< main_~i~1 60))) (and (not (<= (mod v_prenex_1747 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_prenex_1747 4294967296) (- 4294967296)) |main_#t~ret6|)))) (exists ((v_max_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int)) (or (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_236 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_236 4294967296) 2147483647)) (not (< main_~i~1 60))) (and (not (< main_~i~1 60)) (<= (mod v_prenex_1748 4294967296) 2147483647) (= (mod v_prenex_1748 4294967296) |main_#t~ret6|))))) [2019-10-07 15:26:21,009 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:26:21,009 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:21,010 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:21,010 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:26:21,010 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:26:21,010 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:26:21,010 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:26:21,010 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:26:21,011 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_max_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int) (v_prenex_1747 Int) (v_max_~ret~0_BEFORE_RETURN_235 Int)) (or (and (<= main_~ret~1 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_235 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_max_~ret~0_BEFORE_RETURN_235 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (= (mod v_prenex_1748 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1748 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_max_~ret~0_BEFORE_RETURN_236 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_236 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_1747 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_prenex_1747 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:26:21,011 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:21,476 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:21,477 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 25, 25, 11] total 64 [2019-10-07 15:26:21,478 INFO L442 AbstractCegarLoop]: Interpolant automaton has 65 states [2019-10-07 15:26:21,479 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2019-10-07 15:26:21,479 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1184, Invalid=2976, Unknown=0, NotChecked=0, Total=4160 [2019-10-07 15:26:21,479 INFO L87 Difference]: Start difference. First operand 106 states and 110 transitions. Second operand 65 states. [2019-10-07 15:26:25,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:26:25,676 INFO L93 Difference]: Finished difference Result 170 states and 204 transitions. [2019-10-07 15:26:25,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2019-10-07 15:26:25,676 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 155 [2019-10-07 15:26:25,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:26:25,678 INFO L225 Difference]: With dead ends: 170 [2019-10-07 15:26:25,678 INFO L226 Difference]: Without dead ends: 131 [2019-10-07 15:26:25,680 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 533 GetRequests, 410 SyntacticMatches, 0 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3411 ImplicationChecksByTransitivity, 5.1s TimeCoverageRelationStatistics Valid=3834, Invalid=11666, Unknown=0, NotChecked=0, Total=15500 [2019-10-07 15:26:25,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2019-10-07 15:26:25,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 131. [2019-10-07 15:26:25,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2019-10-07 15:26:25,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 135 transitions. [2019-10-07 15:26:25,696 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 135 transitions. Word has length 155 [2019-10-07 15:26:25,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:26:25,696 INFO L462 AbstractCegarLoop]: Abstraction has 131 states and 135 transitions. [2019-10-07 15:26:25,696 INFO L463 AbstractCegarLoop]: Interpolant automaton has 65 states. [2019-10-07 15:26:25,696 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 135 transitions. [2019-10-07 15:26:25,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 229 [2019-10-07 15:26:25,699 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:26:25,699 INFO L385 BasicCegarLoop]: trace histogram [138, 60, 6, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:26:25,904 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:25,905 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:26:25,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:26:25,906 INFO L82 PathProgramCache]: Analyzing trace with hash -1892879699, now seen corresponding path program 11 times [2019-10-07 15:26:25,906 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:26:25,906 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:25,906 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:25,907 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:25,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:26:26,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:26,517 INFO L134 CoverageAnalysis]: Checked inductivity of 11727 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 11706 trivial. 0 not checked. [2019-10-07 15:26:26,517 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:26,517 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:26:26,517 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:26,883 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-10-07 15:26:26,883 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:26:26,885 INFO L256 TraceCheckSpWp]: Trace formula consists of 219 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-07 15:26:26,891 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:26:26,933 INFO L134 CoverageAnalysis]: Checked inductivity of 11727 backedges. 4422 proven. 21 refuted. 0 times theorem prover too weak. 7284 trivial. 0 not checked. [2019-10-07 15:26:26,933 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:26:27,038 INFO L134 CoverageAnalysis]: Checked inductivity of 11727 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 11706 trivial. 0 not checked. [2019-10-07 15:26:27,038 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:26:27,039 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:26:27,040 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:26:27,040 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:26:27,040 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:26:27,040 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:26:27,053 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:28,190 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:26:28,211 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:28,213 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:28,213 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:28,214 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_prenex_1970 Int) (v_prenex_1969 Int) (v_max_~ret~0_BEFORE_RETURN_265 Int) (v_max_~ret~0_BEFORE_RETURN_266 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_prenex_1969 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1969 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_265 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_265 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_266 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_266 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1970 Int) (v_prenex_1969 Int) (v_max_~ret~0_BEFORE_RETURN_265 Int) (v_max_~ret~0_BEFORE_RETURN_266 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_prenex_1969 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1969 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_265 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_265 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_266 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_266 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:26:28,214 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:28,214 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:26:28,214 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:26:28,214 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:26:28,214 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:26:28,214 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:28,214 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:28,215 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_1941 Int) (v_max_~ret~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 60)) (= (mod v_prenex_1941 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1941 4294967296) 2147483647)) (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_261 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647)) (not (< main_~i~1 60))))) (exists ((v_prenex_1942 Int) (v_max_~ret~0_BEFORE_RETURN_262 Int)) (or (and (not (< main_~i~1 60)) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (= (+ (mod v_prenex_1942 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (not (< main_~i~1 60)) (= (mod v_max_~ret~0_BEFORE_RETURN_262 4294967296) |main_#t~ret6|) (<= (mod v_max_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647))))) [2019-10-07 15:26:28,215 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:28,215 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:26:28,215 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:28,215 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:26:28,215 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:26:28,215 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:26:28,215 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:26:28,216 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:26:28,216 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_max_~ret~0_BEFORE_RETURN_261 Int) (v_max_~ret~0_BEFORE_RETURN_262 Int)) (or (and (= (+ (mod v_prenex_1942 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647)) (not (< main_~i~1 60)) (= main_~ret~1 (+ (mod v_max_~ret~0_BEFORE_RETURN_261 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_1941 4294967296)) (<= (mod v_prenex_1941 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_262 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_max_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:26:28,216 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:28,508 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:28,509 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 11] total 27 [2019-10-07 15:26:28,510 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-10-07 15:26:28,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-10-07 15:26:28,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=591, Unknown=0, NotChecked=0, Total=756 [2019-10-07 15:26:28,510 INFO L87 Difference]: Start difference. First operand 131 states and 135 transitions. Second operand 28 states. [2019-10-07 15:26:29,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:26:29,503 INFO L93 Difference]: Finished difference Result 193 states and 205 transitions. [2019-10-07 15:26:29,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-10-07 15:26:29,503 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 228 [2019-10-07 15:26:29,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:26:29,504 INFO L225 Difference]: With dead ends: 193 [2019-10-07 15:26:29,505 INFO L226 Difference]: Without dead ends: 139 [2019-10-07 15:26:29,506 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 715 GetRequests, 667 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 611 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=486, Invalid=1964, Unknown=0, NotChecked=0, Total=2450 [2019-10-07 15:26:29,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2019-10-07 15:26:29,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2019-10-07 15:26:29,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2019-10-07 15:26:29,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 143 transitions. [2019-10-07 15:26:29,523 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 143 transitions. Word has length 228 [2019-10-07 15:26:29,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:26:29,523 INFO L462 AbstractCegarLoop]: Abstraction has 139 states and 143 transitions. [2019-10-07 15:26:29,523 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-10-07 15:26:29,523 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 143 transitions. [2019-10-07 15:26:29,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 237 [2019-10-07 15:26:29,526 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:26:29,526 INFO L385 BasicCegarLoop]: trace histogram [138, 60, 14, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:26:29,731 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:29,732 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:26:29,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:26:29,732 INFO L82 PathProgramCache]: Analyzing trace with hash -1741873747, now seen corresponding path program 12 times [2019-10-07 15:26:29,733 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:26:29,733 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:29,733 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:29,733 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:29,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:26:29,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:30,243 INFO L134 CoverageAnalysis]: Checked inductivity of 11811 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 11706 trivial. 0 not checked. [2019-10-07 15:26:30,244 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:30,244 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:26:30,244 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:30,786 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:26:30,786 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:26:30,792 INFO L256 TraceCheckSpWp]: Trace formula consists of 1085 conjuncts, 48 conjunts are in the unsatisfiable core [2019-10-07 15:26:30,799 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:26:31,923 INFO L134 CoverageAnalysis]: Checked inductivity of 11811 backedges. 4420 proven. 1081 refuted. 0 times theorem prover too weak. 6310 trivial. 0 not checked. [2019-10-07 15:26:31,923 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:26:33,462 INFO L134 CoverageAnalysis]: Checked inductivity of 11811 backedges. 0 proven. 5501 refuted. 0 times theorem prover too weak. 6310 trivial. 0 not checked. [2019-10-07 15:26:33,462 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:26:33,464 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:26:33,464 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:26:33,464 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:26:33,464 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:26:33,465 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:26:33,500 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:34,577 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:26:34,596 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:34,598 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:34,598 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:34,599 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (not (= main_~ret~1 main_~ret5~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_291 Int) (v_max_~ret~0_BEFORE_RETURN_292 Int) (v_prenex_2163 Int) (v_prenex_2164 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_292 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_292 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_2163 4294967296)) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2163 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_prenex_2164 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_2164 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_291 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_291 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_max_~ret~0_BEFORE_RETURN_291 Int) (v_max_~ret~0_BEFORE_RETURN_292 Int) (v_prenex_2163 Int) (v_prenex_2164 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_292 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_292 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_2163 4294967296)) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2163 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_prenex_2164 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_2164 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_max_~ret~0_BEFORE_RETURN_291 4294967296) (- 4294967296))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_291 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:26:34,599 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:34,599 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:26:34,599 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:26:34,599 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:26:34,599 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:26:34,600 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:34,600 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:34,600 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_2136 Int) (v_max_~ret~0_BEFORE_RETURN_288 Int)) (or (and (= |main_#t~ret6| (mod v_prenex_2136 4294967296)) (not (< main_~i~1 60)) (<= (mod v_prenex_2136 4294967296) 2147483647)) (and (not (< main_~i~1 60)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_288 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_288 4294967296) (- 4294967296)) |main_#t~ret6|)))) (exists ((v_prenex_2135 Int) (v_max_~ret~0_BEFORE_RETURN_287 Int)) (or (and (<= (mod v_prenex_2135 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret6| (mod v_prenex_2135 4294967296))) (and (not (< main_~i~1 60)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_287 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_287 4294967296) 2147483647)))))) [2019-10-07 15:26:34,600 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:34,600 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:26:34,600 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:34,600 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:26:34,600 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:26:34,600 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:26:34,601 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:26:34,601 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:26:34,601 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_2135 Int) (v_prenex_2136 Int) (v_max_~ret~0_BEFORE_RETURN_287 Int) (v_max_~ret~0_BEFORE_RETURN_288 Int)) (or (and (<= main_~ret~1 2147483647) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_288 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_288 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= (mod v_prenex_2135 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (<= (mod v_prenex_2135 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_max_~ret~0_BEFORE_RETURN_287 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_287 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_2136 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (<= (mod v_prenex_2136 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:26:34,601 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:35,343 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:35,344 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 49, 49, 11] total 87 [2019-10-07 15:26:35,345 INFO L442 AbstractCegarLoop]: Interpolant automaton has 88 states [2019-10-07 15:26:35,346 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2019-10-07 15:26:35,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2055, Invalid=5601, Unknown=0, NotChecked=0, Total=7656 [2019-10-07 15:26:35,348 INFO L87 Difference]: Start difference. First operand 139 states and 143 transitions. Second operand 88 states. [2019-10-07 15:26:42,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:26:42,161 INFO L93 Difference]: Finished difference Result 226 states and 250 transitions. [2019-10-07 15:26:42,161 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2019-10-07 15:26:42,161 INFO L78 Accepts]: Start accepts. Automaton has 88 states. Word has length 236 [2019-10-07 15:26:42,162 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:26:42,163 INFO L225 Difference]: With dead ends: 226 [2019-10-07 15:26:42,163 INFO L226 Difference]: Without dead ends: 154 [2019-10-07 15:26:42,166 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 808 GetRequests, 605 SyntacticMatches, 34 SemanticMatches, 169 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7102 ImplicationChecksByTransitivity, 9.6s TimeCoverageRelationStatistics Valid=6549, Invalid=22521, Unknown=0, NotChecked=0, Total=29070 [2019-10-07 15:26:42,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2019-10-07 15:26:42,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 154. [2019-10-07 15:26:42,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2019-10-07 15:26:42,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 158 transitions. [2019-10-07 15:26:42,180 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 158 transitions. Word has length 236 [2019-10-07 15:26:42,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:26:42,180 INFO L462 AbstractCegarLoop]: Abstraction has 154 states and 158 transitions. [2019-10-07 15:26:42,180 INFO L463 AbstractCegarLoop]: Interpolant automaton has 88 states. [2019-10-07 15:26:42,180 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 158 transitions. [2019-10-07 15:26:42,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 280 [2019-10-07 15:26:42,184 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:26:42,184 INFO L385 BasicCegarLoop]: trace histogram [180, 60, 15, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:26:42,389 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:42,389 INFO L410 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:26:42,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:26:42,390 INFO L82 PathProgramCache]: Analyzing trace with hash -1786050045, now seen corresponding path program 13 times [2019-10-07 15:26:42,390 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:26:42,391 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:42,391 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:42,391 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:42,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:26:42,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:43,192 INFO L134 CoverageAnalysis]: Checked inductivity of 18609 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:26:43,192 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:43,192 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:26:43,192 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:43,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:43,781 INFO L256 TraceCheckSpWp]: Trace formula consists of 1257 conjuncts, 17 conjunts are in the unsatisfiable core [2019-10-07 15:26:43,788 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:26:43,852 INFO L134 CoverageAnalysis]: Checked inductivity of 18609 backedges. 7446 proven. 120 refuted. 0 times theorem prover too weak. 11043 trivial. 0 not checked. [2019-10-07 15:26:43,853 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:26:44,503 INFO L134 CoverageAnalysis]: Checked inductivity of 18609 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:26:44,503 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:26:44,506 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:26:44,507 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:26:44,510 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:26:44,510 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:26:44,511 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:26:44,530 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:26:45,592 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:26:45,609 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:26:45,610 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:26:45,610 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:26:45,611 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_prenex_2358 Int) (v_max_~ret~0_BEFORE_RETURN_317 Int) (v_max_~ret~0_BEFORE_RETURN_318 Int) (v_prenex_2357 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2357 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_2357 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_318 4294967296)) (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_318 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_2358 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2358 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_max_~ret~0_BEFORE_RETURN_317 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_317 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_2358 Int) (v_max_~ret~0_BEFORE_RETURN_317 Int) (v_max_~ret~0_BEFORE_RETURN_318 Int) (v_prenex_2357 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2357 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_2357 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_318 4294967296)) (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_max_~ret~0_BEFORE_RETURN_318 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_2358 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2358 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_max_~ret~0_BEFORE_RETURN_317 4294967296) 2147483647) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_317 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:26:45,611 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:26:45,611 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:26:45,611 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:26:45,611 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:26:45,611 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:26:45,612 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:45,612 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:45,612 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_max_~ret~0_BEFORE_RETURN_313 Int) (v_prenex_2329 Int)) (or (and (= |main_#t~ret6| (+ (mod v_prenex_2329 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (not (<= (mod v_prenex_2329 4294967296) 2147483647))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_313 4294967296) 2147483647) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_313 4294967296)) (not (< main_~i~1 60))))) (exists ((v_max_~ret~0_BEFORE_RETURN_314 Int) (v_prenex_2330 Int)) (or (and (<= (mod v_prenex_2330 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_prenex_2330 4294967296) |main_#t~ret6|)) (and (not (< main_~i~1 60)) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_314 4294967296) 2147483647)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_314 4294967296) (- 4294967296)) |main_#t~ret6|))))) [2019-10-07 15:26:45,612 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:26:45,613 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:26:45,613 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:26:45,613 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:26:45,613 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:26:45,613 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:26:45,613 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:26:45,614 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:26:45,614 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_max_~ret~0_BEFORE_RETURN_313 Int) (v_max_~ret~0_BEFORE_RETURN_314 Int) (v_prenex_2330 Int) (v_prenex_2329 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_314 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_314 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_2329 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2329 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (<= (mod v_prenex_2330 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_2330 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_313 4294967296) 2147483647) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_313 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:26:45,614 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:26:45,965 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:26:45,965 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 11] total 45 [2019-10-07 15:26:45,967 INFO L442 AbstractCegarLoop]: Interpolant automaton has 46 states [2019-10-07 15:26:45,967 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2019-10-07 15:26:45,968 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=624, Invalid=1446, Unknown=0, NotChecked=0, Total=2070 [2019-10-07 15:26:45,968 INFO L87 Difference]: Start difference. First operand 154 states and 158 transitions. Second operand 46 states. [2019-10-07 15:26:49,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:26:49,868 INFO L93 Difference]: Finished difference Result 239 states and 260 transitions. [2019-10-07 15:26:49,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2019-10-07 15:26:49,868 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 279 [2019-10-07 15:26:49,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:26:49,870 INFO L225 Difference]: With dead ends: 239 [2019-10-07 15:26:49,870 INFO L226 Difference]: Without dead ends: 171 [2019-10-07 15:26:49,871 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 895 GetRequests, 811 SyntacticMatches, 0 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1690 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=1863, Invalid=5446, Unknown=1, NotChecked=0, Total=7310 [2019-10-07 15:26:49,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2019-10-07 15:26:49,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 171. [2019-10-07 15:26:49,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2019-10-07 15:26:49,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 175 transitions. [2019-10-07 15:26:49,883 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 175 transitions. Word has length 279 [2019-10-07 15:26:49,884 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:26:49,884 INFO L462 AbstractCegarLoop]: Abstraction has 171 states and 175 transitions. [2019-10-07 15:26:49,884 INFO L463 AbstractCegarLoop]: Interpolant automaton has 46 states. [2019-10-07 15:26:49,884 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 175 transitions. [2019-10-07 15:26:49,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 297 [2019-10-07 15:26:49,888 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:26:49,888 INFO L385 BasicCegarLoop]: trace histogram [180, 60, 32, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:26:50,094 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:26:50,095 INFO L410 AbstractCegarLoop]: === Iteration 17 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:26:50,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:26:50,095 INFO L82 PathProgramCache]: Analyzing trace with hash -1355716307, now seen corresponding path program 14 times [2019-10-07 15:26:50,096 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:26:50,096 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:50,096 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:50,096 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:26:50,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:26:51,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:26:52,685 INFO L134 CoverageAnalysis]: Checked inductivity of 19017 backedges. 0 proven. 528 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:26:52,685 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:26:52,686 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:26:52,686 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:27:10,960 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2019-10-07 15:27:10,961 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:27:10,972 INFO L256 TraceCheckSpWp]: Trace formula consists of 687 conjuncts, 34 conjunts are in the unsatisfiable core [2019-10-07 15:27:10,976 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:27:11,045 INFO L134 CoverageAnalysis]: Checked inductivity of 19017 backedges. 7446 proven. 528 refuted. 0 times theorem prover too weak. 11043 trivial. 0 not checked. [2019-10-07 15:27:11,045 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:27:12,504 INFO L134 CoverageAnalysis]: Checked inductivity of 19017 backedges. 0 proven. 528 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:27:12,504 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:27:12,505 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:27:12,505 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:27:12,505 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:27:12,506 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:27:12,506 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:27:12,521 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:27:13,599 INFO L199 IcfgInterpreter]: Interpreting procedure max with input of size 1 for LOIs [2019-10-07 15:27:13,616 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:27:13,619 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:27:13,619 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:27:13,619 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 238#(or (and (exists ((v_prenex_2552 Int) (v_prenex_2551 Int) (v_max_~ret~0_BEFORE_RETURN_343 Int) (v_max_~ret~0_BEFORE_RETURN_344 Int)) (or (and (not (< main_~i~2 59)) (= (mod v_prenex_2551 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2551 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_343 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_343 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2552 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2552 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_344 4294967296)) (<= main_~ret5~0 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_344 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_2552 Int) (v_prenex_2551 Int) (v_max_~ret~0_BEFORE_RETURN_343 Int) (v_max_~ret~0_BEFORE_RETURN_344 Int)) (or (and (not (< main_~i~2 59)) (= (mod v_prenex_2551 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2551 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_max_~ret~0_BEFORE_RETURN_343 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_max_~ret~0_BEFORE_RETURN_343 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2552 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2552 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_max_~ret~0_BEFORE_RETURN_344 4294967296)) (<= main_~ret5~0 2147483647) (<= (mod v_max_~ret~0_BEFORE_RETURN_344 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:27:13,620 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 656#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:27:13,620 INFO L193 IcfgInterpreter]: Reachable states at location maxEXIT satisfy 652#(and (not (< max_~i~0 60)) (<= 60 max_~i~0) (<= 0 max_~i~0) (= (ite (<= (mod max_~ret~0 4294967296) 2147483647) (mod max_~ret~0 4294967296) (+ (mod max_~ret~0 4294967296) (- 4294967296))) |max_#res|)) [2019-10-07 15:27:13,620 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 483#true [2019-10-07 15:27:13,620 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 526#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:27:13,620 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 647#(<= 0 max_~i~0) [2019-10-07 15:27:13,621 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:13,621 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:13,621 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 124#(or (exists ((v_prenex_2523 Int) (v_max_~ret~0_BEFORE_RETURN_339 Int)) (or (and (not (< main_~i~1 60)) (not (<= (mod v_prenex_2523 4294967296) 2147483647)) (= (+ (mod v_prenex_2523 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_339 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_max_~ret~0_BEFORE_RETURN_339 4294967296) |main_#t~ret6|)))) (exists ((v_prenex_2524 Int) (v_max_~ret~0_BEFORE_RETURN_340 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_340 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret6| (mod v_max_~ret~0_BEFORE_RETURN_340 4294967296))) (and (= (+ (mod v_prenex_2524 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_prenex_2524 4294967296) 2147483647)))))) [2019-10-07 15:27:13,621 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 661#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:27:13,621 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 384#true [2019-10-07 15:27:13,621 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:27:13,622 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 317#true [2019-10-07 15:27:13,622 INFO L193 IcfgInterpreter]: Reachable states at location maxENTRY satisfy 605#true [2019-10-07 15:27:13,622 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 591#true [2019-10-07 15:27:13,622 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 564#true [2019-10-07 15:27:13,622 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:27:13,622 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 596#(exists ((v_prenex_2523 Int) (v_prenex_2524 Int) (v_max_~ret~0_BEFORE_RETURN_339 Int) (v_max_~ret~0_BEFORE_RETURN_340 Int)) (or (and (<= (mod v_max_~ret~0_BEFORE_RETURN_340 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_340 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (+ (mod v_prenex_2523 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2523 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2524 4294967296) 2147483647)) (= (+ (mod v_prenex_2524 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_max_~ret~0_BEFORE_RETURN_339 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_max_~ret~0_BEFORE_RETURN_339 4294967296)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:27:13,622 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:27:14,128 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:27:14,128 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35, 11] total 72 [2019-10-07 15:27:14,130 INFO L442 AbstractCegarLoop]: Interpolant automaton has 73 states [2019-10-07 15:27:14,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2019-10-07 15:27:14,131 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1920, Invalid=3336, Unknown=0, NotChecked=0, Total=5256 [2019-10-07 15:27:14,131 INFO L87 Difference]: Start difference. First operand 171 states and 175 transitions. Second operand 73 states. [2019-10-07 15:27:18,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:27:18,494 INFO L93 Difference]: Finished difference Result 266 states and 297 transitions. [2019-10-07 15:27:18,494 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2019-10-07 15:27:18,494 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 296 [2019-10-07 15:27:18,495 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:27:18,496 INFO L225 Difference]: With dead ends: 266 [2019-10-07 15:27:18,496 INFO L226 Difference]: Without dead ends: 198 [2019-10-07 15:27:18,498 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 990 GetRequests, 845 SyntacticMatches, 7 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4129 ImplicationChecksByTransitivity, 6.4s TimeCoverageRelationStatistics Valid=5751, Invalid=13709, Unknown=0, NotChecked=0, Total=19460 [2019-10-07 15:27:18,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states. [2019-10-07 15:27:18,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2019-10-07 15:27:18,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198 states. [2019-10-07 15:27:18,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 202 transitions. [2019-10-07 15:27:18,510 INFO L78 Accepts]: Start accepts. Automaton has 198 states and 202 transitions. Word has length 296 [2019-10-07 15:27:18,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:27:18,511 INFO L462 AbstractCegarLoop]: Abstraction has 198 states and 202 transitions. [2019-10-07 15:27:18,511 INFO L463 AbstractCegarLoop]: Interpolant automaton has 73 states. [2019-10-07 15:27:18,511 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 202 transitions. [2019-10-07 15:27:18,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 324 [2019-10-07 15:27:18,513 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:27:18,513 INFO L385 BasicCegarLoop]: trace histogram [180, 60, 59, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:27:18,728 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:27:18,729 INFO L410 AbstractCegarLoop]: === Iteration 18 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:27:18,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:27:18,730 INFO L82 PathProgramCache]: Analyzing trace with hash 878710147, now seen corresponding path program 15 times [2019-10-07 15:27:18,730 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:27:18,730 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:27:18,730 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:27:18,731 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:27:18,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY