java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/sep20-1.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:36:11,740 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:36:11,743 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:36:11,763 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:36:11,763 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:36:11,766 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:36:11,768 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:36:11,779 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:36:11,784 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:36:11,787 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:36:11,789 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:36:11,790 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:36:11,790 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:36:11,792 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:36:11,795 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:36:11,796 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:36:11,798 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:36:11,799 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:36:11,801 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:36:11,806 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:36:11,810 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:36:11,813 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:36:11,816 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:36:11,816 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:36:11,819 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 15:36:11,831 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:36:11,832 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:36:11,833 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:36:11,835 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:36:11,868 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:36:11,870 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:36:11,872 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:36:11,872 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:36:11,875 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:36:11,876 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:36:11,876 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:36:11,876 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:36:11,876 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:36:11,876 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:36:11,876 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:36:11,877 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:36:11,877 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:36:11,877 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:36:11,877 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:36:11,877 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:36:11,878 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:36:11,878 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:36:11,878 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:36:11,879 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:36:11,879 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:36:11,879 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:36:11,879 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:36:11,880 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:36:11,880 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:36:11,880 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:36:11,881 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:36:11,881 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:36:11,881 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:36:12,160 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:36:12,173 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:36:12,177 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:36:12,179 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:36:12,179 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:36:12,180 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/sep20-1.i [2019-10-07 15:36:12,258 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7fdce9ccc/8099a5b8bbe948579989b957247cc9fc/FLAG06886cf50 [2019-10-07 15:36:12,749 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:36:12,749 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/sep20-1.i [2019-10-07 15:36:12,758 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7fdce9ccc/8099a5b8bbe948579989b957247cc9fc/FLAG06886cf50 [2019-10-07 15:36:13,135 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7fdce9ccc/8099a5b8bbe948579989b957247cc9fc [2019-10-07 15:36:13,148 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:36:13,150 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:36:13,151 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:36:13,152 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:36:13,159 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:36:13,160 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:36:13" (1/1) ... [2019-10-07 15:36:13,163 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@672436ec and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:13, skipping insertion in model container [2019-10-07 15:36:13,163 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:36:13" (1/1) ... [2019-10-07 15:36:13,171 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:36:13,189 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:36:13,397 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:36:13,410 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:36:13,433 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:36:13,534 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:36:13,535 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:13 WrapperNode [2019-10-07 15:36:13,535 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:36:13,536 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:36:13,536 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:36:13,537 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:36:13,552 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:13" (1/1) ... [2019-10-07 15:36:13,552 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:13" (1/1) ... [2019-10-07 15:36:13,561 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:13" (1/1) ... [2019-10-07 15:36:13,562 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:13" (1/1) ... [2019-10-07 15:36:13,571 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:13" (1/1) ... [2019-10-07 15:36:13,577 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:13" (1/1) ... [2019-10-07 15:36:13,578 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:13" (1/1) ... [2019-10-07 15:36:13,582 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:36:13,583 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:36:13,583 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:36:13,583 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:36:13,584 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:13" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:36:13,646 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:36:13,646 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:36:13,646 INFO L138 BoogieDeclarations]: Found implementation of procedure sep [2019-10-07 15:36:13,646 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:36:13,647 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:36:13,647 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:36:13,647 INFO L130 BoogieDeclarations]: Found specification of procedure sep [2019-10-07 15:36:13,647 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:36:13,647 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:36:13,648 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:36:13,648 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:36:13,648 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:36:13,648 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:36:13,648 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:36:14,063 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:36:14,064 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:36:14,065 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:36:14 BoogieIcfgContainer [2019-10-07 15:36:14,065 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:36:14,066 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:36:14,067 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:36:14,070 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:36:14,070 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:36:13" (1/3) ... [2019-10-07 15:36:14,071 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5fdb310 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:36:14, skipping insertion in model container [2019-10-07 15:36:14,072 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:13" (2/3) ... [2019-10-07 15:36:14,072 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5fdb310 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:36:14, skipping insertion in model container [2019-10-07 15:36:14,072 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:36:14" (3/3) ... [2019-10-07 15:36:14,074 INFO L109 eAbstractionObserver]: Analyzing ICFG sep20-1.i [2019-10-07 15:36:14,084 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:36:14,093 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:36:14,106 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:36:14,128 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:36:14,129 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:36:14,129 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:36:14,129 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:36:14,129 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:36:14,129 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:36:14,129 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:36:14,130 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:36:14,145 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:36:14,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:36:14,151 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:14,151 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:14,153 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:14,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:14,158 INFO L82 PathProgramCache]: Analyzing trace with hash -1553264816, now seen corresponding path program 1 times [2019-10-07 15:36:14,165 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:14,166 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:14,166 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:14,166 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:14,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:14,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:14,348 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:36:14,348 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:14,349 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:36:14,352 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:36:14,357 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:36:14,369 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:36:14,370 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:36:14,371 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:36:14,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:14,404 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:36:14,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:36:14,406 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:36:14,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:14,415 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:36:14,416 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:36:14,420 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:36:14,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:36:14,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:36:14,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:36:14,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:36:14,458 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:36:14,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:14,459 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:36:14,459 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:36:14,459 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:36:14,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:36:14,461 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:14,461 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:14,462 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:14,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:14,462 INFO L82 PathProgramCache]: Analyzing trace with hash -1274606805, now seen corresponding path program 1 times [2019-10-07 15:36:14,463 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:14,463 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:14,463 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:14,463 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:14,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:14,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:14,556 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:36:14,557 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:14,562 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:14,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:14,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:14,631 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:36:14,639 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:14,669 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:36:14,669 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:14,719 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:36:14,720 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:36:14,720 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:36:14,722 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:36:14,722 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:36:14,723 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:36:14,724 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:36:14,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:14,749 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:36:14,750 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:36:14,750 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:36:14,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:14,751 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:36:14,751 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:36:14,753 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:36:14,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:36:14,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:36:14,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:36:14,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:36:14,761 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:36:14,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:14,762 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:36:14,762 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:36:14,763 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:36:14,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:36:14,766 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:14,766 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:14,973 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:14,974 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:14,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:14,975 INFO L82 PathProgramCache]: Analyzing trace with hash -544560989, now seen corresponding path program 1 times [2019-10-07 15:36:14,975 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:14,976 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:14,976 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:14,976 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:14,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:15,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:15,109 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:36:15,110 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:15,110 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:36:15,110 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:36:15,111 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:36:15,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:36:15,112 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:36:15,112 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:36:15,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:15,123 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:36:15,123 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:36:15,124 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:36:15,124 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:15,125 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:36:15,125 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:36:15,126 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:36:15,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:36:15,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:36:15,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:36:15,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:36:15,133 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:36:15,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:15,135 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:36:15,135 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:36:15,135 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:36:15,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:36:15,137 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:15,137 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:15,137 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:15,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:15,138 INFO L82 PathProgramCache]: Analyzing trace with hash -5957836, now seen corresponding path program 1 times [2019-10-07 15:36:15,138 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:15,138 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:15,138 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:15,139 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:15,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:15,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:15,277 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:36:15,278 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:15,278 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:15,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:15,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:15,362 INFO L256 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:36:15,365 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:15,381 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:36:15,381 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:15,424 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:36:15,424 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:15,453 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:15,454 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:15,461 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:15,470 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:15,471 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:15,615 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:17,794 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:17,848 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:17,852 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:17,853 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:17,853 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:36:17,854 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_2 Int) (v_prenex_1 Int) (v_sep_~ret~0_BEFORE_RETURN_2 Int) (v_sep_~ret~0_BEFORE_RETURN_1 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_2 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_1 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~ret~1 (mod v_prenex_1 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~ret~1 (mod v_prenex_2 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_2 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:17,854 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:17,854 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:17,854 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:17,854 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:17,855 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_sep_~ret~0_BEFORE_RETURN_6 Int) (v_sep_~ret~0_BEFORE_RETURN_5 Int)) (or (and (<= (mod v_prenex_29 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_29 4294967296) main_~ret5~0) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_6 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647) (not (< main_~i~2 19))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_5 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 19)))))) (and (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_sep_~ret~0_BEFORE_RETURN_6 Int) (v_sep_~ret~0_BEFORE_RETURN_5 Int)) (or (and (<= (mod v_prenex_29 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_29 4294967296) main_~ret5~0) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_6 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647) (not (< main_~i~2 19))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_5 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:36:17,855 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:17,856 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:17,856 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:17,856 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:17,856 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:17,857 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:36:17,857 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 20 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 20))) [2019-10-07 15:36:17,857 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_1 Int) (v_sep_~ret~0_BEFORE_RETURN_1 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_1 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (not (< main_~i~1 20)) (= (mod v_prenex_1 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1 4294967296) 2147483647)))) (exists ((v_prenex_2 Int) (v_sep_~ret~0_BEFORE_RETURN_2 Int)) (or (and (not (< main_~i~1 20)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_2 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= (mod v_prenex_2 4294967296) |main_#t~ret6|) (<= (mod v_prenex_2 4294967296) 2147483647))))) [2019-10-07 15:36:17,857 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:17,858 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:17,858 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:17,858 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:18,269 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:18,269 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:36:18,271 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-07 15:36:18,272 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-07 15:36:18,273 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-07 15:36:18,273 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-07 15:36:19,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:19,437 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:36:19,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-07 15:36:19,438 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-07 15:36:19,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:19,439 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:36:19,439 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:36:19,440 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=133, Invalid=737, Unknown=0, NotChecked=0, Total=870 [2019-10-07 15:36:19,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:36:19,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:36:19,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:36:19,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:36:19,447 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:36:19,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:19,448 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:36:19,448 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-07 15:36:19,448 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:36:19,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:36:19,449 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:19,449 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:19,660 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:19,661 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:19,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:19,662 INFO L82 PathProgramCache]: Analyzing trace with hash -1961836647, now seen corresponding path program 2 times [2019-10-07 15:36:19,662 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:19,663 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:19,663 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:19,663 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:19,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:19,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:19,748 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:36:19,749 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:19,749 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:19,749 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:19,826 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:36:19,826 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:19,833 INFO L256 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:36:19,837 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:19,855 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:36:19,856 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:19,889 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:36:19,889 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:19,892 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:19,893 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:19,893 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:19,894 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:19,894 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:19,930 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:21,414 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:21,463 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:21,468 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:21,469 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:21,469 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:36:21,470 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_196 Int) (v_sep_~ret~0_BEFORE_RETURN_28 Int) (v_sep_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 20)) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_28 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_195 4294967296) main_~ret~1) (<= (mod v_prenex_195 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:21,470 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:21,470 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:21,470 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:21,471 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:21,471 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret5~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_sep_~ret~0_BEFORE_RETURN_32 Int) (v_prenex_223 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_prenex_224 4294967296))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_31 4294967296) main_~ret5~0) (<= (mod v_sep_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647))) (and (not (<= (mod v_prenex_223 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_223 4294967296) (- 4294967296))) (not (< main_~i~2 19)))))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_sep_~ret~0_BEFORE_RETURN_32 Int) (v_prenex_223 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_prenex_224 4294967296))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_31 4294967296) main_~ret5~0) (<= (mod v_sep_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647))) (and (not (<= (mod v_prenex_223 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_223 4294967296) (- 4294967296))) (not (< main_~i~2 19))))))) [2019-10-07 15:36:21,471 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:21,471 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:21,472 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:21,472 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:21,472 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:21,472 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:36:21,472 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 20 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 20))) [2019-10-07 15:36:21,473 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 20)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= (mod v_prenex_195 4294967296) |main_#t~ret6|) (<= (mod v_prenex_195 4294967296) 2147483647)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_28 Int) (v_prenex_196 Int)) (or (and (not (< main_~i~1 20)) (= (mod v_sep_~ret~0_BEFORE_RETURN_28 4294967296) |main_#t~ret6|) (<= (mod v_sep_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret6|))))) [2019-10-07 15:36:21,473 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:21,473 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:21,473 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:21,473 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:21,990 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:21,990 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:36:21,991 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-07 15:36:21,992 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-07 15:36:21,992 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-07 15:36:21,992 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-07 15:36:27,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:27,026 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:36:27,026 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:36:27,026 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-07 15:36:27,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:27,027 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:36:27,027 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:36:27,029 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 304 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=210, Invalid=1271, Unknown=1, NotChecked=0, Total=1482 [2019-10-07 15:36:27,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:36:27,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:36:27,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:36:27,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:36:27,036 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:36:27,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:27,036 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:36:27,037 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-07 15:36:27,037 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:36:27,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:36:27,038 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:27,038 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:27,246 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:27,247 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:27,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:27,248 INFO L82 PathProgramCache]: Analyzing trace with hash 1603069542, now seen corresponding path program 3 times [2019-10-07 15:36:27,248 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:27,248 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:27,249 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:27,249 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:27,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:27,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:27,389 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:36:27,389 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:27,389 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:27,390 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:27,538 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:36:27,539 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:27,540 INFO L256 TraceCheckSpWp]: Trace formula consists of 199 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:36:27,557 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:27,571 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:36:27,572 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:27,672 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:36:27,673 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:27,676 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:27,677 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:27,678 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:27,678 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:27,678 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:27,700 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:29,495 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:29,530 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:29,534 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:29,534 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:29,535 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:36:29,535 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int) (v_sep_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (mod v_prenex_389 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_sep_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int) (v_sep_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (mod v_prenex_389 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:36:29,535 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:29,536 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:29,536 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:29,536 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:29,537 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_417 Int) (v_sep_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_418 Int) (v_sep_~ret~0_BEFORE_RETURN_58 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_58 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647)) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (not (< main_~i~2 19)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296))))))) (and (not (= main_~ret~1 main_~ret5~0)) (exists ((v_prenex_417 Int) (v_sep_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_418 Int) (v_sep_~ret~0_BEFORE_RETURN_58 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_58 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647)) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (not (< main_~i~2 19)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296)))))))) [2019-10-07 15:36:29,537 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:29,537 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:29,537 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:29,538 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:29,538 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:29,538 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:36:29,538 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 20 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 20))) [2019-10-07 15:36:29,539 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int)) (or (and (not (< main_~i~1 20)) (<= (mod v_prenex_389 4294967296) 2147483647) (= (mod v_prenex_389 4294967296) |main_#t~ret6|)) (and (not (< main_~i~1 20)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296)) |main_#t~ret6|)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_prenex_390 4294967296) (- 4294967296)))) (and (= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) |main_#t~ret6|) (not (< main_~i~1 20)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647))))) [2019-10-07 15:36:29,539 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:29,539 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:29,539 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:29,539 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:29,926 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:29,926 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-07 15:36:29,927 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-07 15:36:29,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-07 15:36:29,928 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-07 15:36:29,928 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-07 15:36:35,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:35,036 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-07 15:36:35,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-07 15:36:35,036 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-07 15:36:35,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:35,037 INFO L225 Difference]: With dead ends: 54 [2019-10-07 15:36:35,038 INFO L226 Difference]: Without dead ends: 36 [2019-10-07 15:36:35,039 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 551 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=369, Invalid=1700, Unknown=1, NotChecked=0, Total=2070 [2019-10-07 15:36:35,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-07 15:36:35,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-07 15:36:35,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-07 15:36:35,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-07 15:36:35,047 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-07 15:36:35,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:35,048 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-07 15:36:35,048 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-07 15:36:35,048 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-07 15:36:35,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-07 15:36:35,049 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:35,049 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:35,253 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:35,259 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:35,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:35,259 INFO L82 PathProgramCache]: Analyzing trace with hash 1700782945, now seen corresponding path program 4 times [2019-10-07 15:36:35,259 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:35,259 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:35,259 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:35,260 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:35,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:35,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:35,483 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:36:35,483 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:35,483 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:35,484 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:35,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:35,635 INFO L256 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:36:35,642 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:35,663 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:36:35,664 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:35,873 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:36:35,873 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:35,875 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:35,875 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:35,876 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:35,876 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:35,876 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:35,905 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:37,413 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:37,474 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:37,478 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:37,479 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:37,479 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:36:37,479 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(or (exists ((v_prenex_583 Int) (v_prenex_584 Int) (v_sep_~ret~0_BEFORE_RETURN_80 Int) (v_sep_~ret~0_BEFORE_RETURN_79 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (mod v_prenex_584 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_584 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_583 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) main_~ret~1) (<= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_prenex_583 Int) (v_prenex_584 Int) (v_sep_~ret~0_BEFORE_RETURN_80 Int) (v_sep_~ret~0_BEFORE_RETURN_79 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (mod v_prenex_584 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_584 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_583 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:36:37,479 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:37,480 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:37,480 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:37,480 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:37,480 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_sep_~ret~0_BEFORE_RETURN_84 Int) (v_sep_~ret~0_BEFORE_RETURN_83 Int)) (or (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (not (<= (mod v_prenex_612 4294967296) 2147483647))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_611 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_sep_~ret~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (not (< main_~i~2 19)))))) (and (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_sep_~ret~0_BEFORE_RETURN_84 Int) (v_sep_~ret~0_BEFORE_RETURN_83 Int)) (or (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (not (<= (mod v_prenex_612 4294967296) 2147483647))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_611 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_sep_~ret~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:36:37,480 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:37,481 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:37,481 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:37,481 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:37,481 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:37,481 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:36:37,482 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 20 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 20))) [2019-10-07 15:36:37,482 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_584 Int) (v_sep_~ret~0_BEFORE_RETURN_80 Int)) (or (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 20)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= (mod v_prenex_584 4294967296) |main_#t~ret6|) (<= (mod v_prenex_584 4294967296) 2147483647)))) (exists ((v_prenex_583 Int) (v_sep_~ret~0_BEFORE_RETURN_79 Int)) (or (and (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 20)) (not (<= (mod v_prenex_583 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) |main_#t~ret6|) (<= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647))))) [2019-10-07 15:36:37,482 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:37,482 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:37,482 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:37,482 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:37,909 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:37,909 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 33 [2019-10-07 15:36:37,911 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2019-10-07 15:36:37,912 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-10-07 15:36:37,912 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=282, Invalid=840, Unknown=0, NotChecked=0, Total=1122 [2019-10-07 15:36:37,912 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 34 states. [2019-10-07 15:36:39,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:39,197 INFO L93 Difference]: Finished difference Result 62 states and 77 transitions. [2019-10-07 15:36:39,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-10-07 15:36:39,198 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 49 [2019-10-07 15:36:39,198 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:39,199 INFO L225 Difference]: With dead ends: 62 [2019-10-07 15:36:39,199 INFO L226 Difference]: Without dead ends: 44 [2019-10-07 15:36:39,201 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 192 GetRequests, 126 SyntacticMatches, 6 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 977 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=797, Invalid=2985, Unknown=0, NotChecked=0, Total=3782 [2019-10-07 15:36:39,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2019-10-07 15:36:39,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2019-10-07 15:36:39,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2019-10-07 15:36:39,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 48 transitions. [2019-10-07 15:36:39,209 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 48 transitions. Word has length 49 [2019-10-07 15:36:39,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:39,210 INFO L462 AbstractCegarLoop]: Abstraction has 44 states and 48 transitions. [2019-10-07 15:36:39,210 INFO L463 AbstractCegarLoop]: Interpolant automaton has 34 states. [2019-10-07 15:36:39,210 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 48 transitions. [2019-10-07 15:36:39,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-10-07 15:36:39,211 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:39,211 INFO L385 BasicCegarLoop]: trace histogram [20, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:39,432 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:39,433 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:39,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:39,433 INFO L82 PathProgramCache]: Analyzing trace with hash 582890977, now seen corresponding path program 5 times [2019-10-07 15:36:39,434 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:39,434 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:39,434 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:39,434 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:39,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:39,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:39,565 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 26 proven. 36 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2019-10-07 15:36:39,565 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:39,566 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:39,566 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:39,728 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:36:39,728 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:39,729 INFO L256 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:36:39,732 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:39,745 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2019-10-07 15:36:39,746 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:39,818 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2019-10-07 15:36:39,819 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:39,820 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:39,821 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:39,821 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:39,821 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:39,822 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:39,836 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:41,204 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:41,233 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:41,235 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:41,236 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:41,236 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:36:41,236 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_777 Int) (v_sep_~ret~0_BEFORE_RETURN_105 Int) (v_sep_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_105 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_777 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_777 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:41,236 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:41,237 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:41,237 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:41,237 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:41,237 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (exists ((v_sep_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_806 Int) (v_prenex_805 Int) (v_sep_~ret~0_BEFORE_RETURN_109 Int)) (or (and (= main_~ret5~0 (mod v_prenex_805 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (not (< main_~i~2 19))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_109 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_806 Int) (v_prenex_805 Int) (v_sep_~ret~0_BEFORE_RETURN_109 Int)) (or (and (= main_~ret5~0 (mod v_prenex_805 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (not (< main_~i~2 19))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_109 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))))) [2019-10-07 15:36:41,237 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:41,238 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:36:41,238 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:41,238 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:41,238 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:41,238 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:36:41,239 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 20 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 20))) [2019-10-07 15:36:41,239 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (not (< main_~i~1 20)) (= |main_#t~ret6| (+ (mod v_sep_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296)))) (and (not (< main_~i~1 20)) (= |main_#t~ret6| (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647)))) (exists ((v_prenex_777 Int) (v_sep_~ret~0_BEFORE_RETURN_105 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_777 4294967296) 2147483647)) (= (+ (mod v_prenex_777 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (not (< main_~i~1 20)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= |main_#t~ret6| (mod v_sep_~ret~0_BEFORE_RETURN_105 4294967296)))))) [2019-10-07 15:36:41,239 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:41,239 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:41,239 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:41,239 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:41,642 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:41,642 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 23 [2019-10-07 15:36:41,643 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-10-07 15:36:41,643 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-10-07 15:36:41,644 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=108, Invalid=444, Unknown=0, NotChecked=0, Total=552 [2019-10-07 15:36:41,644 INFO L87 Difference]: Start difference. First operand 44 states and 48 transitions. Second operand 24 states. [2019-10-07 15:36:42,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:42,692 INFO L93 Difference]: Finished difference Result 67 states and 82 transitions. [2019-10-07 15:36:42,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-10-07 15:36:42,692 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 57 [2019-10-07 15:36:42,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:42,693 INFO L225 Difference]: With dead ends: 67 [2019-10-07 15:36:42,694 INFO L226 Difference]: Without dead ends: 50 [2019-10-07 15:36:42,695 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 195 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 428 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=353, Invalid=1369, Unknown=0, NotChecked=0, Total=1722 [2019-10-07 15:36:42,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-07 15:36:42,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-07 15:36:42,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-07 15:36:42,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-07 15:36:42,703 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 57 [2019-10-07 15:36:42,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:42,703 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-07 15:36:42,703 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-10-07 15:36:42,704 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-07 15:36:42,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-10-07 15:36:42,705 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:42,705 INFO L385 BasicCegarLoop]: trace histogram [30, 20, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:42,909 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:42,909 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:42,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:42,910 INFO L82 PathProgramCache]: Analyzing trace with hash -971041183, now seen corresponding path program 6 times [2019-10-07 15:36:42,910 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:42,911 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:42,911 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:42,911 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:42,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:43,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:43,288 INFO L134 CoverageAnalysis]: Checked inductivity of 745 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 446 trivial. 0 not checked. [2019-10-07 15:36:43,289 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:43,289 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:43,289 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:43,501 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:36:43,501 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:43,503 INFO L256 TraceCheckSpWp]: Trace formula consists of 361 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-07 15:36:43,514 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:43,535 INFO L134 CoverageAnalysis]: Checked inductivity of 745 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 446 trivial. 0 not checked. [2019-10-07 15:36:43,535 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:43,736 INFO L134 CoverageAnalysis]: Checked inductivity of 745 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 446 trivial. 0 not checked. [2019-10-07 15:36:43,737 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:43,741 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:43,741 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:43,742 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:43,742 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:43,742 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:43,765 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:45,340 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:45,380 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:45,384 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:45,384 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:45,385 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:36:45,385 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_131 Int) (v_sep_~ret~0_BEFORE_RETURN_132 Int) (v_prenex_972 Int) (v_prenex_971 Int)) (or (and (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_131 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_972 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_972 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:45,385 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:45,386 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:45,386 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:45,386 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:45,387 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (exists ((v_sep_~ret~0_BEFORE_RETURN_135 Int) (v_sep_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_1000 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_prenex_999 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (= (+ (mod v_prenex_999 4294967296) (- 4294967296)) main_~ret5~0)) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_135 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_135 Int) (v_sep_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_1000 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_prenex_999 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (= (+ (mod v_prenex_999 4294967296) (- 4294967296)) main_~ret5~0)) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_135 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))))) [2019-10-07 15:36:45,387 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:45,387 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:45,388 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:45,388 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:45,388 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:45,388 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:36:45,389 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 20 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 20))) [2019-10-07 15:36:45,389 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_132 Int) (v_prenex_972 Int)) (or (and (= (mod v_prenex_972 4294967296) |main_#t~ret6|) (not (< main_~i~1 20)) (<= (mod v_prenex_972 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) |main_#t~ret6|)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_131 Int) (v_prenex_971 Int)) (or (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 20)) (= (+ (mod v_prenex_971 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (= |main_#t~ret6| (mod v_sep_~ret~0_BEFORE_RETURN_131 4294967296)) (not (< main_~i~1 20)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647))))) [2019-10-07 15:36:45,389 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:45,390 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:45,390 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:45,390 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:45,832 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:45,833 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 11] total 33 [2019-10-07 15:36:45,834 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2019-10-07 15:36:45,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-10-07 15:36:45,835 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=283, Invalid=839, Unknown=0, NotChecked=0, Total=1122 [2019-10-07 15:36:45,836 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 34 states. [2019-10-07 15:36:47,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:47,459 INFO L93 Difference]: Finished difference Result 83 states and 102 transitions. [2019-10-07 15:36:47,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-10-07 15:36:47,460 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 75 [2019-10-07 15:36:47,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:47,461 INFO L225 Difference]: With dead ends: 83 [2019-10-07 15:36:47,461 INFO L226 Difference]: Without dead ends: 60 [2019-10-07 15:36:47,463 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 205 SyntacticMatches, 2 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 924 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=918, Invalid=2864, Unknown=0, NotChecked=0, Total=3782 [2019-10-07 15:36:47,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2019-10-07 15:36:47,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2019-10-07 15:36:47,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2019-10-07 15:36:47,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 64 transitions. [2019-10-07 15:36:47,473 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 64 transitions. Word has length 75 [2019-10-07 15:36:47,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:47,473 INFO L462 AbstractCegarLoop]: Abstraction has 60 states and 64 transitions. [2019-10-07 15:36:47,473 INFO L463 AbstractCegarLoop]: Interpolant automaton has 34 states. [2019-10-07 15:36:47,473 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 64 transitions. [2019-10-07 15:36:47,475 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2019-10-07 15:36:47,475 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:47,475 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:47,679 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:47,680 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:47,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:47,681 INFO L82 PathProgramCache]: Analyzing trace with hash -1274945055, now seen corresponding path program 7 times [2019-10-07 15:36:47,681 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:47,681 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:47,681 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:47,682 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:47,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:47,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:48,024 INFO L134 CoverageAnalysis]: Checked inductivity of 2170 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:36:48,024 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:48,025 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:48,025 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:48,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:48,370 INFO L256 TraceCheckSpWp]: Trace formula consists of 481 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:36:48,373 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:48,392 INFO L134 CoverageAnalysis]: Checked inductivity of 2170 backedges. 886 proven. 1 refuted. 0 times theorem prover too weak. 1283 trivial. 0 not checked. [2019-10-07 15:36:48,392 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:48,425 INFO L134 CoverageAnalysis]: Checked inductivity of 2170 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:36:48,425 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:48,427 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:48,427 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:48,428 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:48,428 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:48,428 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:48,444 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:49,958 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:49,995 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:49,999 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:50,000 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:50,000 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:36:50,000 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_157 Int) (v_sep_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int) (v_prenex_1165 Int)) (or (and (not (< main_~i~1 20)) (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1165 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sep_~ret~0_BEFORE_RETURN_157 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1166 4294967296)) (not (< main_~i~1 20)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:50,001 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:50,001 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:50,001 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:50,001 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:50,002 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (exists ((v_prenex_1194 Int) (v_sep_~ret~0_BEFORE_RETURN_161 Int) (v_prenex_1193 Int) (v_sep_~ret~0_BEFORE_RETURN_162 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_161 4294967296)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (not (< main_~i~2 19))) (and (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0)))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1194 Int) (v_sep_~ret~0_BEFORE_RETURN_161 Int) (v_prenex_1193 Int) (v_sep_~ret~0_BEFORE_RETURN_162 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_161 4294967296)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (not (< main_~i~2 19))) (and (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0)))))) [2019-10-07 15:36:50,002 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:50,002 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:50,003 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:50,003 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:50,003 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:50,004 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:36:50,004 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 20 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 20))) [2019-10-07 15:36:50,004 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int)) (or (and (not (< main_~i~1 20)) (<= (mod v_prenex_1166 4294967296) 2147483647) (= (mod v_prenex_1166 4294967296) |main_#t~ret6|)) (and (not (< main_~i~1 20)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret6|)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_157 Int) (v_prenex_1165 Int)) (or (and (= (mod v_sep_~ret~0_BEFORE_RETURN_157 4294967296) |main_#t~ret6|) (<= (mod v_sep_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647) (not (< main_~i~1 20))) (and (not (< main_~i~1 20)) (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_1165 4294967296) 2147483647)))))) [2019-10-07 15:36:50,004 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:50,005 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:50,005 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:50,005 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:50,308 WARN L191 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 21 DAG size of output: 19 [2019-10-07 15:36:50,492 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:50,492 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:36:50,493 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-07 15:36:50,493 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-07 15:36:50,494 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-07 15:36:50,494 INFO L87 Difference]: Start difference. First operand 60 states and 64 transitions. Second operand 18 states. [2019-10-07 15:36:51,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:51,228 INFO L93 Difference]: Finished difference Result 91 states and 98 transitions. [2019-10-07 15:36:51,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-07 15:36:51,228 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 105 [2019-10-07 15:36:51,230 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:51,231 INFO L225 Difference]: With dead ends: 91 [2019-10-07 15:36:51,231 INFO L226 Difference]: Without dead ends: 63 [2019-10-07 15:36:51,232 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 331 GetRequests, 303 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 186 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=141, Invalid=729, Unknown=0, NotChecked=0, Total=870 [2019-10-07 15:36:51,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2019-10-07 15:36:51,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2019-10-07 15:36:51,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2019-10-07 15:36:51,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 67 transitions. [2019-10-07 15:36:51,242 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 67 transitions. Word has length 105 [2019-10-07 15:36:51,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:51,242 INFO L462 AbstractCegarLoop]: Abstraction has 63 states and 67 transitions. [2019-10-07 15:36:51,242 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-07 15:36:51,243 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 67 transitions. [2019-10-07 15:36:51,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2019-10-07 15:36:51,244 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:51,245 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:51,449 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:51,450 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:51,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:51,451 INFO L82 PathProgramCache]: Analyzing trace with hash -1410112048, now seen corresponding path program 8 times [2019-10-07 15:36:51,451 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:51,451 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:51,451 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:51,452 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:51,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:51,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:51,746 INFO L134 CoverageAnalysis]: Checked inductivity of 2179 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:36:51,746 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:51,746 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:51,747 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:52,023 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2019-10-07 15:36:52,023 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:52,025 INFO L256 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:36:52,029 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:52,050 INFO L134 CoverageAnalysis]: Checked inductivity of 2179 backedges. 886 proven. 10 refuted. 0 times theorem prover too weak. 1283 trivial. 0 not checked. [2019-10-07 15:36:52,050 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:52,121 INFO L134 CoverageAnalysis]: Checked inductivity of 2179 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:36:52,121 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:52,128 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:52,128 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:52,128 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:52,129 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:52,129 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:52,145 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:53,531 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:53,572 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:53,574 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:53,575 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:53,575 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:36:53,575 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_1359 Int) (v_prenex_1360 Int) (v_sep_~ret~0_BEFORE_RETURN_183 Int) (v_sep_~ret~0_BEFORE_RETURN_184 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_1360 4294967296)) (<= (mod v_prenex_1360 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1359 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1359 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_183 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_184 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:53,576 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:53,576 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:53,576 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:53,576 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:53,577 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_187 Int) (v_sep_~ret~0_BEFORE_RETURN_188 Int) (v_prenex_1388 Int) (v_prenex_1387 Int)) (or (and (not (<= (mod v_prenex_1387 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1387 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= (mod v_sep_~ret~0_BEFORE_RETURN_187 4294967296) main_~ret5~0) (<= (mod v_sep_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_188 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (not (< main_~i~2 19)) (<= (mod v_prenex_1388 4294967296) 2147483647))))) (and (exists ((v_sep_~ret~0_BEFORE_RETURN_187 Int) (v_sep_~ret~0_BEFORE_RETURN_188 Int) (v_prenex_1388 Int) (v_prenex_1387 Int)) (or (and (not (<= (mod v_prenex_1387 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1387 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= (mod v_sep_~ret~0_BEFORE_RETURN_187 4294967296) main_~ret5~0) (<= (mod v_sep_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_188 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (not (< main_~i~2 19)) (<= (mod v_prenex_1388 4294967296) 2147483647)))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:36:53,577 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:53,577 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:53,578 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:53,578 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:53,579 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:53,579 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:36:53,579 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 20 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 20))) [2019-10-07 15:36:53,579 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_1360 Int) (v_sep_~ret~0_BEFORE_RETURN_184 Int)) (or (and (not (< main_~i~1 20)) (= (mod v_prenex_1360 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1360 4294967296) 2147483647)) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647)) (not (< main_~i~1 20)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_184 4294967296) (- 4294967296)) |main_#t~ret6|)))) (exists ((v_prenex_1359 Int) (v_sep_~ret~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_sep_~ret~0_BEFORE_RETURN_183 4294967296) (- 4294967296)))) (and (not (< main_~i~1 20)) (= (mod v_prenex_1359 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1359 4294967296) 2147483647))))) [2019-10-07 15:36:53,580 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:53,580 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:53,580 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:53,580 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:56,011 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:56,011 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 23 [2019-10-07 15:36:56,012 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-10-07 15:36:56,013 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-10-07 15:36:56,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=444, Unknown=1, NotChecked=0, Total=552 [2019-10-07 15:36:56,013 INFO L87 Difference]: Start difference. First operand 63 states and 67 transitions. Second operand 24 states. [2019-10-07 15:36:57,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:57,571 INFO L93 Difference]: Finished difference Result 97 states and 107 transitions. [2019-10-07 15:36:57,571 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-10-07 15:36:57,571 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 108 [2019-10-07 15:36:57,572 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:57,573 INFO L225 Difference]: With dead ends: 97 [2019-10-07 15:36:57,573 INFO L226 Difference]: Without dead ends: 69 [2019-10-07 15:36:57,574 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 349 GetRequests, 309 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 426 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=312, Invalid=1409, Unknown=1, NotChecked=0, Total=1722 [2019-10-07 15:36:57,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2019-10-07 15:36:57,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2019-10-07 15:36:57,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2019-10-07 15:36:57,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 73 transitions. [2019-10-07 15:36:57,586 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 73 transitions. Word has length 108 [2019-10-07 15:36:57,587 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:57,587 INFO L462 AbstractCegarLoop]: Abstraction has 69 states and 73 transitions. [2019-10-07 15:36:57,587 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-10-07 15:36:57,587 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 73 transitions. [2019-10-07 15:36:57,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2019-10-07 15:36:57,589 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:57,589 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 10, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:57,798 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:57,799 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:57,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:57,799 INFO L82 PathProgramCache]: Analyzing trace with hash -791659472, now seen corresponding path program 9 times [2019-10-07 15:36:57,800 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:57,800 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:57,800 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:57,800 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:57,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:58,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:58,290 INFO L134 CoverageAnalysis]: Checked inductivity of 2224 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:36:58,291 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:58,291 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:58,291 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:58,609 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:36:58,609 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:58,612 INFO L256 TraceCheckSpWp]: Trace formula consists of 517 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-07 15:36:58,615 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:58,636 INFO L134 CoverageAnalysis]: Checked inductivity of 2224 backedges. 886 proven. 55 refuted. 0 times theorem prover too weak. 1283 trivial. 0 not checked. [2019-10-07 15:36:58,636 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:58,857 INFO L134 CoverageAnalysis]: Checked inductivity of 2224 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:36:58,858 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:58,859 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:58,859 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:58,860 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:58,860 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:58,860 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:58,875 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:37:00,139 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:37:00,165 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:37:00,167 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:37:00,168 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:37:00,168 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:37:00,168 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_sep_~ret~0_BEFORE_RETURN_209 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (+ (mod v_prenex_1553 4294967296) (- 4294967296))) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (not (<= (mod v_prenex_1553 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_209 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1554 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1554 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:37:00,168 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:37:00,169 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:37:00,169 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:37:00,169 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:37:00,169 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_213 Int) (v_sep_~ret~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_sep_~ret~0_BEFORE_RETURN_214 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_213 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (mod v_prenex_1581 4294967296)) (<= (mod v_prenex_1581 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)))))) (and (exists ((v_sep_~ret~0_BEFORE_RETURN_213 Int) (v_sep_~ret~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_sep_~ret~0_BEFORE_RETURN_214 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_213 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (mod v_prenex_1581 4294967296)) (<= (mod v_prenex_1581 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:37:00,169 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:00,170 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:37:00,170 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:00,170 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:37:00,170 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:37:00,170 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:37:00,170 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 20 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 20))) [2019-10-07 15:37:00,171 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_1553 Int) (v_sep_~ret~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_1553 4294967296) 2147483647)) (= (+ (mod v_prenex_1553 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (not (< main_~i~1 20)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647) (= |main_#t~ret6| (mod v_sep_~ret~0_BEFORE_RETURN_209 4294967296))))) (exists ((v_sep_~ret~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int)) (or (and (not (< main_~i~1 20)) (= (mod v_prenex_1554 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1554 4294967296) 2147483647)) (and (= |main_#t~ret6| (+ (mod v_sep_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (not (< main_~i~1 20)))))) [2019-10-07 15:37:00,171 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:37:00,171 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:37:00,171 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:37:00,171 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:37:00,563 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:37:00,563 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 11] total 32 [2019-10-07 15:37:00,565 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-10-07 15:37:00,565 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-10-07 15:37:00,566 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=260, Invalid=796, Unknown=0, NotChecked=0, Total=1056 [2019-10-07 15:37:00,566 INFO L87 Difference]: Start difference. First operand 69 states and 73 transitions. Second operand 33 states. [2019-10-07 15:37:02,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:02,042 INFO L93 Difference]: Finished difference Result 106 states and 119 transitions. [2019-10-07 15:37:02,042 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-10-07 15:37:02,042 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 114 [2019-10-07 15:37:02,043 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:02,043 INFO L225 Difference]: With dead ends: 106 [2019-10-07 15:37:02,043 INFO L226 Difference]: Without dead ends: 78 [2019-10-07 15:37:02,045 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 382 GetRequests, 321 SyntacticMatches, 3 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 864 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=771, Invalid=2769, Unknown=0, NotChecked=0, Total=3540 [2019-10-07 15:37:02,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2019-10-07 15:37:02,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 78. [2019-10-07 15:37:02,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2019-10-07 15:37:02,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 82 transitions. [2019-10-07 15:37:02,058 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 82 transitions. Word has length 114 [2019-10-07 15:37:02,058 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:02,058 INFO L462 AbstractCegarLoop]: Abstraction has 78 states and 82 transitions. [2019-10-07 15:37:02,058 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-10-07 15:37:02,058 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 82 transitions. [2019-10-07 15:37:02,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2019-10-07 15:37:02,060 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:02,060 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 19, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:02,266 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:02,267 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:02,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:02,267 INFO L82 PathProgramCache]: Analyzing trace with hash 1882262209, now seen corresponding path program 10 times [2019-10-07 15:37:02,267 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:02,268 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:02,268 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:02,268 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:02,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY