java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/sep40-1.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:36:12,413 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:36:12,416 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:36:12,428 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:36:12,428 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:36:12,429 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:36:12,431 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:36:12,432 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:36:12,434 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:36:12,435 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:36:12,436 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:36:12,437 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:36:12,437 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:36:12,438 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:36:12,439 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:36:12,440 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:36:12,441 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:36:12,442 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:36:12,443 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:36:12,448 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:36:12,450 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:36:12,451 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:36:12,453 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:36:12,454 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:36:12,458 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 15:36:12,471 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:36:12,472 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:36:12,473 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:36:12,474 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:36:12,487 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:36:12,488 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:36:12,489 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:36:12,489 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:36:12,489 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:36:12,489 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:36:12,490 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:36:12,490 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:36:12,490 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:36:12,490 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:36:12,490 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:36:12,491 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:36:12,491 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:36:12,491 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:36:12,491 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:36:12,491 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:36:12,492 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:36:12,492 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:36:12,492 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:36:12,492 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:36:12,492 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:36:12,493 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:36:12,493 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:36:12,493 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:36:12,493 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:36:12,493 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:36:12,494 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:36:12,494 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:36:12,494 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:36:12,771 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:36:12,784 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:36:12,788 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:36:12,789 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:36:12,790 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:36:12,790 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/sep40-1.i [2019-10-07 15:36:12,852 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5b2fb94be/e9dc50b6a5d841b9927c23f0940e2156/FLAG6c6fc6f1e [2019-10-07 15:36:13,318 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:36:13,319 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/sep40-1.i [2019-10-07 15:36:13,325 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5b2fb94be/e9dc50b6a5d841b9927c23f0940e2156/FLAG6c6fc6f1e [2019-10-07 15:36:13,720 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5b2fb94be/e9dc50b6a5d841b9927c23f0940e2156 [2019-10-07 15:36:13,730 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:36:13,732 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:36:13,733 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:36:13,733 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:36:13,737 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:36:13,738 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:36:13" (1/1) ... [2019-10-07 15:36:13,741 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5e90e1fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:13, skipping insertion in model container [2019-10-07 15:36:13,741 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:36:13" (1/1) ... [2019-10-07 15:36:13,748 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:36:13,766 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:36:14,029 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:36:14,042 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:36:14,085 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:36:14,244 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:36:14,244 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:14 WrapperNode [2019-10-07 15:36:14,245 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:36:14,246 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:36:14,246 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:36:14,247 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:36:14,261 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:14" (1/1) ... [2019-10-07 15:36:14,261 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:14" (1/1) ... [2019-10-07 15:36:14,284 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:14" (1/1) ... [2019-10-07 15:36:14,285 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:14" (1/1) ... [2019-10-07 15:36:14,301 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:14" (1/1) ... [2019-10-07 15:36:14,311 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:14" (1/1) ... [2019-10-07 15:36:14,313 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:14" (1/1) ... [2019-10-07 15:36:14,315 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:36:14,315 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:36:14,316 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:36:14,316 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:36:14,317 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:14" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:36:14,375 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:36:14,375 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:36:14,375 INFO L138 BoogieDeclarations]: Found implementation of procedure sep [2019-10-07 15:36:14,376 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:36:14,376 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:36:14,376 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:36:14,376 INFO L130 BoogieDeclarations]: Found specification of procedure sep [2019-10-07 15:36:14,376 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:36:14,376 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:36:14,377 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:36:14,377 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:36:14,377 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:36:14,377 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:36:14,377 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:36:14,789 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:36:14,789 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:36:14,791 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:36:14 BoogieIcfgContainer [2019-10-07 15:36:14,791 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:36:14,792 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:36:14,792 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:36:14,795 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:36:14,795 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:36:13" (1/3) ... [2019-10-07 15:36:14,796 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7324e565 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:36:14, skipping insertion in model container [2019-10-07 15:36:14,796 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:36:14" (2/3) ... [2019-10-07 15:36:14,797 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7324e565 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:36:14, skipping insertion in model container [2019-10-07 15:36:14,797 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:36:14" (3/3) ... [2019-10-07 15:36:14,799 INFO L109 eAbstractionObserver]: Analyzing ICFG sep40-1.i [2019-10-07 15:36:14,809 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:36:14,817 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:36:14,828 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:36:14,854 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:36:14,855 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:36:14,855 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:36:14,855 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:36:14,855 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:36:14,856 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:36:14,856 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:36:14,856 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:36:14,874 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:36:14,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:36:14,880 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:14,881 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:14,883 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:14,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:14,889 INFO L82 PathProgramCache]: Analyzing trace with hash -1553264816, now seen corresponding path program 1 times [2019-10-07 15:36:14,898 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:14,899 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:14,899 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:14,899 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:14,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:15,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:15,082 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:36:15,083 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:15,084 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:36:15,084 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:36:15,088 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:36:15,100 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:36:15,101 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:36:15,103 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:36:15,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:15,140 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:36:15,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:36:15,142 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:36:15,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:15,150 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:36:15,150 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:36:15,154 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:36:15,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:36:15,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:36:15,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:36:15,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:36:15,193 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:36:15,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:15,193 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:36:15,194 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:36:15,194 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:36:15,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:36:15,196 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:15,196 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:15,196 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:15,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:15,197 INFO L82 PathProgramCache]: Analyzing trace with hash -1274606805, now seen corresponding path program 1 times [2019-10-07 15:36:15,197 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:15,198 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:15,198 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:15,198 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:15,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:15,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:15,272 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:36:15,273 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:15,273 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:15,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:15,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:15,354 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:36:15,362 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:15,389 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:36:15,389 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:15,432 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:36:15,432 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:36:15,433 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:36:15,434 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:36:15,435 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:36:15,435 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:36:15,435 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:36:15,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:15,450 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:36:15,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:36:15,450 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:36:15,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:15,452 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:36:15,452 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:36:15,453 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:36:15,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:36:15,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:36:15,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:36:15,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:36:15,459 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:36:15,459 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:15,459 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:36:15,459 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:36:15,459 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:36:15,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:36:15,462 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:15,462 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:15,667 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:15,667 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:15,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:15,668 INFO L82 PathProgramCache]: Analyzing trace with hash -544560989, now seen corresponding path program 1 times [2019-10-07 15:36:15,668 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:15,668 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:15,669 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:15,669 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:15,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:15,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:15,786 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:36:15,787 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:15,787 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:36:15,787 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:36:15,788 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:36:15,788 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:36:15,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:36:15,789 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:36:15,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:15,799 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:36:15,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:36:15,800 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:36:15,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:15,801 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:36:15,802 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:36:15,802 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:36:15,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:36:15,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:36:15,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:36:15,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:36:15,809 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:36:15,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:15,811 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:36:15,811 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:36:15,811 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:36:15,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:36:15,812 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:15,813 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:15,813 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:15,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:15,813 INFO L82 PathProgramCache]: Analyzing trace with hash -5957836, now seen corresponding path program 1 times [2019-10-07 15:36:15,814 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:15,814 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:15,814 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:15,814 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:15,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:15,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:15,977 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 5 proven. 6 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-10-07 15:36:15,977 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:15,978 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:15,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:16,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:16,043 INFO L256 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:36:16,046 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:16,088 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:36:16,089 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:16,133 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:36:16,134 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:16,159 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:16,160 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:16,166 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:16,174 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:16,174 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:16,301 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:18,206 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:18,279 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:18,283 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:18,283 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:18,284 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:36:18,284 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_2 Int) (v_prenex_1 Int) (v_sep_~ret~0_BEFORE_RETURN_2 Int) (v_sep_~ret~0_BEFORE_RETURN_1 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_1 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_2 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (mod v_prenex_1 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (mod v_prenex_2 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_2 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:18,284 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:18,285 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:18,285 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:18,285 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:18,285 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_sep_~ret~0_BEFORE_RETURN_6 Int) (v_sep_~ret~0_BEFORE_RETURN_5 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_5 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_29 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (= (mod v_prenex_29 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_6 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_sep_~ret~0_BEFORE_RETURN_6 Int) (v_sep_~ret~0_BEFORE_RETURN_5 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_5 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_29 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (= (mod v_prenex_29 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_6 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:36:18,286 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:18,286 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:18,286 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:18,286 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:18,287 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:18,287 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:36:18,287 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 40 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 40))) [2019-10-07 15:36:18,287 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_2 Int) (v_sep_~ret~0_BEFORE_RETURN_2 Int)) (or (and (not (< main_~i~1 40)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_2 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (= (mod v_prenex_2 4294967296) |main_#t~ret6|) (<= (mod v_prenex_2 4294967296) 2147483647)))) (exists ((v_prenex_1 Int) (v_sep_~ret~0_BEFORE_RETURN_1 Int)) (or (and (not (< main_~i~1 40)) (= (mod v_prenex_1 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_1 4294967296) (- 4294967296)) |main_#t~ret6|))))) [2019-10-07 15:36:18,288 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:18,288 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:18,288 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:18,289 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:18,667 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:18,667 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 18 [2019-10-07 15:36:18,668 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-10-07 15:36:18,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-10-07 15:36:18,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=292, Unknown=0, NotChecked=0, Total=342 [2019-10-07 15:36:18,670 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 19 states. [2019-10-07 15:36:19,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:19,399 INFO L93 Difference]: Finished difference Result 41 states and 55 transitions. [2019-10-07 15:36:19,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-10-07 15:36:19,399 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 29 [2019-10-07 15:36:19,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:19,400 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:36:19,400 INFO L226 Difference]: Without dead ends: 26 [2019-10-07 15:36:19,401 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 74 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 209 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=154, Invalid=902, Unknown=0, NotChecked=0, Total=1056 [2019-10-07 15:36:19,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2019-10-07 15:36:19,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2019-10-07 15:36:19,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2019-10-07 15:36:19,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 30 transitions. [2019-10-07 15:36:19,408 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 30 transitions. Word has length 29 [2019-10-07 15:36:19,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:19,409 INFO L462 AbstractCegarLoop]: Abstraction has 26 states and 30 transitions. [2019-10-07 15:36:19,409 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-10-07 15:36:19,409 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 30 transitions. [2019-10-07 15:36:19,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-10-07 15:36:19,410 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:19,410 INFO L385 BasicCegarLoop]: trace histogram [6, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:19,617 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:19,618 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:19,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:19,618 INFO L82 PathProgramCache]: Analyzing trace with hash -1231398047, now seen corresponding path program 2 times [2019-10-07 15:36:19,618 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:19,618 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:19,619 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:19,619 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:19,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:19,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:19,745 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2019-10-07 15:36:19,746 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:19,746 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:19,747 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:19,822 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:36:19,822 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:19,823 INFO L256 TraceCheckSpWp]: Trace formula consists of 111 conjuncts, 4 conjunts are in the unsatisfiable core [2019-10-07 15:36:19,826 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:19,857 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 20 proven. 3 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2019-10-07 15:36:19,857 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:19,903 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 20 proven. 3 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2019-10-07 15:36:19,903 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:19,904 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:19,905 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:19,905 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:19,905 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:19,906 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:19,936 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:21,474 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:21,506 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:21,510 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:21,510 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:21,510 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:36:21,511 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_196 Int) (v_sep_~ret~0_BEFORE_RETURN_28 Int) (v_sep_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_195 4294967296) main_~ret~1) (<= (mod v_prenex_195 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (mod v_sep_~ret~0_BEFORE_RETURN_28 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:21,511 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:21,511 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:21,511 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:21,512 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:21,512 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (exists ((v_sep_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_sep_~ret~0_BEFORE_RETURN_32 Int) (v_prenex_223 Int)) (or (and (<= main_~ret5~0 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_31 4294967296) main_~ret5~0) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_223 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_223 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_sep_~ret~0_BEFORE_RETURN_32 Int) (v_prenex_223 Int)) (or (and (<= main_~ret5~0 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_31 4294967296) main_~ret5~0) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_223 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_223 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:36:21,512 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:21,512 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:21,513 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:21,513 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:21,513 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:21,513 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:36:21,513 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 40 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 40))) [2019-10-07 15:36:21,514 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_28 Int) (v_prenex_196 Int)) (or (and (not (< main_~i~1 40)) (= (mod v_sep_~ret~0_BEFORE_RETURN_28 4294967296) |main_#t~ret6|) (<= (mod v_sep_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647)) (and (not (<= (mod v_prenex_196 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret6|)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (not (< main_~i~1 40))) (and (= (mod v_prenex_195 4294967296) |main_#t~ret6|) (not (< main_~i~1 40)) (<= (mod v_prenex_195 4294967296) 2147483647))))) [2019-10-07 15:36:21,514 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:21,514 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:21,514 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:21,514 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:21,911 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:21,912 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5, 5, 11] total 23 [2019-10-07 15:36:21,913 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-10-07 15:36:21,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-10-07 15:36:21,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=475, Unknown=0, NotChecked=0, Total=552 [2019-10-07 15:36:21,916 INFO L87 Difference]: Start difference. First operand 26 states and 30 transitions. Second operand 24 states. [2019-10-07 15:36:23,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:23,002 INFO L93 Difference]: Finished difference Result 47 states and 62 transitions. [2019-10-07 15:36:23,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-10-07 15:36:23,002 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 35 [2019-10-07 15:36:23,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:23,003 INFO L225 Difference]: With dead ends: 47 [2019-10-07 15:36:23,003 INFO L226 Difference]: Without dead ends: 31 [2019-10-07 15:36:23,005 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 130 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 397 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=261, Invalid=1545, Unknown=0, NotChecked=0, Total=1806 [2019-10-07 15:36:23,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2019-10-07 15:36:23,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 31. [2019-10-07 15:36:23,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2019-10-07 15:36:23,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 35 transitions. [2019-10-07 15:36:23,013 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 35 transitions. Word has length 35 [2019-10-07 15:36:23,013 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:23,013 INFO L462 AbstractCegarLoop]: Abstraction has 31 states and 35 transitions. [2019-10-07 15:36:23,013 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-10-07 15:36:23,014 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 35 transitions. [2019-10-07 15:36:23,015 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-10-07 15:36:23,015 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:23,015 INFO L385 BasicCegarLoop]: trace histogram [18, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:23,218 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:23,219 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:23,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:23,219 INFO L82 PathProgramCache]: Analyzing trace with hash -670981082, now seen corresponding path program 3 times [2019-10-07 15:36:23,219 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:23,219 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:23,219 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:23,219 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:23,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:23,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:23,371 INFO L134 CoverageAnalysis]: Checked inductivity of 232 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 217 trivial. 0 not checked. [2019-10-07 15:36:23,371 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:23,371 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:23,372 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:23,514 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:36:23,514 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:23,516 INFO L256 TraceCheckSpWp]: Trace formula consists of 223 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:36:23,519 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:23,533 INFO L134 CoverageAnalysis]: Checked inductivity of 232 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 217 trivial. 0 not checked. [2019-10-07 15:36:23,534 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:23,612 INFO L134 CoverageAnalysis]: Checked inductivity of 232 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 217 trivial. 0 not checked. [2019-10-07 15:36:23,613 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:23,614 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:23,615 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:23,615 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:23,615 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:23,616 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:23,641 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:25,100 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:25,146 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:25,156 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:25,156 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:25,156 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:36:25,157 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int) (v_sep_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_389 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:25,157 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:25,158 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:25,159 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:25,159 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:25,159 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_sep_~ret~0_BEFORE_RETURN_58 Int)) (or (and (<= main_~ret5~0 2147483647) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_58 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_sep_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_sep_~ret~0_BEFORE_RETURN_58 Int)) (or (and (<= main_~ret5~0 2147483647) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_58 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:36:25,160 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:25,160 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:25,160 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:25,161 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:25,161 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:25,161 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:36:25,161 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 40 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 40))) [2019-10-07 15:36:25,162 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_prenex_390 4294967296) (- 4294967296)))) (and (= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) |main_#t~ret6|) (not (< main_~i~1 40)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (not (< main_~i~1 40)) (<= (mod v_prenex_389 4294967296) 2147483647) (= (mod v_prenex_389 4294967296) |main_#t~ret6|))))) [2019-10-07 15:36:25,162 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:25,162 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:25,162 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:25,162 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:25,667 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:25,667 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-07 15:36:25,669 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-07 15:36:25,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-07 15:36:25,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-07 15:36:25,670 INFO L87 Difference]: Start difference. First operand 31 states and 35 transitions. Second operand 26 states. [2019-10-07 15:36:26,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:26,606 INFO L93 Difference]: Finished difference Result 58 states and 72 transitions. [2019-10-07 15:36:26,606 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-07 15:36:26,607 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 48 [2019-10-07 15:36:26,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:26,608 INFO L225 Difference]: With dead ends: 58 [2019-10-07 15:36:26,608 INFO L226 Difference]: Without dead ends: 38 [2019-10-07 15:36:26,609 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 174 GetRequests, 130 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-07 15:36:26,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2019-10-07 15:36:26,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 38. [2019-10-07 15:36:26,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2019-10-07 15:36:26,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 42 transitions. [2019-10-07 15:36:26,617 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 42 transitions. Word has length 48 [2019-10-07 15:36:26,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:26,618 INFO L462 AbstractCegarLoop]: Abstraction has 38 states and 42 transitions. [2019-10-07 15:36:26,618 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-07 15:36:26,618 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 42 transitions. [2019-10-07 15:36:26,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-10-07 15:36:26,619 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:26,620 INFO L385 BasicCegarLoop]: trace histogram [18, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:26,823 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:26,824 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:26,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:26,824 INFO L82 PathProgramCache]: Analyzing trace with hash 946059489, now seen corresponding path program 4 times [2019-10-07 15:36:26,824 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:26,824 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:26,824 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:26,825 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:26,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:26,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:26,990 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 217 trivial. 0 not checked. [2019-10-07 15:36:26,991 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:26,991 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:26,991 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:27,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:27,156 INFO L256 TraceCheckSpWp]: Trace formula consists of 265 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:36:27,168 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:27,186 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 217 trivial. 0 not checked. [2019-10-07 15:36:27,186 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:27,420 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 217 trivial. 0 not checked. [2019-10-07 15:36:27,421 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:27,422 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:27,422 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:27,423 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:27,423 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:27,423 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:27,448 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:28,678 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:28,706 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:28,710 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:28,710 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:28,711 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:36:28,711 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(or (exists ((v_prenex_583 Int) (v_prenex_584 Int) (v_sep_~ret~0_BEFORE_RETURN_80 Int) (v_sep_~ret~0_BEFORE_RETURN_79 Int)) (or (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_583 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_584 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_584 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_prenex_583 Int) (v_prenex_584 Int) (v_sep_~ret~0_BEFORE_RETURN_80 Int) (v_sep_~ret~0_BEFORE_RETURN_79 Int)) (or (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_583 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_584 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_584 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) main_~ret~1) (<= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:36:28,711 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:28,711 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:28,712 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:28,712 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:28,712 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret5~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_sep_~ret~0_BEFORE_RETURN_84 Int) (v_sep_~ret~0_BEFORE_RETURN_83 Int)) (or (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_611 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_sep_~ret~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_sep_~ret~0_BEFORE_RETURN_84 Int) (v_sep_~ret~0_BEFORE_RETURN_83 Int)) (or (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_611 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_sep_~ret~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:36:28,712 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:28,712 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:28,713 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:28,713 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:28,713 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:28,713 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:36:28,713 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 40 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 40))) [2019-10-07 15:36:28,713 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_583 Int) (v_sep_~ret~0_BEFORE_RETURN_79 Int)) (or (and (= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) |main_#t~ret6|) (not (< main_~i~1 40)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647)) (and (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 40)) (not (<= (mod v_prenex_583 4294967296) 2147483647))))) (exists ((v_prenex_584 Int) (v_sep_~ret~0_BEFORE_RETURN_80 Int)) (or (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 40)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (= (mod v_prenex_584 4294967296) |main_#t~ret6|) (<= (mod v_prenex_584 4294967296) 2147483647))))) [2019-10-07 15:36:28,714 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:28,714 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:28,714 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:28,715 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:29,141 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:29,141 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-07 15:36:29,143 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-07 15:36:29,143 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-07 15:36:29,144 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:36:29,144 INFO L87 Difference]: Start difference. First operand 38 states and 42 transitions. Second operand 40 states. [2019-10-07 15:36:32,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:32,629 INFO L93 Difference]: Finished difference Result 72 states and 93 transitions. [2019-10-07 15:36:32,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-07 15:36:32,630 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 55 [2019-10-07 15:36:32,630 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:32,631 INFO L225 Difference]: With dead ends: 72 [2019-10-07 15:36:32,631 INFO L226 Difference]: Without dead ends: 52 [2019-10-07 15:36:32,633 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 216 GetRequests, 144 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:36:32,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2019-10-07 15:36:32,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2019-10-07 15:36:32,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2019-10-07 15:36:32,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 56 transitions. [2019-10-07 15:36:32,642 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 56 transitions. Word has length 55 [2019-10-07 15:36:32,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:32,642 INFO L462 AbstractCegarLoop]: Abstraction has 52 states and 56 transitions. [2019-10-07 15:36:32,642 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-07 15:36:32,642 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 56 transitions. [2019-10-07 15:36:32,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-10-07 15:36:32,644 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:32,644 INFO L385 BasicCegarLoop]: trace histogram [26, 18, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:32,847 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:32,848 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:32,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:32,849 INFO L82 PathProgramCache]: Analyzing trace with hash 1395957057, now seen corresponding path program 5 times [2019-10-07 15:36:32,849 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:32,850 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:32,850 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:32,850 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:32,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:32,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:33,388 INFO L134 CoverageAnalysis]: Checked inductivity of 568 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 217 trivial. 0 not checked. [2019-10-07 15:36:33,389 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:33,389 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:33,389 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:33,547 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:36:33,547 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:33,549 INFO L256 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:36:33,563 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:33,608 INFO L134 CoverageAnalysis]: Checked inductivity of 568 backedges. 102 proven. 1 refuted. 0 times theorem prover too weak. 465 trivial. 0 not checked. [2019-10-07 15:36:33,608 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:33,663 INFO L134 CoverageAnalysis]: Checked inductivity of 568 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 567 trivial. 0 not checked. [2019-10-07 15:36:33,663 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:33,665 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:33,665 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:33,665 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:33,666 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:33,666 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:33,681 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:34,899 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:34,931 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:34,934 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:34,934 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:34,934 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:36:34,935 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_777 Int) (v_sep_~ret~0_BEFORE_RETURN_105 Int) (v_sep_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_prenex_777 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (+ (mod v_prenex_777 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_105 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:34,935 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:34,935 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:34,935 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:34,935 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:34,936 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_806 Int) (v_prenex_805 Int) (v_sep_~ret~0_BEFORE_RETURN_109 Int)) (or (and (= main_~ret5~0 (mod v_prenex_805 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_805 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_109 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_sep_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_806 Int) (v_prenex_805 Int) (v_sep_~ret~0_BEFORE_RETURN_109 Int)) (or (and (= main_~ret5~0 (mod v_prenex_805 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_805 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_109 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:36:34,936 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:34,936 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:36:34,936 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:34,936 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:34,937 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:34,937 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:36:34,937 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 40 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 40))) [2019-10-07 15:36:34,937 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_777 Int) (v_sep_~ret~0_BEFORE_RETURN_105 Int)) (or (and (not (< main_~i~1 40)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= |main_#t~ret6| (mod v_sep_~ret~0_BEFORE_RETURN_105 4294967296))) (and (not (<= (mod v_prenex_777 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod v_prenex_777 4294967296) (- 4294967296)) |main_#t~ret6|)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (< main_~i~1 40)) (= |main_#t~ret6| (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647)) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (not (< main_~i~1 40)) (= |main_#t~ret6| (+ (mod v_sep_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296))))))) [2019-10-07 15:36:34,937 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:34,938 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:34,938 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:34,938 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:35,464 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:35,464 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-07 15:36:35,465 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-07 15:36:35,466 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-07 15:36:35,467 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-07 15:36:35,467 INFO L87 Difference]: Start difference. First operand 52 states and 56 transitions. Second operand 44 states. [2019-10-07 15:36:39,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:39,488 INFO L93 Difference]: Finished difference Result 76 states and 87 transitions. [2019-10-07 15:36:39,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-07 15:36:39,488 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 69 [2019-10-07 15:36:39,488 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:39,489 INFO L225 Difference]: With dead ends: 76 [2019-10-07 15:36:39,490 INFO L226 Difference]: Without dead ends: 56 [2019-10-07 15:36:39,493 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 275 GetRequests, 194 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1350 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1349, Invalid=5457, Unknown=0, NotChecked=0, Total=6806 [2019-10-07 15:36:39,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2019-10-07 15:36:39,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 56. [2019-10-07 15:36:39,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2019-10-07 15:36:39,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 60 transitions. [2019-10-07 15:36:39,501 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 60 transitions. Word has length 69 [2019-10-07 15:36:39,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:39,501 INFO L462 AbstractCegarLoop]: Abstraction has 56 states and 60 transitions. [2019-10-07 15:36:39,501 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-07 15:36:39,501 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 60 transitions. [2019-10-07 15:36:39,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-10-07 15:36:39,503 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:39,503 INFO L385 BasicCegarLoop]: trace histogram [27, 18, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:39,705 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:39,706 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:39,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:39,707 INFO L82 PathProgramCache]: Analyzing trace with hash 653286155, now seen corresponding path program 6 times [2019-10-07 15:36:39,707 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:39,707 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:39,708 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:39,708 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:39,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:39,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:40,268 INFO L134 CoverageAnalysis]: Checked inductivity of 604 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 226 trivial. 0 not checked. [2019-10-07 15:36:40,269 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:40,269 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:40,269 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:40,490 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:36:40,490 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:40,492 INFO L256 TraceCheckSpWp]: Trace formula consists of 367 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-07 15:36:40,494 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:40,512 INFO L134 CoverageAnalysis]: Checked inductivity of 604 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 226 trivial. 0 not checked. [2019-10-07 15:36:40,513 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:41,151 INFO L134 CoverageAnalysis]: Checked inductivity of 604 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 226 trivial. 0 not checked. [2019-10-07 15:36:41,152 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:41,153 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:41,153 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:41,154 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:41,154 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:41,154 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:41,178 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:42,431 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:42,481 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:42,483 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:42,483 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:42,484 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:36:42,484 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_131 Int) (v_sep_~ret~0_BEFORE_RETURN_132 Int) (v_prenex_972 Int) (v_prenex_971 Int)) (or (and (= main_~ret~1 (mod v_prenex_972 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_972 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_131 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:42,484 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:42,484 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:42,484 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:42,485 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:42,485 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (exists ((v_sep_~ret~0_BEFORE_RETURN_135 Int) (v_sep_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_135 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_999 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_999 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1000 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (exists ((v_sep_~ret~0_BEFORE_RETURN_135 Int) (v_sep_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_135 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_999 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_999 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1000 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret2~0)))) [2019-10-07 15:36:42,485 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:42,485 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:42,486 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:42,486 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:42,486 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:42,486 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:36:42,486 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 40 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 40))) [2019-10-07 15:36:42,487 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_131 Int) (v_prenex_971 Int)) (or (and (= |main_#t~ret6| (mod v_sep_~ret~0_BEFORE_RETURN_131 4294967296)) (not (< main_~i~1 40)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod v_prenex_971 4294967296) (- 4294967296)) |main_#t~ret6|)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_132 Int) (v_prenex_972 Int)) (or (and (= (mod v_prenex_972 4294967296) |main_#t~ret6|) (not (< main_~i~1 40)) (<= (mod v_prenex_972 4294967296) 2147483647)) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) |main_#t~ret6|))))) [2019-10-07 15:36:42,487 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:42,487 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:42,487 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:42,487 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:43,033 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:43,033 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 53 [2019-10-07 15:36:43,034 INFO L442 AbstractCegarLoop]: Interpolant automaton has 54 states [2019-10-07 15:36:43,035 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2019-10-07 15:36:43,036 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=932, Invalid=1930, Unknown=0, NotChecked=0, Total=2862 [2019-10-07 15:36:43,036 INFO L87 Difference]: Start difference. First operand 56 states and 60 transitions. Second operand 54 states. [2019-10-07 15:36:45,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:45,349 INFO L93 Difference]: Finished difference Result 92 states and 112 transitions. [2019-10-07 15:36:45,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-10-07 15:36:45,350 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 73 [2019-10-07 15:36:45,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:45,351 INFO L225 Difference]: With dead ends: 92 [2019-10-07 15:36:45,352 INFO L226 Difference]: Without dead ends: 69 [2019-10-07 15:36:45,355 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 299 GetRequests, 183 SyntacticMatches, 16 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2497 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=2707, Invalid=7595, Unknown=0, NotChecked=0, Total=10302 [2019-10-07 15:36:45,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2019-10-07 15:36:45,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2019-10-07 15:36:45,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2019-10-07 15:36:45,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 73 transitions. [2019-10-07 15:36:45,363 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 73 transitions. Word has length 73 [2019-10-07 15:36:45,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:45,364 INFO L462 AbstractCegarLoop]: Abstraction has 69 states and 73 transitions. [2019-10-07 15:36:45,364 INFO L463 AbstractCegarLoop]: Interpolant automaton has 54 states. [2019-10-07 15:36:45,364 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 73 transitions. [2019-10-07 15:36:45,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-10-07 15:36:45,365 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:45,365 INFO L385 BasicCegarLoop]: trace histogram [40, 18, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:45,568 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:45,569 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:45,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:45,570 INFO L82 PathProgramCache]: Analyzing trace with hash -689436464, now seen corresponding path program 7 times [2019-10-07 15:36:45,570 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:45,570 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:45,570 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:45,571 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:45,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:45,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:45,687 INFO L134 CoverageAnalysis]: Checked inductivity of 1046 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 1036 trivial. 0 not checked. [2019-10-07 15:36:45,687 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:45,687 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:45,688 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:45,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:45,922 INFO L256 TraceCheckSpWp]: Trace formula consists of 445 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-07 15:36:45,924 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:45,993 INFO L134 CoverageAnalysis]: Checked inductivity of 1046 backedges. 100 proven. 21 refuted. 0 times theorem prover too weak. 925 trivial. 0 not checked. [2019-10-07 15:36:45,993 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:46,112 INFO L134 CoverageAnalysis]: Checked inductivity of 1046 backedges. 0 proven. 121 refuted. 0 times theorem prover too weak. 925 trivial. 0 not checked. [2019-10-07 15:36:46,113 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:46,114 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:46,114 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:46,115 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:46,115 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:46,115 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:46,129 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:47,314 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:47,343 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:47,346 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:47,346 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:47,346 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:36:47,347 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_157 Int) (v_sep_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int) (v_prenex_1165 Int)) (or (and (= main_~ret~1 (mod v_prenex_1166 4294967296)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sep_~ret~0_BEFORE_RETURN_157 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1165 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:47,347 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:47,347 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:47,347 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:47,347 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:47,348 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret5~0)) (exists ((v_prenex_1194 Int) (v_prenex_1193 Int) (v_sep_~ret~0_BEFORE_RETURN_161 Int) (v_sep_~ret~0_BEFORE_RETURN_162 Int)) (or (and (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_161 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1194 Int) (v_prenex_1193 Int) (v_sep_~ret~0_BEFORE_RETURN_161 Int) (v_sep_~ret~0_BEFORE_RETURN_162 Int)) (or (and (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_161 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:36:47,348 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:47,348 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:47,348 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:47,348 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:47,349 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:47,349 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:36:47,349 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 40 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 40))) [2019-10-07 15:36:47,350 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (<= (mod v_prenex_1166 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_1166 4294967296) |main_#t~ret6|)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_157 Int) (v_prenex_1165 Int)) (or (and (not (< main_~i~1 40)) (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_1165 4294967296) 2147483647))) (and (= (mod v_sep_~ret~0_BEFORE_RETURN_157 4294967296) |main_#t~ret6|) (<= (mod v_sep_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647) (not (< main_~i~1 40)))))) [2019-10-07 15:36:47,350 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:47,350 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:47,350 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:47,351 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:47,740 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:47,740 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 9, 9, 11] total 31 [2019-10-07 15:36:47,741 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2019-10-07 15:36:47,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2019-10-07 15:36:47,742 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=169, Invalid=823, Unknown=0, NotChecked=0, Total=992 [2019-10-07 15:36:47,742 INFO L87 Difference]: Start difference. First operand 69 states and 73 transitions. Second operand 32 states. [2019-10-07 15:36:49,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:49,198 INFO L93 Difference]: Finished difference Result 100 states and 118 transitions. [2019-10-07 15:36:49,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-10-07 15:36:49,199 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 86 [2019-10-07 15:36:49,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:49,200 INFO L225 Difference]: With dead ends: 100 [2019-10-07 15:36:49,200 INFO L226 Difference]: Without dead ends: 78 [2019-10-07 15:36:49,202 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 292 GetRequests, 235 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 800 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=595, Invalid=2827, Unknown=0, NotChecked=0, Total=3422 [2019-10-07 15:36:49,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2019-10-07 15:36:49,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 78. [2019-10-07 15:36:49,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2019-10-07 15:36:49,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 82 transitions. [2019-10-07 15:36:49,212 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 82 transitions. Word has length 86 [2019-10-07 15:36:49,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:49,213 INFO L462 AbstractCegarLoop]: Abstraction has 78 states and 82 transitions. [2019-10-07 15:36:49,213 INFO L463 AbstractCegarLoop]: Interpolant automaton has 32 states. [2019-10-07 15:36:49,213 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 82 transitions. [2019-10-07 15:36:49,214 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2019-10-07 15:36:49,215 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:49,215 INFO L385 BasicCegarLoop]: trace histogram [42, 40, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:49,419 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:49,419 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:49,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:49,420 INFO L82 PathProgramCache]: Analyzing trace with hash 1653046113, now seen corresponding path program 8 times [2019-10-07 15:36:49,420 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:49,420 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:49,420 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:49,421 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:49,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:49,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:49,705 INFO L134 CoverageAnalysis]: Checked inductivity of 1831 backedges. 226 proven. 331 refuted. 0 times theorem prover too weak. 1274 trivial. 0 not checked. [2019-10-07 15:36:49,706 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:49,706 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:49,706 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:49,998 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-10-07 15:36:49,998 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:50,000 INFO L256 TraceCheckSpWp]: Trace formula consists of 215 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:36:50,003 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:50,087 INFO L134 CoverageAnalysis]: Checked inductivity of 1831 backedges. 454 proven. 15 refuted. 0 times theorem prover too weak. 1362 trivial. 0 not checked. [2019-10-07 15:36:50,088 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:50,214 INFO L134 CoverageAnalysis]: Checked inductivity of 1831 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 1816 trivial. 0 not checked. [2019-10-07 15:36:50,214 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:50,215 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:50,216 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:50,216 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:50,216 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:50,216 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:50,229 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:51,689 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:51,720 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:51,722 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:51,723 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:51,723 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:36:51,723 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_1359 Int) (v_prenex_1360 Int) (v_sep_~ret~0_BEFORE_RETURN_183 Int) (v_sep_~ret~0_BEFORE_RETURN_184 Int)) (or (and (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_183 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1359 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1359 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_1360 4294967296)) (<= (mod v_prenex_1360 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_184 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:51,723 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:51,723 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:51,723 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:51,724 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:51,724 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_187 Int) (v_sep_~ret~0_BEFORE_RETURN_188 Int) (v_prenex_1388 Int) (v_prenex_1387 Int)) (or (and (= (mod v_sep_~ret~0_BEFORE_RETURN_187 4294967296) main_~ret5~0) (<= (mod v_sep_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_1387 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1387 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= (mod v_prenex_1388 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_188 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_sep_~ret~0_BEFORE_RETURN_187 Int) (v_sep_~ret~0_BEFORE_RETURN_188 Int) (v_prenex_1388 Int) (v_prenex_1387 Int)) (or (and (= (mod v_sep_~ret~0_BEFORE_RETURN_187 4294967296) main_~ret5~0) (<= (mod v_sep_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_1387 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1387 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= (mod v_prenex_1388 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_188 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:36:51,724 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:51,724 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:51,725 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:51,725 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:51,725 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:51,725 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:36:51,725 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 40 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 40))) [2019-10-07 15:36:51,726 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_1360 Int) (v_sep_~ret~0_BEFORE_RETURN_184 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_184 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (not (< main_~i~1 40)) (= (mod v_prenex_1360 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1360 4294967296) 2147483647)))) (exists ((v_prenex_1359 Int) (v_sep_~ret~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_sep_~ret~0_BEFORE_RETURN_183 4294967296) (- 4294967296)))) (and (not (< main_~i~1 40)) (= (mod v_prenex_1359 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1359 4294967296) 2147483647))))) [2019-10-07 15:36:51,726 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:51,726 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:51,726 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:51,726 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:52,125 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:52,125 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 8, 8, 11] total 39 [2019-10-07 15:36:52,126 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-07 15:36:52,127 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-07 15:36:52,128 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=256, Invalid=1304, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:36:52,128 INFO L87 Difference]: Start difference. First operand 78 states and 82 transitions. Second operand 40 states. [2019-10-07 15:36:54,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:36:54,112 INFO L93 Difference]: Finished difference Result 117 states and 134 transitions. [2019-10-07 15:36:54,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-10-07 15:36:54,112 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 111 [2019-10-07 15:36:54,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:36:54,114 INFO L225 Difference]: With dead ends: 117 [2019-10-07 15:36:54,114 INFO L226 Difference]: Without dead ends: 86 [2019-10-07 15:36:54,117 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 385 GetRequests, 312 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1276 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=874, Invalid=4676, Unknown=0, NotChecked=0, Total=5550 [2019-10-07 15:36:54,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states. [2019-10-07 15:36:54,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 86. [2019-10-07 15:36:54,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2019-10-07 15:36:54,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 90 transitions. [2019-10-07 15:36:54,127 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 90 transitions. Word has length 111 [2019-10-07 15:36:54,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:36:54,128 INFO L462 AbstractCegarLoop]: Abstraction has 86 states and 90 transitions. [2019-10-07 15:36:54,128 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-07 15:36:54,128 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 90 transitions. [2019-10-07 15:36:54,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2019-10-07 15:36:54,130 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:36:54,130 INFO L385 BasicCegarLoop]: trace histogram [45, 40, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:36:54,338 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:54,338 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:36:54,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:36:54,339 INFO L82 PathProgramCache]: Analyzing trace with hash -1531615906, now seen corresponding path program 9 times [2019-10-07 15:36:54,339 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:36:54,339 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:54,339 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:54,339 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:36:54,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:36:54,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:36:54,682 INFO L134 CoverageAnalysis]: Checked inductivity of 2032 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 1954 trivial. 0 not checked. [2019-10-07 15:36:54,683 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:36:54,683 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:36:54,683 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:36:55,006 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:36:55,006 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:36:55,009 INFO L256 TraceCheckSpWp]: Trace formula consists of 585 conjuncts, 17 conjunts are in the unsatisfiable core [2019-10-07 15:36:55,012 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:36:55,306 INFO L134 CoverageAnalysis]: Checked inductivity of 2032 backedges. 514 proven. 120 refuted. 0 times theorem prover too weak. 1398 trivial. 0 not checked. [2019-10-07 15:36:55,306 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:36:55,696 INFO L134 CoverageAnalysis]: Checked inductivity of 2032 backedges. 0 proven. 634 refuted. 0 times theorem prover too weak. 1398 trivial. 0 not checked. [2019-10-07 15:36:55,697 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:36:55,698 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:36:55,698 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:36:55,698 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:36:55,699 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:36:55,699 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:36:55,715 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:36:56,927 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:36:56,952 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:36:56,954 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:36:56,955 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:36:56,955 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:36:56,955 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_sep_~ret~0_BEFORE_RETURN_209 Int)) (or (and (= main_~ret~1 (mod v_prenex_1554 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1554 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_209 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (+ (mod v_prenex_1553 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (not (<= (mod v_prenex_1553 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:36:56,955 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:36:56,955 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:36:56,956 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:36:56,956 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:36:56,956 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_213 Int) (v_sep_~ret~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_214 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_prenex_1581 4294967296)) (<= (mod v_prenex_1581 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_213 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_sep_~ret~0_BEFORE_RETURN_213 Int) (v_sep_~ret~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_214 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_prenex_1581 4294967296)) (<= (mod v_prenex_1581 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_213 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:36:56,956 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:56,956 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:36:56,957 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:36:56,957 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:36:56,957 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:36:56,957 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:36:56,957 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 40 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 40))) [2019-10-07 15:36:56,957 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int)) (or (and (not (< main_~i~1 40)) (= (mod v_prenex_1554 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1554 4294967296) 2147483647)) (and (= |main_#t~ret6| (+ (mod v_sep_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (not (< main_~i~1 40))))) (exists ((v_prenex_1553 Int) (v_sep_~ret~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 40)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647) (= |main_#t~ret6| (mod v_sep_~ret~0_BEFORE_RETURN_209 4294967296))) (and (not (< main_~i~1 40)) (not (<= (mod v_prenex_1553 4294967296) 2147483647)) (= (+ (mod v_prenex_1553 4294967296) (- 4294967296)) |main_#t~ret6|))))) [2019-10-07 15:36:56,958 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:36:56,958 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:36:56,958 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:36:56,958 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:36:57,421 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:36:57,421 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 18, 18, 11] total 57 [2019-10-07 15:36:57,423 INFO L442 AbstractCegarLoop]: Interpolant automaton has 58 states [2019-10-07 15:36:57,423 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2019-10-07 15:36:57,425 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=694, Invalid=2612, Unknown=0, NotChecked=0, Total=3306 [2019-10-07 15:36:57,425 INFO L87 Difference]: Start difference. First operand 86 states and 90 transitions. Second operand 58 states. [2019-10-07 15:37:02,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:02,800 INFO L93 Difference]: Finished difference Result 143 states and 170 transitions. [2019-10-07 15:37:02,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2019-10-07 15:37:02,800 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 121 [2019-10-07 15:37:02,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:02,801 INFO L225 Difference]: With dead ends: 143 [2019-10-07 15:37:02,802 INFO L226 Difference]: Without dead ends: 104 [2019-10-07 15:37:02,805 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 431 GetRequests, 322 SyntacticMatches, 0 SemanticMatches, 109 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2893 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=2294, Invalid=9916, Unknown=0, NotChecked=0, Total=12210 [2019-10-07 15:37:02,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2019-10-07 15:37:02,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 104. [2019-10-07 15:37:02,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2019-10-07 15:37:02,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 108 transitions. [2019-10-07 15:37:02,818 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 108 transitions. Word has length 121 [2019-10-07 15:37:02,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:02,818 INFO L462 AbstractCegarLoop]: Abstraction has 104 states and 108 transitions. [2019-10-07 15:37:02,819 INFO L463 AbstractCegarLoop]: Interpolant automaton has 58 states. [2019-10-07 15:37:02,819 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 108 transitions. [2019-10-07 15:37:02,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2019-10-07 15:37:02,820 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:02,820 INFO L385 BasicCegarLoop]: trace histogram [96, 40, 13, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:03,025 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:03,026 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:03,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:03,026 INFO L82 PathProgramCache]: Analyzing trace with hash 809383009, now seen corresponding path program 10 times [2019-10-07 15:37:03,027 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:03,027 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:03,027 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:03,027 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:03,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:03,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:03,626 INFO L134 CoverageAnalysis]: Checked inductivity of 5768 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 5677 trivial. 0 not checked. [2019-10-07 15:37:03,626 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:03,627 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:37:03,627 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:04,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:04,080 INFO L256 TraceCheckSpWp]: Trace formula consists of 793 conjuncts, 34 conjunts are in the unsatisfiable core [2019-10-07 15:37:04,082 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:37:04,700 INFO L134 CoverageAnalysis]: Checked inductivity of 5768 backedges. 2180 proven. 528 refuted. 0 times theorem prover too weak. 3060 trivial. 0 not checked. [2019-10-07 15:37:04,701 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:37:05,526 INFO L134 CoverageAnalysis]: Checked inductivity of 5768 backedges. 0 proven. 2708 refuted. 0 times theorem prover too weak. 3060 trivial. 0 not checked. [2019-10-07 15:37:05,527 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:37:05,528 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:37:05,528 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:37:05,529 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:37:05,529 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:37:05,529 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:37:05,541 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:37:06,727 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:37:06,780 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:37:06,783 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:37:06,783 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:37:06,784 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:37:06,784 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_235 Int) (v_sep_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int) (v_prenex_1747 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_235 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_235 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1747 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_1747 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_236 4294967296) 2147483647) (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_236 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_1748 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (not (<= (mod v_prenex_1748 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:37:06,784 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:37:06,784 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:37:06,784 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:37:06,784 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:37:06,785 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1776 Int) (v_prenex_1775 Int) (v_sep_~ret~0_BEFORE_RETURN_239 Int) (v_sep_~ret~0_BEFORE_RETURN_240 Int)) (or (and (<= (mod v_prenex_1775 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_240 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_240 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1776 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1776 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_239 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_prenex_1776 Int) (v_prenex_1775 Int) (v_sep_~ret~0_BEFORE_RETURN_239 Int) (v_sep_~ret~0_BEFORE_RETURN_240 Int)) (or (and (<= (mod v_prenex_1775 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_240 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_240 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1776 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1776 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_239 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:37:06,785 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:06,785 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:06,785 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:06,785 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:37:06,786 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:37:06,786 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:37:06,786 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 40 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 40))) [2019-10-07 15:37:06,786 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_235 Int) (v_prenex_1747 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_235 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_235 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 40))) (and (not (< main_~i~1 40)) (= (mod v_prenex_1747 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1747 4294967296) 2147483647)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int)) (or (and (not (< main_~i~1 40)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_236 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_236 4294967296) |main_#t~ret6|)) (and (= (+ (mod v_prenex_1748 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 40)) (not (<= (mod v_prenex_1748 4294967296) 2147483647)))))) [2019-10-07 15:37:06,786 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:37:06,786 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:37:06,786 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:37:06,787 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:37:07,423 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:37:07,424 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 35, 35, 11] total 66 [2019-10-07 15:37:07,425 INFO L442 AbstractCegarLoop]: Interpolant automaton has 67 states [2019-10-07 15:37:07,425 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2019-10-07 15:37:07,427 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1009, Invalid=3413, Unknown=0, NotChecked=0, Total=4422 [2019-10-07 15:37:07,427 INFO L87 Difference]: Start difference. First operand 104 states and 108 transitions. Second operand 67 states. [2019-10-07 15:37:11,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:11,987 INFO L93 Difference]: Finished difference Result 170 states and 188 transitions. [2019-10-07 15:37:11,987 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2019-10-07 15:37:11,987 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 173 [2019-10-07 15:37:11,988 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:11,989 INFO L225 Difference]: With dead ends: 170 [2019-10-07 15:37:11,989 INFO L226 Difference]: Without dead ends: 113 [2019-10-07 15:37:11,992 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 597 GetRequests, 444 SyntacticMatches, 26 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4123 ImplicationChecksByTransitivity, 6.1s TimeCoverageRelationStatistics Valid=3289, Invalid=13223, Unknown=0, NotChecked=0, Total=16512 [2019-10-07 15:37:11,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2019-10-07 15:37:12,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2019-10-07 15:37:12,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2019-10-07 15:37:12,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 117 transitions. [2019-10-07 15:37:12,005 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 117 transitions. Word has length 173 [2019-10-07 15:37:12,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:12,005 INFO L462 AbstractCegarLoop]: Abstraction has 113 states and 117 transitions. [2019-10-07 15:37:12,005 INFO L463 AbstractCegarLoop]: Interpolant automaton has 67 states. [2019-10-07 15:37:12,005 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 117 transitions. [2019-10-07 15:37:12,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2019-10-07 15:37:12,007 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:12,007 INFO L385 BasicCegarLoop]: trace histogram [120, 40, 14, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:12,212 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:12,213 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:12,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:12,213 INFO L82 PathProgramCache]: Analyzing trace with hash 1753514672, now seen corresponding path program 11 times [2019-10-07 15:37:12,214 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:12,214 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:12,214 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:12,214 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:12,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:12,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:12,757 INFO L134 CoverageAnalysis]: Checked inductivity of 8434 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:37:12,758 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:12,758 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:37:12,758 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:14,675 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2019-10-07 15:37:14,676 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:37:14,679 INFO L256 TraceCheckSpWp]: Trace formula consists of 363 conjuncts, 16 conjunts are in the unsatisfiable core [2019-10-07 15:37:14,683 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:37:14,718 INFO L134 CoverageAnalysis]: Checked inductivity of 8434 backedges. 3366 proven. 105 refuted. 0 times theorem prover too weak. 4963 trivial. 0 not checked. [2019-10-07 15:37:14,718 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:37:15,013 INFO L134 CoverageAnalysis]: Checked inductivity of 8434 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:37:15,013 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:37:15,015 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:37:15,015 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:37:15,015 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:37:15,015 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:37:15,015 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:37:15,028 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:37:16,201 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:37:16,227 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:37:16,228 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:37:16,229 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:37:16,229 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:37:16,229 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_sep_~ret~0_BEFORE_RETURN_261 Int) (v_sep_~ret~0_BEFORE_RETURN_262 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (mod v_sep_~ret~0_BEFORE_RETURN_261 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sep_~ret~0_BEFORE_RETURN_262 4294967296) main_~ret~1) (<= (mod v_sep_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_1942 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (+ (mod v_prenex_1941 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:37:16,229 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:37:16,229 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:37:16,229 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:37:16,229 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:37:16,230 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret5~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_265 Int) (v_sep_~ret~0_BEFORE_RETURN_266 Int) (v_prenex_1970 Int) (v_prenex_1969 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_265 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_265 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1969 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_266 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_266 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_265 Int) (v_sep_~ret~0_BEFORE_RETURN_266 Int) (v_prenex_1970 Int) (v_prenex_1969 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_265 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_265 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1969 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_266 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_266 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:37:16,230 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:16,230 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:16,230 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:16,230 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:37:16,230 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:37:16,230 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:37:16,230 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 40 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 40))) [2019-10-07 15:37:16,230 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_1942 Int) (v_sep_~ret~0_BEFORE_RETURN_262 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (= (+ (mod v_prenex_1942 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (not (< main_~i~1 40)) (= (mod v_sep_~ret~0_BEFORE_RETURN_262 4294967296) |main_#t~ret6|) (<= (mod v_sep_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647)))) (exists ((v_prenex_1941 Int) (v_sep_~ret~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 40)) (= (+ (mod v_prenex_1941 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_1941 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_261 4294967296) |main_#t~ret6|))))) [2019-10-07 15:37:16,231 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:37:16,231 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:37:16,231 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:37:16,231 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:37:16,640 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:37:16,640 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 11] total 43 [2019-10-07 15:37:16,641 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-07 15:37:16,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-07 15:37:16,642 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=557, Invalid=1335, Unknown=0, NotChecked=0, Total=1892 [2019-10-07 15:37:16,642 INFO L87 Difference]: Start difference. First operand 113 states and 117 transitions. Second operand 44 states. [2019-10-07 15:37:18,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:18,567 INFO L93 Difference]: Finished difference Result 177 states and 197 transitions. [2019-10-07 15:37:18,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2019-10-07 15:37:18,567 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 198 [2019-10-07 15:37:18,568 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:18,569 INFO L225 Difference]: With dead ends: 177 [2019-10-07 15:37:18,569 INFO L226 Difference]: Without dead ends: 129 [2019-10-07 15:37:18,570 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 649 GetRequests, 569 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1551 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1662, Invalid=4980, Unknown=0, NotChecked=0, Total=6642 [2019-10-07 15:37:18,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2019-10-07 15:37:18,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 129. [2019-10-07 15:37:18,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2019-10-07 15:37:18,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 133 transitions. [2019-10-07 15:37:18,582 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 133 transitions. Word has length 198 [2019-10-07 15:37:18,582 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:18,583 INFO L462 AbstractCegarLoop]: Abstraction has 129 states and 133 transitions. [2019-10-07 15:37:18,583 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-07 15:37:18,583 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 133 transitions. [2019-10-07 15:37:18,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2019-10-07 15:37:18,584 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:18,584 INFO L385 BasicCegarLoop]: trace histogram [120, 40, 30, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:18,790 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:18,791 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:18,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:18,792 INFO L82 PathProgramCache]: Analyzing trace with hash -493538384, now seen corresponding path program 12 times [2019-10-07 15:37:18,792 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:18,792 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:18,792 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:18,793 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:18,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:20,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:20,969 INFO L134 CoverageAnalysis]: Checked inductivity of 8794 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:37:20,970 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:20,970 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:37:20,970 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:21,499 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:37:21,499 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:37:21,503 INFO L256 TraceCheckSpWp]: Trace formula consists of 957 conjuncts, 32 conjunts are in the unsatisfiable core [2019-10-07 15:37:21,508 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:37:21,604 INFO L134 CoverageAnalysis]: Checked inductivity of 8794 backedges. 3366 proven. 465 refuted. 0 times theorem prover too weak. 4963 trivial. 0 not checked. [2019-10-07 15:37:21,604 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:37:22,187 INFO L134 CoverageAnalysis]: Checked inductivity of 8794 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:37:22,187 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:37:22,188 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:37:22,188 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:37:22,189 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:37:22,189 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:37:22,189 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:37:22,205 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:37:23,336 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:37:23,363 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:37:23,365 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:37:23,365 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:37:23,365 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:37:23,366 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_287 Int) (v_sep_~ret~0_BEFORE_RETURN_288 Int) (v_prenex_2135 Int) (v_prenex_2136 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_287 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_287 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (= (mod v_prenex_2135 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_prenex_2135 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_288 4294967296) 2147483647) (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_288 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_2136 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_2136 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:37:23,366 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:37:23,366 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:37:23,366 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:37:23,366 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:37:23,366 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_2163 Int) (v_prenex_2164 Int) (v_sep_~ret~0_BEFORE_RETURN_291 Int) (v_sep_~ret~0_BEFORE_RETURN_292 Int)) (or (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_291 4294967296) 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_291 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_sep_~ret~0_BEFORE_RETURN_292 4294967296) main_~ret5~0) (<= (mod v_sep_~ret~0_BEFORE_RETURN_292 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_2163 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2163 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_2164 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2164 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (not (= main_~ret~1 main_~ret5~0)) (exists ((v_prenex_2163 Int) (v_prenex_2164 Int) (v_sep_~ret~0_BEFORE_RETURN_291 Int) (v_sep_~ret~0_BEFORE_RETURN_292 Int)) (or (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_291 4294967296) 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_291 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_sep_~ret~0_BEFORE_RETURN_292 4294967296) main_~ret5~0) (<= (mod v_sep_~ret~0_BEFORE_RETURN_292 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_2163 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2163 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_2164 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2164 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:37:23,366 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:23,367 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:23,367 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:23,367 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:37:23,367 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:37:23,367 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:37:23,367 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (<= 40 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0) (not (< sep_~i~0 40))) [2019-10-07 15:37:23,367 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_287 Int) (v_prenex_2135 Int)) (or (and (not (< main_~i~1 40)) (<= (mod v_prenex_2135 4294967296) 2147483647) (= |main_#t~ret6| (mod v_prenex_2135 4294967296))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_287 4294967296) 2147483647)) (not (< main_~i~1 40)) (= |main_#t~ret6| (+ (mod v_sep_~ret~0_BEFORE_RETURN_287 4294967296) (- 4294967296)))))) (exists ((v_sep_~ret~0_BEFORE_RETURN_288 Int) (v_prenex_2136 Int)) (or (and (not (< main_~i~1 40)) (= (+ (mod v_prenex_2136 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_2136 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_288 4294967296) 2147483647) (= |main_#t~ret6| (mod v_sep_~ret~0_BEFORE_RETURN_288 4294967296)))))) [2019-10-07 15:37:23,367 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:37:23,367 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:37:23,368 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:37:23,368 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:37:23,873 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:37:23,873 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 11] total 52 [2019-10-07 15:37:23,875 INFO L442 AbstractCegarLoop]: Interpolant automaton has 53 states [2019-10-07 15:37:23,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2019-10-07 15:37:23,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=890, Invalid=1866, Unknown=0, NotChecked=0, Total=2756 [2019-10-07 15:37:23,876 INFO L87 Difference]: Start difference. First operand 129 states and 133 transitions. Second operand 53 states. [2019-10-07 15:37:26,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:26,683 INFO L93 Difference]: Finished difference Result 186 states and 199 transitions. [2019-10-07 15:37:26,683 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2019-10-07 15:37:26,683 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 214 [2019-10-07 15:37:26,684 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:26,685 INFO L225 Difference]: With dead ends: 186 [2019-10-07 15:37:26,685 INFO L226 Difference]: Without dead ends: 138 [2019-10-07 15:37:26,687 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 722 GetRequests, 601 SyntacticMatches, 23 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2344 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=2661, Invalid=7239, Unknown=0, NotChecked=0, Total=9900 [2019-10-07 15:37:26,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2019-10-07 15:37:26,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2019-10-07 15:37:26,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2019-10-07 15:37:26,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 142 transitions. [2019-10-07 15:37:26,699 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 142 transitions. Word has length 214 [2019-10-07 15:37:26,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:26,699 INFO L462 AbstractCegarLoop]: Abstraction has 138 states and 142 transitions. [2019-10-07 15:37:26,699 INFO L463 AbstractCegarLoop]: Interpolant automaton has 53 states. [2019-10-07 15:37:26,699 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 142 transitions. [2019-10-07 15:37:26,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 224 [2019-10-07 15:37:26,700 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:26,700 INFO L385 BasicCegarLoop]: trace histogram [120, 40, 39, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:26,901 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:26,901 INFO L410 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:26,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:26,902 INFO L82 PathProgramCache]: Analyzing trace with hash -573932863, now seen corresponding path program 13 times [2019-10-07 15:37:26,902 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:26,902 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:26,903 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:26,903 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:26,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY