java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/sep60-2.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:37:23,438 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:37:23,441 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:37:23,457 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:37:23,457 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:37:23,459 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:37:23,460 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:37:23,462 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:37:23,474 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:37:23,475 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:37:23,477 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:37:23,478 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:37:23,479 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:37:23,480 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:37:23,481 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:37:23,483 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:37:23,485 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:37:23,486 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:37:23,489 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:37:23,494 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:37:23,495 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:37:23,496 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:37:23,497 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:37:23,498 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:37:23,500 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-10-07 15:37:23,500 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-10-07 15:37:23,500 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-10-07 15:37:23,501 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-10-07 15:37:23,502 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-10-07 15:37:23,502 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-10-07 15:37:23,503 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-07 15:37:23,503 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-07 15:37:23,504 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-07 15:37:23,505 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-07 15:37:23,506 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-07 15:37:23,506 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-07 15:37:23,506 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-07 15:37:23,507 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-07 15:37:23,507 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:37:23,508 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:37:23,509 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:37:23,509 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:37:23,523 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:37:23,524 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:37:23,525 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:37:23,525 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:37:23,525 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:37:23,526 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:37:23,526 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:37:23,526 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:37:23,526 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:37:23,526 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:37:23,527 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:37:23,527 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:37:23,527 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:37:23,527 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:37:23,527 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:37:23,528 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:37:23,528 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:37:23,528 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:37:23,528 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:37:23,528 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:37:23,529 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:37:23,529 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:37:23,529 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:37:23,529 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:37:23,529 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:37:23,530 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:37:23,530 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:37:23,530 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:37:23,530 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:37:23,822 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:37:23,843 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:37:23,846 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:37:23,849 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:37:23,849 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:37:23,850 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/sep60-2.i [2019-10-07 15:37:23,925 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/940b13770/65c5cb800c3a4c249d98bcdeea8883e6/FLAG8291f6303 [2019-10-07 15:37:24,402 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:37:24,403 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/sep60-2.i [2019-10-07 15:37:24,410 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/940b13770/65c5cb800c3a4c249d98bcdeea8883e6/FLAG8291f6303 [2019-10-07 15:37:24,778 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/940b13770/65c5cb800c3a4c249d98bcdeea8883e6 [2019-10-07 15:37:24,787 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:37:24,788 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:37:24,789 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:37:24,791 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:37:24,795 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:37:24,796 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:37:24" (1/1) ... [2019-10-07 15:37:24,799 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1568f796 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:24, skipping insertion in model container [2019-10-07 15:37:24,799 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:37:24" (1/1) ... [2019-10-07 15:37:24,808 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:37:24,827 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:37:25,032 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:37:25,041 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:37:25,071 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:37:25,168 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:37:25,168 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:25 WrapperNode [2019-10-07 15:37:25,168 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:37:25,169 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:37:25,169 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:37:25,169 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:37:25,182 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:25" (1/1) ... [2019-10-07 15:37:25,182 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:25" (1/1) ... [2019-10-07 15:37:25,189 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:25" (1/1) ... [2019-10-07 15:37:25,190 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:25" (1/1) ... [2019-10-07 15:37:25,198 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:25" (1/1) ... [2019-10-07 15:37:25,204 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:25" (1/1) ... [2019-10-07 15:37:25,206 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:25" (1/1) ... [2019-10-07 15:37:25,208 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:37:25,208 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:37:25,209 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:37:25,209 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:37:25,210 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:25" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:37:25,277 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:37:25,278 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:37:25,278 INFO L138 BoogieDeclarations]: Found implementation of procedure sep [2019-10-07 15:37:25,278 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:37:25,278 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:37:25,278 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:37:25,278 INFO L130 BoogieDeclarations]: Found specification of procedure sep [2019-10-07 15:37:25,279 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:37:25,279 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:37:25,279 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:37:25,279 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:37:25,279 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:37:25,279 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:37:25,279 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:37:25,707 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:37:25,708 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:37:25,709 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:37:25 BoogieIcfgContainer [2019-10-07 15:37:25,709 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:37:25,710 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:37:25,711 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:37:25,714 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:37:25,714 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:37:24" (1/3) ... [2019-10-07 15:37:25,715 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5ffaba17 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:37:25, skipping insertion in model container [2019-10-07 15:37:25,715 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:25" (2/3) ... [2019-10-07 15:37:25,716 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5ffaba17 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:37:25, skipping insertion in model container [2019-10-07 15:37:25,716 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:37:25" (3/3) ... [2019-10-07 15:37:25,718 INFO L109 eAbstractionObserver]: Analyzing ICFG sep60-2.i [2019-10-07 15:37:25,726 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:37:25,738 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:37:25,749 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:37:25,772 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:37:25,772 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:37:25,772 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:37:25,772 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:37:25,773 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:37:25,773 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:37:25,773 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:37:25,773 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:37:25,789 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:37:25,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:37:25,795 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:25,795 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:25,797 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:25,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:25,802 INFO L82 PathProgramCache]: Analyzing trace with hash -1553264816, now seen corresponding path program 1 times [2019-10-07 15:37:25,808 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:25,809 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:25,809 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:25,809 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:25,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:25,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:25,993 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:37:25,994 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:25,994 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:37:25,995 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:37:25,999 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:37:26,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:37:26,012 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:37:26,014 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:37:26,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:26,054 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:37:26,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:37:26,056 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:37:26,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:26,066 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:37:26,066 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:37:26,069 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:37:26,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:37:26,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:37:26,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:37:26,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:37:26,106 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:37:26,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:26,107 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:37:26,107 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:37:26,107 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:37:26,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:37:26,109 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:26,109 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:26,110 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:26,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:26,110 INFO L82 PathProgramCache]: Analyzing trace with hash -1274606805, now seen corresponding path program 1 times [2019-10-07 15:37:26,111 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:26,111 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:26,111 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:26,111 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:26,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:26,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:26,180 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:37:26,180 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:26,180 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:37:26,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:26,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:26,286 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:37:26,298 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:37:26,334 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:37:26,334 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:37:26,377 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:37:26,377 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:37:26,377 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:37:26,379 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:37:26,380 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:37:26,380 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:37:26,380 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:37:26,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:26,392 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:37:26,392 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:37:26,392 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:37:26,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:26,394 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:37:26,394 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:37:26,395 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:37:26,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:37:26,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:37:26,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:37:26,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:37:26,401 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:37:26,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:26,402 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:37:26,402 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:37:26,402 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:37:26,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:37:26,403 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:26,403 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:26,613 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:26,613 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:26,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:26,614 INFO L82 PathProgramCache]: Analyzing trace with hash -544560989, now seen corresponding path program 1 times [2019-10-07 15:37:26,615 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:26,615 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:26,616 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:26,621 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:26,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:26,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:26,745 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:37:26,745 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:26,746 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:37:26,746 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:37:26,746 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:37:26,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:37:26,747 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:37:26,747 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:37:26,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:26,766 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:37:26,766 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:37:26,767 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:37:26,767 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:26,768 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:37:26,768 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:37:26,769 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:37:26,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:37:26,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:37:26,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:37:26,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:37:26,775 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:37:26,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:26,777 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:37:26,778 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:37:26,778 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:37:26,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:37:26,780 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:26,781 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:26,781 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:26,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:26,782 INFO L82 PathProgramCache]: Analyzing trace with hash -5957836, now seen corresponding path program 1 times [2019-10-07 15:37:26,782 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:26,782 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:26,782 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:26,783 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:26,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:26,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:26,909 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:37:26,909 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:26,909 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:37:26,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:27,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:27,002 INFO L256 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:37:27,005 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:37:27,046 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:37:27,048 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:37:27,103 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:37:27,104 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:37:27,143 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:37:27,143 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:37:27,153 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:37:27,167 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:37:27,168 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:37:27,372 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:37:29,360 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:37:29,430 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:37:29,436 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:37:29,436 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:37:29,437 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:37:29,437 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_2 Int) (v_prenex_1 Int) (v_sep_~ret~0_BEFORE_RETURN_2 Int) (v_sep_~ret~0_BEFORE_RETURN_1 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~ret~1 (mod v_prenex_2 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_2 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~ret~1 (mod v_prenex_1 4294967296)) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_2 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647)) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_1 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:37:29,437 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:37:29,437 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:37:29,437 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:37:29,438 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:37:29,438 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_sep_~ret~0_BEFORE_RETURN_6 Int) (v_sep_~ret~0_BEFORE_RETURN_5 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_6 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_29 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_29 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_5 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_sep_~ret~0_BEFORE_RETURN_6 Int) (v_sep_~ret~0_BEFORE_RETURN_5 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_6 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_prenex_30 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_30 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_29 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_29 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_5 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:37:29,438 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:29,438 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:29,439 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:29,439 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:37:29,439 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:37:29,439 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:37:29,440 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:37:29,440 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_2 Int) (v_sep_~ret~0_BEFORE_RETURN_2 Int)) (or (and (= (mod v_prenex_2 4294967296) |main_#t~ret6|) (not (< main_~i~1 60)) (<= (mod v_prenex_2 4294967296) 2147483647)) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_2 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647))))) (exists ((v_prenex_1 Int) (v_sep_~ret~0_BEFORE_RETURN_1 Int)) (or (and (= (mod v_prenex_1 4294967296) |main_#t~ret6|) (not (< main_~i~1 60)) (<= (mod v_prenex_1 4294967296) 2147483647)) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_1 4294967296) (- 4294967296)) |main_#t~ret6|))))) [2019-10-07 15:37:29,440 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:37:29,440 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:37:29,441 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:37:29,441 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:37:29,829 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:37:29,829 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:37:29,831 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-07 15:37:29,831 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-07 15:37:29,832 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-07 15:37:29,834 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-07 15:37:34,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:34,730 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:37:34,730 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-07 15:37:34,730 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-07 15:37:34,730 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:34,731 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:37:34,731 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:37:34,733 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 197 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=133, Invalid=736, Unknown=1, NotChecked=0, Total=870 [2019-10-07 15:37:34,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:37:34,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:37:34,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:37:34,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:37:34,739 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:37:34,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:34,740 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:37:34,740 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-07 15:37:34,740 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:37:34,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:37:34,741 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:34,741 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:34,952 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:34,952 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:34,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:34,953 INFO L82 PathProgramCache]: Analyzing trace with hash -1961836647, now seen corresponding path program 2 times [2019-10-07 15:37:34,953 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:34,954 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:34,954 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:34,954 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:34,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:34,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:35,033 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:37:35,034 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:35,034 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:37:35,034 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:35,121 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:37:35,122 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:37:35,123 INFO L256 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:37:35,125 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:37:35,175 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:37:35,175 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:37:35,211 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:37:35,212 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:37:35,216 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:37:35,216 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:37:35,217 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:37:35,217 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:37:35,217 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:37:35,244 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:37:36,791 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:37:36,832 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:37:36,836 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:37:36,836 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:37:36,837 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:37:36,837 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_196 Int) (v_sep_~ret~0_BEFORE_RETURN_28 Int) (v_sep_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_195 4294967296) main_~ret~1) (<= (mod v_prenex_195 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_28 4294967296) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:37:36,837 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:37:36,843 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:37:36,844 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:37:36,844 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:37:36,846 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (exists ((v_sep_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_sep_~ret~0_BEFORE_RETURN_32 Int) (v_prenex_223 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_223 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_223 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_31 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_sep_~ret~0_BEFORE_RETURN_32 Int) (v_prenex_223 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_223 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_223 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_31 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:37:36,846 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:36,846 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:36,846 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:36,846 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:37:36,846 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:37:36,847 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:37:36,847 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:37:36,847 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (not (< main_~i~1 60))) (and (= (mod v_prenex_195 4294967296) |main_#t~ret6|) (not (< main_~i~1 60)) (<= (mod v_prenex_195 4294967296) 2147483647)))) (exists ((v_prenex_196 Int) (v_sep_~ret~0_BEFORE_RETURN_28 Int)) (or (and (not (<= (mod v_prenex_196 4294967296) 2147483647)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60))) (and (not (< main_~i~1 60)) (= (mod v_sep_~ret~0_BEFORE_RETURN_28 4294967296) |main_#t~ret6|) (<= (mod v_sep_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647))))) [2019-10-07 15:37:36,847 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:37:36,847 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:37:36,848 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:37:36,848 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:37:37,209 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:37:37,210 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:37:37,211 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-07 15:37:37,211 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-07 15:37:37,212 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-07 15:37:37,212 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-07 15:37:38,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:38,198 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:37:38,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:37:38,198 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-07 15:37:38,198 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:38,199 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:37:38,199 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:37:38,200 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-07 15:37:38,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:37:38,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:37:38,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:37:38,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:37:38,207 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:37:38,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:38,207 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:37:38,207 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-07 15:37:38,208 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:37:38,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:37:38,209 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:38,209 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:38,413 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:38,414 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:38,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:38,414 INFO L82 PathProgramCache]: Analyzing trace with hash 1603069542, now seen corresponding path program 3 times [2019-10-07 15:37:38,415 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:38,415 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:38,415 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:38,415 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:38,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:38,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:38,538 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:37:38,538 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:38,538 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:37:38,538 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:38,661 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:37:38,661 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:37:38,663 INFO L256 TraceCheckSpWp]: Trace formula consists of 199 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:37:38,677 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:37:38,686 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:37:38,686 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:37:38,764 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:37:38,765 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:37:38,767 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:37:38,767 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:37:38,767 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:37:38,768 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:37:38,768 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:37:38,787 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:37:40,360 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:37:40,405 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:37:40,409 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:37:40,410 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:37:40,410 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:37:40,411 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int) (v_sep_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (<= main_~ret~1 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (mod v_prenex_389 4294967296) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_sep_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int) (v_sep_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (<= main_~ret~1 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (mod v_prenex_389 4294967296) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:37:40,411 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:37:40,412 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:37:40,412 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:37:40,412 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:37:40,413 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_417 Int) (v_sep_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_418 Int) (v_sep_~ret~0_BEFORE_RETURN_58 Int)) (or (and (not (< main_~i~2 59)) (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_58 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_prenex_417 Int) (v_sep_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_418 Int) (v_sep_~ret~0_BEFORE_RETURN_58 Int)) (or (and (not (< main_~i~2 59)) (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_58 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:37:40,413 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:40,413 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:40,414 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:40,414 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:37:40,414 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:37:40,415 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:37:40,415 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:37:40,415 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int)) (or (and (not (< main_~i~1 60)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_53 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (not (< main_~i~1 60)) (<= (mod v_prenex_389 4294967296) 2147483647) (= (mod v_prenex_389 4294967296) |main_#t~ret6|)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) |main_#t~ret6|) (not (< main_~i~1 60)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647)) (and (not (< main_~i~1 60)) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_prenex_390 4294967296) (- 4294967296))))))) [2019-10-07 15:37:40,416 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:37:40,416 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:37:40,416 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:37:40,416 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:37:40,923 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:37:40,923 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-07 15:37:40,924 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-07 15:37:40,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-07 15:37:40,925 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-07 15:37:40,925 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-07 15:37:41,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:41,890 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-07 15:37:41,890 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-07 15:37:41,890 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-07 15:37:41,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:41,891 INFO L225 Difference]: With dead ends: 54 [2019-10-07 15:37:41,892 INFO L226 Difference]: Without dead ends: 36 [2019-10-07 15:37:41,893 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-07 15:37:41,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-07 15:37:41,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-07 15:37:41,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-07 15:37:41,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-07 15:37:41,900 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-07 15:37:41,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:41,901 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-07 15:37:41,901 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-07 15:37:41,901 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-07 15:37:41,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-07 15:37:41,902 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:41,903 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:42,107 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:42,108 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:42,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:42,109 INFO L82 PathProgramCache]: Analyzing trace with hash 1700782945, now seen corresponding path program 4 times [2019-10-07 15:37:42,109 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:42,109 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:42,109 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:42,110 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:42,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:42,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:42,295 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:37:42,295 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:42,295 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:37:42,295 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:42,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:42,445 INFO L256 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:37:42,449 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:37:42,459 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:37:42,459 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:37:42,755 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:37:42,755 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:37:42,757 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:37:42,757 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:37:42,758 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:37:42,758 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:37:42,758 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:37:42,781 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:37:44,013 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:37:44,039 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:37:44,042 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:37:44,042 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:37:44,042 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:37:44,042 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(or (exists ((v_prenex_583 Int) (v_prenex_584 Int) (v_sep_~ret~0_BEFORE_RETURN_80 Int) (v_sep_~ret~0_BEFORE_RETURN_79 Int)) (or (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= (mod v_prenex_584 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_584 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_583 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_prenex_583 Int) (v_prenex_584 Int) (v_sep_~ret~0_BEFORE_RETURN_80 Int) (v_sep_~ret~0_BEFORE_RETURN_79 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) main_~ret~1) (<= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= (mod v_prenex_584 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_584 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_583 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:37:44,043 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:37:44,043 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:37:44,043 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:37:44,043 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:37:44,043 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_sep_~ret~0_BEFORE_RETURN_84 Int) (v_sep_~ret~0_BEFORE_RETURN_83 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_prenex_611 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_sep_~ret~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_sep_~ret~0_BEFORE_RETURN_84 Int) (v_sep_~ret~0_BEFORE_RETURN_83 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_prenex_611 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_sep_~ret~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:37:44,044 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:44,044 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:44,044 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:44,044 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:37:44,044 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:37:44,045 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:37:44,045 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:37:44,045 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_583 Int) (v_sep_~ret~0_BEFORE_RETURN_79 Int)) (or (and (= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) |main_#t~ret6|) (not (< main_~i~1 60)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647)) (and (= (+ (mod v_prenex_583 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_prenex_583 4294967296) 2147483647))))) (exists ((v_prenex_584 Int) (v_sep_~ret~0_BEFORE_RETURN_80 Int)) (or (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647))) (and (not (< main_~i~1 60)) (= (mod v_prenex_584 4294967296) |main_#t~ret6|) (<= (mod v_prenex_584 4294967296) 2147483647))))) [2019-10-07 15:37:44,045 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:37:44,045 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:37:44,045 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:37:44,046 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:37:44,437 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:37:44,437 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-07 15:37:44,439 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-07 15:37:44,440 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-07 15:37:44,440 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:37:44,440 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 40 states. [2019-10-07 15:37:46,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:46,056 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-07 15:37:46,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-07 15:37:46,056 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 49 [2019-10-07 15:37:46,056 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:46,058 INFO L225 Difference]: With dead ends: 68 [2019-10-07 15:37:46,058 INFO L226 Difference]: Without dead ends: 50 [2019-10-07 15:37:46,061 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:37:46,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-07 15:37:46,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-07 15:37:46,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-07 15:37:46,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-07 15:37:46,070 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-07 15:37:46,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:46,070 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-07 15:37:46,070 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-07 15:37:46,070 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-07 15:37:46,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-07 15:37:46,071 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:46,072 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:46,286 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:46,287 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:46,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:46,287 INFO L82 PathProgramCache]: Analyzing trace with hash -1773432895, now seen corresponding path program 5 times [2019-10-07 15:37:46,288 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:46,288 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:46,288 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:46,288 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:46,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:46,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:46,742 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:37:46,742 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:46,742 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:37:46,743 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:46,910 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:37:46,910 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:37:46,911 INFO L256 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:37:46,914 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:37:46,958 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-07 15:37:46,958 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:37:47,008 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-07 15:37:47,008 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:37:47,009 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:37:47,010 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:37:47,010 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:37:47,010 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:37:47,011 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:37:47,029 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:37:48,329 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:37:48,357 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:37:48,359 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:37:48,360 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:37:48,360 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:37:48,360 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_777 Int) (v_sep_~ret~0_BEFORE_RETURN_105 Int) (v_sep_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_105 4294967296)) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_777 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_777 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:37:48,360 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:37:48,360 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:37:48,360 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:37:48,361 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:37:48,361 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (exists ((v_sep_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_806 Int) (v_sep_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_805 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_109 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_805 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_805 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_806 Int) (v_sep_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_805 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_109 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_805 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_805 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:37:48,361 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:48,361 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:37:48,362 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:48,362 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:37:48,362 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:37:48,362 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:37:48,362 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:37:48,362 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (not (< main_~i~1 60)) (= |main_#t~ret6| (+ (mod v_sep_~ret~0_BEFORE_RETURN_106 4294967296) (- 4294967296)))) (and (not (< main_~i~1 60)) (= |main_#t~ret6| (mod v_prenex_778 4294967296)) (<= (mod v_prenex_778 4294967296) 2147483647)))) (exists ((v_prenex_777 Int) (v_sep_~ret~0_BEFORE_RETURN_105 Int)) (or (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret6| (mod v_sep_~ret~0_BEFORE_RETURN_105 4294967296))) (and (not (<= (mod v_prenex_777 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_prenex_777 4294967296) (- 4294967296)) |main_#t~ret6|))))) [2019-10-07 15:37:48,363 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:37:48,363 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:37:48,363 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:37:48,363 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:37:48,925 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:37:48,926 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-07 15:37:48,927 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-07 15:37:48,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-07 15:37:48,928 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-07 15:37:48,928 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 44 states. [2019-10-07 15:37:51,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:51,197 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-07 15:37:51,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-07 15:37:51,197 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 63 [2019-10-07 15:37:51,198 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:51,199 INFO L225 Difference]: With dead ends: 72 [2019-10-07 15:37:51,199 INFO L226 Difference]: Without dead ends: 54 [2019-10-07 15:37:51,202 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1350 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1349, Invalid=5457, Unknown=0, NotChecked=0, Total=6806 [2019-10-07 15:37:51,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-07 15:37:51,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-07 15:37:51,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-07 15:37:51,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-07 15:37:51,211 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-07 15:37:51,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:51,211 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-07 15:37:51,211 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-07 15:37:51,211 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-07 15:37:51,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-07 15:37:51,213 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:51,213 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:51,416 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:51,417 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:51,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:51,417 INFO L82 PathProgramCache]: Analyzing trace with hash -806625269, now seen corresponding path program 6 times [2019-10-07 15:37:51,418 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:51,418 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:51,418 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:51,418 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:51,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:51,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:51,902 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:37:51,902 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:51,902 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:37:51,902 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:52,146 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:37:52,147 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:37:52,149 INFO L256 TraceCheckSpWp]: Trace formula consists of 343 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-07 15:37:52,152 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:37:52,175 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:37:52,175 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:37:53,090 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:37:53,090 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:37:53,092 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:37:53,092 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:37:53,092 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:37:53,093 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:37:53,093 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:37:53,116 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:37:54,397 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:37:54,450 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:37:54,454 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:37:54,455 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:37:54,455 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:37:54,455 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_131 Int) (v_sep_~ret~0_BEFORE_RETURN_132 Int) (v_prenex_972 Int) (v_prenex_971 Int)) (or (and (= main_~ret~1 (mod v_prenex_972 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_972 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~ret~1 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_131 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:37:54,456 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:37:54,456 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:37:54,456 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:37:54,456 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:37:54,457 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (exists ((v_sep_~ret~0_BEFORE_RETURN_135 Int) (v_sep_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_999 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_999 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_135 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_1000 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_135 Int) (v_sep_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_999 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_999 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_135 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_1000 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:37:54,457 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:54,458 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:54,458 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:37:54,458 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:37:54,458 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:37:54,459 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:37:54,459 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:37:54,459 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_132 Int) (v_prenex_972 Int)) (or (and (= (mod v_prenex_972 4294967296) |main_#t~ret6|) (not (< main_~i~1 60)) (<= (mod v_prenex_972 4294967296) 2147483647)) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) |main_#t~ret6|)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_131 Int) (v_prenex_971 Int)) (or (and (= |main_#t~ret6| (mod v_sep_~ret~0_BEFORE_RETURN_131 4294967296)) (not (< main_~i~1 60)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (= (+ (mod v_prenex_971 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)))))) [2019-10-07 15:37:54,460 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:37:54,460 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:37:54,460 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:37:54,460 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:37:54,985 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:37:54,985 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-07 15:37:54,986 INFO L442 AbstractCegarLoop]: Interpolant automaton has 70 states [2019-10-07 15:37:54,987 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2019-10-07 15:37:54,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1740, Invalid=3090, Unknown=0, NotChecked=0, Total=4830 [2019-10-07 15:37:54,989 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 70 states. [2019-10-07 15:37:58,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:58,295 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-07 15:37:58,296 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2019-10-07 15:37:58,296 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 67 [2019-10-07 15:37:58,296 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:37:58,298 INFO L225 Difference]: With dead ends: 104 [2019-10-07 15:37:58,298 INFO L226 Difference]: Without dead ends: 83 [2019-10-07 15:37:58,303 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3929 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=5099, Invalid=12723, Unknown=0, NotChecked=0, Total=17822 [2019-10-07 15:37:58,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-07 15:37:58,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-07 15:37:58,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-07 15:37:58,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-07 15:37:58,312 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-07 15:37:58,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:37:58,313 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-07 15:37:58,313 INFO L463 AbstractCegarLoop]: Interpolant automaton has 70 states. [2019-10-07 15:37:58,313 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-07 15:37:58,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-07 15:37:58,314 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:58,315 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:58,518 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:37:58,519 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:58,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:58,519 INFO L82 PathProgramCache]: Analyzing trace with hash 1712308368, now seen corresponding path program 7 times [2019-10-07 15:37:58,520 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:58,520 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:58,520 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:58,521 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:58,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:58,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:59,903 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:37:59,903 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:59,903 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:37:59,904 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:00,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:00,187 INFO L256 TraceCheckSpWp]: Trace formula consists of 517 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-07 15:38:00,190 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:00,213 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:38:00,213 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:01,715 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:38:01,716 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:01,717 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:01,717 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:01,718 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:01,718 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:01,718 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:01,733 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:03,020 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:38:03,050 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:03,052 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:03,053 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:03,053 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:03,053 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_157 Int) (v_sep_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int) (v_prenex_1165 Int)) (or (and (<= main_~ret~1 2147483647) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1165 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1166 4294967296)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sep_~ret~0_BEFORE_RETURN_157 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:03,053 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:03,054 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:38:03,054 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:38:03,054 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:38:03,054 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (exists ((v_prenex_1194 Int) (v_sep_~ret~0_BEFORE_RETURN_161 Int) (v_prenex_1193 Int) (v_sep_~ret~0_BEFORE_RETURN_162 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_161 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (exists ((v_prenex_1194 Int) (v_sep_~ret~0_BEFORE_RETURN_161 Int) (v_prenex_1193 Int) (v_sep_~ret~0_BEFORE_RETURN_162 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_161 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_1193 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1193 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret2~0)))) [2019-10-07 15:38:03,054 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:03,054 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:03,055 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:03,055 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:38:03,055 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:03,055 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:03,055 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:38:03,055 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (<= (mod v_prenex_1166 4294967296) 2147483647) (= (mod v_prenex_1166 4294967296) |main_#t~ret6|) (not (< main_~i~1 60))))) (exists ((v_sep_~ret~0_BEFORE_RETURN_157 Int) (v_prenex_1165 Int)) (or (and (= (mod v_sep_~ret~0_BEFORE_RETURN_157 4294967296) |main_#t~ret6|) (<= (mod v_sep_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647) (not (< main_~i~1 60))) (and (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_prenex_1165 4294967296) 2147483647)))))) [2019-10-07 15:38:03,055 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:38:03,055 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:38:03,056 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:38:03,056 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:38:03,706 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:03,707 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 73 [2019-10-07 15:38:03,708 INFO L442 AbstractCegarLoop]: Interpolant automaton has 74 states [2019-10-07 15:38:03,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2019-10-07 15:38:03,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1982, Invalid=3420, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:38:03,711 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 74 states. [2019-10-07 15:38:07,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:07,684 INFO L93 Difference]: Finished difference Result 108 states and 119 transitions. [2019-10-07 15:38:07,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2019-10-07 15:38:07,684 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 96 [2019-10-07 15:38:07,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:07,685 INFO L225 Difference]: With dead ends: 108 [2019-10-07 15:38:07,685 INFO L226 Difference]: Without dead ends: 87 [2019-10-07 15:38:07,691 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 417 GetRequests, 223 SyntacticMatches, 54 SemanticMatches, 140 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5139 ImplicationChecksByTransitivity, 6.9s TimeCoverageRelationStatistics Valid=5817, Invalid=14205, Unknown=0, NotChecked=0, Total=20022 [2019-10-07 15:38:07,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2019-10-07 15:38:07,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2019-10-07 15:38:07,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2019-10-07 15:38:07,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 91 transitions. [2019-10-07 15:38:07,707 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 91 transitions. Word has length 96 [2019-10-07 15:38:07,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:07,707 INFO L462 AbstractCegarLoop]: Abstraction has 87 states and 91 transitions. [2019-10-07 15:38:07,707 INFO L463 AbstractCegarLoop]: Interpolant automaton has 74 states. [2019-10-07 15:38:07,707 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 91 transitions. [2019-10-07 15:38:07,709 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2019-10-07 15:38:07,709 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:07,709 INFO L385 BasicCegarLoop]: trace histogram [60, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:07,914 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:07,915 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:07,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:07,915 INFO L82 PathProgramCache]: Analyzing trace with hash 127704912, now seen corresponding path program 8 times [2019-10-07 15:38:07,916 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:07,916 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:07,916 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:07,916 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:07,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:08,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:08,079 INFO L134 CoverageAnalysis]: Checked inductivity of 1951 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 1941 trivial. 0 not checked. [2019-10-07 15:38:08,080 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:08,080 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:08,080 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:08,323 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:38:08,323 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:08,325 INFO L256 TraceCheckSpWp]: Trace formula consists of 147 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:38:08,327 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:08,370 INFO L134 CoverageAnalysis]: Checked inductivity of 1951 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 1889 trivial. 0 not checked. [2019-10-07 15:38:08,370 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:08,446 INFO L134 CoverageAnalysis]: Checked inductivity of 1951 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 1889 trivial. 0 not checked. [2019-10-07 15:38:08,446 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:08,448 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:08,448 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:08,448 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:08,449 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:08,449 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:08,460 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:09,684 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:38:09,713 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:09,716 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:09,716 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:09,716 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:09,717 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_1359 Int) (v_prenex_1360 Int) (v_sep_~ret~0_BEFORE_RETURN_183 Int) (v_sep_~ret~0_BEFORE_RETURN_184 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_1360 4294967296)) (<= (mod v_prenex_1360 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_183 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1359 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1359 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_184 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:09,717 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:09,717 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:38:09,717 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:38:09,717 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:38:09,718 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_187 Int) (v_sep_~ret~0_BEFORE_RETURN_188 Int) (v_prenex_1388 Int) (v_prenex_1387 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= (mod v_prenex_1388 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_188 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_sep_~ret~0_BEFORE_RETURN_187 4294967296) main_~ret5~0) (<= (mod v_sep_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_1387 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1387 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_sep_~ret~0_BEFORE_RETURN_187 Int) (v_sep_~ret~0_BEFORE_RETURN_188 Int) (v_prenex_1388 Int) (v_prenex_1387 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= (mod v_prenex_1388 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_188 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_sep_~ret~0_BEFORE_RETURN_187 4294967296) main_~ret5~0) (<= (mod v_sep_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_1387 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1387 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:09,718 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:09,718 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:09,718 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:09,719 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:38:09,719 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:09,719 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:09,719 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:38:09,720 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_1359 Int) (v_sep_~ret~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 60)) (= (mod v_prenex_1359 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1359 4294967296) 2147483647)) (and (not (< main_~i~1 60)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_sep_~ret~0_BEFORE_RETURN_183 4294967296) (- 4294967296)))))) (exists ((v_prenex_1360 Int) (v_sep_~ret~0_BEFORE_RETURN_184 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_184 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60))) (and (= (mod v_prenex_1360 4294967296) |main_#t~ret6|) (not (< main_~i~1 60)) (<= (mod v_prenex_1360 4294967296) 2147483647))))) [2019-10-07 15:38:09,720 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:38:09,720 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:38:09,720 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:38:09,720 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:38:10,061 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:10,062 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 27 [2019-10-07 15:38:10,063 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-10-07 15:38:10,063 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-10-07 15:38:10,064 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=641, Unknown=0, NotChecked=0, Total=756 [2019-10-07 15:38:10,064 INFO L87 Difference]: Start difference. First operand 87 states and 91 transitions. Second operand 28 states. [2019-10-07 15:38:13,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:13,226 INFO L93 Difference]: Finished difference Result 114 states and 130 transitions. [2019-10-07 15:38:13,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-10-07 15:38:13,226 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 100 [2019-10-07 15:38:13,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:13,228 INFO L225 Difference]: With dead ends: 114 [2019-10-07 15:38:13,228 INFO L226 Difference]: Without dead ends: 94 [2019-10-07 15:38:13,229 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 329 GetRequests, 280 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 581 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=409, Invalid=2141, Unknown=0, NotChecked=0, Total=2550 [2019-10-07 15:38:13,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2019-10-07 15:38:13,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 94. [2019-10-07 15:38:13,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2019-10-07 15:38:13,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 98 transitions. [2019-10-07 15:38:13,241 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 98 transitions. Word has length 100 [2019-10-07 15:38:13,241 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:13,241 INFO L462 AbstractCegarLoop]: Abstraction has 94 states and 98 transitions. [2019-10-07 15:38:13,241 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-10-07 15:38:13,241 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 98 transitions. [2019-10-07 15:38:13,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2019-10-07 15:38:13,243 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:13,243 INFO L385 BasicCegarLoop]: trace histogram [60, 30, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:13,446 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:13,447 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:13,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:13,448 INFO L82 PathProgramCache]: Analyzing trace with hash 638131873, now seen corresponding path program 9 times [2019-10-07 15:38:13,448 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:13,449 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:13,449 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:13,450 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:13,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:13,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:13,693 INFO L134 CoverageAnalysis]: Checked inductivity of 2379 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 2080 trivial. 0 not checked. [2019-10-07 15:38:13,693 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:13,693 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:13,694 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:14,049 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:38:14,050 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:14,053 INFO L256 TraceCheckSpWp]: Trace formula consists of 617 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-07 15:38:14,057 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:14,087 INFO L134 CoverageAnalysis]: Checked inductivity of 2379 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 2080 trivial. 0 not checked. [2019-10-07 15:38:14,087 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:14,267 INFO L134 CoverageAnalysis]: Checked inductivity of 2379 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 2080 trivial. 0 not checked. [2019-10-07 15:38:14,267 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:14,268 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:14,268 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:14,269 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:14,270 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:14,270 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:14,290 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:15,474 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:38:15,503 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:15,505 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:15,505 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:15,506 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:15,506 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_sep_~ret~0_BEFORE_RETURN_209 Int)) (or (and (<= main_~ret~1 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_209 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1554 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1554 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (+ (mod v_prenex_1553 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (not (<= (mod v_prenex_1553 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:15,506 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:15,506 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:38:15,506 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:38:15,506 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:38:15,506 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_213 Int) (v_sep_~ret~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_213 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_1581 4294967296)) (<= (mod v_prenex_1581 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_214 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_sep_~ret~0_BEFORE_RETURN_213 Int) (v_sep_~ret~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_prenex_1582 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1582 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_213 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_1581 4294967296)) (<= (mod v_prenex_1581 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_214 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:15,507 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:15,507 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:38:15,507 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:15,507 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:38:15,507 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:15,507 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:15,507 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:38:15,507 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_1553 Int) (v_sep_~ret~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 60)) (not (<= (mod v_prenex_1553 4294967296) 2147483647)) (= (+ (mod v_prenex_1553 4294967296) (- 4294967296)) |main_#t~ret6|)) (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret6| (mod v_sep_~ret~0_BEFORE_RETURN_209 4294967296))))) (exists ((v_sep_~ret~0_BEFORE_RETURN_210 Int) (v_prenex_1554 Int)) (or (and (not (< main_~i~1 60)) (= (mod v_prenex_1554 4294967296) |main_#t~ret6|) (<= (mod v_prenex_1554 4294967296) 2147483647)) (and (= |main_#t~ret6| (+ (mod v_sep_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (not (< main_~i~1 60)))))) [2019-10-07 15:38:15,507 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:38:15,508 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:38:15,508 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:38:15,508 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:38:15,837 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:15,838 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 11] total 35 [2019-10-07 15:38:15,839 INFO L442 AbstractCegarLoop]: Interpolant automaton has 36 states [2019-10-07 15:38:15,840 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2019-10-07 15:38:15,840 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=330, Invalid=930, Unknown=0, NotChecked=0, Total=1260 [2019-10-07 15:38:15,840 INFO L87 Difference]: Start difference. First operand 94 states and 98 transitions. Second operand 36 states. [2019-10-07 15:38:17,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:17,526 INFO L93 Difference]: Finished difference Result 133 states and 154 transitions. [2019-10-07 15:38:17,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-10-07 15:38:17,527 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 119 [2019-10-07 15:38:17,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:17,528 INFO L225 Difference]: With dead ends: 133 [2019-10-07 15:38:17,528 INFO L226 Difference]: Without dead ends: 106 [2019-10-07 15:38:17,529 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 399 GetRequests, 335 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1043 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1067, Invalid=3223, Unknown=0, NotChecked=0, Total=4290 [2019-10-07 15:38:17,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2019-10-07 15:38:17,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 106. [2019-10-07 15:38:17,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2019-10-07 15:38:17,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 110 transitions. [2019-10-07 15:38:17,541 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 110 transitions. Word has length 119 [2019-10-07 15:38:17,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:17,541 INFO L462 AbstractCegarLoop]: Abstraction has 106 states and 110 transitions. [2019-10-07 15:38:17,541 INFO L463 AbstractCegarLoop]: Interpolant automaton has 36 states. [2019-10-07 15:38:17,541 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 110 transitions. [2019-10-07 15:38:17,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2019-10-07 15:38:17,543 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:17,543 INFO L385 BasicCegarLoop]: trace histogram [66, 60, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:17,745 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:17,746 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:17,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:17,747 INFO L82 PathProgramCache]: Analyzing trace with hash -2051260511, now seen corresponding path program 10 times [2019-10-07 15:38:17,747 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:17,747 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:17,747 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:17,748 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:17,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:18,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:18,550 INFO L134 CoverageAnalysis]: Checked inductivity of 4197 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 4182 trivial. 0 not checked. [2019-10-07 15:38:18,550 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:18,550 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:18,550 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:18,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:19,002 INFO L256 TraceCheckSpWp]: Trace formula consists of 761 conjuncts, 24 conjunts are in the unsatisfiable core [2019-10-07 15:38:19,006 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:19,411 INFO L134 CoverageAnalysis]: Checked inductivity of 4197 backedges. 1060 proven. 253 refuted. 0 times theorem prover too weak. 2884 trivial. 0 not checked. [2019-10-07 15:38:19,411 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:20,157 INFO L134 CoverageAnalysis]: Checked inductivity of 4197 backedges. 0 proven. 1313 refuted. 0 times theorem prover too weak. 2884 trivial. 0 not checked. [2019-10-07 15:38:20,158 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:20,159 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:20,159 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:20,160 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:20,160 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:20,160 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:20,173 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:21,373 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:38:21,403 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:21,405 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:21,406 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:21,406 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:21,406 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_235 Int) (v_sep_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int) (v_prenex_1747 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1747 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_1747 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_235 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_235 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_236 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_236 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_prenex_1748 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (not (<= (mod v_prenex_1748 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:21,406 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:21,406 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:38:21,406 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:38:21,407 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:38:21,407 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1776 Int) (v_prenex_1775 Int) (v_sep_~ret~0_BEFORE_RETURN_239 Int) (v_sep_~ret~0_BEFORE_RETURN_240 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_prenex_1775 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_239 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_240 4294967296) (- 4294967296))) (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_240 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1776 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1776 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_prenex_1776 Int) (v_prenex_1775 Int) (v_sep_~ret~0_BEFORE_RETURN_239 Int) (v_sep_~ret~0_BEFORE_RETURN_240 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_prenex_1775 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_239 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_240 4294967296) (- 4294967296))) (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_240 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1776 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_1776 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:21,407 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:21,407 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:21,407 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:21,408 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:38:21,408 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:21,408 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:21,408 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:38:21,408 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int)) (or (and (= (+ (mod v_prenex_1748 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_prenex_1748 4294967296) 2147483647))) (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_236 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_sep_~ret~0_BEFORE_RETURN_236 4294967296) |main_#t~ret6|)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_235 Int) (v_prenex_1747 Int)) (or (and (= (mod v_prenex_1747 4294967296) |main_#t~ret6|) (not (< main_~i~1 60)) (<= (mod v_prenex_1747 4294967296) 2147483647)) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_235 4294967296) 2147483647)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_235 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)))))) [2019-10-07 15:38:21,408 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:38:21,408 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:38:21,409 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:38:21,409 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:38:21,958 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:21,958 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 25, 25, 11] total 64 [2019-10-07 15:38:21,959 INFO L442 AbstractCegarLoop]: Interpolant automaton has 65 states [2019-10-07 15:38:21,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2019-10-07 15:38:21,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1184, Invalid=2976, Unknown=0, NotChecked=0, Total=4160 [2019-10-07 15:38:21,960 INFO L87 Difference]: Start difference. First operand 106 states and 110 transitions. Second operand 65 states. [2019-10-07 15:38:26,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:26,273 INFO L93 Difference]: Finished difference Result 170 states and 204 transitions. [2019-10-07 15:38:26,274 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2019-10-07 15:38:26,274 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 155 [2019-10-07 15:38:26,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:26,275 INFO L225 Difference]: With dead ends: 170 [2019-10-07 15:38:26,275 INFO L226 Difference]: Without dead ends: 131 [2019-10-07 15:38:26,277 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 533 GetRequests, 410 SyntacticMatches, 0 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3411 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=3834, Invalid=11666, Unknown=0, NotChecked=0, Total=15500 [2019-10-07 15:38:26,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2019-10-07 15:38:26,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 131. [2019-10-07 15:38:26,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2019-10-07 15:38:26,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 135 transitions. [2019-10-07 15:38:26,290 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 135 transitions. Word has length 155 [2019-10-07 15:38:26,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:26,291 INFO L462 AbstractCegarLoop]: Abstraction has 131 states and 135 transitions. [2019-10-07 15:38:26,291 INFO L463 AbstractCegarLoop]: Interpolant automaton has 65 states. [2019-10-07 15:38:26,291 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 135 transitions. [2019-10-07 15:38:26,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 229 [2019-10-07 15:38:26,293 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:26,293 INFO L385 BasicCegarLoop]: trace histogram [138, 60, 6, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:26,498 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:26,504 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:26,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:26,504 INFO L82 PathProgramCache]: Analyzing trace with hash -2067647056, now seen corresponding path program 11 times [2019-10-07 15:38:26,504 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:26,504 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:26,504 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:26,504 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:26,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:26,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:27,044 INFO L134 CoverageAnalysis]: Checked inductivity of 11727 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 11706 trivial. 0 not checked. [2019-10-07 15:38:27,045 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:27,045 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:27,045 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:27,521 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-10-07 15:38:27,521 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:27,523 INFO L256 TraceCheckSpWp]: Trace formula consists of 219 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-07 15:38:27,526 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:27,556 INFO L134 CoverageAnalysis]: Checked inductivity of 11727 backedges. 4422 proven. 21 refuted. 0 times theorem prover too weak. 7284 trivial. 0 not checked. [2019-10-07 15:38:27,556 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:27,674 INFO L134 CoverageAnalysis]: Checked inductivity of 11727 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 11706 trivial. 0 not checked. [2019-10-07 15:38:27,674 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:27,675 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:27,675 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:27,676 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:27,676 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:27,676 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:27,700 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:28,801 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:38:28,827 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:28,829 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:28,829 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:28,829 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:28,829 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_sep_~ret~0_BEFORE_RETURN_261 Int) (v_sep_~ret~0_BEFORE_RETURN_262 Int)) (or (and (= (+ (mod v_prenex_1942 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_1941 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_261 4294967296) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sep_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sep_~ret~0_BEFORE_RETURN_262 4294967296) main_~ret~1) (<= (mod v_sep_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:28,830 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:28,830 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:38:28,830 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:38:28,830 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:38:28,830 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (exists ((v_sep_~ret~0_BEFORE_RETURN_265 Int) (v_sep_~ret~0_BEFORE_RETURN_266 Int) (v_prenex_1970 Int) (v_prenex_1969 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_266 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_266 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_1969 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_265 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_265 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret2~0))) (and (exists ((v_sep_~ret~0_BEFORE_RETURN_265 Int) (v_sep_~ret~0_BEFORE_RETURN_266 Int) (v_prenex_1970 Int) (v_prenex_1969 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_266 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_266 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_1969 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_265 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_265 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:28,830 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:28,830 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:28,830 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:28,831 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:38:28,831 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:28,831 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:28,831 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:38:28,831 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_1942 Int) (v_sep_~ret~0_BEFORE_RETURN_262 Int)) (or (and (not (< main_~i~1 60)) (= (mod v_sep_~ret~0_BEFORE_RETURN_262 4294967296) |main_#t~ret6|) (<= (mod v_sep_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647)) (and (not (< main_~i~1 60)) (not (<= (mod v_prenex_1942 4294967296) 2147483647)) (= (+ (mod v_prenex_1942 4294967296) (- 4294967296)) |main_#t~ret6|)))) (exists ((v_prenex_1941 Int) (v_sep_~ret~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 60)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_261 4294967296) |main_#t~ret6|)) (and (not (< main_~i~1 60)) (= (+ (mod v_prenex_1941 4294967296) (- 4294967296)) |main_#t~ret6|) (not (<= (mod v_prenex_1941 4294967296) 2147483647)))))) [2019-10-07 15:38:28,831 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:38:28,831 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:38:28,831 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:38:28,832 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:38:29,138 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:29,138 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 11] total 27 [2019-10-07 15:38:29,140 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-10-07 15:38:29,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-10-07 15:38:29,140 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=591, Unknown=0, NotChecked=0, Total=756 [2019-10-07 15:38:29,141 INFO L87 Difference]: Start difference. First operand 131 states and 135 transitions. Second operand 28 states. [2019-10-07 15:38:30,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:30,236 INFO L93 Difference]: Finished difference Result 193 states and 205 transitions. [2019-10-07 15:38:30,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-10-07 15:38:30,236 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 228 [2019-10-07 15:38:30,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:30,237 INFO L225 Difference]: With dead ends: 193 [2019-10-07 15:38:30,237 INFO L226 Difference]: Without dead ends: 139 [2019-10-07 15:38:30,238 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 715 GetRequests, 667 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 611 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=486, Invalid=1964, Unknown=0, NotChecked=0, Total=2450 [2019-10-07 15:38:30,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2019-10-07 15:38:30,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2019-10-07 15:38:30,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2019-10-07 15:38:30,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 143 transitions. [2019-10-07 15:38:30,252 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 143 transitions. Word has length 228 [2019-10-07 15:38:30,253 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:30,253 INFO L462 AbstractCegarLoop]: Abstraction has 139 states and 143 transitions. [2019-10-07 15:38:30,253 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-10-07 15:38:30,253 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 143 transitions. [2019-10-07 15:38:30,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 237 [2019-10-07 15:38:30,256 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:30,256 INFO L385 BasicCegarLoop]: trace histogram [138, 60, 14, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:30,469 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:30,469 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:30,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:30,470 INFO L82 PathProgramCache]: Analyzing trace with hash -636686800, now seen corresponding path program 12 times [2019-10-07 15:38:30,470 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:30,470 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:30,471 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:30,471 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:30,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:30,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:31,852 INFO L134 CoverageAnalysis]: Checked inductivity of 11811 backedges. 4420 proven. 1081 refuted. 0 times theorem prover too weak. 6310 trivial. 0 not checked. [2019-10-07 15:38:31,853 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:31,853 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:31,853 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:32,473 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:38:32,473 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:32,478 INFO L256 TraceCheckSpWp]: Trace formula consists of 1085 conjuncts, 48 conjunts are in the unsatisfiable core [2019-10-07 15:38:32,483 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:32,550 INFO L134 CoverageAnalysis]: Checked inductivity of 11811 backedges. 4420 proven. 1081 refuted. 0 times theorem prover too weak. 6310 trivial. 0 not checked. [2019-10-07 15:38:32,550 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:34,196 INFO L134 CoverageAnalysis]: Checked inductivity of 11811 backedges. 0 proven. 5501 refuted. 0 times theorem prover too weak. 6310 trivial. 0 not checked. [2019-10-07 15:38:34,196 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:34,206 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:34,207 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:34,207 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:34,211 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:34,212 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:34,224 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:35,484 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:38:35,507 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:35,509 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:35,509 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:35,509 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:35,510 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_287 Int) (v_sep_~ret~0_BEFORE_RETURN_288 Int) (v_prenex_2135 Int) (v_prenex_2136 Int)) (or (and (<= main_~ret~1 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_288 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_288 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_287 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_287 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (= (mod v_prenex_2135 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (<= (mod v_prenex_2135 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_2136 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_2136 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:35,510 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:35,510 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:38:35,510 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:38:35,510 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:38:35,510 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_2163 Int) (v_prenex_2164 Int) (v_sep_~ret~0_BEFORE_RETURN_291 Int) (v_sep_~ret~0_BEFORE_RETURN_292 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_291 4294967296) 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_291 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2163 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2163 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2164 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2164 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_sep_~ret~0_BEFORE_RETURN_292 4294967296) main_~ret5~0) (<= (mod v_sep_~ret~0_BEFORE_RETURN_292 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_prenex_2163 Int) (v_prenex_2164 Int) (v_sep_~ret~0_BEFORE_RETURN_291 Int) (v_sep_~ret~0_BEFORE_RETURN_292 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_291 4294967296) 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_291 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2163 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2163 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2164 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2164 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_sep_~ret~0_BEFORE_RETURN_292 4294967296) main_~ret5~0) (<= (mod v_sep_~ret~0_BEFORE_RETURN_292 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:35,510 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:35,511 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:35,511 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:35,511 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:38:35,511 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:35,511 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:35,511 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:38:35,511 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_288 Int) (v_prenex_2136 Int)) (or (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_288 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret6| (mod v_sep_~ret~0_BEFORE_RETURN_288 4294967296))) (and (= (+ (mod v_prenex_2136 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_prenex_2136 4294967296) 2147483647))))) (exists ((v_sep_~ret~0_BEFORE_RETURN_287 Int) (v_prenex_2135 Int)) (or (and (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_287 4294967296) 2147483647)) (not (< main_~i~1 60)) (= |main_#t~ret6| (+ (mod v_sep_~ret~0_BEFORE_RETURN_287 4294967296) (- 4294967296)))) (and (<= (mod v_prenex_2135 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret6| (mod v_prenex_2135 4294967296)))))) [2019-10-07 15:38:35,512 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:38:35,512 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:38:35,512 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:38:35,512 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:38:36,099 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:36,100 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49, 11] total 73 [2019-10-07 15:38:36,101 INFO L442 AbstractCegarLoop]: Interpolant automaton has 74 states [2019-10-07 15:38:36,102 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2019-10-07 15:38:36,103 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1983, Invalid=3419, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:38:36,103 INFO L87 Difference]: Start difference. First operand 139 states and 143 transitions. Second operand 74 states. [2019-10-07 15:38:41,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:41,655 INFO L93 Difference]: Finished difference Result 225 states and 248 transitions. [2019-10-07 15:38:41,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2019-10-07 15:38:41,655 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 236 [2019-10-07 15:38:41,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:41,657 INFO L225 Difference]: With dead ends: 225 [2019-10-07 15:38:41,657 INFO L226 Difference]: Without dead ends: 153 [2019-10-07 15:38:41,659 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 824 GetRequests, 650 SyntacticMatches, 34 SemanticMatches, 140 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4586 ImplicationChecksByTransitivity, 8.1s TimeCoverageRelationStatistics Valid=6178, Invalid=13844, Unknown=0, NotChecked=0, Total=20022 [2019-10-07 15:38:41,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2019-10-07 15:38:41,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 153. [2019-10-07 15:38:41,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2019-10-07 15:38:41,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 157 transitions. [2019-10-07 15:38:41,672 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 157 transitions. Word has length 236 [2019-10-07 15:38:41,673 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:41,673 INFO L462 AbstractCegarLoop]: Abstraction has 153 states and 157 transitions. [2019-10-07 15:38:41,673 INFO L463 AbstractCegarLoop]: Interpolant automaton has 74 states. [2019-10-07 15:38:41,673 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 157 transitions. [2019-10-07 15:38:41,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 279 [2019-10-07 15:38:41,674 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:41,675 INFO L385 BasicCegarLoop]: trace histogram [180, 60, 14, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:41,876 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:41,877 INFO L410 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:41,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:41,878 INFO L82 PathProgramCache]: Analyzing trace with hash -893145872, now seen corresponding path program 13 times [2019-10-07 15:38:41,878 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:41,878 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:41,878 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:41,878 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:41,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:44,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:44,743 INFO L134 CoverageAnalysis]: Checked inductivity of 18594 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:38:44,744 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:44,744 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:44,744 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:45,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:45,453 INFO L256 TraceCheckSpWp]: Trace formula consists of 1253 conjuncts, 16 conjunts are in the unsatisfiable core [2019-10-07 15:38:45,459 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:45,512 INFO L134 CoverageAnalysis]: Checked inductivity of 18594 backedges. 7446 proven. 105 refuted. 0 times theorem prover too weak. 11043 trivial. 0 not checked. [2019-10-07 15:38:45,513 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:45,834 INFO L134 CoverageAnalysis]: Checked inductivity of 18594 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:38:45,835 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:45,836 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:45,836 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:45,836 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:45,836 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:45,837 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:45,854 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:46,981 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:38:47,001 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:47,004 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:47,004 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:47,004 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:47,005 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(exists ((v_sep_~ret~0_BEFORE_RETURN_313 Int) (v_sep_~ret~0_BEFORE_RETURN_314 Int) (v_prenex_2330 Int) (v_prenex_2329 Int)) (or (and (<= main_~ret~1 2147483647) (<= (mod v_prenex_2329 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_2329 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (<= (mod v_prenex_2330 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_2330 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sep_~ret~0_BEFORE_RETURN_313 4294967296) (- 4294967296))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_313 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_314 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_314 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:47,005 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:47,005 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:38:47,005 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:38:47,005 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:38:47,006 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_2358 Int) (v_prenex_2357 Int) (v_sep_~ret~0_BEFORE_RETURN_317 Int) (v_sep_~ret~0_BEFORE_RETURN_318 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_317 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_317 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_2358 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2358 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_2357 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_2357 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_318 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_318 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_prenex_2358 Int) (v_prenex_2357 Int) (v_sep_~ret~0_BEFORE_RETURN_317 Int) (v_sep_~ret~0_BEFORE_RETURN_318 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_317 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_sep_~ret~0_BEFORE_RETURN_317 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_2358 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2358 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_2357 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_2357 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_318 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_318 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:47,006 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:47,006 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:47,007 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:47,007 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:38:47,007 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:47,007 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:47,007 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:38:47,007 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_sep_~ret~0_BEFORE_RETURN_313 Int) (v_prenex_2329 Int)) (or (and (<= (mod v_prenex_2329 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret6| (mod v_prenex_2329 4294967296))) (and (not (< main_~i~1 60)) (= |main_#t~ret6| (+ (mod v_sep_~ret~0_BEFORE_RETURN_313 4294967296) (- 4294967296))) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_313 4294967296) 2147483647))))) (exists ((v_sep_~ret~0_BEFORE_RETURN_314 Int) (v_prenex_2330 Int)) (or (and (<= (mod v_prenex_2330 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_prenex_2330 4294967296) |main_#t~ret6|)) (and (= (+ (mod v_sep_~ret~0_BEFORE_RETURN_314 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_sep_~ret~0_BEFORE_RETURN_314 4294967296) 2147483647)))))) [2019-10-07 15:38:47,007 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:38:47,007 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:38:47,008 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:38:47,008 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:38:47,353 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:47,353 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 11] total 43 [2019-10-07 15:38:47,355 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-07 15:38:47,355 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-07 15:38:47,355 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=557, Invalid=1335, Unknown=0, NotChecked=0, Total=1892 [2019-10-07 15:38:47,355 INFO L87 Difference]: Start difference. First operand 153 states and 157 transitions. Second operand 44 states. [2019-10-07 15:38:49,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:49,135 INFO L93 Difference]: Finished difference Result 237 states and 257 transitions. [2019-10-07 15:38:49,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2019-10-07 15:38:49,135 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 278 [2019-10-07 15:38:49,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:49,137 INFO L225 Difference]: With dead ends: 237 [2019-10-07 15:38:49,137 INFO L226 Difference]: Without dead ends: 169 [2019-10-07 15:38:49,139 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 889 GetRequests, 809 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1551 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1662, Invalid=4980, Unknown=0, NotChecked=0, Total=6642 [2019-10-07 15:38:49,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2019-10-07 15:38:49,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 169. [2019-10-07 15:38:49,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2019-10-07 15:38:49,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 173 transitions. [2019-10-07 15:38:49,154 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 173 transitions. Word has length 278 [2019-10-07 15:38:49,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:49,154 INFO L462 AbstractCegarLoop]: Abstraction has 169 states and 173 transitions. [2019-10-07 15:38:49,154 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-07 15:38:49,154 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 173 transitions. [2019-10-07 15:38:49,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 295 [2019-10-07 15:38:49,156 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:49,156 INFO L385 BasicCegarLoop]: trace histogram [180, 60, 30, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:49,368 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:49,368 INFO L410 AbstractCegarLoop]: === Iteration 17 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:49,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:49,369 INFO L82 PathProgramCache]: Analyzing trace with hash -585146896, now seen corresponding path program 14 times [2019-10-07 15:38:49,369 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:49,369 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:49,369 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:49,370 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:49,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:50,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:51,315 INFO L134 CoverageAnalysis]: Checked inductivity of 18954 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:38:51,316 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:51,316 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:51,316 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:03,739 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2019-10-07 15:39:03,739 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:39:03,751 INFO L256 TraceCheckSpWp]: Trace formula consists of 651 conjuncts, 32 conjunts are in the unsatisfiable core [2019-10-07 15:39:03,755 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:39:03,829 INFO L134 CoverageAnalysis]: Checked inductivity of 18954 backedges. 7446 proven. 465 refuted. 0 times theorem prover too weak. 11043 trivial. 0 not checked. [2019-10-07 15:39:03,829 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:39:05,187 INFO L134 CoverageAnalysis]: Checked inductivity of 18954 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:39:05,188 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:39:05,189 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:39:05,189 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:39:05,189 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:39:05,190 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:39:05,190 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:39:05,202 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:39:06,319 INFO L199 IcfgInterpreter]: Interpreting procedure sep with input of size 1 for LOIs [2019-10-07 15:39:06,341 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:39:06,344 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:39:06,344 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:39:06,344 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:39:06,345 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 601#(or (exists ((v_prenex_2523 Int) (v_sep_~ret~0_BEFORE_RETURN_340 Int) (v_prenex_2524 Int) (v_sep_~ret~0_BEFORE_RETURN_339 Int)) (or (and (= main_~ret~1 (+ (mod v_prenex_2523 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2523 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2524 4294967296) 2147483647)) (= (+ (mod v_prenex_2524 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_340 4294967296)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_340 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_339 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_339 4294967296) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_prenex_2523 Int) (v_sep_~ret~0_BEFORE_RETURN_340 Int) (v_prenex_2524 Int) (v_sep_~ret~0_BEFORE_RETURN_339 Int)) (or (and (= main_~ret~1 (+ (mod v_prenex_2523 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2523 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_340 4294967296) 2147483647) (= main_~ret~1 (mod v_sep_~ret~0_BEFORE_RETURN_340 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2524 4294967296) 2147483647)) (= (+ (mod v_prenex_2524 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (<= (mod v_sep_~ret~0_BEFORE_RETURN_339 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_339 4294967296) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:39:06,345 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 666#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:39:06,345 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-07 15:39:06,345 INFO L193 IcfgInterpreter]: Reachable states at location L7-3 satisfy 657#(<= 0 sep_~i~0) [2019-10-07 15:39:06,346 INFO L193 IcfgInterpreter]: Reachable states at location sepENTRY satisfy 610#true [2019-10-07 15:39:06,346 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 243#(or (and (exists ((v_sep_~ret~0_BEFORE_RETURN_343 Int) (v_sep_~ret~0_BEFORE_RETURN_344 Int) (v_prenex_2552 Int) (v_prenex_2551 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2551 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2551 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_sep_~ret~0_BEFORE_RETURN_344 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_344 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_343 4294967296)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_343 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2552 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2552 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sep_~ret~0_BEFORE_RETURN_343 Int) (v_sep_~ret~0_BEFORE_RETURN_344 Int) (v_prenex_2552 Int) (v_prenex_2551 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2551 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2551 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_sep_~ret~0_BEFORE_RETURN_344 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_344 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sep_~ret~0_BEFORE_RETURN_343 4294967296)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_343 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2552 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2552 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:39:06,346 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:06,346 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:06,346 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 671#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:06,346 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 488#true [2019-10-07 15:39:06,347 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:39:06,347 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 531#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:39:06,347 INFO L193 IcfgInterpreter]: Reachable states at location sepEXIT satisfy 662#(and (not (< sep_~i~0 60)) (<= 60 sep_~i~0) (= |sep_#res| (ite (<= (mod sep_~ret~0 4294967296) 2147483647) (mod sep_~ret~0 4294967296) (+ (mod sep_~ret~0 4294967296) (- 4294967296)))) (<= 0 sep_~i~0)) [2019-10-07 15:39:06,347 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 129#(or (exists ((v_prenex_2523 Int) (v_sep_~ret~0_BEFORE_RETURN_339 Int)) (or (and (not (< main_~i~1 60)) (not (<= (mod v_prenex_2523 4294967296) 2147483647)) (= |main_#t~ret6| (+ (mod v_prenex_2523 4294967296) (- 4294967296)))) (and (<= (mod v_sep_~ret~0_BEFORE_RETURN_339 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_sep_~ret~0_BEFORE_RETURN_339 4294967296) |main_#t~ret6|)))) (exists ((v_sep_~ret~0_BEFORE_RETURN_340 Int) (v_prenex_2524 Int)) (or (and (= (+ (mod v_prenex_2524 4294967296) (- 4294967296)) |main_#t~ret6|) (not (< main_~i~1 60)) (not (<= (mod v_prenex_2524 4294967296) 2147483647))) (and (not (< main_~i~1 60)) (<= (mod v_sep_~ret~0_BEFORE_RETURN_340 4294967296) 2147483647) (= (mod v_sep_~ret~0_BEFORE_RETURN_340 4294967296) |main_#t~ret6|))))) [2019-10-07 15:39:06,347 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 433#true [2019-10-07 15:39:06,347 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 322#true [2019-10-07 15:39:06,347 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 569#true [2019-10-07 15:39:06,347 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 596#true [2019-10-07 15:39:06,816 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:39:06,816 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 11] total 72 [2019-10-07 15:39:06,818 INFO L442 AbstractCegarLoop]: Interpolant automaton has 73 states [2019-10-07 15:39:06,819 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2019-10-07 15:39:06,819 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1920, Invalid=3336, Unknown=0, NotChecked=0, Total=5256 [2019-10-07 15:39:06,820 INFO L87 Difference]: Start difference. First operand 169 states and 173 transitions. Second operand 73 states. [2019-10-07 15:39:11,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:39:11,109 INFO L93 Difference]: Finished difference Result 266 states and 299 transitions. [2019-10-07 15:39:11,109 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2019-10-07 15:39:11,109 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 294 [2019-10-07 15:39:11,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:39:11,110 INFO L225 Difference]: With dead ends: 266 [2019-10-07 15:39:11,110 INFO L226 Difference]: Without dead ends: 198 [2019-10-07 15:39:11,112 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 982 GetRequests, 841 SyntacticMatches, 3 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4094 ImplicationChecksByTransitivity, 6.0s TimeCoverageRelationStatistics Valid=5751, Invalid=13709, Unknown=0, NotChecked=0, Total=19460 [2019-10-07 15:39:11,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states. [2019-10-07 15:39:11,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2019-10-07 15:39:11,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198 states. [2019-10-07 15:39:11,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 202 transitions. [2019-10-07 15:39:11,124 INFO L78 Accepts]: Start accepts. Automaton has 198 states and 202 transitions. Word has length 294 [2019-10-07 15:39:11,124 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:39:11,125 INFO L462 AbstractCegarLoop]: Abstraction has 198 states and 202 transitions. [2019-10-07 15:39:11,125 INFO L463 AbstractCegarLoop]: Interpolant automaton has 73 states. [2019-10-07 15:39:11,125 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 202 transitions. [2019-10-07 15:39:11,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 324 [2019-10-07 15:39:11,127 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:39:11,127 INFO L385 BasicCegarLoop]: trace histogram [180, 60, 59, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:39:11,341 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:11,341 INFO L410 AbstractCegarLoop]: === Iteration 18 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:39:11,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:39:11,341 INFO L82 PathProgramCache]: Analyzing trace with hash 396110529, now seen corresponding path program 15 times [2019-10-07 15:39:11,342 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:39:11,342 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:11,342 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:11,342 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:11,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY