java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/sum20-2.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:37:57,326 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:37:57,329 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:37:57,346 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:37:57,346 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:37:57,348 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:37:57,350 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:37:57,359 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:37:57,363 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:37:57,366 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:37:57,367 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:37:57,369 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:37:57,369 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:37:57,370 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:37:57,373 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:37:57,374 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:37:57,375 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:37:57,376 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:37:57,377 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:37:57,382 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:37:57,385 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:37:57,388 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:37:57,391 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:37:57,392 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:37:57,394 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 15:37:57,402 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:37:57,402 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:37:57,403 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:37:57,404 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:37:57,417 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:37:57,417 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:37:57,418 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:37:57,419 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:37:57,419 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:37:57,419 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:37:57,419 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:37:57,419 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:37:57,420 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:37:57,420 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:37:57,420 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:37:57,420 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:37:57,420 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:37:57,421 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:37:57,421 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:37:57,421 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:37:57,421 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:37:57,421 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:37:57,421 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:37:57,422 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:37:57,422 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:37:57,422 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:37:57,422 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:37:57,422 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:37:57,423 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:37:57,423 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:37:57,423 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:37:57,423 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:37:57,423 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:37:57,694 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:37:57,705 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:37:57,708 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:37:57,710 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:37:57,710 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:37:57,711 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/sum20-2.i [2019-10-07 15:37:57,786 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a47b3b619/3d976af48d994120b99178d1a399ce79/FLAGb85c8bd03 [2019-10-07 15:37:58,240 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:37:58,241 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/sum20-2.i [2019-10-07 15:37:58,247 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a47b3b619/3d976af48d994120b99178d1a399ce79/FLAGb85c8bd03 [2019-10-07 15:37:58,642 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a47b3b619/3d976af48d994120b99178d1a399ce79 [2019-10-07 15:37:58,652 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:37:58,654 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:37:58,655 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:37:58,655 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:37:58,661 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:37:58,662 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:37:58" (1/1) ... [2019-10-07 15:37:58,665 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1f5d49d8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:58, skipping insertion in model container [2019-10-07 15:37:58,665 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:37:58" (1/1) ... [2019-10-07 15:37:58,673 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:37:58,694 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:37:58,963 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:37:58,979 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:37:59,018 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:37:59,127 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:37:59,128 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:59 WrapperNode [2019-10-07 15:37:59,128 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:37:59,129 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:37:59,129 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:37:59,129 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:37:59,144 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:59" (1/1) ... [2019-10-07 15:37:59,144 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:59" (1/1) ... [2019-10-07 15:37:59,154 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:59" (1/1) ... [2019-10-07 15:37:59,156 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:59" (1/1) ... [2019-10-07 15:37:59,174 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:59" (1/1) ... [2019-10-07 15:37:59,179 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:59" (1/1) ... [2019-10-07 15:37:59,180 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:59" (1/1) ... [2019-10-07 15:37:59,182 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:37:59,182 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:37:59,183 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:37:59,183 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:37:59,184 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:59" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:37:59,241 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:37:59,242 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:37:59,242 INFO L138 BoogieDeclarations]: Found implementation of procedure sum [2019-10-07 15:37:59,242 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:37:59,242 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:37:59,242 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:37:59,243 INFO L130 BoogieDeclarations]: Found specification of procedure sum [2019-10-07 15:37:59,243 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:37:59,243 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:37:59,243 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:37:59,243 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:37:59,243 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:37:59,244 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:37:59,244 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:37:59,643 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:37:59,643 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:37:59,645 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:37:59 BoogieIcfgContainer [2019-10-07 15:37:59,645 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:37:59,646 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:37:59,646 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:37:59,649 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:37:59,649 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:37:58" (1/3) ... [2019-10-07 15:37:59,650 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3512fa70 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:37:59, skipping insertion in model container [2019-10-07 15:37:59,650 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:37:59" (2/3) ... [2019-10-07 15:37:59,651 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3512fa70 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:37:59, skipping insertion in model container [2019-10-07 15:37:59,651 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:37:59" (3/3) ... [2019-10-07 15:37:59,653 INFO L109 eAbstractionObserver]: Analyzing ICFG sum20-2.i [2019-10-07 15:37:59,662 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:37:59,669 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:37:59,679 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:37:59,701 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:37:59,701 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:37:59,701 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:37:59,701 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:37:59,701 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:37:59,701 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:37:59,702 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:37:59,702 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:37:59,716 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:37:59,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:37:59,722 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:37:59,723 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:37:59,725 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:37:59,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:37:59,731 INFO L82 PathProgramCache]: Analyzing trace with hash -1818423299, now seen corresponding path program 1 times [2019-10-07 15:37:59,740 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:37:59,741 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:59,741 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:59,741 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:37:59,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:37:59,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:37:59,928 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:37:59,928 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:37:59,929 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:37:59,929 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:37:59,933 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:37:59,947 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:37:59,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:37:59,950 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:37:59,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:37:59,994 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:37:59,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:37:59,997 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:37:59,999 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:00,008 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:38:00,008 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:38:00,011 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:38:00,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:38:00,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:38:00,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:38:00,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:38:00,046 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:38:00,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:00,046 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:38:00,046 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:38:00,047 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:38:00,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:38:00,049 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:00,049 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:00,049 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:00,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:00,050 INFO L82 PathProgramCache]: Analyzing trace with hash -2093950433, now seen corresponding path program 1 times [2019-10-07 15:38:00,050 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:00,051 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:00,051 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:00,051 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:00,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:00,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:00,127 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:38:00,131 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:00,132 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:00,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:00,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:00,197 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:38:00,203 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:00,238 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:38:00,238 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:00,280 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:38:00,280 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:38:00,280 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:38:00,282 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:38:00,282 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:38:00,283 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:38:00,283 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:38:00,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:00,294 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:38:00,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:38:00,295 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:38:00,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:00,296 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:38:00,296 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:38:00,297 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:38:00,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:38:00,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:38:00,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:38:00,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:38:00,303 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:38:00,303 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:00,304 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:38:00,304 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:38:00,304 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:38:00,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:38:00,305 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:00,305 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:00,512 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:00,513 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:00,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:00,514 INFO L82 PathProgramCache]: Analyzing trace with hash 903502258, now seen corresponding path program 1 times [2019-10-07 15:38:00,514 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:00,514 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:00,514 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:00,515 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:00,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:00,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:00,627 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:00,627 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:00,628 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:38:00,628 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:38:00,628 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:38:00,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:38:00,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:38:00,629 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:38:00,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:00,644 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:38:00,645 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:38:00,645 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:38:00,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:00,646 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:38:00,646 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:38:00,648 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:38:00,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:38:00,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:38:00,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:38:00,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:38:00,659 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:38:00,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:00,664 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:38:00,664 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:38:00,665 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:38:00,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:38:00,666 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:00,666 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:00,666 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:00,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:00,667 INFO L82 PathProgramCache]: Analyzing trace with hash 2130547361, now seen corresponding path program 1 times [2019-10-07 15:38:00,667 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:00,667 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:00,667 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:00,668 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:00,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:00,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:00,763 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:00,763 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:00,763 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:00,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:00,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:00,844 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:38:00,862 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:00,880 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:00,880 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:00,920 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:00,921 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:00,961 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:00,962 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:00,970 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:00,983 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:00,984 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:01,116 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:03,108 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:03,150 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:03,154 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:03,154 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:03,154 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:03,155 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_29 Int) (v_sum_~ret~0_BEFORE_RETURN_5 Int) (v_sum_~ret~0_BEFORE_RETURN_6 Int) (v_prenex_30 Int)) (or (and (<= (mod v_prenex_29 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_29 4294967296) main_~ret5~0) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_6 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_30 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_sum_~ret~0_BEFORE_RETURN_5 Int) (v_sum_~ret~0_BEFORE_RETURN_6 Int) (v_prenex_30 Int)) (or (and (<= (mod v_prenex_29 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_29 4294967296) main_~ret5~0) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_6 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_30 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))))) [2019-10-07 15:38:03,155 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:03,155 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:03,155 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:38:03,156 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:03,156 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:03,156 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_2 Int) (v_sum_~ret~0_BEFORE_RETURN_2 Int)) (or (and (not (< main_~i~1 20)) (= (mod v_sum_~ret~0_BEFORE_RETURN_2 4294967296) |main_#t~ret4|) (<= (mod v_sum_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647)) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 20)) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_prenex_1 Int) (v_sum_~ret~0_BEFORE_RETURN_1 Int)) (or (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 20)) (= (mod v_sum_~ret~0_BEFORE_RETURN_1 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (= |main_#t~ret4| (+ (mod v_prenex_1 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1 4294967296) 2147483647)))))) [2019-10-07 15:38:03,156 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:03,157 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:03,157 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:03,157 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:03,157 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:03,157 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:03,158 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:03,158 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:38:03,158 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_2 Int) (v_prenex_1 Int) (v_sum_~ret~0_BEFORE_RETURN_1 Int) (v_sum_~ret~0_BEFORE_RETURN_2 Int)) (or (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_1 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (mod v_sum_~ret~0_BEFORE_RETURN_2 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:03,158 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:03,159 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 20)) (<= 20 sum_~i~0)) [2019-10-07 15:38:03,512 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:03,513 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:38:03,515 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-07 15:38:03,516 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-07 15:38:03,516 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-07 15:38:03,516 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-07 15:38:04,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:04,122 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:38:04,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-07 15:38:04,122 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-07 15:38:04,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:04,123 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:38:04,123 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:38:04,124 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=133, Invalid=737, Unknown=0, NotChecked=0, Total=870 [2019-10-07 15:38:04,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:38:04,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:38:04,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:38:04,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:38:04,137 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:38:04,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:04,137 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:38:04,138 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-07 15:38:04,138 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:38:04,140 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:38:04,140 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:04,140 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:04,344 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:04,345 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:04,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:04,345 INFO L82 PathProgramCache]: Analyzing trace with hash 356639231, now seen corresponding path program 2 times [2019-10-07 15:38:04,346 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:04,346 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:04,346 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:04,347 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:04,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:04,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:04,473 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:04,473 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:04,473 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:04,473 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:04,555 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:38:04,555 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:04,559 INFO L256 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:38:04,562 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:04,592 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:38:04,593 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:04,623 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:38:04,623 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:04,625 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:04,626 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:04,628 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:04,628 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:04,629 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:04,656 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:06,117 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:06,145 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:06,148 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:06,149 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:06,149 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:06,149 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_32 Int) (v_prenex_224 Int) (v_sum_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_prenex_224 4294967296))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)))))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_32 Int) (v_prenex_224 Int) (v_sum_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (not (< main_~i~2 19)) (= main_~ret5~0 (mod v_prenex_224 4294967296))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:06,149 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:06,150 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:06,150 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:38:06,150 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:06,150 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:06,151 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (not (< main_~i~1 20)) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_27 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_195 4294967296) 2147483647)) (= (+ (mod v_prenex_195 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_prenex_196 Int) (v_sum_~ret~0_BEFORE_RETURN_28 Int)) (or (and (not (< main_~i~1 20)) (<= (mod v_prenex_196 4294967296) 2147483647) (= (mod v_prenex_196 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_28 4294967296) (- 4294967296))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647)))))) [2019-10-07 15:38:06,151 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:06,151 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:06,151 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:06,151 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:06,152 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:06,152 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:06,152 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:06,152 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:38:06,152 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_sum_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_196 Int) (v_prenex_195 Int) (v_sum_~ret~0_BEFORE_RETURN_28 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (not (<= (mod v_prenex_195 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_prenex_195 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_27 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (<= (mod v_prenex_196 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_196 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_28 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:06,153 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:06,153 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 20)) (<= 20 sum_~i~0)) [2019-10-07 15:38:06,532 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:06,533 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:38:06,534 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-07 15:38:06,534 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-07 15:38:06,535 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-07 15:38:06,535 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-07 15:38:07,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:07,381 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:38:07,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:38:07,381 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-07 15:38:07,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:07,382 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:38:07,383 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:38:07,384 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-07 15:38:07,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:38:07,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:38:07,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:38:07,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:38:07,390 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:38:07,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:07,391 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:38:07,391 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-07 15:38:07,391 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:38:07,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:38:07,392 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:07,392 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:07,598 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:07,598 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:07,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:07,599 INFO L82 PathProgramCache]: Analyzing trace with hash 906031436, now seen corresponding path program 3 times [2019-10-07 15:38:07,599 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:07,599 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:07,599 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:07,599 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:07,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:07,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:07,696 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:07,696 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:07,696 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:07,697 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:07,825 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:38:07,825 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:07,834 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:38:07,838 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:07,852 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:07,852 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:07,939 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:07,939 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:07,941 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:07,941 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:07,942 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:07,942 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:07,942 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:07,961 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:09,306 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:09,339 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:09,343 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:09,343 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:09,343 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:09,344 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_58 Int) (v_sum_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_sum_~ret~0_BEFORE_RETURN_58 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_sum_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647)) (not (< main_~i~2 19)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0)) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (not (< main_~i~2 19)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296))))))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_58 Int) (v_sum_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_sum_~ret~0_BEFORE_RETURN_58 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_sum_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647)) (not (< main_~i~2 19)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0)) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (not (< main_~i~2 19)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:09,344 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:09,344 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:09,344 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:38:09,345 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:09,345 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:09,345 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_389 Int) (v_sum_~ret~0_BEFORE_RETURN_53 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_389 4294967296) 2147483647)) (= (+ (mod v_prenex_389 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (mod v_sum_~ret~0_BEFORE_RETURN_53 4294967296) |main_#t~ret4|) (not (< main_~i~1 20)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)))) (exists ((v_sum_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 20)) (not (<= (mod v_prenex_390 4294967296) 2147483647))) (and (= (mod v_sum_~ret~0_BEFORE_RETURN_54 4294967296) |main_#t~ret4|) (<= (mod v_sum_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (not (< main_~i~1 20)))))) [2019-10-07 15:38:09,346 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:09,346 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:09,346 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:09,347 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:09,347 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:09,347 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:09,347 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:09,348 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:38:09,348 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_389 Int) (v_sum_~ret~0_BEFORE_RETURN_54 Int) (v_sum_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (+ (mod v_prenex_389 4294967296) (- 4294967296))) (not (<= (mod v_prenex_389 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (= (mod v_sum_~ret~0_BEFORE_RETURN_53 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (<= (mod v_sum_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sum_~ret~0_BEFORE_RETURN_54 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:09,348 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:09,349 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 20)) (<= 20 sum_~i~0)) [2019-10-07 15:38:09,863 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:09,863 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-07 15:38:09,865 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-07 15:38:09,865 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-07 15:38:09,868 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-07 15:38:09,868 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-07 15:38:11,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:11,022 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-07 15:38:11,022 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-07 15:38:11,023 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-07 15:38:11,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:11,023 INFO L225 Difference]: With dead ends: 54 [2019-10-07 15:38:11,024 INFO L226 Difference]: Without dead ends: 36 [2019-10-07 15:38:11,028 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-07 15:38:11,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-07 15:38:11,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-07 15:38:11,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-07 15:38:11,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-07 15:38:11,043 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-07 15:38:11,043 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:11,043 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-07 15:38:11,044 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-07 15:38:11,044 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-07 15:38:11,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-07 15:38:11,045 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:11,046 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:11,250 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:11,251 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:11,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:11,252 INFO L82 PathProgramCache]: Analyzing trace with hash -1194663378, now seen corresponding path program 4 times [2019-10-07 15:38:11,252 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:11,253 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:11,253 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:11,253 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:11,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:11,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:11,395 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:11,395 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:11,395 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:11,396 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:11,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:11,527 INFO L256 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:38:11,530 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:11,542 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:11,543 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:11,725 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:11,725 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:11,726 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:11,726 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:11,727 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:11,727 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:11,727 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:11,749 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:12,896 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:12,919 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:12,921 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:12,922 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:12,922 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:12,927 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_611 Int) (v_sum_~ret~0_BEFORE_RETURN_84 Int) (v_prenex_612 Int) (v_sum_~ret~0_BEFORE_RETURN_83 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_84 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_612 4294967296) 2147483647) (not (< main_~i~2 19)) (= (mod v_prenex_612 4294967296) main_~ret5~0)) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_prenex_611 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_611 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_83 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_sum_~ret~0_BEFORE_RETURN_84 Int) (v_prenex_612 Int) (v_sum_~ret~0_BEFORE_RETURN_83 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_84 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_612 4294967296) 2147483647) (not (< main_~i~2 19)) (= (mod v_prenex_612 4294967296) main_~ret5~0)) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_prenex_611 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_611 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_83 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647)))))) [2019-10-07 15:38:12,928 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:12,928 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:12,928 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:38:12,928 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:12,928 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:12,929 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_583 Int) (v_sum_~ret~0_BEFORE_RETURN_79 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_79 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (mod v_prenex_583 4294967296) |main_#t~ret4|) (not (< main_~i~1 20)) (<= (mod v_prenex_583 4294967296) 2147483647)))) (exists ((v_prenex_584 Int) (v_sum_~ret~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 20)) (= |main_#t~ret4| (+ (mod v_prenex_584 4294967296) (- 4294967296))) (not (<= (mod v_prenex_584 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_80 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647))))) [2019-10-07 15:38:12,929 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:12,929 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:12,929 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:12,929 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:12,930 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:12,930 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:12,930 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:12,930 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:38:12,930 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_583 Int) (v_sum_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_584 Int) (v_sum_~ret~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_80 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_584 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_prenex_584 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (<= (mod v_prenex_583 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_583 4294967296)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:12,931 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:12,931 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 20)) (<= 20 sum_~i~0)) [2019-10-07 15:38:13,341 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:13,341 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 33 [2019-10-07 15:38:13,343 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2019-10-07 15:38:13,343 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-10-07 15:38:13,344 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=282, Invalid=840, Unknown=0, NotChecked=0, Total=1122 [2019-10-07 15:38:13,344 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 34 states. [2019-10-07 15:38:14,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:14,560 INFO L93 Difference]: Finished difference Result 62 states and 77 transitions. [2019-10-07 15:38:14,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-10-07 15:38:14,560 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 49 [2019-10-07 15:38:14,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:14,561 INFO L225 Difference]: With dead ends: 62 [2019-10-07 15:38:14,561 INFO L226 Difference]: Without dead ends: 44 [2019-10-07 15:38:14,563 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 192 GetRequests, 126 SyntacticMatches, 6 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 977 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=797, Invalid=2985, Unknown=0, NotChecked=0, Total=3782 [2019-10-07 15:38:14,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2019-10-07 15:38:14,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2019-10-07 15:38:14,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2019-10-07 15:38:14,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 48 transitions. [2019-10-07 15:38:14,571 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 48 transitions. Word has length 49 [2019-10-07 15:38:14,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:14,571 INFO L462 AbstractCegarLoop]: Abstraction has 44 states and 48 transitions. [2019-10-07 15:38:14,571 INFO L463 AbstractCegarLoop]: Interpolant automaton has 34 states. [2019-10-07 15:38:14,571 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 48 transitions. [2019-10-07 15:38:14,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-10-07 15:38:14,573 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:14,573 INFO L385 BasicCegarLoop]: trace histogram [20, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:14,780 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:14,780 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:14,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:14,780 INFO L82 PathProgramCache]: Analyzing trace with hash -716222162, now seen corresponding path program 5 times [2019-10-07 15:38:14,781 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:14,781 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:14,781 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:14,781 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:14,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:14,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:14,896 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2019-10-07 15:38:14,896 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:14,897 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:14,897 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:15,070 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:38:15,071 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:15,072 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:38:15,074 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:15,116 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2019-10-07 15:38:15,117 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:15,173 INFO L134 CoverageAnalysis]: Checked inductivity of 322 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2019-10-07 15:38:15,174 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:15,175 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:15,175 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:15,176 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:15,176 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:15,176 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:15,192 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:16,442 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:16,463 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:16,466 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:16,466 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:16,466 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:16,467 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_sum_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_109 4294967296)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (not (< main_~i~2 19)))))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_sum_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_109 4294967296)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:16,467 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:16,467 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:16,467 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:38:16,467 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:16,467 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:38:16,468 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (< main_~i~1 20)) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_106 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)) (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 20)) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_prenex_777 Int) (v_sum_~ret~0_BEFORE_RETURN_105 Int)) (or (and (<= (mod v_prenex_777 4294967296) 2147483647) (not (< main_~i~1 20)) (= (mod v_prenex_777 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_105 4294967296) (- 4294967296))))))) [2019-10-07 15:38:16,468 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:16,468 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:16,468 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:16,468 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:16,469 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:16,469 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:16,469 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:16,469 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:38:16,469 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_777 Int) (v_sum_~ret~0_BEFORE_RETURN_106 Int) (v_sum_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 20)) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_106 4294967296)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_prenex_777 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_777 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_105 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:16,470 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:16,470 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 20)) (<= 20 sum_~i~0)) [2019-10-07 15:38:16,840 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:16,840 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 7, 7, 11] total 24 [2019-10-07 15:38:16,842 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-10-07 15:38:16,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-10-07 15:38:16,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=500, Unknown=0, NotChecked=0, Total=600 [2019-10-07 15:38:16,843 INFO L87 Difference]: Start difference. First operand 44 states and 48 transitions. Second operand 25 states. [2019-10-07 15:38:17,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:17,850 INFO L93 Difference]: Finished difference Result 68 states and 84 transitions. [2019-10-07 15:38:17,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-07 15:38:17,850 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 57 [2019-10-07 15:38:17,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:17,851 INFO L225 Difference]: With dead ends: 68 [2019-10-07 15:38:17,851 INFO L226 Difference]: Without dead ends: 51 [2019-10-07 15:38:17,852 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 194 GetRequests, 151 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 440 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=358, Invalid=1622, Unknown=0, NotChecked=0, Total=1980 [2019-10-07 15:38:17,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2019-10-07 15:38:17,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2019-10-07 15:38:17,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2019-10-07 15:38:17,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 55 transitions. [2019-10-07 15:38:17,860 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 55 transitions. Word has length 57 [2019-10-07 15:38:17,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:17,861 INFO L462 AbstractCegarLoop]: Abstraction has 51 states and 55 transitions. [2019-10-07 15:38:17,861 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-10-07 15:38:17,861 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 55 transitions. [2019-10-07 15:38:17,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-10-07 15:38:17,862 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:17,862 INFO L385 BasicCegarLoop]: trace histogram [30, 20, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:18,063 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:18,064 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:18,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:18,064 INFO L82 PathProgramCache]: Analyzing trace with hash 696436029, now seen corresponding path program 6 times [2019-10-07 15:38:18,065 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:18,065 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:18,065 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:18,065 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:18,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:18,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:18,208 INFO L134 CoverageAnalysis]: Checked inductivity of 747 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 448 trivial. 0 not checked. [2019-10-07 15:38:18,208 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:18,208 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:18,208 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:18,420 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:38:18,420 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:18,421 INFO L256 TraceCheckSpWp]: Trace formula consists of 395 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-07 15:38:18,424 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:18,444 INFO L134 CoverageAnalysis]: Checked inductivity of 747 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 448 trivial. 0 not checked. [2019-10-07 15:38:18,444 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:18,629 INFO L134 CoverageAnalysis]: Checked inductivity of 747 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 448 trivial. 0 not checked. [2019-10-07 15:38:18,629 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:18,631 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:18,631 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:18,631 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:18,632 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:18,632 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:18,655 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:19,772 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:19,805 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:19,807 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:19,808 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:19,808 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:19,808 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_sum_~ret~0_BEFORE_RETURN_135 Int) (v_prenex_999 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1000 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_136 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647)))))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_sum_~ret~0_BEFORE_RETURN_135 Int) (v_prenex_999 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1000 4294967296) 2147483647)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_136 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:19,808 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:19,809 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:19,809 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:38:19,809 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:19,809 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:19,809 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_971 Int) (v_sum_~ret~0_BEFORE_RETURN_131 Int)) (or (and (= |main_#t~ret4| (+ (mod v_prenex_971 4294967296) (- 4294967296))) (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 20))) (and (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_131 4294967296)) (not (< main_~i~1 20)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647)))) (exists ((v_prenex_972 Int) (v_sum_~ret~0_BEFORE_RETURN_132 Int)) (or (and (= (mod v_sum_~ret~0_BEFORE_RETURN_132 4294967296) |main_#t~ret4|) (not (< main_~i~1 20)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647)) (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (= (+ (mod v_prenex_972 4294967296) (- 4294967296)) |main_#t~ret4|))))) [2019-10-07 15:38:19,809 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:19,810 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:19,810 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:19,810 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:19,810 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:19,810 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:19,810 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:19,811 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:38:19,811 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_sum_~ret~0_BEFORE_RETURN_132 Int) (v_sum_~ret~0_BEFORE_RETURN_131 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (<= (mod v_sum_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_132 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_131 4294967296)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:19,811 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:19,811 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 20)) (<= 20 sum_~i~0)) [2019-10-07 15:38:20,143 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:20,143 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 11] total 33 [2019-10-07 15:38:20,144 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2019-10-07 15:38:20,145 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-10-07 15:38:20,145 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=283, Invalid=839, Unknown=0, NotChecked=0, Total=1122 [2019-10-07 15:38:20,146 INFO L87 Difference]: Start difference. First operand 51 states and 55 transitions. Second operand 34 states. [2019-10-07 15:38:21,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:21,595 INFO L93 Difference]: Finished difference Result 85 states and 104 transitions. [2019-10-07 15:38:21,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-10-07 15:38:21,595 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 76 [2019-10-07 15:38:21,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:21,596 INFO L225 Difference]: With dead ends: 85 [2019-10-07 15:38:21,596 INFO L226 Difference]: Without dead ends: 61 [2019-10-07 15:38:21,598 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 270 GetRequests, 208 SyntacticMatches, 2 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 924 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=918, Invalid=2864, Unknown=0, NotChecked=0, Total=3782 [2019-10-07 15:38:21,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2019-10-07 15:38:21,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2019-10-07 15:38:21,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2019-10-07 15:38:21,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 65 transitions. [2019-10-07 15:38:21,608 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 65 transitions. Word has length 76 [2019-10-07 15:38:21,608 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:21,608 INFO L462 AbstractCegarLoop]: Abstraction has 61 states and 65 transitions. [2019-10-07 15:38:21,608 INFO L463 AbstractCegarLoop]: Interpolant automaton has 34 states. [2019-10-07 15:38:21,608 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 65 transitions. [2019-10-07 15:38:21,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2019-10-07 15:38:21,610 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:21,610 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:21,814 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:21,815 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:21,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:21,815 INFO L82 PathProgramCache]: Analyzing trace with hash 1048054237, now seen corresponding path program 7 times [2019-10-07 15:38:21,815 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:21,815 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:21,815 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:21,816 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:21,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:21,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:21,949 INFO L134 CoverageAnalysis]: Checked inductivity of 2172 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:38:21,949 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:21,949 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:21,950 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:22,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:22,198 INFO L256 TraceCheckSpWp]: Trace formula consists of 545 conjuncts, 4 conjunts are in the unsatisfiable core [2019-10-07 15:38:22,209 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:22,229 INFO L134 CoverageAnalysis]: Checked inductivity of 2172 backedges. 886 proven. 3 refuted. 0 times theorem prover too weak. 1283 trivial. 0 not checked. [2019-10-07 15:38:22,229 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:22,270 INFO L134 CoverageAnalysis]: Checked inductivity of 2172 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:38:22,271 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:22,275 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:22,275 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:22,276 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:22,276 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:22,276 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:22,290 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:23,432 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:23,465 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:23,468 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:23,468 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:23,469 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:23,469 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_sum_~ret~0_BEFORE_RETURN_162 Int) (v_prenex_1194 Int) (v_sum_~ret~0_BEFORE_RETURN_161 Int) (v_prenex_1193 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_1193 4294967296) 2147483647) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_162 Int) (v_prenex_1194 Int) (v_sum_~ret~0_BEFORE_RETURN_161 Int) (v_prenex_1193 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= (mod v_prenex_1193 4294967296) 2147483647) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))))) [2019-10-07 15:38:23,469 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:23,469 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:23,470 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:38:23,470 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:23,470 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:23,470 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int)) (or (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (not (< main_~i~1 20)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (<= (mod v_prenex_1166 4294967296) 2147483647) (= |main_#t~ret4| (mod v_prenex_1166 4294967296))))) (exists ((v_prenex_1165 Int) (v_sum_~ret~0_BEFORE_RETURN_157 Int)) (or (and (<= (mod v_prenex_1165 4294967296) 2147483647) (not (< main_~i~1 20)) (= (mod v_prenex_1165 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296))))))) [2019-10-07 15:38:23,470 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:23,471 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:23,471 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:23,471 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:23,471 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:23,472 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:23,472 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:23,472 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:38:23,473 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_sum_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int) (v_prenex_1165 Int) (v_sum_~ret~0_BEFORE_RETURN_157 Int)) (or (and (<= (mod v_prenex_1165 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_1165 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1166 4294967296)) (not (< main_~i~1 20)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:23,473 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:23,473 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 20)) (<= 20 sum_~i~0)) [2019-10-07 15:38:23,831 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:23,831 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 11] total 19 [2019-10-07 15:38:23,832 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-10-07 15:38:23,832 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-10-07 15:38:23,833 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2019-10-07 15:38:23,833 INFO L87 Difference]: Start difference. First operand 61 states and 65 transitions. Second operand 20 states. [2019-10-07 15:38:26,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:26,580 INFO L93 Difference]: Finished difference Result 93 states and 101 transitions. [2019-10-07 15:38:26,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-10-07 15:38:26,580 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 106 [2019-10-07 15:38:26,581 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:26,581 INFO L225 Difference]: With dead ends: 93 [2019-10-07 15:38:26,582 INFO L226 Difference]: Without dead ends: 65 [2019-10-07 15:38:26,582 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 337 GetRequests, 305 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=186, Invalid=936, Unknown=0, NotChecked=0, Total=1122 [2019-10-07 15:38:26,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2019-10-07 15:38:26,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 65. [2019-10-07 15:38:26,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65 states. [2019-10-07 15:38:26,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 69 transitions. [2019-10-07 15:38:26,591 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 69 transitions. Word has length 106 [2019-10-07 15:38:26,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:26,591 INFO L462 AbstractCegarLoop]: Abstraction has 65 states and 69 transitions. [2019-10-07 15:38:26,591 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-10-07 15:38:26,592 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 69 transitions. [2019-10-07 15:38:26,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-10-07 15:38:26,593 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:26,593 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 6, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:26,798 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:26,799 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:26,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:26,799 INFO L82 PathProgramCache]: Analyzing trace with hash -1255666147, now seen corresponding path program 8 times [2019-10-07 15:38:26,799 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:26,799 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:26,800 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:26,800 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:26,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:26,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:26,939 INFO L134 CoverageAnalysis]: Checked inductivity of 2190 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:38:26,940 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:26,940 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:26,940 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:27,307 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-10-07 15:38:27,308 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:27,309 INFO L256 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 8 conjunts are in the unsatisfiable core [2019-10-07 15:38:27,311 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:27,335 INFO L134 CoverageAnalysis]: Checked inductivity of 2190 backedges. 886 proven. 21 refuted. 0 times theorem prover too weak. 1283 trivial. 0 not checked. [2019-10-07 15:38:27,335 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:27,416 INFO L134 CoverageAnalysis]: Checked inductivity of 2190 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:38:27,416 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:27,418 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:27,418 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:27,418 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:27,418 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:27,419 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:27,437 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:28,631 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:28,652 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:28,654 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:28,655 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:28,655 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:28,655 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_sum_~ret~0_BEFORE_RETURN_188 Int) (v_sum_~ret~0_BEFORE_RETURN_187 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (not (< main_~i~2 19)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296)))) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647))) (and (= (mod v_sum_~ret~0_BEFORE_RETURN_188 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647) (not (< main_~i~2 19)))))) (and (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_sum_~ret~0_BEFORE_RETURN_188 Int) (v_sum_~ret~0_BEFORE_RETURN_187 Int)) (or (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (not (< main_~i~2 19)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296)))) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647))) (and (= (mod v_sum_~ret~0_BEFORE_RETURN_188 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:28,655 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:28,656 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:28,656 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:38:28,656 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:28,656 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:28,656 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1359 Int) (v_sum_~ret~0_BEFORE_RETURN_183 Int)) (or (and (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_183 4294967296) (- 4294967296))) (not (< main_~i~1 20)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= (mod v_prenex_1359 4294967296) |main_#t~ret4|) (<= (mod v_prenex_1359 4294967296) 2147483647)))) (exists ((v_prenex_1360 Int) (v_sum_~ret~0_BEFORE_RETURN_184 Int)) (or (and (not (< main_~i~1 20)) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod v_prenex_1360 4294967296) 2147483647))) (and (not (< main_~i~1 20)) (= (mod v_sum_~ret~0_BEFORE_RETURN_184 4294967296) |main_#t~ret4|) (<= (mod v_sum_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647))))) [2019-10-07 15:38:28,656 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:28,656 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:28,657 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:28,657 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:28,657 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:28,657 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:28,657 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:28,657 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:38:28,658 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_1359 Int) (v_prenex_1360 Int) (v_sum_~ret~0_BEFORE_RETURN_184 Int) (v_sum_~ret~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sum_~ret~0_BEFORE_RETURN_184 4294967296) main_~ret~1) (<= (mod v_sum_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1359 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1359 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_183 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_1360 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:28,658 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:28,658 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 20)) (<= 20 sum_~i~0)) [2019-10-07 15:38:28,995 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:28,996 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 11] total 27 [2019-10-07 15:38:28,997 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-10-07 15:38:28,998 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-10-07 15:38:28,998 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=591, Unknown=0, NotChecked=0, Total=756 [2019-10-07 15:38:28,998 INFO L87 Difference]: Start difference. First operand 65 states and 69 transitions. Second operand 28 states. [2019-10-07 15:38:29,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:29,987 INFO L93 Difference]: Finished difference Result 101 states and 113 transitions. [2019-10-07 15:38:29,987 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-10-07 15:38:29,987 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 110 [2019-10-07 15:38:29,988 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:29,989 INFO L225 Difference]: With dead ends: 101 [2019-10-07 15:38:29,989 INFO L226 Difference]: Without dead ends: 73 [2019-10-07 15:38:29,991 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 361 GetRequests, 313 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 611 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=486, Invalid=1964, Unknown=0, NotChecked=0, Total=2450 [2019-10-07 15:38:29,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2019-10-07 15:38:29,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2019-10-07 15:38:29,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2019-10-07 15:38:30,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 77 transitions. [2019-10-07 15:38:30,000 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 77 transitions. Word has length 110 [2019-10-07 15:38:30,000 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:30,000 INFO L462 AbstractCegarLoop]: Abstraction has 73 states and 77 transitions. [2019-10-07 15:38:30,001 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-10-07 15:38:30,001 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 77 transitions. [2019-10-07 15:38:30,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2019-10-07 15:38:30,002 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:30,002 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 14, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:30,212 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:30,213 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:30,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:30,213 INFO L82 PathProgramCache]: Analyzing trace with hash 2034480797, now seen corresponding path program 9 times [2019-10-07 15:38:30,214 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:30,214 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:30,214 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:30,214 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:30,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:30,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:30,417 INFO L134 CoverageAnalysis]: Checked inductivity of 2274 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:38:30,417 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:30,417 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:30,418 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:30,725 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:38:30,726 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:30,728 INFO L256 TraceCheckSpWp]: Trace formula consists of 593 conjuncts, 16 conjunts are in the unsatisfiable core [2019-10-07 15:38:30,731 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:30,770 INFO L134 CoverageAnalysis]: Checked inductivity of 2274 backedges. 886 proven. 105 refuted. 0 times theorem prover too weak. 1283 trivial. 0 not checked. [2019-10-07 15:38:30,771 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:30,933 INFO L134 CoverageAnalysis]: Checked inductivity of 2274 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 2169 trivial. 0 not checked. [2019-10-07 15:38:30,933 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:30,934 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:30,935 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:30,935 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:30,935 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:30,935 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:30,948 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:32,080 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:32,116 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:32,118 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:32,119 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:32,119 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:32,119 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_sum_~ret~0_BEFORE_RETURN_214 Int) (v_sum_~ret~0_BEFORE_RETURN_213 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_214 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (<= (mod v_prenex_1582 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_213 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647) (not (< main_~i~2 19))) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_214 Int) (v_sum_~ret~0_BEFORE_RETURN_213 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_214 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (<= (mod v_prenex_1582 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))) (and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_213 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647) (not (< main_~i~2 19))) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (< main_~i~2 19))))))) [2019-10-07 15:38:32,119 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:32,119 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:32,119 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 76))) (<= 19 main_~i~2) (not (< main_~i~2 19))) [2019-10-07 15:38:32,119 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:32,120 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:38:32,120 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_209 Int) (v_prenex_1553 Int)) (or (and (not (< main_~i~1 20)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 20)) (= (mod v_prenex_1553 4294967296) |main_#t~ret4|) (<= (mod v_prenex_1553 4294967296) 2147483647)))) (exists ((v_prenex_1554 Int) (v_sum_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (not (< main_~i~1 20)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296)))) (and (not (< main_~i~1 20)) (= (mod v_prenex_1554 4294967296) |main_#t~ret4|) (<= (mod v_prenex_1554 4294967296) 2147483647))))) [2019-10-07 15:38:32,120 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:32,120 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:32,120 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:32,120 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:32,120 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:32,120 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:32,120 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:32,121 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 20)) (<= 20 main_~i~1)) [2019-10-07 15:38:32,121 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_209 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_sum_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1554 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1554 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1553 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_1553 4294967296)) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_sum_~ret~0_BEFORE_RETURN_209 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_sum_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1554 4294967296)) (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1554 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (< main_~i~1 20)) (<= main_~ret~1 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_1553 4294967296)) (<= (mod v_prenex_1553 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:38:32,121 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:32,121 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 20)) (<= 20 sum_~i~0)) [2019-10-07 15:38:32,469 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:32,469 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 11] total 32 [2019-10-07 15:38:32,471 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-10-07 15:38:32,471 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-10-07 15:38:32,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=260, Invalid=796, Unknown=0, NotChecked=0, Total=1056 [2019-10-07 15:38:32,472 INFO L87 Difference]: Start difference. First operand 73 states and 77 transitions. Second operand 33 states. [2019-10-07 15:38:33,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:33,810 INFO L93 Difference]: Finished difference Result 106 states and 115 transitions. [2019-10-07 15:38:33,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-10-07 15:38:33,811 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 118 [2019-10-07 15:38:33,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:33,813 INFO L225 Difference]: With dead ends: 106 [2019-10-07 15:38:33,813 INFO L226 Difference]: Without dead ends: 78 [2019-10-07 15:38:33,814 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 398 GetRequests, 329 SyntacticMatches, 11 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 858 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=771, Invalid=2769, Unknown=0, NotChecked=0, Total=3540 [2019-10-07 15:38:33,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2019-10-07 15:38:33,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 78. [2019-10-07 15:38:33,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2019-10-07 15:38:33,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 82 transitions. [2019-10-07 15:38:33,824 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 82 transitions. Word has length 118 [2019-10-07 15:38:33,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:33,824 INFO L462 AbstractCegarLoop]: Abstraction has 78 states and 82 transitions. [2019-10-07 15:38:33,824 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-10-07 15:38:33,824 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 82 transitions. [2019-10-07 15:38:33,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2019-10-07 15:38:33,826 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:33,826 INFO L385 BasicCegarLoop]: trace histogram [60, 20, 19, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:34,042 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:34,043 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:34,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:34,043 INFO L82 PathProgramCache]: Analyzing trace with hash 1761197326, now seen corresponding path program 10 times [2019-10-07 15:38:34,043 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:34,043 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:34,043 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:34,043 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:34,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:38,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat