java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/sum40-2.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:38:06,266 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:38:06,268 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:38:06,281 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:38:06,282 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:38:06,283 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:38:06,284 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:38:06,286 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:38:06,288 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:38:06,289 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:38:06,290 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:38:06,291 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:38:06,291 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:38:06,292 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:38:06,293 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:38:06,294 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:38:06,295 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:38:06,296 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:38:06,298 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:38:06,300 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:38:06,302 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:38:06,303 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:38:06,304 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:38:06,305 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:38:06,311 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 15:38:06,324 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:38:06,325 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:38:06,326 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:38:06,327 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:38:06,352 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:38:06,352 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:38:06,353 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:38:06,353 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:38:06,354 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:38:06,354 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:38:06,354 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:38:06,354 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:38:06,354 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:38:06,355 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:38:06,355 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:38:06,355 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:38:06,355 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:38:06,355 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:38:06,356 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:38:06,356 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:38:06,356 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:38:06,356 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:38:06,356 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:38:06,357 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:38:06,357 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:38:06,357 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:38:06,357 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:38:06,357 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:38:06,358 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:38:06,358 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:38:06,358 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:38:06,358 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:38:06,358 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:38:06,639 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:38:06,663 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:38:06,667 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:38:06,668 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:38:06,668 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:38:06,669 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/sum40-2.i [2019-10-07 15:38:06,732 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/17a61ce17/77b60ca40d96441cbcb9517ec0b9836d/FLAG93b65a7b2 [2019-10-07 15:38:07,215 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:38:07,217 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/sum40-2.i [2019-10-07 15:38:07,224 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/17a61ce17/77b60ca40d96441cbcb9517ec0b9836d/FLAG93b65a7b2 [2019-10-07 15:38:07,613 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/17a61ce17/77b60ca40d96441cbcb9517ec0b9836d [2019-10-07 15:38:07,624 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:38:07,626 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:38:07,627 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:38:07,627 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:38:07,630 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:38:07,631 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:38:07" (1/1) ... [2019-10-07 15:38:07,635 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@49584703 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:07, skipping insertion in model container [2019-10-07 15:38:07,635 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:38:07" (1/1) ... [2019-10-07 15:38:07,642 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:38:07,657 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:38:07,835 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:38:07,846 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:38:07,867 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:38:07,881 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:38:07,882 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:07 WrapperNode [2019-10-07 15:38:07,882 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:38:07,882 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:38:07,882 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:38:07,882 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:38:07,972 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:07" (1/1) ... [2019-10-07 15:38:07,973 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:07" (1/1) ... [2019-10-07 15:38:07,980 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:07" (1/1) ... [2019-10-07 15:38:07,980 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:07" (1/1) ... [2019-10-07 15:38:07,989 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:07" (1/1) ... [2019-10-07 15:38:07,994 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:07" (1/1) ... [2019-10-07 15:38:07,997 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:07" (1/1) ... [2019-10-07 15:38:08,000 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:38:08,000 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:38:08,001 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:38:08,001 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:38:08,002 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:07" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:38:08,059 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:38:08,060 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:38:08,060 INFO L138 BoogieDeclarations]: Found implementation of procedure sum [2019-10-07 15:38:08,060 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:38:08,060 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:38:08,060 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:38:08,060 INFO L130 BoogieDeclarations]: Found specification of procedure sum [2019-10-07 15:38:08,061 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:38:08,061 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:38:08,061 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:38:08,061 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:38:08,061 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:38:08,061 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:38:08,062 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:38:08,440 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:38:08,440 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:38:08,442 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:38:08 BoogieIcfgContainer [2019-10-07 15:38:08,442 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:38:08,443 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:38:08,443 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:38:08,447 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:38:08,447 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:38:07" (1/3) ... [2019-10-07 15:38:08,448 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7ffab871 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:38:08, skipping insertion in model container [2019-10-07 15:38:08,448 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:07" (2/3) ... [2019-10-07 15:38:08,449 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7ffab871 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:38:08, skipping insertion in model container [2019-10-07 15:38:08,449 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:38:08" (3/3) ... [2019-10-07 15:38:08,451 INFO L109 eAbstractionObserver]: Analyzing ICFG sum40-2.i [2019-10-07 15:38:08,461 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:38:08,469 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:38:08,481 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:38:08,506 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:38:08,506 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:38:08,506 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:38:08,506 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:38:08,506 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:38:08,506 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:38:08,506 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:38:08,507 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:38:08,523 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:38:08,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:38:08,529 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:08,530 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:08,532 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:08,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:08,536 INFO L82 PathProgramCache]: Analyzing trace with hash -1818423299, now seen corresponding path program 1 times [2019-10-07 15:38:08,544 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:08,544 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:08,545 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:08,545 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:08,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:08,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:08,732 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:38:08,733 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:08,734 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:38:08,734 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:38:08,739 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:38:08,757 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:38:08,758 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:38:08,762 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:38:08,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:08,821 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:38:08,825 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:38:08,827 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:38:08,828 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:08,840 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:38:08,841 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:38:08,850 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:38:08,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:38:08,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:38:08,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:38:08,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:38:08,913 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:38:08,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:08,914 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:38:08,914 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:38:08,914 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:38:08,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:38:08,916 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:08,917 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:08,917 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:08,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:08,918 INFO L82 PathProgramCache]: Analyzing trace with hash -2093950433, now seen corresponding path program 1 times [2019-10-07 15:38:08,918 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:08,918 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:08,919 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:08,919 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:08,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:08,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:09,002 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:38:09,002 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:09,003 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:09,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:09,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:09,077 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:38:09,085 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:09,117 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:38:09,117 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:09,173 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:38:09,174 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:38:09,174 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:38:09,176 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:38:09,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:38:09,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:38:09,177 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:38:09,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:09,188 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:38:09,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:38:09,189 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:38:09,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:09,190 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:38:09,190 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:38:09,191 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:38:09,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:38:09,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:38:09,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:38:09,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:38:09,199 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:38:09,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:09,200 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:38:09,200 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:38:09,201 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:38:09,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:38:09,203 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:09,204 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:09,408 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:09,410 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:09,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:09,411 INFO L82 PathProgramCache]: Analyzing trace with hash 903502258, now seen corresponding path program 1 times [2019-10-07 15:38:09,411 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:09,412 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:09,413 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:09,414 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:09,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:09,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:09,545 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:09,545 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:09,546 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:38:09,546 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:38:09,546 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:38:09,547 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:38:09,548 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:38:09,549 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:38:09,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:09,565 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:38:09,565 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:38:09,566 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:38:09,566 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:09,567 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:38:09,567 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:38:09,568 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:38:09,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:38:09,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:38:09,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:38:09,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:38:09,574 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:38:09,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:09,576 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:38:09,576 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:38:09,576 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:38:09,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:38:09,578 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:09,579 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:09,579 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:09,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:09,580 INFO L82 PathProgramCache]: Analyzing trace with hash 2130547361, now seen corresponding path program 1 times [2019-10-07 15:38:09,580 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:09,580 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:09,580 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:09,580 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:09,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:09,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:09,691 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:09,692 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:09,692 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:09,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:09,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:09,759 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:38:09,762 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:09,801 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:09,802 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:09,839 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:09,839 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:09,870 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:09,870 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:09,879 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:09,888 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:09,888 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:10,040 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:12,283 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:12,350 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:12,355 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:12,355 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:12,356 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:12,356 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:12,356 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:12,356 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:38:12,357 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret5~0)) (exists ((v_prenex_29 Int) (v_sum_~ret~0_BEFORE_RETURN_5 Int) (v_sum_~ret~0_BEFORE_RETURN_6 Int) (v_prenex_30 Int)) (or (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (<= (mod v_prenex_30 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_29 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (= (mod v_prenex_29 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_6 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_sum_~ret~0_BEFORE_RETURN_5 Int) (v_sum_~ret~0_BEFORE_RETURN_6 Int) (v_prenex_30 Int)) (or (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (<= (mod v_prenex_30 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_29 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (= (mod v_prenex_29 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_6 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:38:12,357 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:12,357 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:12,358 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1 Int) (v_sum_~ret~0_BEFORE_RETURN_1 Int)) (or (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod v_sum_~ret~0_BEFORE_RETURN_1 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (= |main_#t~ret4| (+ (mod v_prenex_1 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1 4294967296) 2147483647))))) (exists ((v_prenex_2 Int) (v_sum_~ret~0_BEFORE_RETURN_2 Int)) (or (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40))) (and (not (< main_~i~1 40)) (= (mod v_sum_~ret~0_BEFORE_RETURN_2 4294967296) |main_#t~ret4|) (<= (mod v_sum_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647))))) [2019-10-07 15:38:12,358 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:12,358 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:12,358 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:12,359 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:12,359 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:12,359 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:12,359 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:12,359 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:38:12,361 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_2 Int) (v_prenex_1 Int) (v_sum_~ret~0_BEFORE_RETURN_1 Int) (v_sum_~ret~0_BEFORE_RETURN_2 Int)) (or (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (mod v_sum_~ret~0_BEFORE_RETURN_2 4294967296) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_1 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:12,362 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:12,362 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (<= 40 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 40))) [2019-10-07 15:38:12,755 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:12,756 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:38:12,758 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-07 15:38:12,758 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-07 15:38:12,759 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-07 15:38:12,759 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-07 15:38:13,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:13,527 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:38:13,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-07 15:38:13,527 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-07 15:38:13,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:13,528 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:38:13,528 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:38:13,530 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=133, Invalid=737, Unknown=0, NotChecked=0, Total=870 [2019-10-07 15:38:13,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:38:13,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:38:13,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:38:13,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:38:13,537 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:38:13,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:13,537 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:38:13,538 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-07 15:38:13,538 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:38:13,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:38:13,539 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:13,539 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:13,747 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:13,748 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:13,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:13,748 INFO L82 PathProgramCache]: Analyzing trace with hash 356639231, now seen corresponding path program 2 times [2019-10-07 15:38:13,748 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:13,749 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:13,749 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:13,749 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:13,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:13,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:13,855 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:13,855 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:13,855 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:13,855 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:13,946 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:38:13,949 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:13,952 INFO L256 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:38:13,957 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:13,984 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:38:13,985 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:14,031 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:38:14,031 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:14,034 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:14,034 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:14,035 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:14,035 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:14,035 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:14,069 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:15,670 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:15,697 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:15,700 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:15,701 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:15,701 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:15,701 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:15,701 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:15,701 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:38:15,702 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_sum_~ret~0_BEFORE_RETURN_32 Int) (v_prenex_224 Int) (v_sum_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_32 Int) (v_prenex_224 Int) (v_sum_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:38:15,702 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:15,702 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:15,703 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_196 Int) (v_sum_~ret~0_BEFORE_RETURN_28 Int)) (or (and (not (< main_~i~1 40)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_28 4294967296) (- 4294967296))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (<= (mod v_prenex_196 4294967296) 2147483647) (= (mod v_prenex_196 4294967296) |main_#t~ret4|)))) (exists ((v_sum_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod v_prenex_195 4294967296) 2147483647)) (= (+ (mod v_prenex_195 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_27 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647))))) [2019-10-07 15:38:15,703 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:15,703 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:15,703 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:15,703 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:15,703 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:15,704 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:15,704 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:15,704 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:38:15,704 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_196 Int) (v_sum_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int) (v_sum_~ret~0_BEFORE_RETURN_28 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (not (<= (mod v_prenex_195 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_prenex_195 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_prenex_196 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_196 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_28 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_27 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:15,704 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:15,704 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (<= 40 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 40))) [2019-10-07 15:38:16,168 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:16,168 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:38:16,169 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-07 15:38:16,169 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-07 15:38:16,170 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-07 15:38:16,170 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-07 15:38:17,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:17,167 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:38:17,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:38:17,167 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-07 15:38:17,167 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:17,168 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:38:17,168 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:38:17,171 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-07 15:38:17,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:38:17,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:38:17,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:38:17,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:38:17,177 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:38:17,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:17,178 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:38:17,178 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-07 15:38:17,178 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:38:17,179 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:38:17,179 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:17,180 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:17,382 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:17,383 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:17,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:17,384 INFO L82 PathProgramCache]: Analyzing trace with hash 906031436, now seen corresponding path program 3 times [2019-10-07 15:38:17,384 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:17,384 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:17,385 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:17,385 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:17,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:17,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:17,489 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:17,490 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:17,490 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:17,490 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:17,623 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:38:17,623 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:17,625 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:38:17,628 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:17,643 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:17,644 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:17,771 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:17,771 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:17,773 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:17,773 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:17,774 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:17,774 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:17,774 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:17,797 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:19,369 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:19,408 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:19,413 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:19,413 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:19,414 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:19,414 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:19,414 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:19,415 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:38:19,415 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_sum_~ret~0_BEFORE_RETURN_58 Int) (v_sum_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int)) (or (and (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_sum_~ret~0_BEFORE_RETURN_58 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_sum_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret2~0))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_58 Int) (v_sum_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int)) (or (and (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_sum_~ret~0_BEFORE_RETURN_58 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_sum_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:19,416 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:19,416 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:19,416 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_389 Int) (v_sum_~ret~0_BEFORE_RETURN_53 Int)) (or (and (= (mod v_sum_~ret~0_BEFORE_RETURN_53 4294967296) |main_#t~ret4|) (not (< main_~i~1 40)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647)) (and (not (<= (mod v_prenex_389 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod v_prenex_389 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_sum_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 40)) (not (<= (mod v_prenex_390 4294967296) 2147483647))) (and (= (mod v_sum_~ret~0_BEFORE_RETURN_54 4294967296) |main_#t~ret4|) (<= (mod v_sum_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (not (< main_~i~1 40)))))) [2019-10-07 15:38:19,417 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:19,417 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:19,417 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:19,417 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:19,418 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:19,418 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:19,418 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:19,419 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:38:19,419 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_sum_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_389 Int) (v_sum_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_390 Int)) (or (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sum_~ret~0_BEFORE_RETURN_54 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (+ (mod v_prenex_389 4294967296) (- 4294967296))) (not (<= (mod v_prenex_389 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= (mod v_sum_~ret~0_BEFORE_RETURN_53 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:19,419 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:19,420 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (<= 40 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 40))) [2019-10-07 15:38:20,006 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:20,006 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-07 15:38:20,007 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-07 15:38:20,009 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-07 15:38:20,009 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-07 15:38:20,010 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-07 15:38:20,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:20,991 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-07 15:38:20,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-07 15:38:20,991 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-07 15:38:20,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:20,993 INFO L225 Difference]: With dead ends: 54 [2019-10-07 15:38:20,993 INFO L226 Difference]: Without dead ends: 36 [2019-10-07 15:38:20,994 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-07 15:38:20,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-07 15:38:21,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-07 15:38:21,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-07 15:38:21,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-07 15:38:21,021 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-07 15:38:21,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:21,021 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-07 15:38:21,021 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-07 15:38:21,021 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-07 15:38:21,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-07 15:38:21,022 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:21,022 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:21,226 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:21,227 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:21,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:21,228 INFO L82 PathProgramCache]: Analyzing trace with hash -1194663378, now seen corresponding path program 4 times [2019-10-07 15:38:21,228 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:21,228 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:21,228 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:21,229 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:21,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:21,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:21,413 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:21,413 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:21,414 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:21,414 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:21,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:21,584 INFO L256 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:38:21,587 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:21,600 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:21,600 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:21,935 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:21,936 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:21,937 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:21,937 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:21,938 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:21,938 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:21,938 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:21,959 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:23,284 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:23,318 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:23,321 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:23,321 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:23,321 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:23,322 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:23,322 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:23,322 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:38:23,322 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_sum_~ret~0_BEFORE_RETURN_84 Int) (v_sum_~ret~0_BEFORE_RETURN_83 Int)) (or (and (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_83 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_612 4294967296) 2147483647) (= (mod v_prenex_612 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_84 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_611 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_611 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_sum_~ret~0_BEFORE_RETURN_84 Int) (v_sum_~ret~0_BEFORE_RETURN_83 Int)) (or (and (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_83 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_612 4294967296) 2147483647) (= (mod v_prenex_612 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_84 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_611 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_611 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:38:23,323 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:23,323 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:23,323 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_583 Int) (v_sum_~ret~0_BEFORE_RETURN_79 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_79 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (mod v_prenex_583 4294967296) |main_#t~ret4|) (not (< main_~i~1 40)) (<= (mod v_prenex_583 4294967296) 2147483647)))) (exists ((v_prenex_584 Int) (v_sum_~ret~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 40)) (= |main_#t~ret4| (+ (mod v_prenex_584 4294967296) (- 4294967296))) (not (<= (mod v_prenex_584 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_80 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647))))) [2019-10-07 15:38:23,323 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:23,323 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:23,324 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:23,324 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:23,324 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:23,324 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:23,324 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:23,324 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:38:23,325 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_583 Int) (v_prenex_584 Int) (v_sum_~ret~0_BEFORE_RETURN_79 Int) (v_sum_~ret~0_BEFORE_RETURN_80 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_584 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_prenex_584 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_80 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_prenex_583 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_583 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:23,325 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:23,325 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (<= 40 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 40))) [2019-10-07 15:38:23,732 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:23,732 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-07 15:38:23,733 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-07 15:38:23,734 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-07 15:38:23,735 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:38:23,736 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 40 states. [2019-10-07 15:38:25,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:25,391 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-07 15:38:25,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-07 15:38:25,391 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 49 [2019-10-07 15:38:25,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:25,392 INFO L225 Difference]: With dead ends: 68 [2019-10-07 15:38:25,393 INFO L226 Difference]: Without dead ends: 50 [2019-10-07 15:38:25,395 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:38:25,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-07 15:38:25,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-07 15:38:25,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-07 15:38:25,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-07 15:38:25,403 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-07 15:38:25,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:25,403 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-07 15:38:25,403 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-07 15:38:25,403 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-07 15:38:25,404 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-07 15:38:25,405 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:25,405 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:25,605 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:25,606 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:25,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:25,607 INFO L82 PathProgramCache]: Analyzing trace with hash 1997950062, now seen corresponding path program 5 times [2019-10-07 15:38:25,607 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:25,607 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:25,607 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:25,607 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:25,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:25,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:26,202 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:26,203 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:26,203 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:26,203 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:26,399 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:38:26,400 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:26,401 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:38:26,404 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:26,443 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-07 15:38:26,444 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:26,508 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-07 15:38:26,508 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:26,510 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:26,510 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:26,510 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:26,510 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:26,511 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:26,534 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:27,890 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:27,915 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:27,919 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:27,919 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:27,919 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:27,920 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:27,920 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:27,920 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:38:27,920 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_sum_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_109 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_sum_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_109 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:27,921 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:27,921 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:38:27,921 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_106 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)))) (exists ((v_prenex_777 Int) (v_sum_~ret~0_BEFORE_RETURN_105 Int)) (or (and (<= (mod v_prenex_777 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_777 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_105 4294967296) (- 4294967296))))))) [2019-10-07 15:38:27,921 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:27,922 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:27,922 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:27,922 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:27,922 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:27,922 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:27,923 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:27,923 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:38:27,923 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_777 Int) (v_sum_~ret~0_BEFORE_RETURN_106 Int) (v_sum_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_778 Int)) (or (and (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_106 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_prenex_777 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_777 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_105 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:27,923 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:27,923 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (<= 40 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 40))) [2019-10-07 15:38:28,506 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:28,506 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-07 15:38:28,507 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-07 15:38:28,507 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-07 15:38:28,508 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-07 15:38:28,508 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 44 states. [2019-10-07 15:38:31,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:31,052 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-07 15:38:31,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-07 15:38:31,053 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 63 [2019-10-07 15:38:31,053 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:31,054 INFO L225 Difference]: With dead ends: 72 [2019-10-07 15:38:31,054 INFO L226 Difference]: Without dead ends: 54 [2019-10-07 15:38:31,057 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1350 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=1349, Invalid=5457, Unknown=0, NotChecked=0, Total=6806 [2019-10-07 15:38:31,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-07 15:38:31,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-07 15:38:31,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-07 15:38:31,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-07 15:38:31,065 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-07 15:38:31,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:31,066 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-07 15:38:31,066 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-07 15:38:31,066 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-07 15:38:31,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-07 15:38:31,067 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:31,067 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:31,271 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:31,271 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:31,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:31,271 INFO L82 PathProgramCache]: Analyzing trace with hash 1475332959, now seen corresponding path program 6 times [2019-10-07 15:38:31,272 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:31,272 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:31,272 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:31,273 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:31,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:31,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:31,891 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:38:31,891 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:31,892 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:31,892 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:32,182 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:38:32,182 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:32,184 INFO L256 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-07 15:38:32,187 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:32,206 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:38:32,206 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:33,080 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:38:33,081 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:33,082 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:33,082 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:33,083 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:33,083 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:33,083 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:33,103 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:34,496 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:34,523 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:34,526 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:34,526 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:34,526 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:34,527 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:34,527 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:34,527 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:38:34,527 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_sum_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_sum_~ret~0_BEFORE_RETURN_135 Int) (v_prenex_999 Int)) (or (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647))) (and (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_136 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1000 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_sum_~ret~0_BEFORE_RETURN_135 Int) (v_prenex_999 Int)) (or (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647))) (and (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_136 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1000 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:38:34,528 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:34,528 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:34,528 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_972 Int) (v_sum_~ret~0_BEFORE_RETURN_132 Int)) (or (and (= (mod v_sum_~ret~0_BEFORE_RETURN_132 4294967296) |main_#t~ret4|) (not (< main_~i~1 40)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (= (+ (mod v_prenex_972 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_prenex_971 Int) (v_sum_~ret~0_BEFORE_RETURN_131 Int)) (or (and (= |main_#t~ret4| (+ (mod v_prenex_971 4294967296) (- 4294967296))) (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 40))) (and (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_131 4294967296)) (not (< main_~i~1 40)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647))))) [2019-10-07 15:38:34,528 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:34,528 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:34,529 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:34,529 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:34,529 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:34,529 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:34,529 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:34,529 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:38:34,530 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_sum_~ret~0_BEFORE_RETURN_132 Int) (v_sum_~ret~0_BEFORE_RETURN_131 Int)) (or (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_132 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_131 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:34,530 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:34,530 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (<= 40 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 40))) [2019-10-07 15:38:35,031 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:35,032 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 53 [2019-10-07 15:38:35,033 INFO L442 AbstractCegarLoop]: Interpolant automaton has 54 states [2019-10-07 15:38:35,034 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2019-10-07 15:38:35,035 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=932, Invalid=1930, Unknown=0, NotChecked=0, Total=2862 [2019-10-07 15:38:35,036 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 54 states. [2019-10-07 15:38:39,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:39,511 INFO L93 Difference]: Finished difference Result 88 states and 108 transitions. [2019-10-07 15:38:39,511 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-10-07 15:38:39,512 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 67 [2019-10-07 15:38:39,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:39,513 INFO L225 Difference]: With dead ends: 88 [2019-10-07 15:38:39,513 INFO L226 Difference]: Without dead ends: 67 [2019-10-07 15:38:39,516 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 281 GetRequests, 165 SyntacticMatches, 16 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2497 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=2707, Invalid=7595, Unknown=0, NotChecked=0, Total=10302 [2019-10-07 15:38:39,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2019-10-07 15:38:39,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2019-10-07 15:38:39,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2019-10-07 15:38:39,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 71 transitions. [2019-10-07 15:38:39,525 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 71 transitions. Word has length 67 [2019-10-07 15:38:39,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:39,526 INFO L462 AbstractCegarLoop]: Abstraction has 67 states and 71 transitions. [2019-10-07 15:38:39,526 INFO L463 AbstractCegarLoop]: Interpolant automaton has 54 states. [2019-10-07 15:38:39,526 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 71 transitions. [2019-10-07 15:38:39,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2019-10-07 15:38:39,527 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:39,528 INFO L385 BasicCegarLoop]: trace histogram [40, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:39,732 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:39,732 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:39,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:39,732 INFO L82 PathProgramCache]: Analyzing trace with hash 1228286333, now seen corresponding path program 7 times [2019-10-07 15:38:39,733 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:39,733 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:39,733 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:39,733 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:39,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:39,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:39,894 INFO L134 CoverageAnalysis]: Checked inductivity of 941 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 931 trivial. 0 not checked. [2019-10-07 15:38:39,894 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:39,894 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:39,895 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:40,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:40,175 INFO L256 TraceCheckSpWp]: Trace formula consists of 433 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:38:40,178 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:40,228 INFO L134 CoverageAnalysis]: Checked inductivity of 941 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 879 trivial. 0 not checked. [2019-10-07 15:38:40,228 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:40,367 INFO L134 CoverageAnalysis]: Checked inductivity of 941 backedges. 0 proven. 62 refuted. 0 times theorem prover too weak. 879 trivial. 0 not checked. [2019-10-07 15:38:40,367 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:40,369 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:40,369 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:40,369 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:40,370 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:40,370 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:40,386 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:41,587 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:41,620 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:41,623 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:41,623 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:41,623 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:41,623 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:41,624 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:41,624 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:38:41,624 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1194 Int) (v_sum_~ret~0_BEFORE_RETURN_162 Int) (v_prenex_1193 Int) (v_sum_~ret~0_BEFORE_RETURN_161 Int)) (or (and (<= (mod v_prenex_1193 4294967296) 2147483647) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_prenex_1194 Int) (v_sum_~ret~0_BEFORE_RETURN_162 Int) (v_prenex_1193 Int) (v_sum_~ret~0_BEFORE_RETURN_161 Int)) (or (and (<= (mod v_prenex_1193 4294967296) 2147483647) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:41,624 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:41,624 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:41,625 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1165 Int) (v_sum_~ret~0_BEFORE_RETURN_157 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296)))) (and (<= (mod v_prenex_1165 4294967296) 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_1165 4294967296) |main_#t~ret4|)))) (exists ((v_sum_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int)) (or (and (<= (mod v_prenex_1166 4294967296) 2147483647) (not (< main_~i~1 40)) (= |main_#t~ret4| (mod v_prenex_1166 4294967296))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret4|))))) [2019-10-07 15:38:41,625 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:41,625 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:41,625 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:41,626 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:41,626 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:41,626 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:41,626 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:41,626 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:38:41,626 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int) (v_prenex_1165 Int) (v_sum_~ret~0_BEFORE_RETURN_157 Int)) (or (and (= main_~ret~1 (mod v_prenex_1166 4294967296)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_prenex_1165 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_1165 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_sum_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int) (v_prenex_1165 Int) (v_sum_~ret~0_BEFORE_RETURN_157 Int)) (or (and (= main_~ret~1 (mod v_prenex_1166 4294967296)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1165 4294967296)) (<= (mod v_prenex_1165 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:38:41,626 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:41,627 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (<= 40 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 40))) [2019-10-07 15:38:42,017 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:42,018 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 27 [2019-10-07 15:38:42,019 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-10-07 15:38:42,019 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-10-07 15:38:42,020 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=641, Unknown=0, NotChecked=0, Total=756 [2019-10-07 15:38:42,020 INFO L87 Difference]: Start difference. First operand 67 states and 71 transitions. Second operand 28 states. [2019-10-07 15:38:47,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:47,330 INFO L93 Difference]: Finished difference Result 94 states and 110 transitions. [2019-10-07 15:38:47,330 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-10-07 15:38:47,331 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 80 [2019-10-07 15:38:47,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:47,332 INFO L225 Difference]: With dead ends: 94 [2019-10-07 15:38:47,332 INFO L226 Difference]: Without dead ends: 74 [2019-10-07 15:38:47,333 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 270 GetRequests, 221 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 581 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=409, Invalid=2141, Unknown=0, NotChecked=0, Total=2550 [2019-10-07 15:38:47,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2019-10-07 15:38:47,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 74. [2019-10-07 15:38:47,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2019-10-07 15:38:47,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 78 transitions. [2019-10-07 15:38:47,343 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 78 transitions. Word has length 80 [2019-10-07 15:38:47,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:47,344 INFO L462 AbstractCegarLoop]: Abstraction has 74 states and 78 transitions. [2019-10-07 15:38:47,344 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-10-07 15:38:47,344 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 78 transitions. [2019-10-07 15:38:47,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2019-10-07 15:38:47,345 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:47,346 INFO L385 BasicCegarLoop]: trace histogram [40, 30, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:47,549 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:47,550 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:47,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:47,551 INFO L82 PathProgramCache]: Analyzing trace with hash 906923278, now seen corresponding path program 8 times [2019-10-07 15:38:47,551 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:47,551 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:47,551 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:47,552 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:47,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:47,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:47,741 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 1070 trivial. 0 not checked. [2019-10-07 15:38:47,742 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:47,742 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:47,742 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:48,108 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-10-07 15:38:48,108 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:48,110 INFO L256 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:38:48,112 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:48,179 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 246 proven. 15 refuted. 0 times theorem prover too weak. 1108 trivial. 0 not checked. [2019-10-07 15:38:48,179 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:48,325 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 1354 trivial. 0 not checked. [2019-10-07 15:38:48,325 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:48,327 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:48,327 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:48,328 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:48,328 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:48,328 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:48,344 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:49,656 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:49,685 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:49,688 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:49,688 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:49,688 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:49,688 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:49,689 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:49,689 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:38:49,689 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_sum_~ret~0_BEFORE_RETURN_188 Int) (v_sum_~ret~0_BEFORE_RETURN_187 Int)) (or (and (= (mod v_sum_~ret~0_BEFORE_RETURN_188 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_sum_~ret~0_BEFORE_RETURN_188 Int) (v_sum_~ret~0_BEFORE_RETURN_187 Int)) (or (and (= (mod v_sum_~ret~0_BEFORE_RETURN_188 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:38:49,689 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:49,690 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:49,690 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1359 Int) (v_sum_~ret~0_BEFORE_RETURN_183 Int)) (or (and (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_183 4294967296) (- 4294967296))) (not (< main_~i~1 40)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (= (mod v_prenex_1359 4294967296) |main_#t~ret4|) (<= (mod v_prenex_1359 4294967296) 2147483647)))) (exists ((v_prenex_1360 Int) (v_sum_~ret~0_BEFORE_RETURN_184 Int)) (or (and (not (< main_~i~1 40)) (= (mod v_sum_~ret~0_BEFORE_RETURN_184 4294967296) |main_#t~ret4|) (<= (mod v_sum_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647)) (and (not (< main_~i~1 40)) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod v_prenex_1360 4294967296) 2147483647)))))) [2019-10-07 15:38:49,690 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:49,690 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:49,690 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:49,690 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:49,690 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:49,691 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:49,691 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:49,691 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:38:49,691 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_1359 Int) (v_prenex_1360 Int) (v_sum_~ret~0_BEFORE_RETURN_184 Int) (v_sum_~ret~0_BEFORE_RETURN_183 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_1360 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sum_~ret~0_BEFORE_RETURN_184 4294967296) main_~ret~1) (<= (mod v_sum_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1359 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1359 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_183 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:49,691 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:49,691 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (<= 40 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 40))) [2019-10-07 15:38:50,121 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:50,122 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 8, 8, 11] total 35 [2019-10-07 15:38:50,123 INFO L442 AbstractCegarLoop]: Interpolant automaton has 36 states [2019-10-07 15:38:50,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2019-10-07 15:38:50,124 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=198, Invalid=1062, Unknown=0, NotChecked=0, Total=1260 [2019-10-07 15:38:50,124 INFO L87 Difference]: Start difference. First operand 74 states and 78 transitions. Second operand 36 states. [2019-10-07 15:38:52,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:52,031 INFO L93 Difference]: Finished difference Result 109 states and 126 transitions. [2019-10-07 15:38:52,031 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-10-07 15:38:52,031 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 99 [2019-10-07 15:38:52,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:52,032 INFO L225 Difference]: With dead ends: 109 [2019-10-07 15:38:52,032 INFO L226 Difference]: Without dead ends: 82 [2019-10-07 15:38:52,034 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 340 GetRequests, 275 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1030 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=676, Invalid=3746, Unknown=0, NotChecked=0, Total=4422 [2019-10-07 15:38:52,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2019-10-07 15:38:52,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 82. [2019-10-07 15:38:52,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2019-10-07 15:38:52,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 86 transitions. [2019-10-07 15:38:52,043 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 86 transitions. Word has length 99 [2019-10-07 15:38:52,043 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:52,044 INFO L462 AbstractCegarLoop]: Abstraction has 82 states and 86 transitions. [2019-10-07 15:38:52,044 INFO L463 AbstractCegarLoop]: Interpolant automaton has 36 states. [2019-10-07 15:38:52,044 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 86 transitions. [2019-10-07 15:38:52,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2019-10-07 15:38:52,045 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:52,046 INFO L385 BasicCegarLoop]: trace histogram [40, 33, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:52,250 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:52,250 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:52,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:52,251 INFO L82 PathProgramCache]: Analyzing trace with hash -1862605644, now seen corresponding path program 9 times [2019-10-07 15:38:52,251 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:52,251 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:52,252 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:52,252 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:52,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:52,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:52,452 INFO L134 CoverageAnalysis]: Checked inductivity of 1534 backedges. 145 proven. 211 refuted. 0 times theorem prover too weak. 1178 trivial. 0 not checked. [2019-10-07 15:38:52,452 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:52,452 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:52,453 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:52,809 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:38:52,809 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:52,812 INFO L256 TraceCheckSpWp]: Trace formula consists of 570 conjuncts, 13 conjunts are in the unsatisfiable core [2019-10-07 15:38:52,815 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:52,844 INFO L134 CoverageAnalysis]: Checked inductivity of 1534 backedges. 290 proven. 66 refuted. 0 times theorem prover too weak. 1178 trivial. 0 not checked. [2019-10-07 15:38:52,844 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:53,094 INFO L134 CoverageAnalysis]: Checked inductivity of 1534 backedges. 0 proven. 356 refuted. 0 times theorem prover too weak. 1178 trivial. 0 not checked. [2019-10-07 15:38:53,095 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:53,100 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:53,100 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:53,101 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:53,101 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:53,102 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:53,116 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:54,422 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:54,447 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:54,449 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:54,449 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:54,450 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:54,450 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:54,450 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:54,450 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:38:54,450 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_214 Int) (v_sum_~ret~0_BEFORE_RETURN_213 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1582 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_214 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_213 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_214 Int) (v_sum_~ret~0_BEFORE_RETURN_213 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1582 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_214 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_213 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:54,450 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:54,450 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:38:54,451 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1554 Int) (v_sum_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (not (< main_~i~1 40)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296)))) (and (not (< main_~i~1 40)) (= (mod v_prenex_1554 4294967296) |main_#t~ret4|) (<= (mod v_prenex_1554 4294967296) 2147483647)))) (exists ((v_sum_~ret~0_BEFORE_RETURN_209 Int) (v_prenex_1553 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (= (mod v_prenex_1553 4294967296) |main_#t~ret4|) (<= (mod v_prenex_1553 4294967296) 2147483647))))) [2019-10-07 15:38:54,451 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:54,451 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:54,451 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:54,451 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:54,452 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:54,452 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:54,452 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:54,453 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:38:54,453 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_209 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_sum_~ret~0_BEFORE_RETURN_210 Int)) (or (and (= main_~ret~1 (mod v_prenex_1554 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1554 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1553 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_1553 4294967296)) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_sum_~ret~0_BEFORE_RETURN_209 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_sum_~ret~0_BEFORE_RETURN_210 Int)) (or (and (= main_~ret~1 (mod v_prenex_1554 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1554 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_1553 4294967296)) (<= (mod v_prenex_1553 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:38:54,453 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:54,453 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (<= 40 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 40))) [2019-10-07 15:38:54,823 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:54,823 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 11] total 37 [2019-10-07 15:38:54,825 INFO L442 AbstractCegarLoop]: Interpolant automaton has 38 states [2019-10-07 15:38:54,825 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2019-10-07 15:38:54,826 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=381, Invalid=1025, Unknown=0, NotChecked=0, Total=1406 [2019-10-07 15:38:54,826 INFO L87 Difference]: Start difference. First operand 82 states and 86 transitions. Second operand 38 states. [2019-10-07 15:38:56,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:56,803 INFO L93 Difference]: Finished difference Result 130 states and 152 transitions. [2019-10-07 15:38:56,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-10-07 15:38:56,803 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 109 [2019-10-07 15:38:56,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:56,804 INFO L225 Difference]: With dead ends: 130 [2019-10-07 15:38:56,804 INFO L226 Difference]: Without dead ends: 95 [2019-10-07 15:38:56,806 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 373 GetRequests, 305 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1163 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1228, Invalid=3602, Unknown=0, NotChecked=0, Total=4830 [2019-10-07 15:38:56,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2019-10-07 15:38:56,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2019-10-07 15:38:56,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2019-10-07 15:38:56,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 99 transitions. [2019-10-07 15:38:56,823 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 99 transitions. Word has length 109 [2019-10-07 15:38:56,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:56,823 INFO L462 AbstractCegarLoop]: Abstraction has 95 states and 99 transitions. [2019-10-07 15:38:56,823 INFO L463 AbstractCegarLoop]: Interpolant automaton has 38 states. [2019-10-07 15:38:56,824 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 99 transitions. [2019-10-07 15:38:56,825 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2019-10-07 15:38:56,825 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:56,826 INFO L385 BasicCegarLoop]: trace histogram [72, 40, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:57,030 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:57,030 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:57,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:57,031 INFO L82 PathProgramCache]: Analyzing trace with hash 65831741, now seen corresponding path program 10 times [2019-10-07 15:38:57,031 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:57,031 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:57,031 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:57,032 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:57,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:57,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:57,715 INFO L134 CoverageAnalysis]: Checked inductivity of 3679 backedges. 1252 proven. 300 refuted. 0 times theorem prover too weak. 2127 trivial. 0 not checked. [2019-10-07 15:38:57,715 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:57,716 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:57,716 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:58,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:58,179 INFO L256 TraceCheckSpWp]: Trace formula consists of 765 conjuncts, 26 conjunts are in the unsatisfiable core [2019-10-07 15:38:58,182 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:58,232 INFO L134 CoverageAnalysis]: Checked inductivity of 3679 backedges. 1252 proven. 300 refuted. 0 times theorem prover too weak. 2127 trivial. 0 not checked. [2019-10-07 15:38:58,232 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:59,092 INFO L134 CoverageAnalysis]: Checked inductivity of 3679 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 2127 trivial. 0 not checked. [2019-10-07 15:38:59,092 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:59,094 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:59,094 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:59,094 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:59,094 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:59,095 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:59,111 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:39:00,435 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:39:00,505 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:39:00,508 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:39:00,508 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:39:00,508 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:39:00,508 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:39:00,508 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:39:00,508 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:39:00,508 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_sum_~ret~0_BEFORE_RETURN_239 Int) (v_prenex_1776 Int) (v_prenex_1775 Int) (v_sum_~ret~0_BEFORE_RETURN_240 Int)) (or (and (<= (mod v_prenex_1775 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1776 4294967296) 2147483647)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1776 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_239 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_240 4294967296) 2147483647) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_240 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_239 Int) (v_prenex_1776 Int) (v_prenex_1775 Int) (v_sum_~ret~0_BEFORE_RETURN_240 Int)) (or (and (<= (mod v_prenex_1775 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1776 4294967296) 2147483647)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1776 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_239 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_240 4294967296) 2147483647) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_240 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:39:00,509 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:00,509 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:00,509 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int)) (or (and (not (< main_~i~1 40)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_236 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_236 4294967296) (- 4294967296)))) (and (not (< main_~i~1 40)) (<= (mod v_prenex_1748 4294967296) 2147483647) (= (mod v_prenex_1748 4294967296) |main_#t~ret4|)))) (exists ((v_sum_~ret~0_BEFORE_RETURN_235 Int) (v_prenex_1747 Int)) (or (and (not (<= (mod v_prenex_1747 4294967296) 2147483647)) (not (< main_~i~1 40)) (= |main_#t~ret4| (+ (mod v_prenex_1747 4294967296) (- 4294967296)))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_235 4294967296) 2147483647) (not (< main_~i~1 40)) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_235 4294967296)))))) [2019-10-07 15:39:00,509 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:39:00,509 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:39:00,509 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:00,509 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:39:00,509 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:39:00,509 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:39:00,510 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:39:00,510 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:39:00,510 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_sum_~ret~0_BEFORE_RETURN_236 Int) (v_sum_~ret~0_BEFORE_RETURN_235 Int) (v_prenex_1748 Int) (v_prenex_1747 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_236 4294967296) (- 4294967296))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_236 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= (mod v_prenex_1748 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1748 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_1747 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_prenex_1747 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_235 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_235 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:39:00,510 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:39:00,510 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (<= 40 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 40))) [2019-10-07 15:39:01,054 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:39:01,054 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 11] total 53 [2019-10-07 15:39:01,056 INFO L442 AbstractCegarLoop]: Interpolant automaton has 54 states [2019-10-07 15:39:01,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2019-10-07 15:39:01,057 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=933, Invalid=1929, Unknown=0, NotChecked=0, Total=2862 [2019-10-07 15:39:01,057 INFO L87 Difference]: Start difference. First operand 95 states and 99 transitions. Second operand 54 states. [2019-10-07 15:39:04,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:39:04,555 INFO L93 Difference]: Finished difference Result 159 states and 184 transitions. [2019-10-07 15:39:04,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-10-07 15:39:04,555 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 148 [2019-10-07 15:39:04,556 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:39:04,558 INFO L225 Difference]: With dead ends: 159 [2019-10-07 15:39:04,558 INFO L226 Difference]: Without dead ends: 111 [2019-10-07 15:39:04,562 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 518 GetRequests, 408 SyntacticMatches, 10 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2343 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=2948, Invalid=7354, Unknown=0, NotChecked=0, Total=10302 [2019-10-07 15:39:04,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2019-10-07 15:39:04,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2019-10-07 15:39:04,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2019-10-07 15:39:04,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 115 transitions. [2019-10-07 15:39:04,575 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 115 transitions. Word has length 148 [2019-10-07 15:39:04,575 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:39:04,575 INFO L462 AbstractCegarLoop]: Abstraction has 111 states and 115 transitions. [2019-10-07 15:39:04,575 INFO L463 AbstractCegarLoop]: Interpolant automaton has 54 states. [2019-10-07 15:39:04,575 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 115 transitions. [2019-10-07 15:39:04,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 197 [2019-10-07 15:39:04,578 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:39:04,578 INFO L385 BasicCegarLoop]: trace histogram [120, 40, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:39:04,792 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:04,793 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:39:04,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:39:04,794 INFO L82 PathProgramCache]: Analyzing trace with hash -846986179, now seen corresponding path program 11 times [2019-10-07 15:39:04,794 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:39:04,794 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:04,794 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:04,795 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:04,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:39:04,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:39:05,156 INFO L134 CoverageAnalysis]: Checked inductivity of 8407 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:39:05,156 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:05,157 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:39:05,157 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:06,312 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2019-10-07 15:39:06,312 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:39:06,315 INFO L256 TraceCheckSpWp]: Trace formula consists of 353 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:39:06,317 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:39:06,365 INFO L134 CoverageAnalysis]: Checked inductivity of 8407 backedges. 3366 proven. 78 refuted. 0 times theorem prover too weak. 4963 trivial. 0 not checked. [2019-10-07 15:39:06,365 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:39:06,709 INFO L134 CoverageAnalysis]: Checked inductivity of 8407 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:39:06,709 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:39:06,710 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:39:06,710 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:39:06,711 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:39:06,711 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:39:06,711 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:39:06,728 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:39:07,981 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:39:08,004 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:39:08,006 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:39:08,006 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:39:08,006 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:39:08,006 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:39:08,006 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:39:08,007 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:39:08,007 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_1970 Int) (v_sum_~ret~0_BEFORE_RETURN_265 Int) (v_sum_~ret~0_BEFORE_RETURN_266 Int) (v_prenex_1969 Int)) (or (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_266 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_266 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1969 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_265 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_265 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1970 4294967296) 2147483647) (= (mod v_prenex_1970 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1970 Int) (v_sum_~ret~0_BEFORE_RETURN_265 Int) (v_sum_~ret~0_BEFORE_RETURN_266 Int) (v_prenex_1969 Int)) (or (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_266 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_266 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1969 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_265 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_265 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= (mod v_prenex_1970 4294967296) 2147483647) (= (mod v_prenex_1970 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))))) [2019-10-07 15:39:08,007 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:08,007 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:08,007 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1941 Int) (v_sum_~ret~0_BEFORE_RETURN_261 Int)) (or (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_261 4294967296)) (not (< main_~i~1 40))) (and (not (< main_~i~1 40)) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (= (+ (mod v_prenex_1941 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_prenex_1942 Int) (v_sum_~ret~0_BEFORE_RETURN_262 Int)) (or (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647)) (not (< main_~i~1 40)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_262 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 40)) (<= (mod v_prenex_1942 4294967296) 2147483647) (= |main_#t~ret4| (mod v_prenex_1942 4294967296)))))) [2019-10-07 15:39:08,008 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:39:08,008 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:08,008 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:39:08,008 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:39:08,008 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:39:08,009 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:39:08,009 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:39:08,009 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:39:08,010 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(or (exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_sum_~ret~0_BEFORE_RETURN_261 Int) (v_sum_~ret~0_BEFORE_RETURN_262 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_1942 4294967296) main_~ret~1) (<= (mod v_prenex_1942 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_261 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_262 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (+ (mod v_prenex_1941 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_sum_~ret~0_BEFORE_RETURN_261 Int) (v_sum_~ret~0_BEFORE_RETURN_262 Int)) (or (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_261 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= (mod v_prenex_1942 4294967296) main_~ret~1) (<= (mod v_prenex_1942 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_262 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (+ (mod v_prenex_1941 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:39:08,010 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:39:08,010 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (<= 40 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 40))) [2019-10-07 15:39:08,432 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:39:08,433 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-07 15:39:08,434 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-07 15:39:08,434 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-07 15:39:08,435 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:39:08,435 INFO L87 Difference]: Start difference. First operand 111 states and 115 transitions. Second operand 40 states. [2019-10-07 15:39:10,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:39:10,484 INFO L93 Difference]: Finished difference Result 173 states and 191 transitions. [2019-10-07 15:39:10,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-07 15:39:10,484 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 196 [2019-10-07 15:39:10,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:39:10,486 INFO L225 Difference]: With dead ends: 173 [2019-10-07 15:39:10,486 INFO L226 Difference]: Without dead ends: 125 [2019-10-07 15:39:10,488 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 637 GetRequests, 565 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1286 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1296, Invalid=4106, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:39:10,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2019-10-07 15:39:10,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 125. [2019-10-07 15:39:10,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2019-10-07 15:39:10,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 129 transitions. [2019-10-07 15:39:10,500 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 129 transitions. Word has length 196 [2019-10-07 15:39:10,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:39:10,501 INFO L462 AbstractCegarLoop]: Abstraction has 125 states and 129 transitions. [2019-10-07 15:39:10,501 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-07 15:39:10,501 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 129 transitions. [2019-10-07 15:39:10,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 211 [2019-10-07 15:39:10,503 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:39:10,503 INFO L385 BasicCegarLoop]: trace histogram [120, 40, 26, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:39:10,709 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:10,709 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:39:10,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:39:10,710 INFO L82 PathProgramCache]: Analyzing trace with hash -807854307, now seen corresponding path program 12 times [2019-10-07 15:39:10,710 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:39:10,711 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:10,711 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:10,711 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:10,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:39:10,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:39:11,486 INFO L134 CoverageAnalysis]: Checked inductivity of 8680 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:39:11,486 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:11,486 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:39:11,486 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:12,069 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:39:12,069 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:39:12,072 INFO L256 TraceCheckSpWp]: Trace formula consists of 1061 conjuncts, 28 conjunts are in the unsatisfiable core [2019-10-07 15:39:12,075 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:39:12,101 INFO L134 CoverageAnalysis]: Checked inductivity of 8680 backedges. 3366 proven. 351 refuted. 0 times theorem prover too weak. 4963 trivial. 0 not checked. [2019-10-07 15:39:12,101 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:39:12,955 INFO L134 CoverageAnalysis]: Checked inductivity of 8680 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 8329 trivial. 0 not checked. [2019-10-07 15:39:12,955 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:39:12,956 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:39:12,956 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:39:12,957 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:39:12,957 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:39:12,957 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:39:12,974 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:39:14,130 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:39:14,151 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:39:14,153 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:39:14,153 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:39:14,153 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:39:14,154 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:39:14,154 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:39:14,154 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (<= 39 main_~i~2) (not (< main_~i~2 39)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) [2019-10-07 15:39:14,154 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_292 Int) (v_sum_~ret~0_BEFORE_RETURN_291 Int) (v_prenex_2163 Int) (v_prenex_2164 Int)) (or (and (= (mod v_prenex_2164 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_2164 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_292 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_292 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_291 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_291 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_2163 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2163 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156))))))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_292 Int) (v_sum_~ret~0_BEFORE_RETURN_291 Int) (v_prenex_2163 Int) (v_prenex_2164 Int)) (or (and (= (mod v_prenex_2164 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_2164 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_292 4294967296) (- 4294967296))) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_292 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_291 4294967296)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_291 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))) (and (not (<= (mod v_prenex_2163 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (not (< main_~i~2 39)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2163 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 156)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:39:14,154 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:14,154 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:14,155 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_2135 Int) (v_sum_~ret~0_BEFORE_RETURN_287 Int)) (or (and (not (< main_~i~1 40)) (= (+ (mod v_prenex_2135 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod v_prenex_2135 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (= (mod v_sum_~ret~0_BEFORE_RETURN_287 4294967296) |main_#t~ret4|) (<= (mod v_sum_~ret~0_BEFORE_RETURN_287 4294967296) 2147483647)))) (exists ((v_prenex_2136 Int) (v_sum_~ret~0_BEFORE_RETURN_288 Int)) (or (and (not (< main_~i~1 40)) (= (+ (mod v_prenex_2136 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod v_prenex_2136 4294967296) 2147483647))) (and (not (< main_~i~1 40)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_288 4294967296) 2147483647) (= (mod v_sum_~ret~0_BEFORE_RETURN_288 4294967296) |main_#t~ret4|))))) [2019-10-07 15:39:14,155 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:39:14,155 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:14,155 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:39:14,155 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:39:14,155 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:39:14,156 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:39:14,156 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:39:14,156 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (not (< main_~i~1 40)) (<= 40 main_~i~1)) [2019-10-07 15:39:14,156 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_2135 Int) (v_prenex_2136 Int) (v_sum_~ret~0_BEFORE_RETURN_287 Int) (v_sum_~ret~0_BEFORE_RETURN_288 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (+ (mod v_prenex_2135 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2135 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_288 4294967296) 2147483647) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_288 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_287 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_287 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 40)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_2136 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_2136 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:39:14,156 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:39:14,156 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (<= 40 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 40))) [2019-10-07 15:39:14,690 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:39:14,691 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 11] total 52 [2019-10-07 15:39:14,692 INFO L442 AbstractCegarLoop]: Interpolant automaton has 53 states [2019-10-07 15:39:14,693 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2019-10-07 15:39:14,693 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=890, Invalid=1866, Unknown=0, NotChecked=0, Total=2756 [2019-10-07 15:39:14,693 INFO L87 Difference]: Start difference. First operand 125 states and 129 transitions. Second operand 53 states. [2019-10-07 15:39:19,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:39:19,608 INFO L93 Difference]: Finished difference Result 186 states and 203 transitions. [2019-10-07 15:39:19,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2019-10-07 15:39:19,608 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 210 [2019-10-07 15:39:19,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:39:19,610 INFO L225 Difference]: With dead ends: 186 [2019-10-07 15:39:19,610 INFO L226 Difference]: Without dead ends: 138 [2019-10-07 15:39:19,612 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 706 GetRequests, 593 SyntacticMatches, 15 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2285 ImplicationChecksByTransitivity, 6.3s TimeCoverageRelationStatistics Valid=2661, Invalid=7238, Unknown=1, NotChecked=0, Total=9900 [2019-10-07 15:39:19,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2019-10-07 15:39:19,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2019-10-07 15:39:19,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2019-10-07 15:39:19,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 142 transitions. [2019-10-07 15:39:19,625 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 142 transitions. Word has length 210 [2019-10-07 15:39:19,625 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:39:19,625 INFO L462 AbstractCegarLoop]: Abstraction has 138 states and 142 transitions. [2019-10-07 15:39:19,625 INFO L463 AbstractCegarLoop]: Interpolant automaton has 53 states. [2019-10-07 15:39:19,626 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 142 transitions. [2019-10-07 15:39:19,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 224 [2019-10-07 15:39:19,628 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:39:19,628 INFO L385 BasicCegarLoop]: trace histogram [120, 40, 39, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:39:19,834 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:19,834 INFO L410 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:39:19,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:39:19,835 INFO L82 PathProgramCache]: Analyzing trace with hash 476268046, now seen corresponding path program 13 times [2019-10-07 15:39:19,835 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:39:19,835 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:19,835 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:19,836 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:19,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:39:49,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat