java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/reducercommutativity/sum60-2.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-07 15:38:15,569 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-07 15:38:15,571 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-07 15:38:15,586 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-07 15:38:15,586 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-07 15:38:15,589 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-07 15:38:15,590 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-07 15:38:15,600 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-07 15:38:15,605 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-07 15:38:15,608 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-07 15:38:15,609 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-07 15:38:15,610 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-07 15:38:15,611 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-07 15:38:15,612 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-07 15:38:15,615 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-07 15:38:15,616 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-07 15:38:15,618 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-07 15:38:15,619 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-07 15:38:15,620 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-07 15:38:15,625 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-07 15:38:15,629 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-07 15:38:15,631 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-07 15:38:15,634 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-07 15:38:15,635 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-07 15:38:15,637 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-07 15:38:15,646 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-07 15:38:15,647 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-07 15:38:15,648 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-07 15:38:15,649 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-07 15:38:15,674 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-07 15:38:15,675 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-07 15:38:15,676 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-07 15:38:15,676 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-07 15:38:15,676 INFO L138 SettingsManager]: * Use SBE=true [2019-10-07 15:38:15,676 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-07 15:38:15,677 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-07 15:38:15,677 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-07 15:38:15,677 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-07 15:38:15,677 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-07 15:38:15,677 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-07 15:38:15,677 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-07 15:38:15,678 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-07 15:38:15,678 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-07 15:38:15,678 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-07 15:38:15,678 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-07 15:38:15,678 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-07 15:38:15,679 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-07 15:38:15,679 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-07 15:38:15,679 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-07 15:38:15,679 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-07 15:38:15,679 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:38:15,680 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-07 15:38:15,680 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-07 15:38:15,680 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-07 15:38:15,680 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-07 15:38:15,680 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-07 15:38:15,681 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-07 15:38:15,681 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-07 15:38:15,946 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-07 15:38:15,958 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-07 15:38:15,962 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-07 15:38:15,963 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-07 15:38:15,963 INFO L275 PluginConnector]: CDTParser initialized [2019-10-07 15:38:15,964 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/sum60-2.i [2019-10-07 15:38:16,045 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7aedf9661/884d27e4c8ad4f51903b85663543370f/FLAG24dd2859b [2019-10-07 15:38:16,524 INFO L306 CDTParser]: Found 1 translation units. [2019-10-07 15:38:16,524 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/reducercommutativity/sum60-2.i [2019-10-07 15:38:16,529 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7aedf9661/884d27e4c8ad4f51903b85663543370f/FLAG24dd2859b [2019-10-07 15:38:16,896 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7aedf9661/884d27e4c8ad4f51903b85663543370f [2019-10-07 15:38:16,908 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-07 15:38:16,910 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-07 15:38:16,913 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-07 15:38:16,914 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-07 15:38:16,917 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-07 15:38:16,918 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:38:16" (1/1) ... [2019-10-07 15:38:16,921 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@c329988 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:16, skipping insertion in model container [2019-10-07 15:38:16,921 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.10 03:38:16" (1/1) ... [2019-10-07 15:38:16,931 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-07 15:38:16,951 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-07 15:38:17,175 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:38:17,185 INFO L188 MainTranslator]: Completed pre-run [2019-10-07 15:38:17,207 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-07 15:38:17,221 INFO L192 MainTranslator]: Completed translation [2019-10-07 15:38:17,221 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:17 WrapperNode [2019-10-07 15:38:17,222 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-07 15:38:17,222 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-07 15:38:17,222 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-07 15:38:17,223 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-07 15:38:17,318 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:17" (1/1) ... [2019-10-07 15:38:17,318 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:17" (1/1) ... [2019-10-07 15:38:17,327 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:17" (1/1) ... [2019-10-07 15:38:17,328 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:17" (1/1) ... [2019-10-07 15:38:17,339 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:17" (1/1) ... [2019-10-07 15:38:17,343 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:17" (1/1) ... [2019-10-07 15:38:17,345 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:17" (1/1) ... [2019-10-07 15:38:17,347 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-07 15:38:17,347 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-07 15:38:17,348 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-07 15:38:17,348 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-07 15:38:17,349 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:17" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-07 15:38:17,410 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-07 15:38:17,410 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-07 15:38:17,410 INFO L138 BoogieDeclarations]: Found implementation of procedure sum [2019-10-07 15:38:17,410 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-07 15:38:17,411 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-07 15:38:17,411 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-07 15:38:17,411 INFO L130 BoogieDeclarations]: Found specification of procedure sum [2019-10-07 15:38:17,411 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-07 15:38:17,411 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-07 15:38:17,411 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-07 15:38:17,412 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-07 15:38:17,412 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-07 15:38:17,412 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-07 15:38:17,412 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-07 15:38:17,767 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-07 15:38:17,768 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-07 15:38:17,769 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:38:17 BoogieIcfgContainer [2019-10-07 15:38:17,769 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-07 15:38:17,770 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-07 15:38:17,771 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-07 15:38:17,774 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-07 15:38:17,774 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.10 03:38:16" (1/3) ... [2019-10-07 15:38:17,775 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@42228308 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:38:17, skipping insertion in model container [2019-10-07 15:38:17,775 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.10 03:38:17" (2/3) ... [2019-10-07 15:38:17,776 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@42228308 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.10 03:38:17, skipping insertion in model container [2019-10-07 15:38:17,776 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.10 03:38:17" (3/3) ... [2019-10-07 15:38:17,778 INFO L109 eAbstractionObserver]: Analyzing ICFG sum60-2.i [2019-10-07 15:38:17,789 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-07 15:38:17,805 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-07 15:38:17,822 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-07 15:38:17,854 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-07 15:38:17,854 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-07 15:38:17,855 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-07 15:38:17,855 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-07 15:38:17,855 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-07 15:38:17,855 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-07 15:38:17,855 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-07 15:38:17,855 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-07 15:38:17,873 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-07 15:38:17,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-07 15:38:17,879 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:17,880 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:17,882 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:17,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:17,886 INFO L82 PathProgramCache]: Analyzing trace with hash -1818423299, now seen corresponding path program 1 times [2019-10-07 15:38:17,893 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:17,893 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:17,894 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:17,894 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:17,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:17,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:18,073 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-07 15:38:18,074 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:18,075 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:38:18,075 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:38:18,079 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:38:18,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:38:18,092 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:38:18,094 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-07 15:38:18,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:18,129 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-07 15:38:18,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:38:18,132 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-07 15:38:18,132 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:18,142 INFO L225 Difference]: With dead ends: 41 [2019-10-07 15:38:18,142 INFO L226 Difference]: Without dead ends: 20 [2019-10-07 15:38:18,146 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:38:18,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-07 15:38:18,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-07 15:38:18,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-07 15:38:18,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-07 15:38:18,210 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-07 15:38:18,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:18,211 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-07 15:38:18,212 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:38:18,213 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-07 15:38:18,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-07 15:38:18,218 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:18,219 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:18,219 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:18,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:18,222 INFO L82 PathProgramCache]: Analyzing trace with hash -2093950433, now seen corresponding path program 1 times [2019-10-07 15:38:18,222 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:18,223 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:18,223 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:18,223 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:18,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:18,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:18,376 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:38:18,376 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:18,377 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:18,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:18,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:18,478 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-07 15:38:18,488 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:18,523 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:38:18,524 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:18,566 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-07 15:38:18,566 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-07 15:38:18,567 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-07 15:38:18,569 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:38:18,570 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:38:18,570 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:38:18,570 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-07 15:38:18,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:18,585 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-07 15:38:18,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:38:18,586 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-07 15:38:18,587 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:18,587 INFO L225 Difference]: With dead ends: 33 [2019-10-07 15:38:18,588 INFO L226 Difference]: Without dead ends: 21 [2019-10-07 15:38:18,589 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-07 15:38:18,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-07 15:38:18,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-07 15:38:18,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-07 15:38:18,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-07 15:38:18,595 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-07 15:38:18,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:18,595 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-07 15:38:18,596 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:38:18,596 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-07 15:38:18,597 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-07 15:38:18,597 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:18,597 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:18,802 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:18,803 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:18,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:18,804 INFO L82 PathProgramCache]: Analyzing trace with hash 903502258, now seen corresponding path program 1 times [2019-10-07 15:38:18,804 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:18,805 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:18,805 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:18,805 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:18,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:18,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:18,907 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:18,908 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:18,909 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-07 15:38:18,909 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-07 15:38:18,909 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-07 15:38:18,910 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-07 15:38:18,910 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:38:18,910 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-07 15:38:18,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:18,930 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-07 15:38:18,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-07 15:38:18,932 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-07 15:38:18,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:18,933 INFO L225 Difference]: With dead ends: 31 [2019-10-07 15:38:18,934 INFO L226 Difference]: Without dead ends: 22 [2019-10-07 15:38:18,934 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-07 15:38:18,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-07 15:38:18,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-07 15:38:18,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-07 15:38:18,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-07 15:38:18,947 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-07 15:38:18,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:18,949 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-07 15:38:18,950 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-07 15:38:18,950 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-07 15:38:18,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-07 15:38:18,951 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:18,952 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:18,952 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:18,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:18,952 INFO L82 PathProgramCache]: Analyzing trace with hash 2130547361, now seen corresponding path program 1 times [2019-10-07 15:38:18,953 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:18,953 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:18,953 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:18,953 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:18,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:18,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:19,048 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:19,049 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:19,049 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:19,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:19,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:19,140 INFO L256 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:38:19,143 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:19,171 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:19,172 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:19,226 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:19,226 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:19,267 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:19,267 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:19,276 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:19,287 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:19,288 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:19,471 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:21,545 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:21,612 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:21,619 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:21,619 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:21,619 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:21,619 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:21,620 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:21,620 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:21,621 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_sum_~ret~0_BEFORE_RETURN_5 Int) (v_sum_~ret~0_BEFORE_RETURN_6 Int) (v_prenex_30 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_30 4294967296)) (<= (mod v_prenex_30 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_6 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_29 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_29 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_prenex_29 Int) (v_sum_~ret~0_BEFORE_RETURN_5 Int) (v_sum_~ret~0_BEFORE_RETURN_6 Int) (v_prenex_30 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_30 4294967296)) (<= (mod v_prenex_30 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_6 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_6 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_5 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_29 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_29 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:21,621 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:21,622 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:21,622 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1 Int) (v_sum_~ret~0_BEFORE_RETURN_1 Int)) (or (and (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod v_prenex_1 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_sum_~ret~0_BEFORE_RETURN_1 4294967296) |main_#t~ret4|)))) (exists ((v_prenex_2 Int) (v_sum_~ret~0_BEFORE_RETURN_2 Int)) (or (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60))) (and (not (< main_~i~1 60)) (= (mod v_sum_~ret~0_BEFORE_RETURN_2 4294967296) |main_#t~ret4|) (<= (mod v_sum_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647))))) [2019-10-07 15:38:21,622 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:21,622 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:21,622 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:21,623 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:21,623 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:21,623 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:21,623 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:21,623 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:21,625 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_2 Int) (v_prenex_1 Int) (v_sum_~ret~0_BEFORE_RETURN_1 Int) (v_sum_~ret~0_BEFORE_RETURN_2 Int)) (or (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_1 4294967296) 2147483647) (<= main_~ret~1 2147483647) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_1 4294967296)) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (mod v_sum_~ret~0_BEFORE_RETURN_2 4294967296) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_2 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:21,625 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:21,626 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:38:21,991 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:21,991 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-07 15:38:21,993 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-07 15:38:21,993 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-07 15:38:21,996 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-07 15:38:21,996 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-07 15:38:22,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:22,610 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-07 15:38:22,610 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-07 15:38:22,611 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-07 15:38:22,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:22,612 INFO L225 Difference]: With dead ends: 40 [2019-10-07 15:38:22,612 INFO L226 Difference]: Without dead ends: 25 [2019-10-07 15:38:22,616 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=133, Invalid=737, Unknown=0, NotChecked=0, Total=870 [2019-10-07 15:38:22,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-07 15:38:22,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-07 15:38:22,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-07 15:38:22,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-07 15:38:22,627 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-07 15:38:22,627 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:22,627 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-07 15:38:22,628 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-07 15:38:22,628 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-07 15:38:22,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-07 15:38:22,629 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:22,629 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:22,847 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:22,847 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:22,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:22,848 INFO L82 PathProgramCache]: Analyzing trace with hash 356639231, now seen corresponding path program 2 times [2019-10-07 15:38:22,848 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:22,848 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:22,849 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:22,849 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:22,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:22,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:22,981 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-07 15:38:22,982 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:22,982 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:22,982 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:23,060 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-07 15:38:23,061 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:23,068 INFO L256 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:38:23,072 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:23,097 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:38:23,097 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:23,134 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-07 15:38:23,134 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:23,138 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:23,138 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:23,139 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:23,139 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:23,139 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:23,174 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:24,686 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:24,714 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:24,717 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:24,718 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:24,718 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:24,718 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:24,718 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:24,719 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:24,719 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_sum_~ret~0_BEFORE_RETURN_32 Int) (v_prenex_224 Int) (v_sum_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_32 Int) (v_prenex_224 Int) (v_sum_~ret~0_BEFORE_RETURN_31 Int) (v_prenex_223 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_31 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:38:24,719 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:24,719 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:24,720 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (not (< main_~i~1 60)) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_27 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647)) (and (not (<= (mod v_prenex_195 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_prenex_195 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_prenex_196 Int) (v_sum_~ret~0_BEFORE_RETURN_28 Int)) (or (and (<= (mod v_prenex_196 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_prenex_196 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_28 4294967296) (- 4294967296))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647)))))) [2019-10-07 15:38:24,720 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:24,720 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:24,720 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:24,720 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:24,721 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:24,721 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:24,721 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:24,721 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:24,721 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_sum_~ret~0_BEFORE_RETURN_27 Int) (v_prenex_196 Int) (v_sum_~ret~0_BEFORE_RETURN_28 Int) (v_prenex_195 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_28 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_28 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (<= (mod v_prenex_195 4294967296) 2147483647)) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_prenex_195 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_27 4294967296)) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_27 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (<= (mod v_prenex_196 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_196 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:24,722 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:24,722 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:38:25,109 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:25,109 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-07 15:38:25,110 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-07 15:38:25,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-07 15:38:25,111 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-07 15:38:25,111 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-07 15:38:25,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:25,992 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-07 15:38:25,993 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-07 15:38:25,994 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-07 15:38:25,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:25,995 INFO L225 Difference]: With dead ends: 44 [2019-10-07 15:38:25,995 INFO L226 Difference]: Without dead ends: 29 [2019-10-07 15:38:25,997 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-07 15:38:25,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-07 15:38:26,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-07 15:38:26,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-07 15:38:26,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-07 15:38:26,013 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-07 15:38:26,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:26,014 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-07 15:38:26,014 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-07 15:38:26,014 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-07 15:38:26,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-07 15:38:26,016 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:26,016 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:26,223 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:26,224 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:26,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:26,224 INFO L82 PathProgramCache]: Analyzing trace with hash 906031436, now seen corresponding path program 3 times [2019-10-07 15:38:26,225 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:26,225 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:26,225 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:26,225 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:26,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:26,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:26,311 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:26,311 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:26,311 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:26,311 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:26,422 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:38:26,423 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:26,424 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:38:26,435 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:26,446 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:26,447 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:26,539 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:26,539 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:26,541 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:26,541 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:26,542 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:26,542 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:26,542 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:26,562 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:27,966 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:28,002 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:28,005 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:28,006 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:28,006 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:28,006 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:28,007 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:28,007 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:28,007 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_58 Int) (v_sum_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int)) (or (and (not (< main_~i~2 59)) (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_sum_~ret~0_BEFORE_RETURN_58 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_sum_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_58 Int) (v_sum_~ret~0_BEFORE_RETURN_57 Int) (v_prenex_417 Int) (v_prenex_418 Int)) (or (and (not (< main_~i~2 59)) (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_57 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_sum_~ret~0_BEFORE_RETURN_58 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_sum_~ret~0_BEFORE_RETURN_58 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:28,007 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:28,009 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:28,009 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (= (mod v_sum_~ret~0_BEFORE_RETURN_54 4294967296) |main_#t~ret4|) (<= (mod v_sum_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (not (< main_~i~1 60))) (and (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod v_prenex_390 4294967296) 2147483647))))) (exists ((v_prenex_389 Int) (v_sum_~ret~0_BEFORE_RETURN_53 Int)) (or (and (= (mod v_sum_~ret~0_BEFORE_RETURN_53 4294967296) |main_#t~ret4|) (<= (mod v_sum_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647) (not (< main_~i~1 60))) (and (not (<= (mod v_prenex_389 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_prenex_389 4294967296) (- 4294967296)) |main_#t~ret4|))))) [2019-10-07 15:38:28,009 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:28,009 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:28,010 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:28,010 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:28,010 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:28,010 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:28,010 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:28,011 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:28,011 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_sum_~ret~0_BEFORE_RETURN_54 Int) (v_prenex_389 Int) (v_sum_~ret~0_BEFORE_RETURN_53 Int) (v_prenex_390 Int)) (or (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_54 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sum_~ret~0_BEFORE_RETURN_54 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= (mod v_sum_~ret~0_BEFORE_RETURN_53 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (<= (mod v_sum_~ret~0_BEFORE_RETURN_53 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (+ (mod v_prenex_389 4294967296) (- 4294967296))) (not (<= (mod v_prenex_389 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:28,011 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:28,011 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:38:28,514 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:28,515 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-07 15:38:28,516 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-07 15:38:28,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-07 15:38:28,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-07 15:38:28,521 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-07 15:38:29,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:29,522 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-07 15:38:29,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-07 15:38:29,522 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-07 15:38:29,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:29,523 INFO L225 Difference]: With dead ends: 54 [2019-10-07 15:38:29,523 INFO L226 Difference]: Without dead ends: 36 [2019-10-07 15:38:29,525 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-07 15:38:29,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-07 15:38:29,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-07 15:38:29,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-07 15:38:29,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-07 15:38:29,534 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-07 15:38:29,535 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:29,535 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-07 15:38:29,535 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-07 15:38:29,535 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-07 15:38:29,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-07 15:38:29,536 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:29,537 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:29,744 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:29,745 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:29,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:29,745 INFO L82 PathProgramCache]: Analyzing trace with hash -1194663378, now seen corresponding path program 4 times [2019-10-07 15:38:29,745 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:29,746 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:29,746 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:29,746 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:29,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:29,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:29,918 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:29,918 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:29,918 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:29,918 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:30,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:30,052 INFO L256 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:38:30,054 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:30,070 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:30,070 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:30,318 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:30,319 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:30,320 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:30,320 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:30,321 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:30,321 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:30,321 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:30,337 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:31,758 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:31,795 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:31,800 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:31,800 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:31,800 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:31,801 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:31,801 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:31,801 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:31,802 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_sum_~ret~0_BEFORE_RETURN_84 Int) (v_prenex_612 Int) (v_sum_~ret~0_BEFORE_RETURN_83 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_611 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_611 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_84 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_612 4294967296) 2147483647) (= (mod v_prenex_612 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_83 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_prenex_611 Int) (v_sum_~ret~0_BEFORE_RETURN_84 Int) (v_prenex_612 Int) (v_sum_~ret~0_BEFORE_RETURN_83 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_611 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_611 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_84 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_84 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_612 4294967296) 2147483647) (= (mod v_prenex_612 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_83 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_83 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:31,802 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:31,802 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:31,803 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_583 Int) (v_sum_~ret~0_BEFORE_RETURN_79 Int)) (or (and (= (mod v_prenex_583 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (<= (mod v_prenex_583 4294967296) 2147483647)) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_79 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_prenex_584 Int) (v_sum_~ret~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod v_prenex_584 4294967296) (- 4294967296))) (not (<= (mod v_prenex_584 4294967296) 2147483647))) (and (not (< main_~i~1 60)) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_80 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647))))) [2019-10-07 15:38:31,803 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:31,803 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:31,804 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:31,804 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:31,804 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:31,805 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:31,805 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:31,805 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:31,805 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_583 Int) (v_sum_~ret~0_BEFORE_RETURN_79 Int) (v_prenex_584 Int) (v_sum_~ret~0_BEFORE_RETURN_80 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (<= (mod v_prenex_583 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_583 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_80 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_80 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_79 4294967296) 2147483647)) (not (< main_~i~1 60)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_584 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_prenex_584 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:31,806 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:31,806 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:38:32,355 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:32,355 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-07 15:38:32,356 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-07 15:38:32,357 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-07 15:38:32,357 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:38:32,358 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 40 states. [2019-10-07 15:38:35,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:35,853 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-07 15:38:35,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-07 15:38:35,854 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 49 [2019-10-07 15:38:35,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:35,855 INFO L225 Difference]: With dead ends: 68 [2019-10-07 15:38:35,855 INFO L226 Difference]: Without dead ends: 50 [2019-10-07 15:38:35,857 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:38:35,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-07 15:38:35,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-07 15:38:35,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-07 15:38:35,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-07 15:38:35,866 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-07 15:38:35,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:35,866 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-07 15:38:35,866 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-07 15:38:35,867 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-07 15:38:35,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-07 15:38:35,868 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:35,869 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:36,076 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:36,077 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:36,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:36,078 INFO L82 PathProgramCache]: Analyzing trace with hash 1997950062, now seen corresponding path program 5 times [2019-10-07 15:38:36,078 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:36,078 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:36,078 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:36,079 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:36,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:36,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:36,502 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-07 15:38:36,503 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:36,503 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:36,503 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:36,668 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:38:36,669 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:36,670 INFO L256 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-07 15:38:36,673 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:36,718 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-07 15:38:36,718 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:36,766 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-07 15:38:36,767 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:36,768 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:36,768 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:36,769 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:36,769 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:36,769 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:36,785 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:37,979 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:38,003 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:38,005 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:38,005 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:38,006 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:38,006 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:38,006 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:38,006 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:38,007 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_sum_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_109 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_sum_~ret~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_109 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_109 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_prenex_805 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_805 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:38,007 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:38,007 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:38:38,007 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 60)) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_106 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647)))) (exists ((v_prenex_777 Int) (v_sum_~ret~0_BEFORE_RETURN_105 Int)) (or (and (<= (mod v_prenex_777 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_prenex_777 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 60)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_105 4294967296) (- 4294967296))))))) [2019-10-07 15:38:38,007 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:38,007 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:38,008 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:38,008 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:38,008 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:38,008 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:38,008 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:38,008 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:38,009 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_777 Int) (v_sum_~ret~0_BEFORE_RETURN_106 Int) (v_sum_~ret~0_BEFORE_RETURN_105 Int) (v_prenex_778 Int)) (or (and (<= (mod v_prenex_777 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_777 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_105 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_105 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_106 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_106 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:38,009 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:38,009 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:38:38,526 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:38,527 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-07 15:38:38,528 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-07 15:38:38,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-07 15:38:38,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-07 15:38:38,529 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 44 states. [2019-10-07 15:38:40,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:40,458 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-07 15:38:40,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-07 15:38:40,459 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 63 [2019-10-07 15:38:40,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:40,460 INFO L225 Difference]: With dead ends: 72 [2019-10-07 15:38:40,460 INFO L226 Difference]: Without dead ends: 54 [2019-10-07 15:38:40,462 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1350 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1349, Invalid=5457, Unknown=0, NotChecked=0, Total=6806 [2019-10-07 15:38:40,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-07 15:38:40,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-07 15:38:40,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-07 15:38:40,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-07 15:38:40,470 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-07 15:38:40,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:40,471 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-07 15:38:40,471 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-07 15:38:40,471 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-07 15:38:40,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-07 15:38:40,472 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:40,473 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:40,676 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:40,677 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:40,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:40,678 INFO L82 PathProgramCache]: Analyzing trace with hash 1475332959, now seen corresponding path program 6 times [2019-10-07 15:38:40,678 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:40,678 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:40,678 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:40,679 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:40,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:40,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:41,228 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:38:41,228 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:41,228 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:41,228 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:41,426 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:38:41,427 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:38:41,428 INFO L256 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-07 15:38:41,431 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:41,446 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:38:41,447 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:42,822 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:38:42,823 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:42,828 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:42,828 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:42,828 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:42,829 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:42,829 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:42,847 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:44,116 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:44,140 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:44,142 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:44,143 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:44,143 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:44,143 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:44,143 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:44,144 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:44,144 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_sum_~ret~0_BEFORE_RETURN_135 Int) (v_prenex_999 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_136 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1000 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_sum_~ret~0_BEFORE_RETURN_135 Int) (v_prenex_999 Int)) (or (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_136 4294967296)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_136 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_135 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_135 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_prenex_1000 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1000 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:38:44,144 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:44,144 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:44,145 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_971 Int) (v_sum_~ret~0_BEFORE_RETURN_131 Int)) (or (and (= |main_#t~ret4| (+ (mod v_prenex_971 4294967296) (- 4294967296))) (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 60))) (and (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_131 4294967296)) (not (< main_~i~1 60)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647)))) (exists ((v_prenex_972 Int) (v_sum_~ret~0_BEFORE_RETURN_132 Int)) (or (and (not (<= (mod v_prenex_972 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_prenex_972 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (= (mod v_sum_~ret~0_BEFORE_RETURN_132 4294967296) |main_#t~ret4|) (<= (mod v_sum_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647) (not (< main_~i~1 60)))))) [2019-10-07 15:38:44,145 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:44,145 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:44,145 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:44,145 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:44,146 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:44,146 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:44,146 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:44,146 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:44,146 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_sum_~ret~0_BEFORE_RETURN_132 Int) (v_sum_~ret~0_BEFORE_RETURN_131 Int)) (or (and (<= main_~ret~1 2147483647) (<= (mod v_sum_~ret~0_BEFORE_RETURN_132 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_132 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~ret~1 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~ret~1 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_131 4294967296) 2147483647) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_131 4294967296)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:38:44,147 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:44,147 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:38:44,712 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:44,713 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-07 15:38:44,714 INFO L442 AbstractCegarLoop]: Interpolant automaton has 70 states [2019-10-07 15:38:44,715 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2019-10-07 15:38:44,717 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1740, Invalid=3090, Unknown=0, NotChecked=0, Total=4830 [2019-10-07 15:38:44,717 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 70 states. [2019-10-07 15:38:48,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:48,175 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-07 15:38:48,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2019-10-07 15:38:48,176 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 67 [2019-10-07 15:38:48,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:48,177 INFO L225 Difference]: With dead ends: 104 [2019-10-07 15:38:48,177 INFO L226 Difference]: Without dead ends: 83 [2019-10-07 15:38:48,182 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3929 ImplicationChecksByTransitivity, 5.3s TimeCoverageRelationStatistics Valid=5099, Invalid=12723, Unknown=0, NotChecked=0, Total=17822 [2019-10-07 15:38:48,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-07 15:38:48,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-07 15:38:48,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-07 15:38:48,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-07 15:38:48,192 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-07 15:38:48,192 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:48,192 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-07 15:38:48,193 INFO L463 AbstractCegarLoop]: Interpolant automaton has 70 states. [2019-10-07 15:38:48,193 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-07 15:38:48,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-07 15:38:48,194 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:48,195 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:48,397 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:48,397 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:48,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:48,398 INFO L82 PathProgramCache]: Analyzing trace with hash 441486205, now seen corresponding path program 7 times [2019-10-07 15:38:48,398 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:48,398 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:48,399 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:48,399 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:48,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:48,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:49,738 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:38:49,738 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:49,738 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:38:49,739 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:50,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:38:50,010 INFO L256 TraceCheckSpWp]: Trace formula consists of 529 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-07 15:38:50,013 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:38:50,038 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:38:50,039 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:38:51,437 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-07 15:38:51,438 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:38:51,439 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:38:51,439 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:38:51,440 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:38:51,440 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:38:51,440 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:38:51,467 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:38:52,775 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:38:52,797 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:38:52,799 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:38:52,799 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:38:52,800 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:38:52,800 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:38:52,800 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:38:52,800 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:38:52,800 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_1194 Int) (v_sum_~ret~0_BEFORE_RETURN_162 Int) (v_sum_~ret~0_BEFORE_RETURN_161 Int) (v_prenex_1193 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_1193 4294967296) 2147483647) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1194 Int) (v_sum_~ret~0_BEFORE_RETURN_162 Int) (v_sum_~ret~0_BEFORE_RETURN_161 Int) (v_prenex_1193 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_161 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_162 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_1193 4294967296) 2147483647) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:38:52,801 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:52,801 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:52,801 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1165 Int) (v_sum_~ret~0_BEFORE_RETURN_157 Int)) (or (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296)))) (and (<= (mod v_prenex_1165 4294967296) 2147483647) (= (mod v_prenex_1165 4294967296) |main_#t~ret4|) (not (< main_~i~1 60))))) (exists ((v_sum_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int)) (or (and (<= (mod v_prenex_1166 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret4| (mod v_prenex_1166 4294967296))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (not (< main_~i~1 60)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) |main_#t~ret4|))))) [2019-10-07 15:38:52,801 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:38:52,801 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:38:52,801 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:38:52,802 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:38:52,802 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:38:52,802 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:38:52,802 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:38:52,802 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:38:52,803 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int) (v_prenex_1165 Int) (v_sum_~ret~0_BEFORE_RETURN_157 Int)) (or (and (<= (mod v_prenex_1165 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_1165 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1166 4294967296)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_sum_~ret~0_BEFORE_RETURN_158 Int) (v_prenex_1166 Int) (v_prenex_1165 Int) (v_sum_~ret~0_BEFORE_RETURN_157 Int)) (or (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_158 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_157 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1165 4294967296)) (<= (mod v_prenex_1165 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1166 4294967296)) (<= (mod v_prenex_1166 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:38:52,803 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:38:52,803 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:38:53,585 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:38:53,586 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 73 [2019-10-07 15:38:53,587 INFO L442 AbstractCegarLoop]: Interpolant automaton has 74 states [2019-10-07 15:38:53,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2019-10-07 15:38:53,590 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1982, Invalid=3420, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:38:53,590 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 74 states. [2019-10-07 15:38:59,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:38:59,682 INFO L93 Difference]: Finished difference Result 108 states and 119 transitions. [2019-10-07 15:38:59,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2019-10-07 15:38:59,682 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 96 [2019-10-07 15:38:59,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:38:59,683 INFO L225 Difference]: With dead ends: 108 [2019-10-07 15:38:59,684 INFO L226 Difference]: Without dead ends: 87 [2019-10-07 15:38:59,688 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 417 GetRequests, 223 SyntacticMatches, 54 SemanticMatches, 140 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5139 ImplicationChecksByTransitivity, 7.0s TimeCoverageRelationStatistics Valid=5817, Invalid=14205, Unknown=0, NotChecked=0, Total=20022 [2019-10-07 15:38:59,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2019-10-07 15:38:59,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2019-10-07 15:38:59,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2019-10-07 15:38:59,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 91 transitions. [2019-10-07 15:38:59,706 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 91 transitions. Word has length 96 [2019-10-07 15:38:59,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:38:59,707 INFO L462 AbstractCegarLoop]: Abstraction has 87 states and 91 transitions. [2019-10-07 15:38:59,707 INFO L463 AbstractCegarLoop]: Interpolant automaton has 74 states. [2019-10-07 15:38:59,707 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 91 transitions. [2019-10-07 15:38:59,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2019-10-07 15:38:59,709 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:38:59,709 INFO L385 BasicCegarLoop]: trace histogram [60, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:38:59,913 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:38:59,914 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:38:59,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:38:59,915 INFO L82 PathProgramCache]: Analyzing trace with hash -29457411, now seen corresponding path program 8 times [2019-10-07 15:38:59,915 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:38:59,915 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:38:59,915 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:59,916 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:38:59,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:38:59,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:39:00,047 INFO L134 CoverageAnalysis]: Checked inductivity of 1951 backedges. 0 proven. 62 refuted. 0 times theorem prover too weak. 1889 trivial. 0 not checked. [2019-10-07 15:39:00,048 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:00,048 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:39:00,048 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:00,290 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-07 15:39:00,290 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:39:00,292 INFO L256 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-07 15:39:00,297 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:39:00,314 INFO L134 CoverageAnalysis]: Checked inductivity of 1951 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 1889 trivial. 0 not checked. [2019-10-07 15:39:00,314 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:39:00,381 INFO L134 CoverageAnalysis]: Checked inductivity of 1951 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 1889 trivial. 0 not checked. [2019-10-07 15:39:00,381 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:39:00,384 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:39:00,384 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:39:00,385 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:39:00,385 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:39:00,385 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:39:00,398 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:39:01,580 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:39:01,610 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:39:01,613 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:39:01,613 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:39:01,613 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:39:01,613 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:39:01,613 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:39:01,614 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:39:01,614 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_sum_~ret~0_BEFORE_RETURN_188 Int) (v_sum_~ret~0_BEFORE_RETURN_187 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_prenex_1387 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_sum_~ret~0_BEFORE_RETURN_188 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_sum_~ret~0_BEFORE_RETURN_188 Int) (v_sum_~ret~0_BEFORE_RETURN_187 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_1388 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1388 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_187 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_prenex_1387 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_sum_~ret~0_BEFORE_RETURN_188 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_188 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret2~0)))) [2019-10-07 15:39:01,614 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:01,614 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:01,614 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1359 Int) (v_sum_~ret~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 60)) (= (mod v_prenex_1359 4294967296) |main_#t~ret4|) (<= (mod v_prenex_1359 4294967296) 2147483647)) (and (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_183 4294967296) (- 4294967296))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647)) (not (< main_~i~1 60))))) (exists ((v_prenex_1360 Int) (v_sum_~ret~0_BEFORE_RETURN_184 Int)) (or (and (= (mod v_sum_~ret~0_BEFORE_RETURN_184 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647)) (and (not (< main_~i~1 60)) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod v_prenex_1360 4294967296) 2147483647)))))) [2019-10-07 15:39:01,615 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:39:01,615 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:39:01,615 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:01,615 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:39:01,615 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:39:01,615 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:39:01,615 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:39:01,616 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:39:01,616 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_1359 Int) (v_prenex_1360 Int) (v_sum_~ret~0_BEFORE_RETURN_184 Int) (v_sum_~ret~0_BEFORE_RETURN_183 Int)) (or (and (<= main_~ret~1 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_183 4294967296) 2147483647)) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_183 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sum_~ret~0_BEFORE_RETURN_184 4294967296) main_~ret~1) (<= (mod v_sum_~ret~0_BEFORE_RETURN_184 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_1360 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_1360 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1359 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1359 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:39:01,616 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:39:01,616 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:39:01,923 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:39:01,923 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 23 [2019-10-07 15:39:01,924 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-10-07 15:39:01,925 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-10-07 15:39:01,925 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=108, Invalid=444, Unknown=0, NotChecked=0, Total=552 [2019-10-07 15:39:01,925 INFO L87 Difference]: Start difference. First operand 87 states and 91 transitions. Second operand 24 states. [2019-10-07 15:39:04,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:39:04,890 INFO L93 Difference]: Finished difference Result 113 states and 128 transitions. [2019-10-07 15:39:04,890 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-10-07 15:39:04,890 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 100 [2019-10-07 15:39:04,891 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:39:04,892 INFO L225 Difference]: With dead ends: 113 [2019-10-07 15:39:04,892 INFO L226 Difference]: Without dead ends: 93 [2019-10-07 15:39:04,893 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 324 GetRequests, 284 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 428 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=353, Invalid=1369, Unknown=0, NotChecked=0, Total=1722 [2019-10-07 15:39:04,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2019-10-07 15:39:04,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2019-10-07 15:39:04,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2019-10-07 15:39:04,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 97 transitions. [2019-10-07 15:39:04,904 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 97 transitions. Word has length 100 [2019-10-07 15:39:04,905 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:39:04,905 INFO L462 AbstractCegarLoop]: Abstraction has 93 states and 97 transitions. [2019-10-07 15:39:04,905 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-10-07 15:39:04,905 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 97 transitions. [2019-10-07 15:39:04,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2019-10-07 15:39:04,907 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:39:04,907 INFO L385 BasicCegarLoop]: trace histogram [60, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:39:05,112 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:05,112 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:39:05,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:39:05,113 INFO L82 PathProgramCache]: Analyzing trace with hash 1214122077, now seen corresponding path program 9 times [2019-10-07 15:39:05,113 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:39:05,114 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:05,114 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:05,114 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:05,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:39:05,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:39:05,403 INFO L134 CoverageAnalysis]: Checked inductivity of 2374 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 2364 trivial. 0 not checked. [2019-10-07 15:39:05,403 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:05,404 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:39:05,404 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:05,723 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:39:05,723 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:39:05,726 INFO L256 TraceCheckSpWp]: Trace formula consists of 643 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-07 15:39:05,729 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:39:05,855 INFO L134 CoverageAnalysis]: Checked inductivity of 2374 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 2075 trivial. 0 not checked. [2019-10-07 15:39:05,855 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:39:06,079 INFO L134 CoverageAnalysis]: Checked inductivity of 2374 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 2075 trivial. 0 not checked. [2019-10-07 15:39:06,080 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:39:06,084 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:39:06,084 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:39:06,085 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:39:06,085 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:39:06,085 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:39:06,098 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:39:07,328 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:39:07,350 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:39:07,352 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:39:07,352 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:39:07,352 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:39:07,353 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:39:07,353 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:39:07,353 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:39:07,353 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_214 Int) (v_sum_~ret~0_BEFORE_RETURN_213 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (<= (mod v_prenex_1582 4294967296) 2147483647) (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 59)) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_214 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_213 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_214 Int) (v_sum_~ret~0_BEFORE_RETURN_213 Int) (v_prenex_1582 Int) (v_prenex_1581 Int)) (or (and (<= (mod v_prenex_1582 4294967296) 2147483647) (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (= (+ (mod v_prenex_1581 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 59)) (not (<= (mod v_prenex_1581 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_214 4294967296) (- 4294967296)) main_~ret5~0) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_214 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_213 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_213 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:39:07,353 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:07,354 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-07 15:39:07,354 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1554 Int) (v_sum_~ret~0_BEFORE_RETURN_210 Int)) (or (and (not (< main_~i~1 60)) (= (mod v_prenex_1554 4294967296) |main_#t~ret4|) (<= (mod v_prenex_1554 4294967296) 2147483647)) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (not (< main_~i~1 60))))) (exists ((v_sum_~ret~0_BEFORE_RETURN_209 Int) (v_prenex_1553 Int)) (or (and (not (< main_~i~1 60)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (not (< main_~i~1 60)) (= (mod v_prenex_1553 4294967296) |main_#t~ret4|) (<= (mod v_prenex_1553 4294967296) 2147483647))))) [2019-10-07 15:39:07,354 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:39:07,354 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:39:07,354 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:07,355 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:39:07,355 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:39:07,355 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:39:07,355 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:39:07,355 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:39:07,355 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_209 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_sum_~ret~0_BEFORE_RETURN_210 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1553 4294967296) 2147483647) (= main_~ret~1 (mod v_prenex_1553 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1554 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1554 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))))) (exists ((v_sum_~ret~0_BEFORE_RETURN_209 Int) (v_prenex_1554 Int) (v_prenex_1553 Int) (v_sum_~ret~0_BEFORE_RETURN_210 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_1553 4294967296)) (<= (mod v_prenex_1553 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_210 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_209 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (= main_~ret~1 (mod v_prenex_1554 4294967296)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1554 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648)))))) [2019-10-07 15:39:07,356 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:39:07,356 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:39:07,926 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:39:07,927 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 13, 13, 11] total 39 [2019-10-07 15:39:07,928 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-07 15:39:07,930 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-07 15:39:07,930 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=1235, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:39:07,930 INFO L87 Difference]: Start difference. First operand 93 states and 97 transitions. Second operand 40 states. [2019-10-07 15:39:09,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:39:09,805 INFO L93 Difference]: Finished difference Result 132 states and 154 transitions. [2019-10-07 15:39:09,805 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-10-07 15:39:09,805 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 118 [2019-10-07 15:39:09,806 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:39:09,807 INFO L225 Difference]: With dead ends: 132 [2019-10-07 15:39:09,807 INFO L226 Difference]: Without dead ends: 106 [2019-10-07 15:39:09,808 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 396 GetRequests, 323 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1298 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1111, Invalid=4439, Unknown=0, NotChecked=0, Total=5550 [2019-10-07 15:39:09,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2019-10-07 15:39:09,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 106. [2019-10-07 15:39:09,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2019-10-07 15:39:09,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 110 transitions. [2019-10-07 15:39:09,819 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 110 transitions. Word has length 118 [2019-10-07 15:39:09,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:39:09,819 INFO L462 AbstractCegarLoop]: Abstraction has 106 states and 110 transitions. [2019-10-07 15:39:09,820 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-07 15:39:09,820 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 110 transitions. [2019-10-07 15:39:09,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2019-10-07 15:39:09,821 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:39:09,821 INFO L385 BasicCegarLoop]: trace histogram [66, 60, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:39:10,024 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:10,024 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:39:10,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:39:10,025 INFO L82 PathProgramCache]: Analyzing trace with hash 680013774, now seen corresponding path program 10 times [2019-10-07 15:39:10,025 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:39:10,026 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:10,026 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:10,026 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:10,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:39:10,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:39:10,552 INFO L134 CoverageAnalysis]: Checked inductivity of 4197 backedges. 0 proven. 1313 refuted. 0 times theorem prover too weak. 2884 trivial. 0 not checked. [2019-10-07 15:39:10,553 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:10,553 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:39:10,553 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:10,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:39:10,918 INFO L256 TraceCheckSpWp]: Trace formula consists of 827 conjuncts, 24 conjunts are in the unsatisfiable core [2019-10-07 15:39:10,923 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:39:10,961 INFO L134 CoverageAnalysis]: Checked inductivity of 4197 backedges. 1060 proven. 253 refuted. 0 times theorem prover too weak. 2884 trivial. 0 not checked. [2019-10-07 15:39:10,961 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:39:11,595 INFO L134 CoverageAnalysis]: Checked inductivity of 4197 backedges. 0 proven. 1313 refuted. 0 times theorem prover too weak. 2884 trivial. 0 not checked. [2019-10-07 15:39:11,595 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:39:11,596 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:39:11,596 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:39:11,597 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:39:11,597 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:39:11,597 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:39:11,613 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:39:12,959 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:39:12,981 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:39:12,984 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:39:12,984 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:39:12,985 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:39:12,985 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:39:12,985 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:39:12,985 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:39:12,985 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_239 Int) (v_prenex_1776 Int) (v_prenex_1775 Int) (v_sum_~ret~0_BEFORE_RETURN_240 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_240 4294967296) 2147483647) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_240 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_1775 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1776 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1776 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_239 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (not (= main_~ret~1 main_~ret5~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_239 Int) (v_prenex_1776 Int) (v_prenex_1775 Int) (v_sum_~ret~0_BEFORE_RETURN_240 Int)) (or (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_240 4294967296) 2147483647) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_240 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_1775 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_1775 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1776 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1776 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_239 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_239 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:39:12,986 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:12,986 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:12,986 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_235 Int) (v_prenex_1747 Int)) (or (and (not (<= (mod v_prenex_1747 4294967296) 2147483647)) (not (< main_~i~1 60)) (= |main_#t~ret4| (+ (mod v_prenex_1747 4294967296) (- 4294967296)))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_235 4294967296) 2147483647) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_235 4294967296)) (not (< main_~i~1 60))))) (exists ((v_sum_~ret~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int)) (or (and (not (< main_~i~1 60)) (<= (mod v_prenex_1748 4294967296) 2147483647) (= (mod v_prenex_1748 4294967296) |main_#t~ret4|)) (and (not (< main_~i~1 60)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_236 4294967296) 2147483647)) (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_236 4294967296) (- 4294967296))))))) [2019-10-07 15:39:12,986 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:39:12,986 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:39:12,986 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:12,987 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:39:12,987 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:39:12,987 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:39:12,987 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:39:12,987 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:39:12,987 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_sum_~ret~0_BEFORE_RETURN_236 Int) (v_sum_~ret~0_BEFORE_RETURN_235 Int) (v_prenex_1748 Int) (v_prenex_1747 Int)) (or (and (= (mod v_prenex_1748 4294967296) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1748 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_235 4294967296) 2147483647) (<= main_~ret~1 2147483647) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_235 4294967296)) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_236 4294967296) (- 4294967296))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_236 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (not (<= (mod v_prenex_1747 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_prenex_1747 4294967296) (- 4294967296))) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:39:12,987 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:39:12,987 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:39:13,411 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:39:13,412 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 11] total 59 [2019-10-07 15:39:13,413 INFO L442 AbstractCegarLoop]: Interpolant automaton has 60 states [2019-10-07 15:39:13,413 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2019-10-07 15:39:13,414 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1206, Invalid=2334, Unknown=0, NotChecked=0, Total=3540 [2019-10-07 15:39:13,414 INFO L87 Difference]: Start difference. First operand 106 states and 110 transitions. Second operand 60 states. [2019-10-07 15:39:17,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:39:17,175 INFO L93 Difference]: Finished difference Result 169 states and 202 transitions. [2019-10-07 15:39:17,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2019-10-07 15:39:17,175 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 155 [2019-10-07 15:39:17,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:39:17,177 INFO L225 Difference]: With dead ends: 169 [2019-10-07 15:39:17,177 INFO L226 Difference]: Without dead ends: 130 [2019-10-07 15:39:17,179 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 545 GetRequests, 433 SyntacticMatches, 0 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2813 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=3791, Invalid=9091, Unknown=0, NotChecked=0, Total=12882 [2019-10-07 15:39:17,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2019-10-07 15:39:17,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 130. [2019-10-07 15:39:17,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2019-10-07 15:39:17,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 134 transitions. [2019-10-07 15:39:17,192 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 134 transitions. Word has length 155 [2019-10-07 15:39:17,192 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:39:17,193 INFO L462 AbstractCegarLoop]: Abstraction has 130 states and 134 transitions. [2019-10-07 15:39:17,193 INFO L463 AbstractCegarLoop]: Interpolant automaton has 60 states. [2019-10-07 15:39:17,193 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 134 transitions. [2019-10-07 15:39:17,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 228 [2019-10-07 15:39:17,195 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:39:17,196 INFO L385 BasicCegarLoop]: trace histogram [138, 60, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:39:17,406 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:17,407 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:39:17,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:39:17,407 INFO L82 PathProgramCache]: Analyzing trace with hash -1126897074, now seen corresponding path program 11 times [2019-10-07 15:39:17,407 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:39:17,407 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:17,407 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:17,407 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:17,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:39:17,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:39:18,871 INFO L134 CoverageAnalysis]: Checked inductivity of 11721 backedges. 2210 proven. 3291 refuted. 0 times theorem prover too weak. 6220 trivial. 0 not checked. [2019-10-07 15:39:18,871 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:18,871 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:39:18,871 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:19,310 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-10-07 15:39:19,310 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:39:19,312 INFO L256 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-07 15:39:19,316 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:39:19,477 INFO L134 CoverageAnalysis]: Checked inductivity of 11721 backedges. 4422 proven. 15 refuted. 0 times theorem prover too weak. 7284 trivial. 0 not checked. [2019-10-07 15:39:19,478 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:39:19,746 INFO L134 CoverageAnalysis]: Checked inductivity of 11721 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 11706 trivial. 0 not checked. [2019-10-07 15:39:19,746 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:39:19,748 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:39:19,748 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:39:19,748 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:39:19,749 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:39:19,749 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:39:19,769 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:39:20,919 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:39:20,936 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:39:20,938 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:39:20,938 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:39:20,938 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:39:20,938 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:39:20,938 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:39:20,939 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:39:20,939 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_1970 Int) (v_sum_~ret~0_BEFORE_RETURN_265 Int) (v_sum_~ret~0_BEFORE_RETURN_266 Int) (v_prenex_1969 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_prenex_1969 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_265 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_265 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (<= (mod v_prenex_1970 4294967296) 2147483647) (not (< main_~i~2 59)) (= (mod v_prenex_1970 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_266 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_266 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_1970 Int) (v_sum_~ret~0_BEFORE_RETURN_265 Int) (v_sum_~ret~0_BEFORE_RETURN_266 Int) (v_prenex_1969 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_prenex_1969 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1969 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_265 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_265 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (<= (mod v_prenex_1970 4294967296) 2147483647) (not (< main_~i~2 59)) (= (mod v_prenex_1970 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_266 4294967296) (- 4294967296)) main_~ret5~0) (<= main_~ret5~0 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_266 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:39:20,939 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:20,939 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:20,940 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_1941 Int) (v_sum_~ret~0_BEFORE_RETURN_261 Int)) (or (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_261 4294967296)) (not (< main_~i~1 60))) (and (not (< main_~i~1 60)) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (= (+ (mod v_prenex_1941 4294967296) (- 4294967296)) |main_#t~ret4|)))) (exists ((v_prenex_1942 Int) (v_sum_~ret~0_BEFORE_RETURN_262 Int)) (or (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647)) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_262 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60))) (and (not (< main_~i~1 60)) (<= (mod v_prenex_1942 4294967296) 2147483647) (= |main_#t~ret4| (mod v_prenex_1942 4294967296)))))) [2019-10-07 15:39:20,940 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:39:20,940 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:20,940 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:39:20,940 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:39:20,941 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:39:20,941 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:39:20,941 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:39:20,941 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:39:20,941 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_sum_~ret~0_BEFORE_RETURN_261 Int) (v_sum_~ret~0_BEFORE_RETURN_262 Int)) (or (and (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_262 4294967296) 2147483647)) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_262 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_261 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_261 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_1941 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (mod v_prenex_1942 4294967296) main_~ret~1) (not (< main_~i~1 60)) (<= (mod v_prenex_1942 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:39:20,941 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:39:20,941 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:39:21,629 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:39:21,630 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 8, 8, 11] total 71 [2019-10-07 15:39:21,633 INFO L442 AbstractCegarLoop]: Interpolant automaton has 72 states [2019-10-07 15:39:21,634 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2019-10-07 15:39:21,634 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1296, Invalid=3816, Unknown=0, NotChecked=0, Total=5112 [2019-10-07 15:39:21,635 INFO L87 Difference]: Start difference. First operand 130 states and 134 transitions. Second operand 72 states. [2019-10-07 15:39:26,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:39:26,739 INFO L93 Difference]: Finished difference Result 201 states and 218 transitions. [2019-10-07 15:39:26,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2019-10-07 15:39:26,739 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 227 [2019-10-07 15:39:26,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:39:26,741 INFO L225 Difference]: With dead ends: 201 [2019-10-07 15:39:26,741 INFO L226 Difference]: Without dead ends: 138 [2019-10-07 15:39:26,743 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 797 GetRequests, 660 SyntacticMatches, 0 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3820 ImplicationChecksByTransitivity, 6.7s TimeCoverageRelationStatistics Valid=4186, Invalid=14996, Unknown=0, NotChecked=0, Total=19182 [2019-10-07 15:39:26,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2019-10-07 15:39:26,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2019-10-07 15:39:26,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2019-10-07 15:39:26,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 142 transitions. [2019-10-07 15:39:26,755 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 142 transitions. Word has length 227 [2019-10-07 15:39:26,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:39:26,756 INFO L462 AbstractCegarLoop]: Abstraction has 138 states and 142 transitions. [2019-10-07 15:39:26,756 INFO L463 AbstractCegarLoop]: Interpolant automaton has 72 states. [2019-10-07 15:39:26,756 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 142 transitions. [2019-10-07 15:39:26,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 238 [2019-10-07 15:39:26,759 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:39:26,759 INFO L385 BasicCegarLoop]: trace histogram [141, 60, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:39:26,964 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:26,965 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:39:26,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:39:26,965 INFO L82 PathProgramCache]: Analyzing trace with hash -864903692, now seen corresponding path program 12 times [2019-10-07 15:39:26,965 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:39:26,966 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:26,966 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:26,966 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:26,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:39:27,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:39:28,204 INFO L134 CoverageAnalysis]: Checked inductivity of 12210 backedges. 2305 proven. 3433 refuted. 0 times theorem prover too weak. 6472 trivial. 0 not checked. [2019-10-07 15:39:28,204 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:28,205 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:39:28,205 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:28,745 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:39:28,745 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:39:28,750 INFO L256 TraceCheckSpWp]: Trace formula consists of 1230 conjuncts, 49 conjunts are in the unsatisfiable core [2019-10-07 15:39:28,754 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:39:28,795 INFO L134 CoverageAnalysis]: Checked inductivity of 12210 backedges. 4610 proven. 1128 refuted. 0 times theorem prover too weak. 6472 trivial. 0 not checked. [2019-10-07 15:39:28,795 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:39:30,171 INFO L134 CoverageAnalysis]: Checked inductivity of 12210 backedges. 0 proven. 5738 refuted. 0 times theorem prover too weak. 6472 trivial. 0 not checked. [2019-10-07 15:39:30,171 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:39:30,172 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:39:30,173 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:39:30,173 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:39:30,173 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:39:30,174 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:39:30,193 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:39:31,434 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:39:31,465 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:39:31,468 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:39:31,468 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:39:31,469 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:39:31,469 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:39:31,469 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:39:31,470 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:39:31,470 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_sum_~ret~0_BEFORE_RETURN_292 Int) (v_sum_~ret~0_BEFORE_RETURN_291 Int) (v_prenex_2163 Int) (v_prenex_2164 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2163 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2163 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_prenex_2164 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_2164 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_292 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_292 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_291 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_291 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0))) (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_292 Int) (v_sum_~ret~0_BEFORE_RETURN_291 Int) (v_prenex_2163 Int) (v_prenex_2164 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2163 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2163 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= (mod v_prenex_2164 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_2164 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_292 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_292 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_291 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_291 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))))) [2019-10-07 15:39:31,470 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:31,471 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:31,471 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_prenex_2136 Int) (v_sum_~ret~0_BEFORE_RETURN_288 Int)) (or (and (not (< main_~i~1 60)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_288 4294967296) 2147483647) (= (mod v_sum_~ret~0_BEFORE_RETURN_288 4294967296) |main_#t~ret4|)) (and (= (+ (mod v_prenex_2136 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod v_prenex_2136 4294967296) 2147483647))))) (exists ((v_prenex_2135 Int) (v_sum_~ret~0_BEFORE_RETURN_287 Int)) (or (and (not (< main_~i~1 60)) (= (+ (mod v_prenex_2135 4294967296) (- 4294967296)) |main_#t~ret4|) (not (<= (mod v_prenex_2135 4294967296) 2147483647))) (and (= (mod v_sum_~ret~0_BEFORE_RETURN_287 4294967296) |main_#t~ret4|) (not (< main_~i~1 60)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_287 4294967296) 2147483647))))) [2019-10-07 15:39:31,471 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:39:31,471 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:31,471 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:39:31,471 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:39:31,472 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:39:31,473 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:39:31,478 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:39:31,478 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:39:31,478 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_2135 Int) (v_prenex_2136 Int) (v_sum_~ret~0_BEFORE_RETURN_287 Int) (v_sum_~ret~0_BEFORE_RETURN_288 Int)) (or (and (<= main_~ret~1 2147483647) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_287 4294967296)) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_287 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_sum_~ret~0_BEFORE_RETURN_288 4294967296) 2147483647) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_288 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= main_~ret~1 (+ (mod v_prenex_2135 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2135 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_prenex_2136 4294967296) (- 4294967296)) main_~ret~1) (not (<= (mod v_prenex_2136 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:39:31,478 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:39:31,479 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:39:32,096 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:39:32,097 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50, 11] total 73 [2019-10-07 15:39:32,098 INFO L442 AbstractCegarLoop]: Interpolant automaton has 74 states [2019-10-07 15:39:32,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2019-10-07 15:39:32,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1983, Invalid=3419, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:39:32,100 INFO L87 Difference]: Start difference. First operand 138 states and 142 transitions. Second operand 74 states. [2019-10-07 15:39:37,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:39:37,813 INFO L93 Difference]: Finished difference Result 222 states and 244 transitions. [2019-10-07 15:39:37,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2019-10-07 15:39:37,813 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 237 [2019-10-07 15:39:37,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:39:37,815 INFO L225 Difference]: With dead ends: 222 [2019-10-07 15:39:37,816 INFO L226 Difference]: Without dead ends: 151 [2019-10-07 15:39:37,818 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 829 GetRequests, 653 SyntacticMatches, 36 SemanticMatches, 140 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4619 ImplicationChecksByTransitivity, 8.0s TimeCoverageRelationStatistics Valid=6178, Invalid=13844, Unknown=0, NotChecked=0, Total=20022 [2019-10-07 15:39:37,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2019-10-07 15:39:37,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 151. [2019-10-07 15:39:37,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2019-10-07 15:39:37,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 155 transitions. [2019-10-07 15:39:37,832 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 155 transitions. Word has length 237 [2019-10-07 15:39:37,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:39:37,833 INFO L462 AbstractCegarLoop]: Abstraction has 151 states and 155 transitions. [2019-10-07 15:39:37,833 INFO L463 AbstractCegarLoop]: Interpolant automaton has 74 states. [2019-10-07 15:39:37,833 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 155 transitions. [2019-10-07 15:39:37,836 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 277 [2019-10-07 15:39:37,836 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:39:37,836 INFO L385 BasicCegarLoop]: trace histogram [180, 60, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:39:38,042 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:38,043 INFO L410 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:39:38,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:39:38,044 INFO L82 PathProgramCache]: Analyzing trace with hash -1920987139, now seen corresponding path program 13 times [2019-10-07 15:39:38,044 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:39:38,044 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:38,044 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:38,044 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:38,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:39:38,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:39:38,554 INFO L134 CoverageAnalysis]: Checked inductivity of 18567 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:39:38,554 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:38,554 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:39:38,555 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:39,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:39:39,126 INFO L256 TraceCheckSpWp]: Trace formula consists of 1425 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-07 15:39:39,132 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:39:39,263 INFO L134 CoverageAnalysis]: Checked inductivity of 18567 backedges. 7446 proven. 78 refuted. 0 times theorem prover too weak. 11043 trivial. 0 not checked. [2019-10-07 15:39:39,263 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:39:39,526 INFO L134 CoverageAnalysis]: Checked inductivity of 18567 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:39:39,526 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:39:39,529 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:39:39,529 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:39:39,530 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:39:39,530 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:39:39,530 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:39:39,543 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:39:40,665 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:39:40,695 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:39:40,698 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:39:40,698 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:39:40,698 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:39:40,698 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:39:40,698 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:39:40,699 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:39:40,699 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_sum_~ret~0_BEFORE_RETURN_317 Int) (v_prenex_2358 Int) (v_sum_~ret~0_BEFORE_RETURN_318 Int) (v_prenex_2357 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_318 4294967296) 2147483647) (= (mod v_sum_~ret~0_BEFORE_RETURN_318 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_317 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_317 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_2358 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2358 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_2357 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_2357 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_sum_~ret~0_BEFORE_RETURN_317 Int) (v_prenex_2358 Int) (v_sum_~ret~0_BEFORE_RETURN_318 Int) (v_prenex_2357 Int)) (or (and (not (< main_~i~2 59)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_318 4294967296) 2147483647) (= (mod v_sum_~ret~0_BEFORE_RETURN_318 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_317 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_317 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_2358 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2358 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_prenex_2357 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_2357 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:39:40,699 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:40,699 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:40,699 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_313 Int) (v_prenex_2329 Int)) (or (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_313 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_313 4294967296) 2147483647))) (and (<= (mod v_prenex_2329 4294967296) 2147483647) (not (< main_~i~1 60)) (= (mod v_prenex_2329 4294967296) |main_#t~ret4|)))) (exists ((v_sum_~ret~0_BEFORE_RETURN_314 Int) (v_prenex_2330 Int)) (or (and (= |main_#t~ret4| (+ (mod v_sum_~ret~0_BEFORE_RETURN_314 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_314 4294967296) 2147483647))) (and (= (mod v_prenex_2330 4294967296) |main_#t~ret4|) (<= (mod v_prenex_2330 4294967296) 2147483647) (not (< main_~i~1 60)))))) [2019-10-07 15:39:40,700 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:39:40,700 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:40,700 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:39:40,700 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:39:40,700 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:39:40,700 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:39:40,701 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:39:40,701 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:39:40,701 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_sum_~ret~0_BEFORE_RETURN_313 Int) (v_sum_~ret~0_BEFORE_RETURN_314 Int) (v_prenex_2330 Int) (v_prenex_2329 Int)) (or (and (<= main_~ret~1 2147483647) (<= (mod v_prenex_2329 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_2329 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~ret~1 (+ (mod v_sum_~ret~0_BEFORE_RETURN_314 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_314 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (<= (mod v_prenex_2330 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_prenex_2330 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_313 4294967296) (- 4294967296)) main_~ret~1) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_313 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:39:40,701 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:39:40,701 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:39:41,098 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:39:41,098 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-07 15:39:41,100 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-07 15:39:41,100 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-07 15:39:41,101 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-07 15:39:41,101 INFO L87 Difference]: Start difference. First operand 151 states and 155 transitions. Second operand 40 states. [2019-10-07 15:39:44,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:39:44,739 INFO L93 Difference]: Finished difference Result 233 states and 251 transitions. [2019-10-07 15:39:44,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-07 15:39:44,739 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 276 [2019-10-07 15:39:44,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:39:44,741 INFO L225 Difference]: With dead ends: 233 [2019-10-07 15:39:44,741 INFO L226 Difference]: Without dead ends: 165 [2019-10-07 15:39:44,742 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 877 GetRequests, 805 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1286 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1296, Invalid=4106, Unknown=0, NotChecked=0, Total=5402 [2019-10-07 15:39:44,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2019-10-07 15:39:44,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 165. [2019-10-07 15:39:44,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2019-10-07 15:39:44,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 169 transitions. [2019-10-07 15:39:44,756 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 169 transitions. Word has length 276 [2019-10-07 15:39:44,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:39:44,757 INFO L462 AbstractCegarLoop]: Abstraction has 165 states and 169 transitions. [2019-10-07 15:39:44,757 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-07 15:39:44,757 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 169 transitions. [2019-10-07 15:39:44,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2019-10-07 15:39:44,759 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:39:44,759 INFO L385 BasicCegarLoop]: trace histogram [180, 60, 26, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:39:44,965 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:44,966 INFO L410 AbstractCegarLoop]: === Iteration 17 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:39:44,966 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:39:44,966 INFO L82 PathProgramCache]: Analyzing trace with hash 623925981, now seen corresponding path program 14 times [2019-10-07 15:39:44,966 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:39:44,967 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:44,967 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:44,967 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:39:44,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:39:45,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:39:45,770 INFO L134 CoverageAnalysis]: Checked inductivity of 18840 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:39:45,770 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:39:45,771 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:39:45,771 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:39:57,455 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2019-10-07 15:39:57,455 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:39:57,467 INFO L256 TraceCheckSpWp]: Trace formula consists of 633 conjuncts, 42 conjunts are in the unsatisfiable core [2019-10-07 15:39:57,472 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:39:57,530 INFO L134 CoverageAnalysis]: Checked inductivity of 18840 backedges. 7506 proven. 351 refuted. 0 times theorem prover too weak. 10983 trivial. 0 not checked. [2019-10-07 15:39:57,530 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:39:58,517 INFO L134 CoverageAnalysis]: Checked inductivity of 18840 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:39:58,518 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:39:58,519 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:39:58,519 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:39:58,519 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:39:58,520 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:39:58,520 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:39:58,531 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:39:59,746 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:39:59,766 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:39:59,769 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:39:59,770 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:39:59,770 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:39:59,770 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:39:59,770 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:39:59,770 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:39:59,771 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_2552 Int) (v_sum_~ret~0_BEFORE_RETURN_344 Int) (v_prenex_2551 Int) (v_sum_~ret~0_BEFORE_RETURN_343 Int)) (or (and (not (< main_~i~2 59)) (= (mod v_prenex_2551 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2551 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_344 4294967296) 2147483647) (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_344 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_343 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_343 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2552 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2552 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_prenex_2552 Int) (v_sum_~ret~0_BEFORE_RETURN_344 Int) (v_prenex_2551 Int) (v_sum_~ret~0_BEFORE_RETURN_343 Int)) (or (and (not (< main_~i~2 59)) (= (mod v_prenex_2551 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2551 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_344 4294967296) 2147483647) (not (< main_~i~2 59)) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_344 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_sum_~ret~0_BEFORE_RETURN_343 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_343 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2552 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2552 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:39:59,771 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:59,771 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:59,771 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_339 Int) (v_prenex_2523 Int)) (or (and (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_339 4294967296) (- 4294967296)) |main_#t~ret4|) (not (< main_~i~1 60)) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_339 4294967296) 2147483647))) (and (not (< main_~i~1 60)) (= (mod v_prenex_2523 4294967296) |main_#t~ret4|) (<= (mod v_prenex_2523 4294967296) 2147483647)))) (exists ((v_prenex_2524 Int) (v_sum_~ret~0_BEFORE_RETURN_340 Int)) (or (and (not (< main_~i~1 60)) (not (<= (mod v_prenex_2524 4294967296) 2147483647)) (= (+ (mod v_prenex_2524 4294967296) (- 4294967296)) |main_#t~ret4|)) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_340 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_340 4294967296)))))) [2019-10-07 15:39:59,771 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:39:59,772 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:39:59,772 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:39:59,772 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:39:59,772 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:39:59,772 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:39:59,772 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:39:59,773 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:39:59,773 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_2523 Int) (v_sum_~ret~0_BEFORE_RETURN_339 Int) (v_prenex_2524 Int) (v_sum_~ret~0_BEFORE_RETURN_340 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~ret~1 (mod v_prenex_2523 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_2523 4294967296) 2147483647) (<= 0 (+ main_~ret~1 2147483648))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_340 4294967296) 2147483647) (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_340 4294967296)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (= (+ (mod v_sum_~ret~0_BEFORE_RETURN_339 4294967296) (- 4294967296)) main_~ret~1) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_sum_~ret~0_BEFORE_RETURN_339 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2524 4294967296) 2147483647)) (= (+ (mod v_prenex_2524 4294967296) (- 4294967296)) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:39:59,773 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:39:59,773 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:40:00,249 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:40:00,249 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 30, 29, 11] total 68 [2019-10-07 15:40:00,251 INFO L442 AbstractCegarLoop]: Interpolant automaton has 69 states [2019-10-07 15:40:00,251 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2019-10-07 15:40:00,252 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1627, Invalid=3065, Unknown=0, NotChecked=0, Total=4692 [2019-10-07 15:40:00,252 INFO L87 Difference]: Start difference. First operand 165 states and 169 transitions. Second operand 69 states. [2019-10-07 15:40:04,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:40:04,344 INFO L93 Difference]: Finished difference Result 261 states and 293 transitions. [2019-10-07 15:40:04,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2019-10-07 15:40:04,344 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 290 [2019-10-07 15:40:04,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:40:04,347 INFO L225 Difference]: With dead ends: 261 [2019-10-07 15:40:04,347 INFO L226 Difference]: Without dead ends: 193 [2019-10-07 15:40:04,349 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 962 GetRequests, 832 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3621 ImplicationChecksByTransitivity, 5.3s TimeCoverageRelationStatistics Valid=4990, Invalid=12302, Unknown=0, NotChecked=0, Total=17292 [2019-10-07 15:40:04,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states. [2019-10-07 15:40:04,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 193. [2019-10-07 15:40:04,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193 states. [2019-10-07 15:40:04,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 197 transitions. [2019-10-07 15:40:04,363 INFO L78 Accepts]: Start accepts. Automaton has 193 states and 197 transitions. Word has length 290 [2019-10-07 15:40:04,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:40:04,364 INFO L462 AbstractCegarLoop]: Abstraction has 193 states and 197 transitions. [2019-10-07 15:40:04,364 INFO L463 AbstractCegarLoop]: Interpolant automaton has 69 states. [2019-10-07 15:40:04,364 INFO L276 IsEmpty]: Start isEmpty. Operand 193 states and 197 transitions. [2019-10-07 15:40:04,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 319 [2019-10-07 15:40:04,365 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:40:04,365 INFO L385 BasicCegarLoop]: trace histogram [180, 60, 54, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:40:04,566 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:40:04,567 INFO L410 AbstractCegarLoop]: === Iteration 18 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:40:04,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:40:04,567 INFO L82 PathProgramCache]: Analyzing trace with hash 54089885, now seen corresponding path program 15 times [2019-10-07 15:40:04,568 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:40:04,568 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:40:04,568 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:40:04,568 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:40:04,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:40:04,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:40:06,341 INFO L134 CoverageAnalysis]: Checked inductivity of 19974 backedges. 0 proven. 1485 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:40:06,341 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:40:06,341 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-07 15:40:06,341 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:40:07,021 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-07 15:40:07,021 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-07 15:40:07,027 INFO L256 TraceCheckSpWp]: Trace formula consists of 1593 conjuncts, 56 conjunts are in the unsatisfiable core [2019-10-07 15:40:07,034 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-07 15:40:07,171 INFO L134 CoverageAnalysis]: Checked inductivity of 19974 backedges. 7446 proven. 1485 refuted. 0 times theorem prover too weak. 11043 trivial. 0 not checked. [2019-10-07 15:40:07,172 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-07 15:40:08,897 INFO L134 CoverageAnalysis]: Checked inductivity of 19974 backedges. 0 proven. 1485 refuted. 0 times theorem prover too weak. 18489 trivial. 0 not checked. [2019-10-07 15:40:08,897 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-07 15:40:08,898 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-07 15:40:08,898 INFO L169 IcfgInterpreter]: Building call graph [2019-10-07 15:40:08,899 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-07 15:40:08,899 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-07 15:40:08,899 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-07 15:40:08,914 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-07 15:40:10,042 INFO L199 IcfgInterpreter]: Interpreting procedure sum with input of size 1 for LOIs [2019-10-07 15:40:10,060 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-07 15:40:10,062 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-07 15:40:10,062 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-07 15:40:10,062 INFO L193 IcfgInterpreter]: Reachable states at location L9-3 satisfy 639#(<= 0 sum_~i~0) [2019-10-07 15:40:10,063 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-07 15:40:10,063 INFO L193 IcfgInterpreter]: Reachable states at location L36-1 satisfy 479#true [2019-10-07 15:40:10,063 INFO L193 IcfgInterpreter]: Reachable states at location L36 satisfy 522#(and (not (< main_~i~2 59)) (<= 59 main_~i~2) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) [2019-10-07 15:40:10,063 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~1 main_~ret2~0)) (exists ((v_prenex_2745 Int) (v_prenex_2746 Int) (v_sum_~ret~0_BEFORE_RETURN_369 Int) (v_sum_~ret~0_BEFORE_RETURN_370 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2746 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2746 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_370 4294967296) 2147483647) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_370 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_prenex_2745 4294967296) (- 4294967296))) (not (<= (mod v_prenex_2745 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_369 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= (mod v_sum_~ret~0_BEFORE_RETURN_369 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236))))))) (and (exists ((v_prenex_2745 Int) (v_prenex_2746 Int) (v_sum_~ret~0_BEFORE_RETURN_369 Int) (v_sum_~ret~0_BEFORE_RETURN_370 Int)) (or (and (not (< main_~i~2 59)) (not (<= (mod v_prenex_2746 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2746 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_370 4294967296) 2147483647) (= main_~ret5~0 (mod v_sum_~ret~0_BEFORE_RETURN_370 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (= main_~ret5~0 (+ (mod v_prenex_2745 4294967296) (- 4294967296))) (not (<= (mod v_prenex_2745 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))) (and (not (< main_~i~2 59)) (<= (mod v_sum_~ret~0_BEFORE_RETURN_369 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (= (mod v_sum_~ret~0_BEFORE_RETURN_369 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 236)))))) (not (= main_~ret~1 main_~ret5~0)))) [2019-10-07 15:40:10,064 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:40:10,064 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:40:10,064 INFO L193 IcfgInterpreter]: Reachable states at location L27 satisfy 120#(or (exists ((v_sum_~ret~0_BEFORE_RETURN_365 Int) (v_prenex_2717 Int)) (or (and (= |main_#t~ret4| (+ (mod v_prenex_2717 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (not (<= (mod v_prenex_2717 4294967296) 2147483647))) (and (<= (mod v_sum_~ret~0_BEFORE_RETURN_365 4294967296) 2147483647) (not (< main_~i~1 60)) (= |main_#t~ret4| (mod v_sum_~ret~0_BEFORE_RETURN_365 4294967296))))) (exists ((v_prenex_2718 Int) (v_sum_~ret~0_BEFORE_RETURN_366 Int)) (or (and (= |main_#t~ret4| (+ (mod v_prenex_2718 4294967296) (- 4294967296))) (not (< main_~i~1 60)) (not (<= (mod v_prenex_2718 4294967296) 2147483647))) (and (= (mod v_sum_~ret~0_BEFORE_RETURN_366 4294967296) |main_#t~ret4|) (<= (mod v_sum_~ret~0_BEFORE_RETURN_366 4294967296) 2147483647) (not (< main_~i~1 60)))))) [2019-10-07 15:40:10,064 INFO L193 IcfgInterpreter]: Reachable states at location sumENTRY satisfy 601#true [2019-10-07 15:40:10,064 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-07 15:40:10,065 INFO L193 IcfgInterpreter]: Reachable states at location L38 satisfy 380#true [2019-10-07 15:40:10,065 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-07 15:40:10,065 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 313#true [2019-10-07 15:40:10,065 INFO L193 IcfgInterpreter]: Reachable states at location L30-1 satisfy 587#true [2019-10-07 15:40:10,065 INFO L193 IcfgInterpreter]: Reachable states at location L32-3 satisfy 560#true [2019-10-07 15:40:10,065 INFO L193 IcfgInterpreter]: Reachable states at location L23-4 satisfy 73#(and (<= 60 main_~i~1) (not (< main_~i~1 60))) [2019-10-07 15:40:10,066 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 592#(exists ((v_prenex_2718 Int) (v_sum_~ret~0_BEFORE_RETURN_366 Int) (v_sum_~ret~0_BEFORE_RETURN_365 Int) (v_prenex_2717 Int)) (or (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2717 4294967296) 2147483647)) (= main_~ret~1 (+ (mod v_prenex_2717 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (<= (mod v_sum_~ret~0_BEFORE_RETURN_366 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_sum_~ret~0_BEFORE_RETURN_366 4294967296) main_~ret~1) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (not (< main_~i~1 60)) (= (+ (mod v_prenex_2718 4294967296) (- 4294967296)) main_~ret~1) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2718 4294967296) 2147483647)) (<= 0 (+ main_~ret~1 2147483648))) (and (<= main_~ret~1 2147483647) (<= (mod v_sum_~ret~0_BEFORE_RETURN_365 4294967296) 2147483647) (not (< main_~i~1 60)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~1 (mod v_sum_~ret~0_BEFORE_RETURN_365 4294967296)) (<= 0 (+ main_~ret~1 2147483648))))) [2019-10-07 15:40:10,066 INFO L193 IcfgInterpreter]: Reachable states at location L23-3 satisfy 68#true [2019-10-07 15:40:10,066 INFO L193 IcfgInterpreter]: Reachable states at location sumEXIT satisfy 644#(and (<= 0 sum_~i~0) (= |sum_#res| (ite (<= (mod sum_~ret~0 4294967296) 2147483647) (mod sum_~ret~0 4294967296) (+ (mod sum_~ret~0 4294967296) (- 4294967296)))) (not (< sum_~i~0 60)) (<= 60 sum_~i~0)) [2019-10-07 15:40:10,695 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-07 15:40:10,696 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57, 57, 11] total 72 [2019-10-07 15:40:10,697 INFO L442 AbstractCegarLoop]: Interpolant automaton has 73 states [2019-10-07 15:40:10,697 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2019-10-07 15:40:10,698 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1920, Invalid=3336, Unknown=0, NotChecked=0, Total=5256 [2019-10-07 15:40:10,698 INFO L87 Difference]: Start difference. First operand 193 states and 197 transitions. Second operand 73 states. [2019-10-07 15:40:15,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-07 15:40:15,967 INFO L93 Difference]: Finished difference Result 266 states and 275 transitions. [2019-10-07 15:40:15,967 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2019-10-07 15:40:15,968 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 318 [2019-10-07 15:40:15,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-07 15:40:15,969 INFO L225 Difference]: With dead ends: 266 [2019-10-07 15:40:15,969 INFO L226 Difference]: Without dead ends: 198 [2019-10-07 15:40:15,970 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1078 GetRequests, 889 SyntacticMatches, 51 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4778 ImplicationChecksByTransitivity, 7.6s TimeCoverageRelationStatistics Valid=5751, Invalid=13709, Unknown=0, NotChecked=0, Total=19460 [2019-10-07 15:40:15,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states. [2019-10-07 15:40:15,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2019-10-07 15:40:15,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198 states. [2019-10-07 15:40:15,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 202 transitions. [2019-10-07 15:40:15,986 INFO L78 Accepts]: Start accepts. Automaton has 198 states and 202 transitions. Word has length 318 [2019-10-07 15:40:15,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-07 15:40:15,986 INFO L462 AbstractCegarLoop]: Abstraction has 198 states and 202 transitions. [2019-10-07 15:40:15,987 INFO L463 AbstractCegarLoop]: Interpolant automaton has 73 states. [2019-10-07 15:40:15,987 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 202 transitions. [2019-10-07 15:40:15,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 324 [2019-10-07 15:40:15,989 INFO L377 BasicCegarLoop]: Found error trace [2019-10-07 15:40:15,989 INFO L385 BasicCegarLoop]: trace histogram [180, 60, 59, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-07 15:40:16,195 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-07 15:40:16,196 INFO L410 AbstractCegarLoop]: === Iteration 19 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-07 15:40:16,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-07 15:40:16,196 INFO L82 PathProgramCache]: Analyzing trace with hash -1910485234, now seen corresponding path program 16 times [2019-10-07 15:40:16,197 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-07 15:40:16,197 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-07 15:40:16,197 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:40:16,197 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-07 15:40:16,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-07 15:41:58,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-07 15:43:26,176 WARN L191 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 103 DAG size of output: 8 [2019-10-07 15:43:28,100 WARN L191 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 117 DAG size of output: 8 [2019-10-07 15:43:28,602 WARN L191 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 120 DAG size of output: 8 [2019-10-07 15:43:28,907 WARN L191 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 126 DAG size of output: 8 [2019-10-07 15:43:29,746 WARN L191 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 123 DAG size of output: 8 [2019-10-07 15:43:30,062 WARN L191 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 135 DAG size of output: 8 [2019-10-07 15:43:30,377 WARN L191 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 129 DAG size of output: 8 [2019-10-07 15:43:30,686 WARN L191 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 128 DAG size of output: 8 [2019-10-07 15:43:31,001 WARN L191 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 129 DAG size of output: 8 [2019-10-07 15:43:31,347 WARN L191 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 138 DAG size of output: 8 [2019-10-07 15:43:31,684 WARN L191 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 141 DAG size of output: 8 [2019-10-07 15:43:32,055 WARN L191 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 144 DAG size of output: 8 [2019-10-07 15:43:32,445 WARN L191 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 147 DAG size of output: 8 [2019-10-07 15:43:32,838 WARN L191 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 150 DAG size of output: 8 [2019-10-07 15:43:33,632 WARN L191 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 156 DAG size of output: 8 [2019-10-07 15:43:38,255 WARN L191 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 74 [2019-10-07 15:43:39,068 WARN L191 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 79 [2019-10-07 15:43:39,515 WARN L191 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 82 [2019-10-07 15:43:39,955 WARN L191 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 86 [2019-10-07 15:43:40,443 WARN L191 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 100 DAG size of output: 89 [2019-10-07 15:43:40,943 WARN L191 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 103 DAG size of output: 92 [2019-10-07 15:43:41,455 WARN L191 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 105 DAG size of output: 94 [2019-10-07 15:43:41,993 WARN L191 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 109 DAG size of output: 98 [2019-10-07 15:43:42,551 WARN L191 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 112 DAG size of output: 101 [2019-10-07 15:43:43,102 WARN L191 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 115 DAG size of output: 103 [2019-10-07 15:43:43,693 WARN L191 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 117 DAG size of output: 106 [2019-10-07 15:43:44,289 WARN L191 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 121 DAG size of output: 110 [2019-10-07 15:43:44,914 WARN L191 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 124 DAG size of output: 113 [2019-10-07 15:43:45,543 WARN L191 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 128 DAG size of output: 115 [2019-10-07 15:43:46,225 WARN L191 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 130 DAG size of output: 117 [2019-10-07 15:43:46,921 WARN L191 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 134 DAG size of output: 122 [2019-10-07 15:43:48,044 WARN L191 SmtUtils]: Spent 548.00 ms on a formula simplification. DAG size of input: 137 DAG size of output: 125 [2019-10-07 15:43:48,783 WARN L191 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 140 DAG size of output: 127 [2019-10-07 15:43:49,531 WARN L191 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 142 DAG size of output: 130 [2019-10-07 15:43:50,259 WARN L191 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 146 DAG size of output: 133 [2019-10-07 15:43:51,010 WARN L191 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 149 DAG size of output: 136 [2019-10-07 15:43:51,830 WARN L191 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 152 DAG size of output: 140 [2019-10-07 15:43:52,671 WARN L191 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 154 DAG size of output: 142 [2019-10-07 15:43:53,508 WARN L191 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 158 DAG size of output: 146 [2019-10-07 15:43:54,387 WARN L191 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 161 DAG size of output: 149 [2019-10-07 15:43:55,256 WARN L191 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 164 DAG size of output: 152 [2019-10-07 15:43:56,159 WARN L191 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 166 DAG size of output: 154 [2019-10-07 15:43:57,074 WARN L191 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 170 DAG size of output: 158 [2019-10-07 15:43:58,018 WARN L191 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 173 DAG size of output: 161 [2019-10-07 15:43:59,009 WARN L191 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 176 DAG size of output: 163 [2019-10-07 15:43:59,946 WARN L191 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 175 DAG size of output: 166 [2019-10-07 15:44:00,894 WARN L191 SmtUtils]: Spent 145.00 ms on a formula simplification. DAG size of input: 179 DAG size of output: 168 [2019-10-07 15:44:01,899 WARN L191 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 182 DAG size of output: 173 [2019-10-07 15:44:02,917 WARN L191 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 185 DAG size of output: 176 [2019-10-07 15:44:04,299 WARN L191 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 187 DAG size of output: 178 [2019-10-07 15:44:05,330 WARN L191 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 191 DAG size of output: 181 [2019-10-07 15:44:06,412 WARN L191 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 194 DAG size of output: 185 [2019-10-07 15:44:07,552 WARN L191 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 197 DAG size of output: 188 [2019-10-07 15:44:08,714 WARN L191 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 200 DAG size of output: 190 [2019-10-07 15:44:09,911 WARN L191 SmtUtils]: Spent 182.00 ms on a formula simplification. DAG size of input: 204 DAG size of output: 194 [2019-10-07 15:44:11,109 WARN L191 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 207 DAG size of output: 197 [2019-10-07 15:44:12,367 WARN L191 SmtUtils]: Spent 201.00 ms on a formula simplification. DAG size of input: 210 DAG size of output: 200 [2019-10-07 15:44:20,566 WARN L191 SmtUtils]: Spent 5.78 s on a formula simplification. DAG size of input: 166 DAG size of output: 151 [2019-10-07 15:44:26,053 WARN L191 SmtUtils]: Spent 2.90 s on a formula simplification. DAG size of input: 431 DAG size of output: 196 [2019-10-07 15:44:29,650 WARN L191 SmtUtils]: Spent 1.33 s on a formula simplification. DAG size of input: 324 DAG size of output: 195 [2019-10-07 15:45:28,478 WARN L191 SmtUtils]: Spent 15.54 s on a formula simplification. DAG size of input: 318 DAG size of output: 184 [2019-10-07 15:46:01,586 WARN L191 SmtUtils]: Spent 18.28 s on a formula simplification. DAG size of input: 436 DAG size of output: 187 [2019-10-07 15:46:13,128 WARN L191 SmtUtils]: Spent 6.49 s on a formula simplification. DAG size of input: 530 DAG size of output: 215 [2019-10-07 15:46:43,586 WARN L191 SmtUtils]: Spent 27.48 s on a formula simplification. DAG size of input: 521 DAG size of output: 210 [2019-10-07 15:47:17,236 WARN L191 SmtUtils]: Spent 28.81 s on a formula simplification. DAG size of input: 518 DAG size of output: 217 [2019-10-07 15:47:37,981 WARN L191 SmtUtils]: Spent 17.59 s on a formula simplification. DAG size of input: 513 DAG size of output: 209 [2019-10-07 15:48:06,358 WARN L191 SmtUtils]: Spent 21.00 s on a formula simplification. DAG size of input: 506 DAG size of output: 210 [2019-10-07 15:48:52,991 WARN L191 SmtUtils]: Spent 43.52 s on a formula simplification. DAG size of input: 510 DAG size of output: 216 [2019-10-07 15:49:17,511 WARN L191 SmtUtils]: Spent 21.48 s on a formula simplification. DAG size of input: 509 DAG size of output: 208 [2019-10-07 15:49:32,418 WARN L191 SmtUtils]: Spent 10.29 s on a formula simplification. DAG size of input: 507 DAG size of output: 208 [2019-10-07 15:50:16,402 WARN L191 SmtUtils]: Spent 37.87 s on a formula simplification. DAG size of input: 507 DAG size of output: 205 [2019-10-07 15:50:29,532 WARN L191 SmtUtils]: Spent 9.83 s on a formula simplification. DAG size of input: 506 DAG size of output: 207