java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/array-crafted/xor1.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-06 23:01:18,067 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-06 23:01:18,070 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-06 23:01:18,088 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-06 23:01:18,088 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-06 23:01:18,090 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-06 23:01:18,092 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-06 23:01:18,097 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-06 23:01:18,099 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-06 23:01:18,105 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-06 23:01:18,105 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-06 23:01:18,106 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-06 23:01:18,107 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-06 23:01:18,109 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-06 23:01:18,110 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-06 23:01:18,111 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-06 23:01:18,111 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-06 23:01:18,112 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-06 23:01:18,114 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-06 23:01:18,117 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-06 23:01:18,121 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-06 23:01:18,122 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-06 23:01:18,123 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-06 23:01:18,124 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-06 23:01:18,127 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-06 23:01:18,140 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-06 23:01:18,141 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-06 23:01:18,142 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-06 23:01:18,146 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-06 23:01:18,165 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-06 23:01:18,165 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-06 23:01:18,166 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-06 23:01:18,166 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-06 23:01:18,166 INFO L138 SettingsManager]: * Use SBE=true [2019-10-06 23:01:18,167 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-06 23:01:18,167 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-06 23:01:18,167 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-06 23:01:18,167 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-06 23:01:18,168 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-06 23:01:18,168 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-06 23:01:18,168 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-06 23:01:18,168 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-06 23:01:18,168 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-06 23:01:18,169 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-06 23:01:18,169 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-06 23:01:18,169 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-06 23:01:18,169 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-06 23:01:18,170 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-06 23:01:18,170 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-06 23:01:18,170 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-06 23:01:18,170 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 23:01:18,171 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-06 23:01:18,171 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-06 23:01:18,171 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-06 23:01:18,171 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-06 23:01:18,171 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-06 23:01:18,172 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-06 23:01:18,172 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-06 23:01:18,476 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-06 23:01:18,490 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-06 23:01:18,493 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-06 23:01:18,495 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-06 23:01:18,495 INFO L275 PluginConnector]: CDTParser initialized [2019-10-06 23:01:18,496 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-crafted/xor1.i [2019-10-06 23:01:18,562 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4b9de7270/11c4309b733c4537bed48ff322b3a3ae/FLAG19f8efd6c [2019-10-06 23:01:19,014 INFO L306 CDTParser]: Found 1 translation units. [2019-10-06 23:01:19,015 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-crafted/xor1.i [2019-10-06 23:01:19,023 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4b9de7270/11c4309b733c4537bed48ff322b3a3ae/FLAG19f8efd6c [2019-10-06 23:01:19,417 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4b9de7270/11c4309b733c4537bed48ff322b3a3ae [2019-10-06 23:01:19,427 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-06 23:01:19,428 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-06 23:01:19,429 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-06 23:01:19,430 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-06 23:01:19,433 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-06 23:01:19,434 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,437 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@ef99201 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19, skipping insertion in model container [2019-10-06 23:01:19,438 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,445 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-06 23:01:19,466 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-06 23:01:19,653 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 23:01:19,663 INFO L188 MainTranslator]: Completed pre-run [2019-10-06 23:01:19,692 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 23:01:19,792 INFO L192 MainTranslator]: Completed translation [2019-10-06 23:01:19,793 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19 WrapperNode [2019-10-06 23:01:19,793 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-06 23:01:19,793 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-06 23:01:19,793 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-06 23:01:19,794 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-06 23:01:19,806 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,806 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,814 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,816 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,825 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,831 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,833 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,835 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-06 23:01:19,836 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-06 23:01:19,836 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-06 23:01:19,836 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-06 23:01:19,837 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 23:01:19,886 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-06 23:01:19,886 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-06 23:01:19,886 INFO L138 BoogieDeclarations]: Found implementation of procedure xor [2019-10-06 23:01:19,886 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-06 23:01:19,887 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-06 23:01:19,887 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-06 23:01:19,887 INFO L130 BoogieDeclarations]: Found specification of procedure xor [2019-10-06 23:01:19,887 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-06 23:01:19,887 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-06 23:01:19,887 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-06 23:01:19,887 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-06 23:01:19,888 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-06 23:01:19,888 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-06 23:01:19,888 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-06 23:01:20,297 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-06 23:01:20,297 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-06 23:01:20,298 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 11:01:20 BoogieIcfgContainer [2019-10-06 23:01:20,299 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-06 23:01:20,300 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-06 23:01:20,300 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-06 23:01:20,303 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-06 23:01:20,303 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.10 11:01:19" (1/3) ... [2019-10-06 23:01:20,304 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@a07a1d2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 11:01:20, skipping insertion in model container [2019-10-06 23:01:20,304 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (2/3) ... [2019-10-06 23:01:20,304 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@a07a1d2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 11:01:20, skipping insertion in model container [2019-10-06 23:01:20,305 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 11:01:20" (3/3) ... [2019-10-06 23:01:20,306 INFO L109 eAbstractionObserver]: Analyzing ICFG xor1.i [2019-10-06 23:01:20,316 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-06 23:01:20,324 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-06 23:01:20,335 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-06 23:01:20,360 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-06 23:01:20,361 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-06 23:01:20,361 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-06 23:01:20,361 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-06 23:01:20,361 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-06 23:01:20,361 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-06 23:01:20,361 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-06 23:01:20,361 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-06 23:01:20,379 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-06 23:01:20,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-06 23:01:20,385 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:20,386 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:20,388 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:20,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:20,394 INFO L82 PathProgramCache]: Analyzing trace with hash -809725829, now seen corresponding path program 1 times [2019-10-06 23:01:20,402 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:20,403 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:20,403 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:20,403 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:20,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:20,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:20,614 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-06 23:01:20,615 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:20,615 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 23:01:20,616 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 23:01:20,620 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 23:01:20,638 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 23:01:20,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 23:01:20,642 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-06 23:01:20,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:20,675 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-06 23:01:20,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 23:01:20,677 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-06 23:01:20,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:20,686 INFO L225 Difference]: With dead ends: 41 [2019-10-06 23:01:20,686 INFO L226 Difference]: Without dead ends: 20 [2019-10-06 23:01:20,690 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 23:01:20,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-06 23:01:20,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-06 23:01:20,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-06 23:01:20,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-06 23:01:20,727 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-06 23:01:20,727 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:20,728 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-06 23:01:20,728 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 23:01:20,728 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-06 23:01:20,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-06 23:01:20,730 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:20,731 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:20,731 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:20,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:20,732 INFO L82 PathProgramCache]: Analyzing trace with hash 994996090, now seen corresponding path program 1 times [2019-10-06 23:01:20,732 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:20,732 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:20,732 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:20,733 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:20,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:20,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:20,803 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 23:01:20,804 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:20,804 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:20,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:20,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:20,876 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-06 23:01:20,883 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:20,913 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 23:01:20,914 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:20,953 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 23:01:20,954 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-06 23:01:20,954 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-06 23:01:20,956 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 23:01:20,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 23:01:20,956 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 23:01:20,957 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-06 23:01:20,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:20,969 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-06 23:01:20,969 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 23:01:20,970 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-06 23:01:20,970 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:20,972 INFO L225 Difference]: With dead ends: 33 [2019-10-06 23:01:20,972 INFO L226 Difference]: Without dead ends: 21 [2019-10-06 23:01:20,974 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 23:01:20,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-06 23:01:20,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-06 23:01:20,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-06 23:01:20,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-06 23:01:20,988 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-06 23:01:20,989 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:20,989 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-06 23:01:20,990 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 23:01:20,990 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-06 23:01:20,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-06 23:01:20,992 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:20,992 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:21,202 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:21,202 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:21,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:21,203 INFO L82 PathProgramCache]: Analyzing trace with hash -421018474, now seen corresponding path program 1 times [2019-10-06 23:01:21,203 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:21,203 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:21,203 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:21,203 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:21,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:21,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:21,299 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 23:01:21,300 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:21,300 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 23:01:21,301 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 23:01:21,301 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 23:01:21,302 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 23:01:21,302 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 23:01:21,302 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-06 23:01:21,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:21,315 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-06 23:01:21,316 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 23:01:21,316 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-06 23:01:21,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:21,317 INFO L225 Difference]: With dead ends: 31 [2019-10-06 23:01:21,318 INFO L226 Difference]: Without dead ends: 22 [2019-10-06 23:01:21,318 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 23:01:21,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-06 23:01:21,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-06 23:01:21,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-06 23:01:21,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-06 23:01:21,327 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-06 23:01:21,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:21,337 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-06 23:01:21,337 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 23:01:21,337 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-06 23:01:21,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-06 23:01:21,342 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:21,342 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:21,342 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:21,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:21,343 INFO L82 PathProgramCache]: Analyzing trace with hash -661634715, now seen corresponding path program 1 times [2019-10-06 23:01:21,346 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:21,347 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:21,347 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:21,347 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:21,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:21,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:21,479 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 23:01:21,480 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:21,480 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:21,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:21,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:21,582 INFO L256 TraceCheckSpWp]: Trace formula consists of 136 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 23:01:21,589 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:21,610 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 23:01:21,610 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:21,643 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 23:01:21,643 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:21,668 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:21,668 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:21,674 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:21,682 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:21,683 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:21,864 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:23,877 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:23,941 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:23,945 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:23,946 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:23,946 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:01:23,946 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:01:23,946 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_2 Int) (v_xor_~res~0_BEFORE_RETURN_2 Int) (v_prenex_1 Int) (v_xor_~res~0_BEFORE_RETURN_1 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_2 4294967296) 2147483647)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_2 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_2 4294967296)) (<= main_~ret~0 2147483647) (<= (mod v_prenex_2 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_1 4294967296))))) [2019-10-06 23:01:23,947 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:23,947 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:23,947 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:23,947 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:23,948 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_xor_~res~0_BEFORE_RETURN_6 Int) (v_xor_~res~0_BEFORE_RETURN_5 Int)) (or (and (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_5 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_5 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_6 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_6 4294967296) 2147483647))) (and (not (<= (mod v_prenex_29 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= main_~ret5~0 (+ (mod v_prenex_29 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (not (< main_~i~2 99)) (<= (mod v_prenex_30 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_xor_~res~0_BEFORE_RETURN_6 Int) (v_xor_~res~0_BEFORE_RETURN_5 Int)) (or (and (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_5 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_5 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_6 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_6 4294967296) 2147483647))) (and (not (<= (mod v_prenex_29 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= main_~ret5~0 (+ (mod v_prenex_29 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (not (< main_~i~2 99)) (<= (mod v_prenex_30 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 23:01:23,948 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:23,948 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:23,948 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:23,948 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:23,949 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:23,949 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:01:23,949 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_xor_~res~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (= (mod v_xor_~res~0_BEFORE_RETURN_1 4294967296) |main_#t~ret5|) (not (< main_~i~1 100)) (<= (mod v_xor_~res~0_BEFORE_RETURN_1 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_1 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_1 4294967296) 2147483647))))) (exists ((v_prenex_2 Int) (v_xor_~res~0_BEFORE_RETURN_2 Int)) (or (and (= |main_#t~ret5| (mod v_prenex_2 4294967296)) (not (< main_~i~1 100)) (<= (mod v_prenex_2 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_2 4294967296) 2147483647)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_2 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 23:01:23,949 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:23,950 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:23,950 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:23,950 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:24,373 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:24,374 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-06 23:01:24,375 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-06 23:01:24,376 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-06 23:01:24,376 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-06 23:01:24,377 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-06 23:01:25,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:25,143 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-06 23:01:25,143 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-06 23:01:25,144 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-06 23:01:25,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:25,145 INFO L225 Difference]: With dead ends: 40 [2019-10-06 23:01:25,145 INFO L226 Difference]: Without dead ends: 25 [2019-10-06 23:01:25,146 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=133, Invalid=737, Unknown=0, NotChecked=0, Total=870 [2019-10-06 23:01:25,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-06 23:01:25,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-06 23:01:25,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-06 23:01:25,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-06 23:01:25,153 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-06 23:01:25,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:25,153 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-06 23:01:25,154 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-06 23:01:25,154 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-06 23:01:25,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-06 23:01:25,155 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:25,155 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:25,358 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:25,359 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:25,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:25,359 INFO L82 PathProgramCache]: Analyzing trace with hash -139894362, now seen corresponding path program 2 times [2019-10-06 23:01:25,360 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:25,360 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:25,360 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:25,360 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:25,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:25,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:25,466 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 23:01:25,466 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:25,467 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:25,467 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:25,557 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-06 23:01:25,557 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:01:25,564 INFO L256 TraceCheckSpWp]: Trace formula consists of 106 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 23:01:25,571 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:25,592 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 23:01:25,592 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:25,624 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 23:01:25,625 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:25,627 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:25,628 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:25,629 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:25,629 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:25,629 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:25,657 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:27,229 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:27,269 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:27,274 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:27,274 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:27,274 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:01:27,274 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:01:27,275 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_196 Int) (v_xor_~res~0_BEFORE_RETURN_27 Int) (v_xor_~res~0_BEFORE_RETURN_28 Int) (v_prenex_195 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_195 4294967296) main_~ret~0) (<= main_~ret~0 2147483647) (<= (mod v_prenex_195 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~0)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_27 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_27 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (<= (mod v_xor_~res~0_BEFORE_RETURN_28 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_xor_~res~0_BEFORE_RETURN_28 4294967296) main_~ret~0)))) [2019-10-06 23:01:27,280 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:27,281 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:27,281 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:27,281 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:27,283 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_prenex_223 Int) (v_xor_~res~0_BEFORE_RETURN_32 Int)) (or (and (not (< main_~i~2 99)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_32 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (not (<= (mod v_prenex_223 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_223 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296))) (and (not (< main_~i~2 99)) (= (mod v_xor_~res~0_BEFORE_RETURN_31 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_31 4294967296) 2147483647))))) (and (not (= main_~ret~0 main_~ret5~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_prenex_223 Int) (v_xor_~res~0_BEFORE_RETURN_32 Int)) (or (and (not (< main_~i~2 99)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_32 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_32 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (not (<= (mod v_prenex_223 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_223 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296))) (and (not (< main_~i~2 99)) (= (mod v_xor_~res~0_BEFORE_RETURN_31 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_31 4294967296) 2147483647)))))) [2019-10-06 23:01:27,283 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:27,283 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:27,284 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:27,284 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:27,284 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:27,284 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:01:27,284 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_xor_~res~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (= |main_#t~ret5| (mod v_prenex_195 4294967296)) (not (< main_~i~1 100)) (<= (mod v_prenex_195 4294967296) 2147483647)) (and (= (+ (mod v_xor_~res~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_27 4294967296) 2147483647)) (not (< main_~i~1 100))))) (exists ((v_prenex_196 Int) (v_xor_~res~0_BEFORE_RETURN_28 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (<= (mod v_xor_~res~0_BEFORE_RETURN_28 4294967296) 2147483647) (= (mod v_xor_~res~0_BEFORE_RETURN_28 4294967296) |main_#t~ret5|))))) [2019-10-06 23:01:27,285 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:27,285 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:27,285 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:27,285 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:27,676 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:27,676 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-06 23:01:27,677 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-06 23:01:27,678 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-06 23:01:27,678 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-06 23:01:27,678 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-06 23:01:28,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:28,632 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-06 23:01:28,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-06 23:01:28,632 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-06 23:01:28,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:28,633 INFO L225 Difference]: With dead ends: 44 [2019-10-06 23:01:28,633 INFO L226 Difference]: Without dead ends: 29 [2019-10-06 23:01:28,634 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-06 23:01:28,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-06 23:01:28,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-06 23:01:28,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-06 23:01:28,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-06 23:01:28,641 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-06 23:01:28,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:28,641 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-06 23:01:28,642 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-06 23:01:28,642 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-06 23:01:28,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-06 23:01:28,643 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:28,643 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:28,848 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:28,849 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:28,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:28,850 INFO L82 PathProgramCache]: Analyzing trace with hash -1028595953, now seen corresponding path program 3 times [2019-10-06 23:01:28,850 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:28,851 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:28,851 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:28,851 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:28,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:28,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:28,943 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:28,943 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:28,943 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:28,943 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:29,081 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 23:01:29,082 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:01:29,083 INFO L256 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-06 23:01:29,097 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:29,116 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:29,116 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:29,185 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:29,186 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:29,188 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:29,188 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:29,189 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:29,189 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:29,189 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:29,208 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:30,576 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:30,600 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:30,603 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:30,603 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:30,603 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:01:30,603 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:01:30,604 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_xor_~res~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int) (v_xor_~res~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= (mod v_xor_~res~0_BEFORE_RETURN_54 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_54 4294967296) 2147483647)) (and (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_53 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= (mod v_prenex_389 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= main_~ret~0 2147483647)))) [2019-10-06 23:01:30,604 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:30,604 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:30,604 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:30,604 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:30,605 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_57 Int) (v_xor_~res~0_BEFORE_RETURN_58 Int) (v_prenex_417 Int) (v_prenex_418 Int)) (or (and (<= (mod v_xor_~res~0_BEFORE_RETURN_58 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_58 4294967296))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= (mod v_prenex_417 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_57 4294967296) (- 4294967296))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_57 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)))))) (and (not (= main_~ret~0 main_~ret5~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_57 Int) (v_xor_~res~0_BEFORE_RETURN_58 Int) (v_prenex_417 Int) (v_prenex_418 Int)) (or (and (<= (mod v_xor_~res~0_BEFORE_RETURN_58 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_58 4294967296))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= (mod v_prenex_417 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_417 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_57 4294967296) (- 4294967296))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_57 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 23:01:30,605 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:30,605 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:30,605 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:30,605 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:30,606 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:30,606 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:01:30,606 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_xor_~res~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_prenex_389 4294967296) 2147483647) (= (mod v_prenex_389 4294967296) |main_#t~ret5|)) (and (= |main_#t~ret5| (+ (mod v_xor_~res~0_BEFORE_RETURN_53 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_53 4294967296) 2147483647))))) (exists ((v_xor_~res~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 100)) (= (mod v_xor_~res~0_BEFORE_RETURN_54 4294967296) |main_#t~ret5|) (<= (mod v_xor_~res~0_BEFORE_RETURN_54 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_prenex_390 4294967296) (- 4294967296))))))) [2019-10-06 23:01:30,606 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:30,606 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:30,606 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:30,607 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:30,936 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:30,936 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-06 23:01:30,938 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-06 23:01:30,938 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-06 23:01:30,939 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-06 23:01:30,939 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-06 23:01:32,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:32,078 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-06 23:01:32,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-06 23:01:32,078 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-06 23:01:32,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:32,080 INFO L225 Difference]: With dead ends: 54 [2019-10-06 23:01:32,080 INFO L226 Difference]: Without dead ends: 36 [2019-10-06 23:01:32,082 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-06 23:01:32,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-06 23:01:32,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-06 23:01:32,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-06 23:01:32,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-06 23:01:32,090 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-06 23:01:32,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:32,090 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-06 23:01:32,090 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-06 23:01:32,090 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-06 23:01:32,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-06 23:01:32,092 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:32,092 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:32,298 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:32,299 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:32,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:32,300 INFO L82 PathProgramCache]: Analyzing trace with hash -500498258, now seen corresponding path program 4 times [2019-10-06 23:01:32,300 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:32,300 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:32,301 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:32,301 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:32,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:32,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:32,493 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:32,493 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:32,494 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:32,494 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:32,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:32,636 INFO L256 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-06 23:01:32,639 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:32,667 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:32,668 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:32,908 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:32,909 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:32,910 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:32,911 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:32,911 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:32,911 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:32,911 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:32,932 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:34,378 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:34,411 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:34,415 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:34,415 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:34,416 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:01:34,416 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:01:34,417 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_xor_~res~0_BEFORE_RETURN_79 Int) (v_prenex_583 Int) (v_prenex_584 Int) (v_xor_~res~0_BEFORE_RETURN_80 Int)) (or (and (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_79 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_prenex_584 4294967296) main_~ret~0) (<= (mod v_prenex_584 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (<= (mod v_prenex_583 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_583 4294967296)) (<= main_~ret~0 2147483647)))) [2019-10-06 23:01:34,417 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:34,417 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:34,418 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:34,418 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:34,418 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_xor_~res~0_BEFORE_RETURN_83 Int) (v_xor_~res~0_BEFORE_RETURN_84 Int)) (or (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_84 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_84 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_612 4294967296) 2147483647) (= (mod v_prenex_612 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_83 4294967296)) (not (< main_~i~2 99)) (<= (mod v_xor_~res~0_BEFORE_RETURN_83 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (not (<= (mod v_prenex_611 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_611 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)))))) (and (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_xor_~res~0_BEFORE_RETURN_83 Int) (v_xor_~res~0_BEFORE_RETURN_84 Int)) (or (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_84 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_84 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_612 4294967296) 2147483647) (= (mod v_prenex_612 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_83 4294967296)) (not (< main_~i~2 99)) (<= (mod v_xor_~res~0_BEFORE_RETURN_83 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (not (<= (mod v_prenex_611 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_611 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 23:01:34,419 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:34,419 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:34,419 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:34,420 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:34,420 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:34,420 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:01:34,421 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_xor_~res~0_BEFORE_RETURN_79 Int) (v_prenex_583 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_79 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_xor_~res~0_BEFORE_RETURN_79 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (= (mod v_prenex_583 4294967296) |main_#t~ret5|) (<= (mod v_prenex_583 4294967296) 2147483647)))) (exists ((v_prenex_584 Int) (v_xor_~res~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 100)) (= (mod v_prenex_584 4294967296) |main_#t~ret5|) (<= (mod v_prenex_584 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_xor_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296))))))) [2019-10-06 23:01:34,421 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:34,421 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:34,422 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:34,422 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:35,099 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:35,100 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-06 23:01:35,101 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-06 23:01:35,102 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-06 23:01:35,105 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-06 23:01:35,105 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 40 states. [2019-10-06 23:01:36,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:36,606 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-06 23:01:36,606 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-06 23:01:36,606 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 49 [2019-10-06 23:01:36,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:36,608 INFO L225 Difference]: With dead ends: 68 [2019-10-06 23:01:36,608 INFO L226 Difference]: Without dead ends: 50 [2019-10-06 23:01:36,613 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-06 23:01:36,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-06 23:01:36,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-06 23:01:36,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-06 23:01:36,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-06 23:01:36,622 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-06 23:01:36,623 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:36,623 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-06 23:01:36,623 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-06 23:01:36,623 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-06 23:01:36,624 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-06 23:01:36,624 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:36,625 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:36,828 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:36,828 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:36,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:36,828 INFO L82 PathProgramCache]: Analyzing trace with hash 1795685774, now seen corresponding path program 5 times [2019-10-06 23:01:36,829 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:36,829 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:36,829 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:36,829 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:36,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:36,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:37,284 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:37,284 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:37,285 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:37,285 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:37,445 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 23:01:37,446 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:01:37,447 INFO L256 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 23:01:37,450 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:37,504 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-06 23:01:37,504 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:37,576 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-06 23:01:37,576 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:37,577 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:37,578 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:37,578 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:37,578 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:37,578 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:37,596 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:38,860 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:38,881 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:38,884 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:38,885 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:38,885 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:01:38,885 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:01:38,886 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_xor_~res~0_BEFORE_RETURN_105 Int) (v_prenex_777 Int) (v_xor_~res~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (<= (mod v_prenex_777 4294967296) 2147483647) (not (< main_~i~1 100)) (= main_~ret~0 (mod v_prenex_777 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_106 4294967296) 2147483647) (not (< main_~i~1 100)) (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_106 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_105 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_105 4294967296) (- 4294967296)))))) [2019-10-06 23:01:38,886 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:38,886 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:38,886 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:38,887 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:38,887 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_xor_~res~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_xor_~res~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (not (< main_~i~2 99)) (not (<= (mod v_prenex_806 4294967296) 2147483647)) (= (+ (mod v_prenex_806 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_prenex_805 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_109 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_109 4294967296) 2147483647))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_110 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_xor_~res~0_BEFORE_RETURN_110 4294967296) main_~ret5~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_xor_~res~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (not (< main_~i~2 99)) (not (<= (mod v_prenex_806 4294967296) 2147483647)) (= (+ (mod v_prenex_806 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_prenex_805 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_109 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_109 4294967296) 2147483647))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_110 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_xor_~res~0_BEFORE_RETURN_110 4294967296) main_~ret5~0)))))) [2019-10-06 23:01:38,888 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:38,888 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 23:01:38,888 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:38,888 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:38,889 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:38,889 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:01:38,889 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_xor_~res~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (= |main_#t~ret5| (+ (mod v_prenex_778 4294967296) (- 4294967296))) (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 100))) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_106 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod v_xor_~res~0_BEFORE_RETURN_106 4294967296) |main_#t~ret5|)))) (exists ((v_xor_~res~0_BEFORE_RETURN_105 Int) (v_prenex_777 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_105 4294967296) 2147483647)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_105 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (<= (mod v_prenex_777 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod v_prenex_777 4294967296) |main_#t~ret5|))))) [2019-10-06 23:01:38,890 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:38,890 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:38,890 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:38,890 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:39,522 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:39,522 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-06 23:01:39,524 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-06 23:01:39,524 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-06 23:01:39,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-06 23:01:39,526 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 44 states. [2019-10-06 23:01:41,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:41,769 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-06 23:01:41,769 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-06 23:01:41,769 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 63 [2019-10-06 23:01:41,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:41,771 INFO L225 Difference]: With dead ends: 72 [2019-10-06 23:01:41,771 INFO L226 Difference]: Without dead ends: 54 [2019-10-06 23:01:41,773 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1350 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1349, Invalid=5457, Unknown=0, NotChecked=0, Total=6806 [2019-10-06 23:01:41,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-06 23:01:41,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-06 23:01:41,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-06 23:01:41,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-06 23:01:41,788 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-06 23:01:41,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:41,788 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-06 23:01:41,788 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-06 23:01:41,789 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-06 23:01:41,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-06 23:01:41,790 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:41,790 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:41,993 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:41,994 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:41,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:41,995 INFO L82 PathProgramCache]: Analyzing trace with hash -344788902, now seen corresponding path program 6 times [2019-10-06 23:01:41,995 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:41,995 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:41,996 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:41,996 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:41,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:42,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:42,405 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:01:42,406 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:42,406 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:42,406 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:42,613 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 23:01:42,613 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:01:42,615 INFO L256 TraceCheckSpWp]: Trace formula consists of 331 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-06 23:01:42,617 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:42,634 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:01:42,634 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:43,555 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:01:43,556 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:43,557 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:43,557 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:43,558 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:43,558 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:43,558 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:43,579 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:44,865 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:44,884 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:44,887 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:44,887 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:44,887 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:01:44,887 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:01:44,888 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_xor_~res~0_BEFORE_RETURN_132 Int) (v_xor_~res~0_BEFORE_RETURN_131 Int)) (or (and (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_131 4294967296)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_131 4294967296) 2147483647)) (and (= main_~ret~0 (mod v_prenex_972 4294967296)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_972 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_132 4294967296) 2147483647)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)))) [2019-10-06 23:01:44,888 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:44,888 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:44,888 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:44,888 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:44,889 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_1000 Int) (v_xor_~res~0_BEFORE_RETURN_136 Int) (v_prenex_999 Int) (v_xor_~res~0_BEFORE_RETURN_135 Int)) (or (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (not (<= (mod v_prenex_999 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_999 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_1000 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0)) (and (= (mod v_xor_~res~0_BEFORE_RETURN_135 4294967296) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_135 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret2~0))) (and (exists ((v_prenex_1000 Int) (v_xor_~res~0_BEFORE_RETURN_136 Int) (v_prenex_999 Int) (v_xor_~res~0_BEFORE_RETURN_135 Int)) (or (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (not (<= (mod v_prenex_999 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_999 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_1000 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0)) (and (= (mod v_xor_~res~0_BEFORE_RETURN_135 4294967296) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_135 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 23:01:44,889 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:44,889 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:44,889 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:44,890 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:44,890 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:44,890 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:01:44,890 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_972 Int) (v_xor_~res~0_BEFORE_RETURN_132 Int)) (or (and (not (< main_~i~1 100)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_132 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= (mod v_prenex_972 4294967296) |main_#t~ret5|) (<= (mod v_prenex_972 4294967296) 2147483647)))) (exists ((v_prenex_971 Int) (v_xor_~res~0_BEFORE_RETURN_131 Int)) (or (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 100)) (= |main_#t~ret5| (+ (mod v_prenex_971 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (= |main_#t~ret5| (mod v_xor_~res~0_BEFORE_RETURN_131 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_131 4294967296) 2147483647))))) [2019-10-06 23:01:44,891 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:44,891 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:44,891 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:44,891 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:45,384 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:45,385 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-06 23:01:45,386 INFO L442 AbstractCegarLoop]: Interpolant automaton has 70 states [2019-10-06 23:01:45,387 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2019-10-06 23:01:45,388 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1740, Invalid=3090, Unknown=0, NotChecked=0, Total=4830 [2019-10-06 23:01:45,389 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 70 states. [2019-10-06 23:01:48,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:48,835 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-06 23:01:48,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2019-10-06 23:01:48,835 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 67 [2019-10-06 23:01:48,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:48,836 INFO L225 Difference]: With dead ends: 104 [2019-10-06 23:01:48,837 INFO L226 Difference]: Without dead ends: 83 [2019-10-06 23:01:48,841 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3929 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=5099, Invalid=12723, Unknown=0, NotChecked=0, Total=17822 [2019-10-06 23:01:48,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-06 23:01:48,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-06 23:01:48,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-06 23:01:48,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-06 23:01:48,851 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-06 23:01:48,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:48,852 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-06 23:01:48,852 INFO L463 AbstractCegarLoop]: Interpolant automaton has 70 states. [2019-10-06 23:01:48,852 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-06 23:01:48,854 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-06 23:01:48,854 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:48,854 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:49,064 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:49,064 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:49,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:49,065 INFO L82 PathProgramCache]: Analyzing trace with hash -303923653, now seen corresponding path program 7 times [2019-10-06 23:01:49,065 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:49,065 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:49,065 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:49,065 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:49,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:49,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:50,531 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:01:50,531 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:50,531 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:50,531 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:50,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:50,810 INFO L256 TraceCheckSpWp]: Trace formula consists of 505 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-06 23:01:50,813 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:50,843 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:01:50,843 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:53,937 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:01:53,937 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:53,938 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:53,938 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:53,939 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:53,939 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:53,939 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:53,957 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:55,099 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:55,138 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:55,140 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:55,141 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:55,141 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:01:55,141 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:01:55,141 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_prenex_1166 Int) (v_prenex_1165 Int) (v_xor_~res~0_BEFORE_RETURN_158 Int) (v_xor_~res~0_BEFORE_RETURN_157 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_xor_~res~0_BEFORE_RETURN_158 4294967296) 2147483647) (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_158 4294967296)) (<= main_~ret~0 2147483647)) (and (= (mod v_xor_~res~0_BEFORE_RETURN_157 4294967296) main_~ret~0) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_xor_~res~0_BEFORE_RETURN_157 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1166 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1166 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1165 4294967296) 2147483647))))) (exists ((v_prenex_1166 Int) (v_prenex_1165 Int) (v_xor_~res~0_BEFORE_RETURN_158 Int) (v_xor_~res~0_BEFORE_RETURN_157 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_158 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_158 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (= (mod v_xor_~res~0_BEFORE_RETURN_157 4294967296) main_~ret~0) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_xor_~res~0_BEFORE_RETURN_157 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1166 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1166 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1165 4294967296) 2147483647)))))) [2019-10-06 23:01:55,141 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:55,142 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:55,142 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:55,142 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:55,142 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_161 Int) (v_xor_~res~0_BEFORE_RETURN_162 Int) (v_prenex_1194 Int) (v_prenex_1193 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_161 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (<= (mod v_prenex_1193 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)))))) (and (not (= main_~ret~0 main_~ret5~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_161 Int) (v_xor_~res~0_BEFORE_RETURN_162 Int) (v_prenex_1194 Int) (v_prenex_1193 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_161 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (<= (mod v_prenex_1193 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= (mod v_prenex_1194 4294967296) 2147483647) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_1194 4294967296))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (<= main_~ret5~0 2147483647) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 23:01:55,142 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:55,143 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:55,143 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:55,143 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:55,143 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:55,143 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:01:55,143 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1165 Int) (v_xor_~res~0_BEFORE_RETURN_157 Int)) (or (and (not (< main_~i~1 100)) (= |main_#t~ret5| (+ (mod v_prenex_1165 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1165 4294967296) 2147483647))) (and (= (mod v_xor_~res~0_BEFORE_RETURN_157 4294967296) |main_#t~ret5|) (not (< main_~i~1 100)) (<= (mod v_xor_~res~0_BEFORE_RETURN_157 4294967296) 2147483647)))) (exists ((v_prenex_1166 Int) (v_xor_~res~0_BEFORE_RETURN_158 Int)) (or (and (= (+ (mod v_prenex_1166 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 100)) (not (<= (mod v_prenex_1166 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= |main_#t~ret5| (mod v_xor_~res~0_BEFORE_RETURN_158 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_158 4294967296) 2147483647))))) [2019-10-06 23:01:55,144 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:55,144 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:55,144 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:55,144 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:55,904 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:55,905 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 113 [2019-10-06 23:01:55,906 INFO L442 AbstractCegarLoop]: Interpolant automaton has 114 states [2019-10-06 23:01:55,907 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 114 interpolants. [2019-10-06 23:01:55,910 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5282, Invalid=7600, Unknown=0, NotChecked=0, Total=12882 [2019-10-06 23:01:55,910 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 114 states. [2019-10-06 23:02:03,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:02:03,967 INFO L93 Difference]: Finished difference Result 148 states and 199 transitions. [2019-10-06 23:02:03,967 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 113 states. [2019-10-06 23:02:03,968 INFO L78 Accepts]: Start accepts. Automaton has 114 states. Word has length 96 [2019-10-06 23:02:03,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:02:03,970 INFO L225 Difference]: With dead ends: 148 [2019-10-06 23:02:03,970 INFO L226 Difference]: Without dead ends: 127 [2019-10-06 23:02:03,976 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 457 GetRequests, 223 SyntacticMatches, 14 SemanticMatches, 220 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9999 ImplicationChecksByTransitivity, 12.6s TimeCoverageRelationStatistics Valid=15637, Invalid=33425, Unknown=0, NotChecked=0, Total=49062 [2019-10-06 23:02:03,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2019-10-06 23:02:03,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 127. [2019-10-06 23:02:03,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127 states. [2019-10-06 23:02:03,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 131 transitions. [2019-10-06 23:02:03,990 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 131 transitions. Word has length 96 [2019-10-06 23:02:03,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:02:03,990 INFO L462 AbstractCegarLoop]: Abstraction has 127 states and 131 transitions. [2019-10-06 23:02:03,990 INFO L463 AbstractCegarLoop]: Interpolant automaton has 114 states. [2019-10-06 23:02:03,990 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 131 transitions. [2019-10-06 23:02:03,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-10-06 23:02:03,992 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:02:03,993 INFO L385 BasicCegarLoop]: trace histogram [100, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:02:04,197 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:04,198 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:02:04,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:02:04,199 INFO L82 PathProgramCache]: Analyzing trace with hash 2128098171, now seen corresponding path program 8 times [2019-10-06 23:02:04,199 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:02:04,199 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:04,200 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:04,200 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:04,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:02:04,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:02:04,411 INFO L134 CoverageAnalysis]: Checked inductivity of 5171 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 5161 trivial. 0 not checked. [2019-10-06 23:02:04,412 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:04,412 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:02:04,412 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:04,651 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 23:02:04,651 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:02:04,652 INFO L256 TraceCheckSpWp]: Trace formula consists of 141 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 23:02:04,657 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:02:04,709 INFO L134 CoverageAnalysis]: Checked inductivity of 5171 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 5109 trivial. 0 not checked. [2019-10-06 23:02:04,710 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:02:04,791 INFO L134 CoverageAnalysis]: Checked inductivity of 5171 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 5109 trivial. 0 not checked. [2019-10-06 23:02:04,791 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:02:04,794 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:02:04,794 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:02:04,795 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:02:04,795 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:02:04,795 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:02:04,806 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:02:06,083 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:02:06,105 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:02:06,107 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:02:06,108 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:02:06,108 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:02:06,108 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:02:06,108 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_1359 Int) (v_xor_~res~0_BEFORE_RETURN_183 Int) (v_xor_~res~0_BEFORE_RETURN_184 Int) (v_prenex_1360 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_1360 4294967296)) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1360 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)) main_~ret~0) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_183 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_184 4294967296) 2147483647)) (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_184 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (= main_~ret~0 (mod v_prenex_1359 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1359 4294967296) 2147483647)))) [2019-10-06 23:02:06,108 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:02:06,108 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:02:06,109 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:02:06,109 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:02:06,109 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_xor_~res~0_BEFORE_RETURN_187 Int) (v_xor_~res~0_BEFORE_RETURN_188 Int)) (or (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_187 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_188 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= (mod v_prenex_1388 4294967296) 2147483647)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_xor_~res~0_BEFORE_RETURN_187 Int) (v_xor_~res~0_BEFORE_RETURN_188 Int)) (or (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_187 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_188 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= (mod v_prenex_1388 4294967296) 2147483647)))))) [2019-10-06 23:02:06,109 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:06,109 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:06,110 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:06,110 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:02:06,110 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:02:06,110 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:02:06,110 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_xor_~res~0_BEFORE_RETURN_184 Int) (v_prenex_1360 Int)) (or (and (= (mod v_prenex_1360 4294967296) |main_#t~ret5|) (not (< main_~i~1 100)) (<= (mod v_prenex_1360 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_184 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_184 4294967296) 2147483647))))) (exists ((v_prenex_1359 Int) (v_xor_~res~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 100)) (= (mod v_prenex_1359 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1359 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_183 4294967296) 2147483647)))))) [2019-10-06 23:02:06,110 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:02:06,110 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:02:06,111 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:02:06,111 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:02:06,436 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:02:06,436 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 11] total 27 [2019-10-06 23:02:06,437 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-10-06 23:02:06,438 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-10-06 23:02:06,438 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=641, Unknown=0, NotChecked=0, Total=756 [2019-10-06 23:02:06,438 INFO L87 Difference]: Start difference. First operand 127 states and 131 transitions. Second operand 28 states. [2019-10-06 23:02:07,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:02:07,558 INFO L93 Difference]: Finished difference Result 154 states and 170 transitions. [2019-10-06 23:02:07,558 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-10-06 23:02:07,558 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 140 [2019-10-06 23:02:07,559 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:02:07,561 INFO L225 Difference]: With dead ends: 154 [2019-10-06 23:02:07,561 INFO L226 Difference]: Without dead ends: 134 [2019-10-06 23:02:07,562 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 449 GetRequests, 400 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 581 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=409, Invalid=2141, Unknown=0, NotChecked=0, Total=2550 [2019-10-06 23:02:07,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2019-10-06 23:02:07,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2019-10-06 23:02:07,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2019-10-06 23:02:07,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 138 transitions. [2019-10-06 23:02:07,579 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 138 transitions. Word has length 140 [2019-10-06 23:02:07,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:02:07,580 INFO L462 AbstractCegarLoop]: Abstraction has 134 states and 138 transitions. [2019-10-06 23:02:07,580 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-10-06 23:02:07,580 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 138 transitions. [2019-10-06 23:02:07,582 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2019-10-06 23:02:07,582 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:02:07,582 INFO L385 BasicCegarLoop]: trace histogram [100, 30, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:02:07,786 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:07,786 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:02:07,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:02:07,786 INFO L82 PathProgramCache]: Analyzing trace with hash 477729134, now seen corresponding path program 9 times [2019-10-06 23:02:07,787 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:02:07,787 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:07,787 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:07,788 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:07,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:02:07,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:02:08,096 INFO L134 CoverageAnalysis]: Checked inductivity of 5599 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 5300 trivial. 0 not checked. [2019-10-06 23:02:08,097 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:08,097 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:02:08,097 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:08,515 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 23:02:08,515 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:02:08,518 INFO L256 TraceCheckSpWp]: Trace formula consists of 827 conjuncts, 12 conjunts are in the unsatisfiable core [2019-10-06 23:02:08,522 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:02:08,549 INFO L134 CoverageAnalysis]: Checked inductivity of 5599 backedges. 244 proven. 55 refuted. 0 times theorem prover too weak. 5300 trivial. 0 not checked. [2019-10-06 23:02:08,550 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:02:08,744 INFO L134 CoverageAnalysis]: Checked inductivity of 5599 backedges. 0 proven. 299 refuted. 0 times theorem prover too weak. 5300 trivial. 0 not checked. [2019-10-06 23:02:08,744 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:02:08,746 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:02:08,746 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:02:08,746 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:02:08,747 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:02:08,747 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:02:08,762 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:02:09,862 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:02:09,885 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:02:09,888 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:02:09,888 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:02:09,888 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:02:09,889 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:02:09,889 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_1554 Int) (v_prenex_1553 Int) (v_xor_~res~0_BEFORE_RETURN_209 Int) (v_xor_~res~0_BEFORE_RETURN_210 Int)) (or (and (<= (mod v_xor_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_xor_~res~0_BEFORE_RETURN_210 4294967296) main_~ret~0) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= (mod v_xor_~res~0_BEFORE_RETURN_209 4294967296) main_~ret~0) (<= (mod v_xor_~res~0_BEFORE_RETURN_209 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_prenex_1553 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (not (<= (mod v_prenex_1553 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)) (<= main_~ret~0 2147483647)))) [2019-10-06 23:02:09,889 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:02:09,889 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:02:09,889 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:02:09,890 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:02:09,890 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_xor_~res~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int) (v_xor_~res~0_BEFORE_RETURN_213 Int)) (or (and (not (< main_~i~2 99)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_213 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_213 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_214 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_214 4294967296) (- 4294967296)) main_~ret5~0)) (and (<= (mod v_prenex_1582 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (mod v_prenex_1581 4294967296)) (not (< main_~i~2 99)) (<= (mod v_prenex_1581 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (exists ((v_xor_~res~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int) (v_xor_~res~0_BEFORE_RETURN_213 Int)) (or (and (not (< main_~i~2 99)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_213 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_213 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_214 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_214 4294967296) (- 4294967296)) main_~ret5~0)) (and (<= (mod v_prenex_1582 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (mod v_prenex_1581 4294967296)) (not (< main_~i~2 99)) (<= (mod v_prenex_1581 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret2~0)))) [2019-10-06 23:02:09,890 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:09,890 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 23:02:09,890 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:09,891 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:02:09,891 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:02:09,891 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:02:09,891 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1553 Int) (v_xor_~res~0_BEFORE_RETURN_209 Int)) (or (and (not (< main_~i~1 100)) (= (mod v_xor_~res~0_BEFORE_RETURN_209 4294967296) |main_#t~ret5|) (<= (mod v_xor_~res~0_BEFORE_RETURN_209 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_1553 4294967296) 2147483647)) (= (+ (mod v_prenex_1553 4294967296) (- 4294967296)) |main_#t~ret5|)))) (exists ((v_prenex_1554 Int) (v_xor_~res~0_BEFORE_RETURN_210 Int)) (or (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_1554 4294967296) 2147483647))) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod v_xor_~res~0_BEFORE_RETURN_210 4294967296) |main_#t~ret5|))))) [2019-10-06 23:02:09,891 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:02:09,891 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:02:09,892 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:02:09,892 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:02:10,279 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:02:10,280 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 11] total 35 [2019-10-06 23:02:10,281 INFO L442 AbstractCegarLoop]: Interpolant automaton has 36 states [2019-10-06 23:02:10,282 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2019-10-06 23:02:10,282 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=330, Invalid=930, Unknown=0, NotChecked=0, Total=1260 [2019-10-06 23:02:10,282 INFO L87 Difference]: Start difference. First operand 134 states and 138 transitions. Second operand 36 states. [2019-10-06 23:02:11,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:02:11,856 INFO L93 Difference]: Finished difference Result 173 states and 194 transitions. [2019-10-06 23:02:11,856 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-10-06 23:02:11,856 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 159 [2019-10-06 23:02:11,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:02:11,857 INFO L225 Difference]: With dead ends: 173 [2019-10-06 23:02:11,858 INFO L226 Difference]: Without dead ends: 146 [2019-10-06 23:02:11,859 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 519 GetRequests, 455 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1043 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1067, Invalid=3223, Unknown=0, NotChecked=0, Total=4290 [2019-10-06 23:02:11,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2019-10-06 23:02:11,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2019-10-06 23:02:11,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2019-10-06 23:02:11,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 150 transitions. [2019-10-06 23:02:11,874 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 150 transitions. Word has length 159 [2019-10-06 23:02:11,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:02:11,875 INFO L462 AbstractCegarLoop]: Abstraction has 146 states and 150 transitions. [2019-10-06 23:02:11,875 INFO L463 AbstractCegarLoop]: Interpolant automaton has 36 states. [2019-10-06 23:02:11,875 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 150 transitions. [2019-10-06 23:02:11,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2019-10-06 23:02:11,877 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:02:11,877 INFO L385 BasicCegarLoop]: trace histogram [100, 66, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:02:12,082 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:12,083 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:02:12,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:02:12,083 INFO L82 PathProgramCache]: Analyzing trace with hash 241860974, now seen corresponding path program 10 times [2019-10-06 23:02:12,084 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:02:12,084 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:12,084 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:12,084 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:12,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:02:12,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:02:12,565 INFO L134 CoverageAnalysis]: Checked inductivity of 7417 backedges. 530 proven. 783 refuted. 0 times theorem prover too weak. 6104 trivial. 0 not checked. [2019-10-06 23:02:12,565 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:12,565 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:02:12,566 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:12,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:02:12,990 INFO L256 TraceCheckSpWp]: Trace formula consists of 935 conjuncts, 24 conjunts are in the unsatisfiable core [2019-10-06 23:02:12,994 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:02:13,038 INFO L134 CoverageAnalysis]: Checked inductivity of 7417 backedges. 1060 proven. 253 refuted. 0 times theorem prover too weak. 6104 trivial. 0 not checked. [2019-10-06 23:02:13,039 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:02:13,735 INFO L134 CoverageAnalysis]: Checked inductivity of 7417 backedges. 0 proven. 1313 refuted. 0 times theorem prover too weak. 6104 trivial. 0 not checked. [2019-10-06 23:02:13,736 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:02:13,737 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:02:13,737 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:02:13,737 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:02:13,737 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:02:13,737 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:02:13,748 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:02:15,031 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:02:15,054 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:02:15,057 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:02:15,057 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:02:15,058 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:02:15,058 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:02:15,058 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_xor_~res~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int) (v_xor_~res~0_BEFORE_RETURN_235 Int) (v_prenex_1747 Int)) (or (and (not (< main_~i~1 100)) (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_235 4294967296) (- 4294967296))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_235 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_236 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_236 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1748 4294967296) 2147483647) (<= main_~ret~0 2147483647) (= (mod v_prenex_1748 4294967296) main_~ret~0)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1747 4294967296) 2147483647) (= main_~ret~0 (mod v_prenex_1747 4294967296)) (<= main_~ret~0 2147483647)))) (exists ((v_xor_~res~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int) (v_xor_~res~0_BEFORE_RETURN_235 Int) (v_prenex_1747 Int)) (or (and (not (< main_~i~1 100)) (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_235 4294967296) (- 4294967296))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_235 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1748 4294967296) 2147483647) (<= main_~ret~0 2147483647) (= (mod v_prenex_1748 4294967296) main_~ret~0)) (and (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_236 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_236 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1747 4294967296) 2147483647) (= main_~ret~0 (mod v_prenex_1747 4294967296)) (<= main_~ret~0 2147483647))))) [2019-10-06 23:02:15,058 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:02:15,059 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:02:15,059 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:02:15,059 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:02:15,059 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_xor_~res~0_BEFORE_RETURN_239 Int) (v_prenex_1776 Int) (v_prenex_1775 Int) (v_xor_~res~0_BEFORE_RETURN_240 Int)) (or (and (not (< main_~i~2 99)) (not (<= (mod v_prenex_1775 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1775 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (<= (mod v_xor_~res~0_BEFORE_RETURN_239 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= (mod v_xor_~res~0_BEFORE_RETURN_239 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= (mod v_xor_~res~0_BEFORE_RETURN_240 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_240 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1776 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1776 4294967296) (- 4294967296)) main_~ret5~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_239 Int) (v_prenex_1776 Int) (v_prenex_1775 Int) (v_xor_~res~0_BEFORE_RETURN_240 Int)) (or (and (not (< main_~i~2 99)) (not (<= (mod v_prenex_1775 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1775 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (<= (mod v_xor_~res~0_BEFORE_RETURN_239 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= (mod v_xor_~res~0_BEFORE_RETURN_239 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= (mod v_xor_~res~0_BEFORE_RETURN_240 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_240 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1776 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1776 4294967296) (- 4294967296)) main_~ret5~0)))))) [2019-10-06 23:02:15,059 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:15,060 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:15,060 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:15,060 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:02:15,060 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:02:15,060 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:02:15,060 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_xor_~res~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_prenex_1748 4294967296) 2147483647) (= (mod v_prenex_1748 4294967296) |main_#t~ret5|)) (and (= (+ (mod v_xor_~res~0_BEFORE_RETURN_236 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_236 4294967296) 2147483647))))) (exists ((v_xor_~res~0_BEFORE_RETURN_235 Int) (v_prenex_1747 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_235 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_xor_~res~0_BEFORE_RETURN_235 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (= |main_#t~ret5| (mod v_prenex_1747 4294967296)) (<= (mod v_prenex_1747 4294967296) 2147483647))))) [2019-10-06 23:02:15,060 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:02:15,060 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:02:15,060 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:02:15,060 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:02:15,467 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:02:15,467 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 11] total 59 [2019-10-06 23:02:15,468 INFO L442 AbstractCegarLoop]: Interpolant automaton has 60 states [2019-10-06 23:02:15,469 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2019-10-06 23:02:15,469 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1206, Invalid=2334, Unknown=0, NotChecked=0, Total=3540 [2019-10-06 23:02:15,470 INFO L87 Difference]: Start difference. First operand 146 states and 150 transitions. Second operand 60 states. [2019-10-06 23:02:21,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:02:21,628 INFO L93 Difference]: Finished difference Result 209 states and 242 transitions. [2019-10-06 23:02:21,629 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2019-10-06 23:02:21,629 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 195 [2019-10-06 23:02:21,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:02:21,631 INFO L225 Difference]: With dead ends: 209 [2019-10-06 23:02:21,631 INFO L226 Difference]: Without dead ends: 170 [2019-10-06 23:02:21,632 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 664 GetRequests, 552 SyntacticMatches, 0 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2812 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=3791, Invalid=9090, Unknown=1, NotChecked=0, Total=12882 [2019-10-06 23:02:21,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2019-10-06 23:02:21,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 170. [2019-10-06 23:02:21,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2019-10-06 23:02:21,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 174 transitions. [2019-10-06 23:02:21,649 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 174 transitions. Word has length 195 [2019-10-06 23:02:21,649 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:02:21,649 INFO L462 AbstractCegarLoop]: Abstraction has 170 states and 174 transitions. [2019-10-06 23:02:21,650 INFO L463 AbstractCegarLoop]: Interpolant automaton has 60 states. [2019-10-06 23:02:21,650 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 174 transitions. [2019-10-06 23:02:21,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 268 [2019-10-06 23:02:21,653 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:02:21,653 INFO L385 BasicCegarLoop]: trace histogram [138, 100, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:02:21,854 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:21,854 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:02:21,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:02:21,855 INFO L82 PathProgramCache]: Analyzing trace with hash -1620024978, now seen corresponding path program 11 times [2019-10-06 23:02:21,855 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:02:21,855 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:21,855 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:21,855 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:21,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:02:21,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:02:22,978 INFO L134 CoverageAnalysis]: Checked inductivity of 14941 backedges. 2210 proven. 3291 refuted. 0 times theorem prover too weak. 9440 trivial. 0 not checked. [2019-10-06 23:02:22,979 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:22,979 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:02:22,979 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:23,365 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-10-06 23:02:23,365 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:02:23,367 INFO L256 TraceCheckSpWp]: Trace formula consists of 201 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-06 23:02:23,371 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:02:23,609 INFO L134 CoverageAnalysis]: Checked inductivity of 14941 backedges. 4422 proven. 15 refuted. 0 times theorem prover too weak. 10504 trivial. 0 not checked. [2019-10-06 23:02:23,609 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:02:23,807 INFO L134 CoverageAnalysis]: Checked inductivity of 14941 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 14926 trivial. 0 not checked. [2019-10-06 23:02:23,807 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:02:23,809 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:02:23,809 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:02:23,809 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:02:23,809 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:02:23,810 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:02:23,833 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:02:24,961 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:02:24,980 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:02:24,983 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:02:24,983 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:02:24,983 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:02:24,983 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:02:24,983 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_xor_~res~0_BEFORE_RETURN_262 Int) (v_xor_~res~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_262 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_262 4294967296) (- 4294967296)) main_~ret~0)) (and (not (< main_~i~1 100)) (= (mod v_prenex_1942 4294967296) main_~ret~0) (<= (mod v_prenex_1942 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_prenex_1941 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_261 4294967296)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_261 4294967296) 2147483647)))) (exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_xor_~res~0_BEFORE_RETURN_262 Int) (v_xor_~res~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_262 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_262 4294967296) (- 4294967296)) main_~ret~0)) (and (= main_~ret~0 (+ (mod v_prenex_1941 4294967296) (- 4294967296))) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= (mod v_prenex_1942 4294967296) 2147483647) (= (mod v_prenex_1942 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_261 4294967296)) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_261 4294967296) 2147483647))))) [2019-10-06 23:02:24,984 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:02:24,984 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:02:24,984 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:02:24,984 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:02:24,984 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_1970 Int) (v_prenex_1969 Int) (v_xor_~res~0_BEFORE_RETURN_266 Int) (v_xor_~res~0_BEFORE_RETURN_265 Int)) (or (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_265 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_265 4294967296))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_prenex_1969 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_prenex_1969 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (<= (mod v_xor_~res~0_BEFORE_RETURN_266 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_266 4294967296))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_1970 Int) (v_prenex_1969 Int) (v_xor_~res~0_BEFORE_RETURN_266 Int) (v_xor_~res~0_BEFORE_RETURN_265 Int)) (or (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_265 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_265 4294967296))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (+ (mod v_prenex_1969 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_prenex_1969 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (<= (mod v_xor_~res~0_BEFORE_RETURN_266 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_266 4294967296))))))) [2019-10-06 23:02:24,985 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:24,985 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:24,985 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:24,985 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:02:24,985 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:02:24,985 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:02:24,985 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1941 Int) (v_xor_~res~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (= (+ (mod v_prenex_1941 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (= |main_#t~ret5| (mod v_xor_~res~0_BEFORE_RETURN_261 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_261 4294967296) 2147483647)))) (exists ((v_prenex_1942 Int) (v_xor_~res~0_BEFORE_RETURN_262 Int)) (or (and (not (< main_~i~1 100)) (= |main_#t~ret5| (mod v_prenex_1942 4294967296)) (<= (mod v_prenex_1942 4294967296) 2147483647)) (and (= (+ (mod v_xor_~res~0_BEFORE_RETURN_262 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 100)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_262 4294967296) 2147483647)))))) [2019-10-06 23:02:24,986 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:02:24,986 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:02:24,986 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:02:24,986 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:02:25,674 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:02:25,675 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 8, 8, 11] total 71 [2019-10-06 23:02:25,676 INFO L442 AbstractCegarLoop]: Interpolant automaton has 72 states [2019-10-06 23:02:25,677 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2019-10-06 23:02:25,677 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1296, Invalid=3816, Unknown=0, NotChecked=0, Total=5112 [2019-10-06 23:02:25,678 INFO L87 Difference]: Start difference. First operand 170 states and 174 transitions. Second operand 72 states. [2019-10-06 23:02:30,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:02:30,905 INFO L93 Difference]: Finished difference Result 241 states and 258 transitions. [2019-10-06 23:02:30,905 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2019-10-06 23:02:30,906 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 267 [2019-10-06 23:02:30,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:02:30,908 INFO L225 Difference]: With dead ends: 241 [2019-10-06 23:02:30,908 INFO L226 Difference]: Without dead ends: 178 [2019-10-06 23:02:30,912 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 917 GetRequests, 780 SyntacticMatches, 0 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3820 ImplicationChecksByTransitivity, 6.3s TimeCoverageRelationStatistics Valid=4186, Invalid=14996, Unknown=0, NotChecked=0, Total=19182 [2019-10-06 23:02:30,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2019-10-06 23:02:30,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2019-10-06 23:02:30,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2019-10-06 23:02:30,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 182 transitions. [2019-10-06 23:02:30,928 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 182 transitions. Word has length 267 [2019-10-06 23:02:30,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:02:30,928 INFO L462 AbstractCegarLoop]: Abstraction has 178 states and 182 transitions. [2019-10-06 23:02:30,928 INFO L463 AbstractCegarLoop]: Interpolant automaton has 72 states. [2019-10-06 23:02:30,928 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 182 transitions. [2019-10-06 23:02:30,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 278 [2019-10-06 23:02:30,932 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:02:30,932 INFO L385 BasicCegarLoop]: trace histogram [141, 100, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:02:31,136 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:31,137 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:02:31,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:02:31,137 INFO L82 PathProgramCache]: Analyzing trace with hash -1125754315, now seen corresponding path program 12 times [2019-10-06 23:02:31,137 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:02:31,137 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:31,137 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:31,138 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:31,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:02:31,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:02:32,778 INFO L134 CoverageAnalysis]: Checked inductivity of 15430 backedges. 0 proven. 5738 refuted. 0 times theorem prover too weak. 9692 trivial. 0 not checked. [2019-10-06 23:02:32,778 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:32,778 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:02:32,778 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:33,341 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 23:02:33,341 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:02:33,348 INFO L256 TraceCheckSpWp]: Trace formula consists of 1188 conjuncts, 49 conjunts are in the unsatisfiable core [2019-10-06 23:02:33,354 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:02:33,474 INFO L134 CoverageAnalysis]: Checked inductivity of 15430 backedges. 4610 proven. 1128 refuted. 0 times theorem prover too weak. 9692 trivial. 0 not checked. [2019-10-06 23:02:33,474 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:02:36,042 INFO L134 CoverageAnalysis]: Checked inductivity of 15430 backedges. 0 proven. 5738 refuted. 0 times theorem prover too weak. 9692 trivial. 0 not checked. [2019-10-06 23:02:36,043 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:02:36,044 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:02:36,044 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:02:36,045 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:02:36,045 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:02:36,045 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:02:36,059 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:02:37,215 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:02:37,238 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:02:37,240 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:02:37,240 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:02:37,240 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:02:37,241 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:02:37,241 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_2135 Int) (v_prenex_2136 Int) (v_xor_~res~0_BEFORE_RETURN_288 Int) (v_xor_~res~0_BEFORE_RETURN_287 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_287 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_287 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= main_~ret~0 (mod v_prenex_2136 4294967296)) (<= (mod v_prenex_2136 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_288 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_288 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_prenex_2135 4294967296) (- 4294967296))) (not (<= (mod v_prenex_2135 4294967296) 2147483647))))) [2019-10-06 23:02:37,241 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:02:37,241 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:02:37,241 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:02:37,241 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:02:37,242 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_xor_~res~0_BEFORE_RETURN_291 Int) (v_xor_~res~0_BEFORE_RETURN_292 Int) (v_prenex_2163 Int) (v_prenex_2164 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_prenex_2164 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2164 4294967296) (- 4294967296)))) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_292 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_292 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_291 4294967296) (- 4294967296))) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_291 4294967296) 2147483647))) (and (= main_~ret5~0 (mod v_prenex_2163 4294967296)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2163 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_291 Int) (v_xor_~res~0_BEFORE_RETURN_292 Int) (v_prenex_2163 Int) (v_prenex_2164 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_prenex_2164 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2164 4294967296) (- 4294967296)))) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_292 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_292 4294967296)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_291 4294967296) (- 4294967296))) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_291 4294967296) 2147483647))) (and (= main_~ret5~0 (mod v_prenex_2163 4294967296)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2163 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))))) [2019-10-06 23:02:37,242 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:37,242 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:37,242 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:37,242 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:02:37,242 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:02:37,242 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:02:37,242 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2135 Int) (v_xor_~res~0_BEFORE_RETURN_287 Int)) (or (and (= |main_#t~ret5| (mod v_xor_~res~0_BEFORE_RETURN_287 4294967296)) (not (< main_~i~1 100)) (<= (mod v_xor_~res~0_BEFORE_RETURN_287 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (= |main_#t~ret5| (+ (mod v_prenex_2135 4294967296) (- 4294967296))) (not (<= (mod v_prenex_2135 4294967296) 2147483647))))) (exists ((v_prenex_2136 Int) (v_xor_~res~0_BEFORE_RETURN_288 Int)) (or (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_288 4294967296) 2147483647)) (not (< main_~i~1 100)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_288 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (<= (mod v_prenex_2136 4294967296) 2147483647) (= |main_#t~ret5| (mod v_prenex_2136 4294967296)))))) [2019-10-06 23:02:37,243 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:02:37,243 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:02:37,243 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:02:37,243 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:02:37,843 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:02:37,844 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50, 11] total 109 [2019-10-06 23:02:37,845 INFO L442 AbstractCegarLoop]: Interpolant automaton has 110 states [2019-10-06 23:02:37,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 110 interpolants. [2019-10-06 23:02:37,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4881, Invalid=7109, Unknown=0, NotChecked=0, Total=11990 [2019-10-06 23:02:37,847 INFO L87 Difference]: Start difference. First operand 178 states and 182 transitions. Second operand 110 states. [2019-10-06 23:02:48,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:02:48,268 INFO L93 Difference]: Finished difference Result 298 states and 356 transitions. [2019-10-06 23:02:48,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 109 states. [2019-10-06 23:02:48,269 INFO L78 Accepts]: Start accepts. Automaton has 110 states. Word has length 277 [2019-10-06 23:02:48,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:02:48,271 INFO L225 Difference]: With dead ends: 298 [2019-10-06 23:02:48,271 INFO L226 Difference]: Without dead ends: 227 [2019-10-06 23:02:48,274 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 986 GetRequests, 774 SyntacticMatches, 0 SemanticMatches, 212 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8813 ImplicationChecksByTransitivity, 14.1s TimeCoverageRelationStatistics Valid=15016, Invalid=30566, Unknown=0, NotChecked=0, Total=45582 [2019-10-06 23:02:48,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227 states. [2019-10-06 23:02:48,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227 to 227. [2019-10-06 23:02:48,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227 states. [2019-10-06 23:02:48,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 231 transitions. [2019-10-06 23:02:48,294 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 231 transitions. Word has length 277 [2019-10-06 23:02:48,295 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:02:48,295 INFO L462 AbstractCegarLoop]: Abstraction has 227 states and 231 transitions. [2019-10-06 23:02:48,295 INFO L463 AbstractCegarLoop]: Interpolant automaton has 110 states. [2019-10-06 23:02:48,295 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 231 transitions. [2019-10-06 23:02:48,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 425 [2019-10-06 23:02:48,298 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:02:48,298 INFO L385 BasicCegarLoop]: trace histogram [288, 100, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:02:48,503 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:48,503 INFO L410 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:02:48,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:02:48,504 INFO L82 PathProgramCache]: Analyzing trace with hash 522341499, now seen corresponding path program 13 times [2019-10-06 23:02:48,504 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:02:48,504 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:48,505 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:48,505 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:48,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:02:48,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:02:49,196 INFO L134 CoverageAnalysis]: Checked inductivity of 47329 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 47251 trivial. 0 not checked. [2019-10-06 23:02:49,197 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:49,197 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:02:49,198 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:49,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:02:49,824 INFO L256 TraceCheckSpWp]: Trace formula consists of 1629 conjuncts, 98 conjunts are in the unsatisfiable core [2019-10-06 23:02:49,832 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:02:53,876 INFO L134 CoverageAnalysis]: Checked inductivity of 47329 backedges. 18820 proven. 4656 refuted. 0 times theorem prover too weak. 23853 trivial. 0 not checked. [2019-10-06 23:02:53,877 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:02:57,909 INFO L134 CoverageAnalysis]: Checked inductivity of 47329 backedges. 0 proven. 23476 refuted. 0 times theorem prover too weak. 23853 trivial. 0 not checked. [2019-10-06 23:02:57,909 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:02:57,911 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:02:57,911 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:02:57,911 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:02:57,911 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:02:57,911 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:02:57,925 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:02:59,071 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:02:59,089 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:02:59,091 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:02:59,091 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:02:59,091 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:02:59,092 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:02:59,092 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_xor_~res~0_BEFORE_RETURN_314 Int) (v_xor_~res~0_BEFORE_RETURN_313 Int) (v_prenex_2330 Int) (v_prenex_2329 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_xor_~res~0_BEFORE_RETURN_313 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_313 4294967296))) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2330 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_prenex_2330 4294967296) (- 4294967296)))) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_314 4294967296) 2147483647) (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_314 4294967296))) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_2329 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_2329 4294967296) 2147483647))))) [2019-10-06 23:02:59,092 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:02:59,092 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:02:59,092 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:02:59,092 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:02:59,093 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_2358 Int) (v_xor_~res~0_BEFORE_RETURN_318 Int) (v_xor_~res~0_BEFORE_RETURN_317 Int) (v_prenex_2357 Int)) (or (and (<= (mod v_prenex_2357 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_prenex_2357 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_318 4294967296) 2147483647) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_318 4294967296))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_2358 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2358 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_317 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_317 4294967296) 2147483647)))))) (and (not (= main_~ret~0 main_~ret5~0)) (exists ((v_prenex_2358 Int) (v_xor_~res~0_BEFORE_RETURN_318 Int) (v_xor_~res~0_BEFORE_RETURN_317 Int) (v_prenex_2357 Int)) (or (and (<= (mod v_prenex_2357 4294967296) 2147483647) (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_prenex_2357 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_318 4294967296) 2147483647) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_318 4294967296))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_2358 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2358 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_317 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_317 4294967296) 2147483647))))))) [2019-10-06 23:02:59,093 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:59,093 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:59,094 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:59,094 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:02:59,094 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:02:59,094 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:02:59,095 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_xor_~res~0_BEFORE_RETURN_314 Int) (v_prenex_2330 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_2330 4294967296) 2147483647)) (= (+ (mod v_prenex_2330 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_314 4294967296) 2147483647) (not (< main_~i~1 100)) (= |main_#t~ret5| (mod v_xor_~res~0_BEFORE_RETURN_314 4294967296))))) (exists ((v_xor_~res~0_BEFORE_RETURN_313 Int) (v_prenex_2329 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_xor_~res~0_BEFORE_RETURN_313 4294967296) 2147483647) (= |main_#t~ret5| (mod v_xor_~res~0_BEFORE_RETURN_313 4294967296))) (and (= (+ (mod v_prenex_2329 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 100)) (not (<= (mod v_prenex_2329 4294967296) 2147483647)))))) [2019-10-06 23:02:59,095 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:02:59,095 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:02:59,095 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:02:59,095 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:03:00,093 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:03:00,093 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 99, 99, 11] total 124 [2019-10-06 23:03:00,095 INFO L442 AbstractCegarLoop]: Interpolant automaton has 125 states [2019-10-06 23:03:00,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 125 interpolants. [2019-10-06 23:03:00,098 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5183, Invalid=10317, Unknown=0, NotChecked=0, Total=15500 [2019-10-06 23:03:00,098 INFO L87 Difference]: Start difference. First operand 227 states and 231 transitions. Second operand 125 states. [2019-10-06 23:03:16,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:03:16,174 INFO L93 Difference]: Finished difference Result 351 states and 364 transitions. [2019-10-06 23:03:16,174 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 125 states. [2019-10-06 23:03:16,174 INFO L78 Accepts]: Start accepts. Automaton has 125 states. Word has length 424 [2019-10-06 23:03:16,175 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:03:16,177 INFO L225 Difference]: With dead ends: 351 [2019-10-06 23:03:16,177 INFO L226 Difference]: Without dead ends: 231 [2019-10-06 23:03:16,181 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1407 GetRequests, 1069 SyntacticMatches, 95 SemanticMatches, 243 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15504 ImplicationChecksByTransitivity, 23.9s TimeCoverageRelationStatistics Valid=16163, Invalid=43616, Unknown=1, NotChecked=0, Total=59780 [2019-10-06 23:03:16,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states. [2019-10-06 23:03:16,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 231. [2019-10-06 23:03:16,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 231 states. [2019-10-06 23:03:16,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231 states to 231 states and 235 transitions. [2019-10-06 23:03:16,200 INFO L78 Accepts]: Start accepts. Automaton has 231 states and 235 transitions. Word has length 424 [2019-10-06 23:03:16,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:03:16,200 INFO L462 AbstractCegarLoop]: Abstraction has 231 states and 235 transitions. [2019-10-06 23:03:16,200 INFO L463 AbstractCegarLoop]: Interpolant automaton has 125 states. [2019-10-06 23:03:16,200 INFO L276 IsEmpty]: Start isEmpty. Operand 231 states and 235 transitions. [2019-10-06 23:03:16,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 435 [2019-10-06 23:03:16,203 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:03:16,204 INFO L385 BasicCegarLoop]: trace histogram [297, 100, 13, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:03:16,409 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:03:16,409 INFO L410 AbstractCegarLoop]: === Iteration 17 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:03:16,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:03:16,410 INFO L82 PathProgramCache]: Analyzing trace with hash 758730214, now seen corresponding path program 14 times [2019-10-06 23:03:16,410 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:03:16,410 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:03:16,411 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:03:16,411 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:03:16,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:03:16,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:03:17,313 INFO L134 CoverageAnalysis]: Checked inductivity of 49997 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 49906 trivial. 0 not checked. [2019-10-06 23:03:17,314 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:03:17,314 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:03:17,318 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:03:19,063 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2019-10-06 23:03:19,063 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:03:19,066 INFO L256 TraceCheckSpWp]: Trace formula consists of 329 conjuncts, 22 conjunts are in the unsatisfiable core [2019-10-06 23:03:19,073 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:03:19,190 INFO L134 CoverageAnalysis]: Checked inductivity of 49997 backedges. 20104 proven. 91 refuted. 0 times theorem prover too weak. 29802 trivial. 0 not checked. [2019-10-06 23:03:19,190 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:03:19,757 INFO L134 CoverageAnalysis]: Checked inductivity of 49997 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 49906 trivial. 0 not checked. [2019-10-06 23:03:19,757 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:03:19,760 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:03:19,760 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:03:19,761 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:03:19,761 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:03:19,762 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:03:19,779 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:03:20,859 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:03:20,880 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:03:20,887 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:03:20,888 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:03:20,888 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:03:20,888 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:03:20,888 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_2523 Int) (v_prenex_2524 Int) (v_xor_~res~0_BEFORE_RETURN_339 Int) (v_xor_~res~0_BEFORE_RETURN_340 Int)) (or (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2523 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_prenex_2523 4294967296) (- 4294967296)))) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_2524 4294967296)) (<= (mod v_prenex_2524 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= (mod v_xor_~res~0_BEFORE_RETURN_339 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_xor_~res~0_BEFORE_RETURN_339 4294967296) main_~ret~0)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_340 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_340 4294967296) 2147483647))))) [2019-10-06 23:03:20,888 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:03:20,889 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:03:20,889 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:03:20,889 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:03:20,889 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_2552 Int) (v_prenex_2551 Int) (v_xor_~res~0_BEFORE_RETURN_343 Int) (v_xor_~res~0_BEFORE_RETURN_344 Int)) (or (and (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_344 4294967296)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_344 4294967296) 2147483647)) (and (not (<= (mod v_prenex_2551 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2551 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_prenex_2552 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2552 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_343 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_343 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)))))) (and (exists ((v_prenex_2552 Int) (v_prenex_2551 Int) (v_xor_~res~0_BEFORE_RETURN_343 Int) (v_xor_~res~0_BEFORE_RETURN_344 Int)) (or (and (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_344 4294967296)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_344 4294967296) 2147483647)) (and (not (<= (mod v_prenex_2551 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_2551 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_prenex_2552 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_2552 4294967296) (- 4294967296)))) (and (not (< main_~i~2 99)) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_343 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_343 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 23:03:20,890 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:03:20,890 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:03:20,890 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:03:20,890 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:03:20,890 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:03:20,890 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:03:20,891 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2524 Int) (v_xor_~res~0_BEFORE_RETURN_340 Int)) (or (and (not (< main_~i~1 100)) (= |main_#t~ret5| (mod v_prenex_2524 4294967296)) (<= (mod v_prenex_2524 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_340 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_340 4294967296) 2147483647))))) (exists ((v_prenex_2523 Int) (v_xor_~res~0_BEFORE_RETURN_339 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_xor_~res~0_BEFORE_RETURN_339 4294967296) 2147483647) (= (mod v_xor_~res~0_BEFORE_RETURN_339 4294967296) |main_#t~ret5|)) (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_2523 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_prenex_2523 4294967296) (- 4294967296))))))) [2019-10-06 23:03:20,891 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:03:20,891 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:03:20,891 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:03:20,891 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:03:21,488 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:03:21,489 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 17, 16, 11] total 42 [2019-10-06 23:03:21,490 INFO L442 AbstractCegarLoop]: Interpolant automaton has 43 states [2019-10-06 23:03:21,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2019-10-06 23:03:21,491 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=1310, Unknown=0, NotChecked=0, Total=1806 [2019-10-06 23:03:21,491 INFO L87 Difference]: Start difference. First operand 231 states and 235 transitions. Second operand 43 states. [2019-10-06 23:03:25,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:03:25,318 INFO L93 Difference]: Finished difference Result 353 states and 372 transitions. [2019-10-06 23:03:25,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-10-06 23:03:25,319 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 434 [2019-10-06 23:03:25,319 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:03:25,321 INFO L225 Difference]: With dead ends: 353 [2019-10-06 23:03:25,322 INFO L226 Difference]: Without dead ends: 246 [2019-10-06 23:03:25,323 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1355 GetRequests, 1277 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1450 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1545, Invalid=4775, Unknown=0, NotChecked=0, Total=6320 [2019-10-06 23:03:25,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2019-10-06 23:03:25,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 246. [2019-10-06 23:03:25,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 246 states. [2019-10-06 23:03:25,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 246 states to 246 states and 250 transitions. [2019-10-06 23:03:25,339 INFO L78 Accepts]: Start accepts. Automaton has 246 states and 250 transitions. Word has length 434 [2019-10-06 23:03:25,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:03:25,339 INFO L462 AbstractCegarLoop]: Abstraction has 246 states and 250 transitions. [2019-10-06 23:03:25,340 INFO L463 AbstractCegarLoop]: Interpolant automaton has 43 states. [2019-10-06 23:03:25,340 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 250 transitions. [2019-10-06 23:03:25,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 450 [2019-10-06 23:03:25,342 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:03:25,343 INFO L385 BasicCegarLoop]: trace histogram [297, 100, 28, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:03:25,549 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:03:25,549 INFO L410 AbstractCegarLoop]: === Iteration 18 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:03:25,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:03:25,550 INFO L82 PathProgramCache]: Analyzing trace with hash -1154481483, now seen corresponding path program 15 times [2019-10-06 23:03:25,550 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:03:25,550 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:03:25,551 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:03:25,551 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:03:25,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:03:25,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:03:26,446 INFO L134 CoverageAnalysis]: Checked inductivity of 50312 backedges. 0 proven. 406 refuted. 0 times theorem prover too weak. 49906 trivial. 0 not checked. [2019-10-06 23:03:26,446 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:03:26,446 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:03:26,446 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:03:27,110 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 23:03:27,110 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:03:27,116 INFO L256 TraceCheckSpWp]: Trace formula consists of 1720 conjuncts, 30 conjunts are in the unsatisfiable core [2019-10-06 23:03:27,122 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:03:27,235 INFO L134 CoverageAnalysis]: Checked inductivity of 50312 backedges. 20004 proven. 406 refuted. 0 times theorem prover too weak. 29902 trivial. 0 not checked. [2019-10-06 23:03:27,235 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:03:28,527 INFO L134 CoverageAnalysis]: Checked inductivity of 50312 backedges. 0 proven. 406 refuted. 0 times theorem prover too weak. 49906 trivial. 0 not checked. [2019-10-06 23:03:28,528 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:03:28,529 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:03:28,529 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:03:28,529 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:03:28,529 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:03:28,530 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:03:28,539 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:03:29,650 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:03:29,668 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:03:29,674 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:03:29,674 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:03:29,674 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:03:29,675 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:03:29,675 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_2718 Int) (v_xor_~res~0_BEFORE_RETURN_365 Int) (v_prenex_2717 Int) (v_xor_~res~0_BEFORE_RETURN_366 Int)) (or (and (not (< main_~i~1 100)) (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_365 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_xor_~res~0_BEFORE_RETURN_365 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2717 4294967296) 2147483647)) (= main_~ret~0 (+ (mod v_prenex_2717 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_2718 4294967296) 2147483647)) (= (+ (mod v_prenex_2718 4294967296) (- 4294967296)) main_~ret~0)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_366 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod v_xor_~res~0_BEFORE_RETURN_366 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-06 23:03:29,675 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:03:29,675 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:03:29,675 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:03:29,676 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:03:29,676 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_369 Int) (v_prenex_2745 Int) (v_prenex_2746 Int) (v_xor_~res~0_BEFORE_RETURN_370 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_369 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_369 4294967296) 2147483647))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2745 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_2745 4294967296) main_~ret5~0)) (and (not (< main_~i~2 99)) (= (mod v_prenex_2746 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2746 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_370 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_370 4294967296) (- 4294967296))))))) (and (exists ((v_xor_~res~0_BEFORE_RETURN_369 Int) (v_prenex_2745 Int) (v_prenex_2746 Int) (v_xor_~res~0_BEFORE_RETURN_370 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_369 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_369 4294967296) 2147483647))) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2745 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_2745 4294967296) main_~ret5~0)) (and (not (< main_~i~2 99)) (= (mod v_prenex_2746 4294967296) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_2746 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_370 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_370 4294967296) (- 4294967296)))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 23:03:29,676 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:03:29,676 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:03:29,677 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:03:29,677 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:03:29,677 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:03:29,677 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:03:29,677 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2718 Int) (v_xor_~res~0_BEFORE_RETURN_366 Int)) (or (and (not (< main_~i~1 100)) (not (<= (mod v_prenex_2718 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_prenex_2718 4294967296) (- 4294967296)))) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_366 4294967296) 2147483647) (not (< main_~i~1 100)) (= (mod v_xor_~res~0_BEFORE_RETURN_366 4294967296) |main_#t~ret5|)))) (exists ((v_xor_~res~0_BEFORE_RETURN_365 Int) (v_prenex_2717 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_xor_~res~0_BEFORE_RETURN_365 4294967296) 2147483647) (= |main_#t~ret5| (mod v_xor_~res~0_BEFORE_RETURN_365 4294967296))) (and (= (+ (mod v_prenex_2717 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 100)) (not (<= (mod v_prenex_2717 4294967296) 2147483647)))))) [2019-10-06 23:03:29,677 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:03:29,677 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:03:29,678 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:03:29,678 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:03:30,143 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:03:30,143 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31, 11] total 71 [2019-10-06 23:03:30,145 INFO L442 AbstractCegarLoop]: Interpolant automaton has 72 states [2019-10-06 23:03:30,145 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2019-10-06 23:03:30,146 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1859, Invalid=3253, Unknown=0, NotChecked=0, Total=5112 [2019-10-06 23:03:30,146 INFO L87 Difference]: Start difference. First operand 246 states and 250 transitions. Second operand 72 states. [2019-10-06 23:03:36,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:03:36,319 INFO L93 Difference]: Finished difference Result 383 states and 417 transitions. [2019-10-06 23:03:36,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2019-10-06 23:03:36,320 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 449 [2019-10-06 23:03:36,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:03:36,322 INFO L225 Difference]: With dead ends: 383 [2019-10-06 23:03:36,322 INFO L226 Difference]: Without dead ends: 276 [2019-10-06 23:03:36,324 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1444 GetRequests, 1308 SyntacticMatches, 0 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3966 ImplicationChecksByTransitivity, 5.7s TimeCoverageRelationStatistics Valid=5568, Invalid=13338, Unknown=0, NotChecked=0, Total=18906 [2019-10-06 23:03:36,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2019-10-06 23:03:36,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 276. [2019-10-06 23:03:36,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 276 states. [2019-10-06 23:03:36,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276 states to 276 states and 280 transitions. [2019-10-06 23:03:36,342 INFO L78 Accepts]: Start accepts. Automaton has 276 states and 280 transitions. Word has length 449 [2019-10-06 23:03:36,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:03:36,342 INFO L462 AbstractCegarLoop]: Abstraction has 276 states and 280 transitions. [2019-10-06 23:03:36,342 INFO L463 AbstractCegarLoop]: Interpolant automaton has 72 states. [2019-10-06 23:03:36,343 INFO L276 IsEmpty]: Start isEmpty. Operand 276 states and 280 transitions. [2019-10-06 23:03:36,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 480 [2019-10-06 23:03:36,346 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:03:36,346 INFO L385 BasicCegarLoop]: trace histogram [297, 100, 58, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:03:36,557 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:03:36,558 INFO L410 AbstractCegarLoop]: === Iteration 19 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:03:36,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:03:36,558 INFO L82 PathProgramCache]: Analyzing trace with hash -2014652779, now seen corresponding path program 16 times [2019-10-06 23:03:36,558 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:03:36,558 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:03:36,558 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:03:36,558 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:03:36,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:03:36,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:03:38,429 INFO L134 CoverageAnalysis]: Checked inductivity of 51617 backedges. 0 proven. 1711 refuted. 0 times theorem prover too weak. 49906 trivial. 0 not checked. [2019-10-06 23:03:38,429 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:03:38,429 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:03:38,429 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:03:39,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:03:39,204 INFO L256 TraceCheckSpWp]: Trace formula consists of 1840 conjuncts, 60 conjunts are in the unsatisfiable core [2019-10-06 23:03:39,211 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:03:39,314 INFO L134 CoverageAnalysis]: Checked inductivity of 51617 backedges. 20004 proven. 1711 refuted. 0 times theorem prover too weak. 29902 trivial. 0 not checked. [2019-10-06 23:03:39,314 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:03:42,485 INFO L134 CoverageAnalysis]: Checked inductivity of 51617 backedges. 0 proven. 1711 refuted. 0 times theorem prover too weak. 49906 trivial. 0 not checked. [2019-10-06 23:03:42,486 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:03:42,487 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:03:42,487 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:03:42,488 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:03:42,488 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:03:42,488 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:03:42,517 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:03:43,621 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:03:43,641 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:03:43,643 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:03:43,643 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:03:43,643 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 100)) (<= 100 xor_~i~0) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|)) [2019-10-06 23:03:43,643 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 100)) (<= 100 main_~i~1)) [2019-10-06 23:03:43,643 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_prenex_2911 Int) (v_xor_~res~0_BEFORE_RETURN_392 Int) (v_xor_~res~0_BEFORE_RETURN_391 Int) (v_prenex_2912 Int)) (or (and (not (< main_~i~1 100)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_391 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_391 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_2912 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2912 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_xor_~res~0_BEFORE_RETURN_392 4294967296) main_~ret~0) (<= (mod v_xor_~res~0_BEFORE_RETURN_392 4294967296) 2147483647)) (and (not (< main_~i~1 100)) (<= (mod v_prenex_2911 4294967296) 2147483647) (= (mod v_prenex_2911 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) (exists ((v_prenex_2911 Int) (v_xor_~res~0_BEFORE_RETURN_392 Int) (v_xor_~res~0_BEFORE_RETURN_391 Int) (v_prenex_2912 Int)) (or (and (not (< main_~i~1 100)) (= (mod v_prenex_2911 4294967296) main_~ret~0) (<= (mod v_prenex_2911 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_391 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_391 4294967296) 2147483647))) (and (not (< main_~i~1 100)) (= (+ (mod v_prenex_2912 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_2912 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 100)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_xor_~res~0_BEFORE_RETURN_392 4294967296) main_~ret~0) (<= (mod v_xor_~res~0_BEFORE_RETURN_392 4294967296) 2147483647))))) [2019-10-06 23:03:43,644 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:03:43,644 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:03:43,644 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:03:43,644 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:03:43,644 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_2940 Int) (v_prenex_2939 Int) (v_xor_~res~0_BEFORE_RETURN_396 Int) (v_xor_~res~0_BEFORE_RETURN_395 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_2940 4294967296) main_~ret5~0) (<= (mod v_prenex_2940 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_2939 4294967296) main_~ret5~0) (<= (mod v_prenex_2939 4294967296) 2147483647)) (and (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_396 4294967296) (- 4294967296))) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_396 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_395 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_395 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0))) (and (exists ((v_prenex_2940 Int) (v_prenex_2939 Int) (v_xor_~res~0_BEFORE_RETURN_396 Int) (v_xor_~res~0_BEFORE_RETURN_395 Int)) (or (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_2940 4294967296) main_~ret5~0) (<= (mod v_prenex_2940 4294967296) 2147483647)) (and (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_2939 4294967296) main_~ret5~0) (<= (mod v_prenex_2939 4294967296) 2147483647)) (and (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_396 4294967296) (- 4294967296))) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_396 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_395 4294967296) 2147483647)) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_395 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret2~0)))) [2019-10-06 23:03:43,644 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:03:43,644 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:03:43,644 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:03:43,644 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:03:43,645 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:03:43,645 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (<= 99 main_~i~2) (not (< main_~i~2 99)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 396)))) [2019-10-06 23:03:43,645 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_2911 Int) (v_xor_~res~0_BEFORE_RETURN_391 Int)) (or (and (not (< main_~i~1 100)) (<= (mod v_prenex_2911 4294967296) 2147483647) (= |main_#t~ret5| (mod v_prenex_2911 4294967296))) (and (not (< main_~i~1 100)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_391 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_391 4294967296) 2147483647))))) (exists ((v_xor_~res~0_BEFORE_RETURN_392 Int) (v_prenex_2912 Int)) (or (and (not (< main_~i~1 100)) (= (mod v_xor_~res~0_BEFORE_RETURN_392 4294967296) |main_#t~ret5|) (<= (mod v_xor_~res~0_BEFORE_RETURN_392 4294967296) 2147483647)) (and (= (+ (mod v_prenex_2912 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 100)) (not (<= (mod v_prenex_2912 4294967296) 2147483647)))))) [2019-10-06 23:03:43,645 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:03:43,645 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:03:43,645 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:03:43,645 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:03:44,312 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:03:44,313 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61, 61, 11] total 112 [2019-10-06 23:03:44,315 INFO L442 AbstractCegarLoop]: Interpolant automaton has 113 states [2019-10-06 23:03:44,316 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 113 interpolants. [2019-10-06 23:03:44,317 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5180, Invalid=7476, Unknown=0, NotChecked=0, Total=12656 [2019-10-06 23:03:44,317 INFO L87 Difference]: Start difference. First operand 276 states and 280 transitions. Second operand 113 states. [2019-10-06 23:03:53,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:03:53,529 INFO L93 Difference]: Finished difference Result 424 states and 469 transitions. [2019-10-06 23:03:53,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 112 states. [2019-10-06 23:03:53,529 INFO L78 Accepts]: Start accepts. Automaton has 113 states. Word has length 479 [2019-10-06 23:03:53,530 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:03:53,532 INFO L225 Difference]: With dead ends: 424 [2019-10-06 23:03:53,532 INFO L226 Difference]: Without dead ends: 317 [2019-10-06 23:03:53,535 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1605 GetRequests, 1368 SyntacticMatches, 19 SemanticMatches, 218 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9648 ImplicationChecksByTransitivity, 13.6s TimeCoverageRelationStatistics Valid=15531, Invalid=32649, Unknown=0, NotChecked=0, Total=48180 [2019-10-06 23:03:53,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states. [2019-10-06 23:03:53,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 317. [2019-10-06 23:03:53,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2019-10-06 23:03:53,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 321 transitions. [2019-10-06 23:03:53,555 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 321 transitions. Word has length 479 [2019-10-06 23:03:53,555 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:03:53,555 INFO L462 AbstractCegarLoop]: Abstraction has 317 states and 321 transitions. [2019-10-06 23:03:53,555 INFO L463 AbstractCegarLoop]: Interpolant automaton has 113 states. [2019-10-06 23:03:53,556 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 321 transitions. [2019-10-06 23:03:53,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 521 [2019-10-06 23:03:53,559 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:03:53,560 INFO L385 BasicCegarLoop]: trace histogram [297, 100, 99, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:03:53,765 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:03:53,766 INFO L410 AbstractCegarLoop]: === Iteration 20 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:03:53,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:03:53,766 INFO L82 PathProgramCache]: Analyzing trace with hash -355669370, now seen corresponding path program 17 times [2019-10-06 23:03:53,766 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:03:53,767 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:03:53,767 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:03:53,767 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:03:53,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:04:03,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-06 23:04:11,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-06 23:04:12,196 INFO L161 tionRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2019-10-06 23:04:12,197 INFO L451 BasicCegarLoop]: Counterexample might be feasible [2019-10-06 23:04:12,527 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 06.10 11:04:12 BoogieIcfgContainer [2019-10-06 23:04:12,527 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-10-06 23:04:12,528 INFO L168 Benchmark]: Toolchain (without parser) took 173100.10 ms. Allocated memory was 140.0 MB in the beginning and 1.5 GB in the end (delta: 1.4 GB). Free memory was 103.8 MB in the beginning and 963.2 MB in the end (delta: -859.4 MB). Peak memory consumption was 1.3 GB. Max. memory is 7.1 GB. [2019-10-06 23:04:12,528 INFO L168 Benchmark]: CDTParser took 0.25 ms. Allocated memory is still 140.0 MB. Free memory was 122.2 MB in the beginning and 121.9 MB in the end (delta: 210.0 kB). Peak memory consumption was 210.0 kB. Max. memory is 7.1 GB. [2019-10-06 23:04:12,529 INFO L168 Benchmark]: CACSL2BoogieTranslator took 363.61 ms. Allocated memory was 140.0 MB in the beginning and 203.4 MB in the end (delta: 63.4 MB). Free memory was 103.4 MB in the beginning and 183.6 MB in the end (delta: -80.2 MB). Peak memory consumption was 22.7 MB. Max. memory is 7.1 GB. [2019-10-06 23:04:12,529 INFO L168 Benchmark]: Boogie Preprocessor took 42.27 ms. Allocated memory is still 203.4 MB. Free memory was 183.6 MB in the beginning and 180.2 MB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 7.1 GB. [2019-10-06 23:04:12,529 INFO L168 Benchmark]: RCFGBuilder took 462.83 ms. Allocated memory is still 203.4 MB. Free memory was 180.2 MB in the beginning and 160.3 MB in the end (delta: 20.0 MB). Peak memory consumption was 20.0 MB. Max. memory is 7.1 GB. [2019-10-06 23:04:12,529 INFO L168 Benchmark]: TraceAbstraction took 172227.28 ms. Allocated memory was 203.4 MB in the beginning and 1.5 GB in the end (delta: 1.3 GB). Free memory was 159.6 MB in the beginning and 963.2 MB in the end (delta: -803.6 MB). Peak memory consumption was 1.2 GB. Max. memory is 7.1 GB. [2019-10-06 23:04:12,530 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25 ms. Allocated memory is still 140.0 MB. Free memory was 122.2 MB in the beginning and 121.9 MB in the end (delta: 210.0 kB). Peak memory consumption was 210.0 kB. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 363.61 ms. Allocated memory was 140.0 MB in the beginning and 203.4 MB in the end (delta: 63.4 MB). Free memory was 103.4 MB in the beginning and 183.6 MB in the end (delta: -80.2 MB). Peak memory consumption was 22.7 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 42.27 ms. Allocated memory is still 203.4 MB. Free memory was 183.6 MB in the beginning and 180.2 MB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 7.1 GB. * RCFGBuilder took 462.83 ms. Allocated memory is still 203.4 MB. Free memory was 180.2 MB in the beginning and 160.3 MB in the end (delta: 20.0 MB). Peak memory consumption was 20.0 MB. Max. memory is 7.1 GB. * TraceAbstraction took 172227.28 ms. Allocated memory was 203.4 MB in the beginning and 1.5 GB in the end (delta: 1.3 GB). Free memory was 159.6 MB in the beginning and 963.2 MB in the end (delta: -803.6 MB). Peak memory consumption was 1.2 GB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 42]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of bitwiseXor at line 13. Possible FailurePath: [L20] int x[100]; [L21] int temp; [L22] int ret; [L23] int ret2; [L24] int ret5; [L26] int i = 0; VAL [i=0, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=1, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=2, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=3, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=4, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=5, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=6, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=7, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=8, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=9, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=10, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=11, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=12, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=13, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=14, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=15, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=16, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=17, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=18, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=19, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=20, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=21, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=22, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=23, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=24, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=25, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=26, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=27, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=28, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=29, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=30, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=31, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=32, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=33, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=34, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=35, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=36, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=37, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=38, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=39, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=40, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=41, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=42, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=43, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=44, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=45, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=46, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=47, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=48, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=49, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=50, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=51, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=52, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=53, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=54, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=55, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=56, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=57, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=58, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=59, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=60, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=61, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=62, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=63, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=64, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=65, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=66, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=67, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=68, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=69, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=70, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=71, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=72, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=73, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=74, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=75, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=76, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=77, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=78, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=79, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=80, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=81, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=82, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=83, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=84, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=85, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=86, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=87, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=88, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=89, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=90, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=91, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=92, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=93, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=94, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=95, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=96, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=97, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=98, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=99, x={1:0}] [L26] COND TRUE i < 100 [L27] x[i] = __VERIFIER_nondet_int() [L26] i++ VAL [i=100, x={1:0}] [L26] COND FALSE !(i < 100) VAL [i=100, x={1:0}] [L30] CALL, EXPR xor(x) VAL [x={1:0}] [L9] int i; [L10] long long res; [L11] EXPR x[0] [L11] res = x[0] [L12] i = 1 VAL [i=1, res=1, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=2, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=3, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=4, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=5, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=6, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=7, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=8, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=9, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=10, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=11, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=12, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=13, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=14, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=15, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=16, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=17, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=18, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=19, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=20, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=21, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=22, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=23, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=24, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=25, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=26, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=27, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=28, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=29, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=30, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=31, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=32, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=33, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=34, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=35, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=36, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=37, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=38, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=39, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=40, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=41, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=42, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=43, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=44, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=45, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=46, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=47, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=48, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=49, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=50, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=51, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=52, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=53, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=54, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=55, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=56, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=57, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=58, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=59, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=60, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=61, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=62, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=63, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=64, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=65, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=66, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=67, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=68, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=69, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=70, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=71, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=72, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=73, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=74, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=75, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=76, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=77, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=78, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=79, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=80, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=81, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=82, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=83, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=84, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=85, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=86, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=87, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=88, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=89, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=90, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=91, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=92, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=93, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=94, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=95, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=96, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=97, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=98, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=99, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=100, x={1:0}, x={1:0}] [L12] COND FALSE !(i < 100) [L15] return res; [L30] RET, EXPR xor(x) VAL [i=100, x={1:0}, xor(x)=7] [L30] ret = xor(x) [L32] EXPR x[0] [L32] temp=x[0] [L32] EXPR x[1] [L32] x[0] = x[1] [L32] x[1] = temp VAL [i=100, ret=7, temp=1, x={1:0}] [L33] CALL, EXPR xor(x) VAL [x={1:0}] [L9] int i; [L10] long long res; [L11] EXPR x[0] [L11] res = x[0] [L12] i = 1 VAL [i=1, res=2, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=2, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=3, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=4, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=5, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=6, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=7, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=8, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=9, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=10, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=11, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=12, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=13, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=14, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=15, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=16, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=17, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=18, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=19, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=20, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=21, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=22, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=23, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=24, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=25, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=26, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=27, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=28, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=29, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=30, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=31, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=32, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=33, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=34, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=35, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=36, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=37, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=38, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=39, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=40, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=41, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=42, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=43, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=44, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=45, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=46, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=47, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=48, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=49, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=50, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=51, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=52, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=53, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=54, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=55, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=56, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=57, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=58, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=59, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=60, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=61, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=62, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=63, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=64, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=65, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=66, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=67, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=68, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=69, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=70, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=71, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=72, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=73, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=74, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=75, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=76, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=77, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=78, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=79, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=80, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=81, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=82, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=83, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=84, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=85, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=86, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=87, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=88, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=89, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=90, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=91, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=92, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=93, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=94, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=95, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=96, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=97, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=98, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=99, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=100, x={1:0}, x={1:0}] [L12] COND FALSE !(i < 100) [L15] return res; [L33] RET, EXPR xor(x) VAL [i=100, ret=7, temp=1, x={1:0}, xor(x)=3] [L33] ret2 = xor(x) [L34] EXPR x[0] [L34] temp=x[0] [L35] int i =0 ; VAL [i=0, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=1, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=2, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=3, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=4, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=5, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=6, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=7, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=8, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=9, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=10, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=11, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=12, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=13, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=14, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=15, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=16, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=17, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=18, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=19, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=20, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=21, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=22, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=23, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=24, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=25, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=26, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=27, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=28, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=29, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=30, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=31, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=32, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=33, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=34, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=35, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=36, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=37, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=38, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=39, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=40, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=41, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=42, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=43, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=44, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=45, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=46, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=47, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=48, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=49, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=50, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=51, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=52, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=53, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=54, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=55, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=56, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=57, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=58, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=59, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=60, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=61, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=62, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=63, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=64, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=65, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=66, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=67, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=68, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=69, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=70, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=71, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=72, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=73, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=74, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=75, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=76, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=77, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=78, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=79, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=80, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=81, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=82, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=83, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=84, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=85, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=86, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=87, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=88, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=89, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=90, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=91, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=92, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=93, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=94, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=95, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=96, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=97, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=98, i=100, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND TRUE i<100 -1 [L36] EXPR x[i+1] [L36] x[i] = x[i+1] [L35] i++ VAL [i=100, i=99, ret=7, ret2=3, temp=2, x={1:0}] [L35] COND FALSE !(i<100 -1) [L38] x[100 -1] = temp VAL [i=100, i=99, ret=7, ret2=3, temp=2, x={1:0}] [L39] CALL, EXPR xor(x) VAL [x={1:0}] [L9] int i; [L10] long long res; [L11] EXPR x[0] [L11] res = x[0] [L12] i = 1 VAL [i=1, res=1, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=2, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=3, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=4, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=5, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=6, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=7, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=8, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=9, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=10, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=11, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=12, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=13, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=14, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=15, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=16, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=17, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=18, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=19, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=20, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=21, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=22, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=23, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=24, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=25, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=26, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=27, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=28, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=29, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=30, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=31, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=32, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=33, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=34, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=35, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=36, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=37, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=38, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=39, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=40, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=41, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=42, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=43, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=44, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=45, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=46, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=47, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=48, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=49, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=50, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=51, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=52, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=53, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=54, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=55, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=56, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=57, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=58, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=59, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=60, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=61, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=62, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=63, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=64, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=65, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=66, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=67, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=68, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=69, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=70, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=71, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=72, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=73, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=74, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=75, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=76, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=77, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=78, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=79, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=80, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=81, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=82, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=83, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=84, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=85, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=86, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=87, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=88, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=89, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=90, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=91, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=92, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=93, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=94, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=95, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=96, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=97, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=98, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=99, x={1:0}, x={1:0}] [L12] COND TRUE i < 100 [L13] EXPR x[i] [L13] res = res ^ x[i] [L12] i++ VAL [i=100, x={1:0}, x={1:0}] [L12] COND FALSE !(i < 100) [L15] return res; [L39] RET, EXPR xor(x) VAL [i=99, i=100, ret=7, ret2=3, temp=2, x={1:0}, xor(x)=5] [L39] ret5 = xor(x) [L41] COND TRUE ret != ret2 || ret !=ret5 VAL [i=99, i=100, ret=7, ret2=3, ret5=5, temp=2, x={1:0}] [L42] __VERIFIER_error() VAL [i=99, i=100, ret=7, ret2=3, ret5=5, temp=2, x={1:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 23 locations, 1 error locations. Result: UNSAFE, OverallTime: 172.1s, OverallIterations: 20, TraceHistogramMax: 297, AutomataDifference: 78.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 262 SDtfs, 357 SDslu, 2120 SDs, 0 SdLazy, 3470 SolverSat, 2411 SolverUnsat, 2 SolverUnknown, 0 SolverNotchecked, 10.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 10993 GetRequests, 8997 SyntacticMatches, 128 SemanticMatches, 1868 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65334 ImplicationChecksByTransitivity, 101.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=317occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 19 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.8s SsaConstructionTime, 15.0s SatisfiabilityAnalysisTime, 30.5s InterpolantComputationTime, 7026 NumberOfCodeBlocks, 6297 NumberOfCodeBlocksAsserted, 59 NumberOfCheckSat, 9680 ConstructedInterpolants, 0 QuantifiedInterpolants, 3810778 SizeOfPredicates, 19 NumberOfNonLiveVariables, 10564 ConjunctsInSsa, 427 ConjunctsInUnsatCore, 53 InterpolantComputations, 3 PerfectInterpolantSequences, 692529/752653 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: OVERALL_TIME[ms]: 21512, ICFG_INTERPRETER_ENTERED_PROCEDURES: 64, DAG_INTERPRETER_EARLY_EXIT_QUERIES: 1632, DAG_INTERPRETER_EARLY_EXITS: 0, TOOLS_POST_APPLICATIONS: 848, TOOLS_POST_TIME[ms]: 15559, TOOLS_POST_CALL_APPLICATIONS: 528, TOOLS_POST_CALL_TIME[ms]: 1441, TOOLS_POST_RETURN_APPLICATIONS: 448, TOOLS_POST_RETURN_TIME[ms]: 827, TOOLS_QUANTIFIERELIM_APPLICATIONS: 1824, TOOLS_QUANTIFIERELIM_TIME[ms]: 17436, TOOLS_QUANTIFIERELIM_MAX_TIME[ms]: 140, FLUID_QUERY_TIME[ms]: 28, FLUID_QUERIES: 1888, FLUID_YES_ANSWERS: 112, DOMAIN_JOIN_APPLICATIONS: 1856, DOMAIN_JOIN_TIME[ms]: 2098, DOMAIN_ALPHA_APPLICATIONS: 112, DOMAIN_ALPHA_TIME[ms]: 45, DOMAIN_WIDEN_APPLICATIONS: 96, DOMAIN_WIDEN_TIME[ms]: 376, DOMAIN_ISSUBSETEQ_APPLICATIONS: 256, DOMAIN_ISSUBSETEQ_TIME[ms]: 323, DOMAIN_ISBOTTOM_APPLICATIONS: 256, DOMAIN_ISBOTTOM_TIME[ms]: 377, LOOP_SUMMARIZER_APPLICATIONS: 160, LOOP_SUMMARIZER_CACHE_MISSES: 160, LOOP_SUMMARIZER_OVERALL_TIME[ms]: 3063, LOOP_SUMMARIZER_NEW_COMPUTATION_TIME[ms]: 3059, LOOP_SUMMARIZER_FIXPOINT_ITERATIONS: 256, CALL_SUMMARIZER_APPLICATIONS: 448, CALL_SUMMARIZER_CACHE_MISSES: 32, CALL_SUMMARIZER_OVERALL_TIME[ms]: 544, CALL_SUMMARIZER_NEW_COMPUTATION_TIME[ms]: 541, PROCEDURE_GRAPH_BUILDER_TIME[ms]: 11, PATH_EXPR_TIME[ms]: 10, REGEX_TO_DAG_TIME[ms]: 9, DAG_COMPRESSION_TIME[ms]: 70, DAG_COMPRESSION_PROCESSED_NODES: 3424, DAG_COMPRESSION_RETAINED_NODES: 1808, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request...