java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/array-crafted/xor2.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-36ac518-m [2019-10-06 23:01:18,158 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-06 23:01:18,161 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-06 23:01:18,179 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-06 23:01:18,179 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-06 23:01:18,181 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-06 23:01:18,182 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-06 23:01:18,184 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-06 23:01:18,196 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-06 23:01:18,197 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-06 23:01:18,198 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-06 23:01:18,200 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-06 23:01:18,201 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-06 23:01:18,202 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-06 23:01:18,205 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-06 23:01:18,207 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-06 23:01:18,207 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-06 23:01:18,211 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-06 23:01:18,214 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-06 23:01:18,217 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-06 23:01:18,220 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-06 23:01:18,223 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-06 23:01:18,224 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-06 23:01:18,225 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-06 23:01:18,230 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-06 23:01:18,244 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-06 23:01:18,245 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-06 23:01:18,247 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-06 23:01:18,248 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-06 23:01:18,267 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-06 23:01:18,267 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-06 23:01:18,268 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-06 23:01:18,269 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-06 23:01:18,269 INFO L138 SettingsManager]: * Use SBE=true [2019-10-06 23:01:18,269 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-06 23:01:18,269 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-06 23:01:18,269 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-06 23:01:18,270 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-06 23:01:18,270 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-06 23:01:18,270 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-06 23:01:18,270 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-06 23:01:18,270 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-06 23:01:18,271 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-06 23:01:18,271 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-06 23:01:18,271 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-06 23:01:18,271 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-06 23:01:18,272 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-06 23:01:18,272 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-06 23:01:18,272 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-06 23:01:18,272 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-06 23:01:18,272 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 23:01:18,273 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-06 23:01:18,273 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-06 23:01:18,273 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-06 23:01:18,273 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-06 23:01:18,273 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-06 23:01:18,274 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-06 23:01:18,274 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-06 23:01:18,548 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-06 23:01:18,562 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-06 23:01:18,568 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-06 23:01:18,570 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-06 23:01:18,570 INFO L275 PluginConnector]: CDTParser initialized [2019-10-06 23:01:18,571 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-crafted/xor2.i [2019-10-06 23:01:18,642 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/515287521/575e5af80aa048c8917b3baa9140bd58/FLAGa112a0ed1 [2019-10-06 23:01:19,119 INFO L306 CDTParser]: Found 1 translation units. [2019-10-06 23:01:19,120 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-crafted/xor2.i [2019-10-06 23:01:19,126 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/515287521/575e5af80aa048c8917b3baa9140bd58/FLAGa112a0ed1 [2019-10-06 23:01:19,500 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/515287521/575e5af80aa048c8917b3baa9140bd58 [2019-10-06 23:01:19,508 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-06 23:01:19,510 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-06 23:01:19,511 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-06 23:01:19,511 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-06 23:01:19,514 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-06 23:01:19,516 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,519 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@76d728e1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19, skipping insertion in model container [2019-10-06 23:01:19,519 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,526 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-06 23:01:19,547 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-06 23:01:19,774 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 23:01:19,785 INFO L188 MainTranslator]: Completed pre-run [2019-10-06 23:01:19,908 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-06 23:01:19,924 INFO L192 MainTranslator]: Completed translation [2019-10-06 23:01:19,925 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19 WrapperNode [2019-10-06 23:01:19,925 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-06 23:01:19,926 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-06 23:01:19,926 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-06 23:01:19,926 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-06 23:01:19,938 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,938 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,946 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,946 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,955 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,961 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,962 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... [2019-10-06 23:01:19,965 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-06 23:01:19,965 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-06 23:01:19,965 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-06 23:01:19,965 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-06 23:01:19,966 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-06 23:01:20,027 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-06 23:01:20,028 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-06 23:01:20,029 INFO L138 BoogieDeclarations]: Found implementation of procedure xor [2019-10-06 23:01:20,029 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-06 23:01:20,029 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-06 23:01:20,030 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-06 23:01:20,031 INFO L130 BoogieDeclarations]: Found specification of procedure xor [2019-10-06 23:01:20,031 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-06 23:01:20,031 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-06 23:01:20,031 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-06 23:01:20,032 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-06 23:01:20,033 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-06 23:01:20,033 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-06 23:01:20,033 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-06 23:01:20,414 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-06 23:01:20,414 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-06 23:01:20,415 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 11:01:20 BoogieIcfgContainer [2019-10-06 23:01:20,416 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-06 23:01:20,417 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-06 23:01:20,417 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-06 23:01:20,419 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-06 23:01:20,420 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.10 11:01:19" (1/3) ... [2019-10-06 23:01:20,420 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7f03fd45 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 11:01:20, skipping insertion in model container [2019-10-06 23:01:20,420 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.10 11:01:19" (2/3) ... [2019-10-06 23:01:20,421 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7f03fd45 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.10 11:01:20, skipping insertion in model container [2019-10-06 23:01:20,421 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.10 11:01:20" (3/3) ... [2019-10-06 23:01:20,422 INFO L109 eAbstractionObserver]: Analyzing ICFG xor2.i [2019-10-06 23:01:20,431 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-06 23:01:20,439 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-06 23:01:20,450 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-06 23:01:20,472 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-06 23:01:20,472 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-06 23:01:20,472 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-06 23:01:20,472 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-06 23:01:20,472 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-06 23:01:20,472 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-06 23:01:20,472 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-06 23:01:20,473 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-06 23:01:20,490 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-06 23:01:20,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-06 23:01:20,496 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:20,497 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:20,499 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:20,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:20,505 INFO L82 PathProgramCache]: Analyzing trace with hash -809725829, now seen corresponding path program 1 times [2019-10-06 23:01:20,515 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:20,515 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:20,515 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:20,515 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:20,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:20,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:20,707 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-06 23:01:20,708 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:20,709 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 23:01:20,709 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 23:01:20,714 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 23:01:20,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 23:01:20,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 23:01:20,730 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-06 23:01:20,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:20,761 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-06 23:01:20,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 23:01:20,764 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-06 23:01:20,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:20,773 INFO L225 Difference]: With dead ends: 41 [2019-10-06 23:01:20,773 INFO L226 Difference]: Without dead ends: 20 [2019-10-06 23:01:20,777 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 23:01:20,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-06 23:01:20,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-06 23:01:20,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-06 23:01:20,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-06 23:01:20,820 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-06 23:01:20,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:20,821 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-06 23:01:20,821 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 23:01:20,821 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-06 23:01:20,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-06 23:01:20,823 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:20,824 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:20,824 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:20,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:20,825 INFO L82 PathProgramCache]: Analyzing trace with hash 994996090, now seen corresponding path program 1 times [2019-10-06 23:01:20,825 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:20,826 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:20,826 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:20,826 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:20,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:20,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:20,911 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 23:01:20,911 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:20,912 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:20,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:21,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:21,012 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-06 23:01:21,023 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:21,058 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 23:01:21,058 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:21,101 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-06 23:01:21,102 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-06 23:01:21,102 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-06 23:01:21,104 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 23:01:21,104 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 23:01:21,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 23:01:21,105 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-06 23:01:21,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:21,116 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-06 23:01:21,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 23:01:21,117 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-06 23:01:21,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:21,119 INFO L225 Difference]: With dead ends: 33 [2019-10-06 23:01:21,120 INFO L226 Difference]: Without dead ends: 21 [2019-10-06 23:01:21,121 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-06 23:01:21,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-06 23:01:21,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-06 23:01:21,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-06 23:01:21,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-06 23:01:21,136 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-06 23:01:21,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:21,136 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-06 23:01:21,137 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 23:01:21,137 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-06 23:01:21,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-06 23:01:21,139 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:21,140 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:21,347 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:21,348 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:21,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:21,348 INFO L82 PathProgramCache]: Analyzing trace with hash -421018474, now seen corresponding path program 1 times [2019-10-06 23:01:21,349 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:21,349 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:21,350 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:21,350 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:21,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:21,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:21,446 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 23:01:21,446 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:21,447 INFO L211 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-06 23:01:21,447 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-06 23:01:21,447 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-06 23:01:21,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-06 23:01:21,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 23:01:21,448 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-06 23:01:21,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:21,466 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-06 23:01:21,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-06 23:01:21,467 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-06 23:01:21,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:21,469 INFO L225 Difference]: With dead ends: 31 [2019-10-06 23:01:21,469 INFO L226 Difference]: Without dead ends: 22 [2019-10-06 23:01:21,470 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-06 23:01:21,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-06 23:01:21,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-06 23:01:21,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-06 23:01:21,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-06 23:01:21,479 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-06 23:01:21,482 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:21,483 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-06 23:01:21,483 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-06 23:01:21,483 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-06 23:01:21,484 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-06 23:01:21,484 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:21,484 INFO L385 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:21,485 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:21,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:21,485 INFO L82 PathProgramCache]: Analyzing trace with hash -661634715, now seen corresponding path program 1 times [2019-10-06 23:01:21,485 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:21,485 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:21,486 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:21,486 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:21,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:21,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:21,602 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 23:01:21,602 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:21,603 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:21,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:21,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:21,688 INFO L256 TraceCheckSpWp]: Trace formula consists of 136 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 23:01:21,714 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:21,733 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 23:01:21,733 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:21,767 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 23:01:21,768 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:21,794 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:21,794 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:21,801 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:21,810 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:21,811 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:21,966 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:23,936 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:24,010 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:24,015 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:24,015 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:24,016 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 1000)) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|) (<= 1000 xor_~i~0)) [2019-10-06 23:01:24,016 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 23:01:24,016 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_2 Int) (v_xor_~res~0_BEFORE_RETURN_2 Int) (v_prenex_1 Int) (v_xor_~res~0_BEFORE_RETURN_1 Int)) (or (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_2 4294967296)) (<= main_~ret~0 2147483647) (<= (mod v_prenex_2 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_1 4294967296))) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_2 4294967296) 2147483647)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_2 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647)))) [2019-10-06 23:01:24,016 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:24,016 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:24,017 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:24,017 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:24,017 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:24,017 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:24,017 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:24,018 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:24,018 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:24,018 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 23:01:24,018 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_xor_~res~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (= (mod v_xor_~res~0_BEFORE_RETURN_1 4294967296) |main_#t~ret5|) (not (< main_~i~1 1000)) (<= (mod v_xor_~res~0_BEFORE_RETURN_1 4294967296) 2147483647)) (and (= (+ (mod v_prenex_1 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 1000)) (not (<= (mod v_prenex_1 4294967296) 2147483647))))) (exists ((v_prenex_2 Int) (v_xor_~res~0_BEFORE_RETURN_2 Int)) (or (and (= |main_#t~ret5| (mod v_prenex_2 4294967296)) (not (< main_~i~1 1000)) (<= (mod v_prenex_2 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_2 4294967296) 2147483647)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_2 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 23:01:24,019 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:24,019 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:24,020 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_xor_~res~0_BEFORE_RETURN_6 Int) (v_xor_~res~0_BEFORE_RETURN_5 Int)) (or (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_6 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_6 4294967296) 2147483647))) (and (not (<= (mod v_prenex_29 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_29 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (<= (mod v_prenex_30 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_5 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_5 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_prenex_30 Int) (v_xor_~res~0_BEFORE_RETURN_6 Int) (v_xor_~res~0_BEFORE_RETURN_5 Int)) (or (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_6 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_6 4294967296) 2147483647))) (and (not (<= (mod v_prenex_29 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_29 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (<= (mod v_prenex_30 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_5 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_5 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))))) [2019-10-06 23:01:24,021 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:24,021 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:24,372 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:24,372 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-06 23:01:24,374 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-06 23:01:24,374 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-06 23:01:24,377 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-06 23:01:24,377 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-06 23:01:25,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:25,029 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-06 23:01:25,029 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-06 23:01:25,031 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-06 23:01:25,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:25,032 INFO L225 Difference]: With dead ends: 40 [2019-10-06 23:01:25,032 INFO L226 Difference]: Without dead ends: 25 [2019-10-06 23:01:25,033 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=133, Invalid=737, Unknown=0, NotChecked=0, Total=870 [2019-10-06 23:01:25,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-06 23:01:25,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-06 23:01:25,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-06 23:01:25,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-06 23:01:25,046 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-06 23:01:25,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:25,046 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-06 23:01:25,046 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-06 23:01:25,047 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-06 23:01:25,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-06 23:01:25,049 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:25,050 INFO L385 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:25,262 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:25,262 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:25,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:25,263 INFO L82 PathProgramCache]: Analyzing trace with hash -139894362, now seen corresponding path program 2 times [2019-10-06 23:01:25,264 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:25,264 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:25,264 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:25,265 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:25,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:25,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:25,391 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-06 23:01:25,391 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:25,391 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:25,392 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:25,469 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-06 23:01:25,470 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:01:25,473 INFO L256 TraceCheckSpWp]: Trace formula consists of 106 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 23:01:25,478 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:25,502 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 23:01:25,502 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:25,540 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-06 23:01:25,542 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:25,543 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:25,544 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:25,546 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:25,547 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:25,547 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:25,582 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:27,355 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:27,415 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:27,424 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:27,424 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:27,425 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 1000)) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|) (<= 1000 xor_~i~0)) [2019-10-06 23:01:27,425 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 23:01:27,425 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_196 Int) (v_xor_~res~0_BEFORE_RETURN_27 Int) (v_xor_~res~0_BEFORE_RETURN_28 Int) (v_prenex_195 Int)) (or (and (not (<= (mod v_prenex_196 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~0)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_28 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_xor_~res~0_BEFORE_RETURN_28 4294967296) main_~ret~0)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_27 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_27 4294967296) (- 4294967296)))) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_prenex_195 4294967296) main_~ret~0) (<= main_~ret~0 2147483647) (<= (mod v_prenex_195 4294967296) 2147483647)))) [2019-10-06 23:01:27,425 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:27,425 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:27,426 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:27,426 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:27,426 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:27,430 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:27,431 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:27,431 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:27,431 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:27,432 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 23:01:27,432 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_196 Int) (v_xor_~res~0_BEFORE_RETURN_28 Int)) (or (and (not (<= (mod v_prenex_196 4294967296) 2147483647)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 1000))) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_28 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod v_xor_~res~0_BEFORE_RETURN_28 4294967296) |main_#t~ret5|)))) (exists ((v_xor_~res~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (= (+ (mod v_xor_~res~0_BEFORE_RETURN_27 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_27 4294967296) 2147483647)) (not (< main_~i~1 1000))) (and (= |main_#t~ret5| (mod v_prenex_195 4294967296)) (not (< main_~i~1 1000)) (<= (mod v_prenex_195 4294967296) 2147483647))))) [2019-10-06 23:01:27,433 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:27,433 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:27,433 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_prenex_223 Int) (v_xor_~res~0_BEFORE_RETURN_32 Int)) (or (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_32 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_32 4294967296) (- 4294967296)))) (and (= (mod v_xor_~res~0_BEFORE_RETURN_31 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_31 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (<= (mod v_prenex_223 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_223 4294967296) (- 4294967296))) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296)))))) (and (exists ((v_xor_~res~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_prenex_223 Int) (v_xor_~res~0_BEFORE_RETURN_32 Int)) (or (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_32 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_32 4294967296) (- 4294967296)))) (and (= (mod v_xor_~res~0_BEFORE_RETURN_31 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_31 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (<= (mod v_prenex_223 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (+ (mod v_prenex_223 4294967296) (- 4294967296))) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 23:01:27,433 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:27,433 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:27,820 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:27,820 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-06 23:01:27,822 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-06 23:01:27,822 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-06 23:01:27,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-06 23:01:27,823 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-06 23:01:30,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:30,831 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-06 23:01:30,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-06 23:01:30,832 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-06 23:01:30,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:30,833 INFO L225 Difference]: With dead ends: 44 [2019-10-06 23:01:30,833 INFO L226 Difference]: Without dead ends: 29 [2019-10-06 23:01:30,835 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 304 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=210, Invalid=1271, Unknown=1, NotChecked=0, Total=1482 [2019-10-06 23:01:30,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-06 23:01:30,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-06 23:01:30,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-06 23:01:30,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-06 23:01:30,842 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-06 23:01:30,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:30,842 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-06 23:01:30,843 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-06 23:01:30,843 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-06 23:01:30,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-06 23:01:30,844 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:30,844 INFO L385 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:31,047 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:31,047 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:31,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:31,048 INFO L82 PathProgramCache]: Analyzing trace with hash -1028595953, now seen corresponding path program 3 times [2019-10-06 23:01:31,048 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:31,049 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:31,049 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:31,049 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:31,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:31,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:31,164 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:31,164 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:31,164 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:31,164 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:31,288 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 23:01:31,289 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:01:31,290 INFO L256 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-06 23:01:31,301 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:31,324 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:31,324 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:31,415 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:31,416 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:31,418 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:31,418 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:31,418 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:31,419 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:31,419 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:31,458 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:33,177 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:33,210 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:33,215 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:33,215 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:33,215 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 1000)) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|) (<= 1000 xor_~i~0)) [2019-10-06 23:01:33,216 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 23:01:33,216 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_xor_~res~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int) (v_xor_~res~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647)) (and (= (mod v_prenex_389 4294967296) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (= (mod v_xor_~res~0_BEFORE_RETURN_54 4294967296) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_54 4294967296) 2147483647)) (and (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_53 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= main_~ret~0 2147483647)))) [2019-10-06 23:01:33,216 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:33,216 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:33,216 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:33,217 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:33,217 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:33,217 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:33,218 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:33,218 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:33,218 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:33,219 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 23:01:33,219 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_xor_~res~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int)) (or (and (= |main_#t~ret5| (+ (mod v_xor_~res~0_BEFORE_RETURN_53 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_53 4294967296) 2147483647))) (and (not (< main_~i~1 1000)) (<= (mod v_prenex_389 4294967296) 2147483647) (= (mod v_prenex_389 4294967296) |main_#t~ret5|)))) (exists ((v_xor_~res~0_BEFORE_RETURN_54 Int) (v_prenex_390 Int)) (or (and (not (< main_~i~1 1000)) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_prenex_390 4294967296) (- 4294967296)))) (and (= (mod v_xor_~res~0_BEFORE_RETURN_54 4294967296) |main_#t~ret5|) (not (< main_~i~1 1000)) (<= (mod v_xor_~res~0_BEFORE_RETURN_54 4294967296) 2147483647))))) [2019-10-06 23:01:33,219 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:33,220 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:33,220 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_xor_~res~0_BEFORE_RETURN_57 Int) (v_xor_~res~0_BEFORE_RETURN_58 Int) (v_prenex_417 Int) (v_prenex_418 Int)) (or (and (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_57 4294967296) (- 4294967296))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_57 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296)))) (and (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_58 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_58 4294967296))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_57 Int) (v_xor_~res~0_BEFORE_RETURN_58 Int) (v_prenex_417 Int) (v_prenex_418 Int)) (or (and (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_57 4294967296) (- 4294967296))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_57 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_prenex_418 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_418 4294967296) (- 4294967296)))) (and (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_58 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_58 4294967296))))))) [2019-10-06 23:01:33,220 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:33,221 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:33,641 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:33,642 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-06 23:01:33,643 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-06 23:01:33,645 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-06 23:01:33,646 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-06 23:01:33,646 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-06 23:01:34,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:34,850 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-06 23:01:34,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-06 23:01:34,850 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-06 23:01:34,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:34,852 INFO L225 Difference]: With dead ends: 54 [2019-10-06 23:01:34,852 INFO L226 Difference]: Without dead ends: 36 [2019-10-06 23:01:34,854 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-06 23:01:34,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-06 23:01:34,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-06 23:01:34,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-06 23:01:34,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-06 23:01:34,862 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-06 23:01:34,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:34,863 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-06 23:01:34,863 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-06 23:01:34,863 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-06 23:01:34,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-06 23:01:34,865 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:34,865 INFO L385 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:35,069 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:35,070 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:35,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:35,070 INFO L82 PathProgramCache]: Analyzing trace with hash -500498258, now seen corresponding path program 4 times [2019-10-06 23:01:35,071 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:35,071 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:35,071 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:35,071 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:35,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:35,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:35,256 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:35,257 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:35,257 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:35,257 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:35,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:35,391 INFO L256 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-06 23:01:35,394 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:35,410 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:35,410 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:35,661 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:35,661 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:35,663 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:35,663 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:35,663 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:35,664 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:35,664 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:35,689 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:37,059 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:37,085 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:37,089 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:37,089 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:37,089 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 1000)) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|) (<= 1000 xor_~i~0)) [2019-10-06 23:01:37,090 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 23:01:37,090 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_xor_~res~0_BEFORE_RETURN_79 Int) (v_prenex_583 Int) (v_prenex_584 Int) (v_xor_~res~0_BEFORE_RETURN_80 Int)) (or (and (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_79 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_prenex_584 4294967296) main_~ret~0) (<= (mod v_prenex_584 4294967296) 2147483647)) (and (<= (mod v_prenex_583 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_583 4294967296)) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (<= main_~ret~0 2147483647)))) [2019-10-06 23:01:37,090 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:37,091 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:37,091 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:37,091 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:37,091 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:37,091 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:37,091 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:37,092 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:37,092 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:37,092 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 23:01:37,092 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_xor_~res~0_BEFORE_RETURN_79 Int) (v_prenex_583 Int)) (or (and (= (mod v_prenex_583 4294967296) |main_#t~ret5|) (not (< main_~i~1 1000)) (<= (mod v_prenex_583 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_79 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_xor_~res~0_BEFORE_RETURN_79 4294967296) (- 4294967296)))))) (exists ((v_prenex_584 Int) (v_xor_~res~0_BEFORE_RETURN_80 Int)) (or (and (not (< main_~i~1 1000)) (= (mod v_prenex_584 4294967296) |main_#t~ret5|) (<= (mod v_prenex_584 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_xor_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296))))))) [2019-10-06 23:01:37,093 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:37,093 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:37,093 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_xor_~res~0_BEFORE_RETURN_83 Int) (v_xor_~res~0_BEFORE_RETURN_84 Int)) (or (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_84 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_84 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (<= (mod v_prenex_611 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_611 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_612 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (mod v_prenex_612 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_83 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_83 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_xor_~res~0_BEFORE_RETURN_83 Int) (v_xor_~res~0_BEFORE_RETURN_84 Int)) (or (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_84 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_84 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (<= (mod v_prenex_611 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_611 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_612 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (mod v_prenex_612 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_83 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_83 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))))) [2019-10-06 23:01:37,093 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:37,094 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:37,562 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:37,562 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-06 23:01:37,564 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-06 23:01:37,564 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-06 23:01:37,566 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-06 23:01:37,567 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 40 states. [2019-10-06 23:01:39,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:39,422 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-06 23:01:39,422 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-06 23:01:39,423 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 49 [2019-10-06 23:01:39,423 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:39,424 INFO L225 Difference]: With dead ends: 68 [2019-10-06 23:01:39,424 INFO L226 Difference]: Without dead ends: 50 [2019-10-06 23:01:39,427 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-06 23:01:39,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-06 23:01:39,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-06 23:01:39,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-06 23:01:39,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-06 23:01:39,436 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-06 23:01:39,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:39,436 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-06 23:01:39,437 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-06 23:01:39,437 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-06 23:01:39,438 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-06 23:01:39,439 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:39,439 INFO L385 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:39,647 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:39,647 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:39,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:39,648 INFO L82 PathProgramCache]: Analyzing trace with hash 1795685774, now seen corresponding path program 5 times [2019-10-06 23:01:39,648 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:39,648 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:39,649 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:39,649 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:39,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:39,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:40,121 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-06 23:01:40,121 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:40,122 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:40,122 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:40,277 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 23:01:40,278 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:01:40,280 INFO L256 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-06 23:01:40,283 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:40,334 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-06 23:01:40,335 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:40,378 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-06 23:01:40,379 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:40,380 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:40,380 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:40,380 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:40,381 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:40,381 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:40,407 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:41,649 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:41,669 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:41,671 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:41,672 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:41,672 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 1000)) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|) (<= 1000 xor_~i~0)) [2019-10-06 23:01:41,672 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 23:01:41,672 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_xor_~res~0_BEFORE_RETURN_105 Int) (v_prenex_777 Int) (v_xor_~res~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) main_~ret~0)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_106 4294967296) 2147483647) (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_106 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_105 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_105 4294967296) (- 4294967296)))) (and (<= (mod v_prenex_777 4294967296) 2147483647) (= main_~ret~0 (mod v_prenex_777 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-06 23:01:41,672 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:41,673 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:41,673 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:41,673 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:41,673 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:41,673 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 23:01:41,673 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:41,674 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:41,674 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:41,674 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 23:01:41,674 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_xor_~res~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (= |main_#t~ret5| (+ (mod v_prenex_778 4294967296) (- 4294967296))) (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 1000))) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_106 4294967296) 2147483647) (= (mod v_xor_~res~0_BEFORE_RETURN_106 4294967296) |main_#t~ret5|) (not (< main_~i~1 1000))))) (exists ((v_xor_~res~0_BEFORE_RETURN_105 Int) (v_prenex_777 Int)) (or (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_105 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_105 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (<= (mod v_prenex_777 4294967296) 2147483647) (= (mod v_prenex_777 4294967296) |main_#t~ret5|) (not (< main_~i~1 1000)))))) [2019-10-06 23:01:41,674 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:41,675 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:41,675 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_xor_~res~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_xor_~res~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (= (+ (mod v_xor_~res~0_BEFORE_RETURN_109 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_109 4294967296) 2147483647))) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_110 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (mod v_xor_~res~0_BEFORE_RETURN_110 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (mod v_prenex_805 4294967296)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (not (<= (mod v_prenex_806 4294967296) 2147483647)) (= (+ (mod v_prenex_806 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_109 Int) (v_prenex_806 Int) (v_xor_~res~0_BEFORE_RETURN_110 Int) (v_prenex_805 Int)) (or (and (= (+ (mod v_xor_~res~0_BEFORE_RETURN_109 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_109 4294967296) 2147483647))) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_110 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (mod v_xor_~res~0_BEFORE_RETURN_110 4294967296) main_~ret5~0)) (and (= main_~ret5~0 (mod v_prenex_805 4294967296)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (not (<= (mod v_prenex_806 4294967296) 2147483647)) (= (+ (mod v_prenex_806 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))))) [2019-10-06 23:01:41,675 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:41,675 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:42,285 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:42,285 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-06 23:01:42,287 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-06 23:01:42,287 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-06 23:01:42,288 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-06 23:01:42,288 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 44 states. [2019-10-06 23:01:44,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:44,420 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-06 23:01:44,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-06 23:01:44,420 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 63 [2019-10-06 23:01:44,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:44,422 INFO L225 Difference]: With dead ends: 72 [2019-10-06 23:01:44,422 INFO L226 Difference]: Without dead ends: 54 [2019-10-06 23:01:44,425 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1350 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1349, Invalid=5457, Unknown=0, NotChecked=0, Total=6806 [2019-10-06 23:01:44,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-06 23:01:44,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-06 23:01:44,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-06 23:01:44,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-06 23:01:44,434 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-06 23:01:44,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:44,435 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-06 23:01:44,435 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-06 23:01:44,435 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-06 23:01:44,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-06 23:01:44,436 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:44,436 INFO L385 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:44,639 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:44,640 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:44,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:44,641 INFO L82 PathProgramCache]: Analyzing trace with hash -344788902, now seen corresponding path program 6 times [2019-10-06 23:01:44,641 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:44,641 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:44,641 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:44,642 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:44,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:44,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:45,059 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:01:45,059 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:45,059 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:45,060 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:45,269 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 23:01:45,269 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:01:45,271 INFO L256 TraceCheckSpWp]: Trace formula consists of 331 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-06 23:01:45,274 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:45,317 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:01:45,317 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:46,270 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:01:46,270 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:46,273 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:46,274 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:46,274 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:46,274 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:46,275 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:46,298 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:47,483 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:47,505 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:47,507 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:47,508 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:47,508 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 1000)) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|) (<= 1000 xor_~i~0)) [2019-10-06 23:01:47,508 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 23:01:47,508 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_xor_~res~0_BEFORE_RETURN_132 Int) (v_xor_~res~0_BEFORE_RETURN_131 Int)) (or (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_132 4294967296) 2147483647)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_131 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_131 4294967296) 2147483647)) (and (= main_~ret~0 (mod v_prenex_972 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_972 4294967296) 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)))) [2019-10-06 23:01:47,509 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:47,509 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:47,509 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:47,509 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:47,509 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:47,510 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:47,510 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:47,510 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:47,510 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:47,511 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 23:01:47,511 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_971 Int) (v_xor_~res~0_BEFORE_RETURN_131 Int)) (or (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= |main_#t~ret5| (+ (mod v_prenex_971 4294967296) (- 4294967296)))) (and (not (< main_~i~1 1000)) (= |main_#t~ret5| (mod v_xor_~res~0_BEFORE_RETURN_131 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_131 4294967296) 2147483647)))) (exists ((v_prenex_972 Int) (v_xor_~res~0_BEFORE_RETURN_132 Int)) (or (and (= (+ (mod v_xor_~res~0_BEFORE_RETURN_132 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_132 4294967296) 2147483647)) (not (< main_~i~1 1000))) (and (not (< main_~i~1 1000)) (= (mod v_prenex_972 4294967296) |main_#t~ret5|) (<= (mod v_prenex_972 4294967296) 2147483647))))) [2019-10-06 23:01:47,511 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:47,511 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:47,511 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_1000 Int) (v_xor_~res~0_BEFORE_RETURN_136 Int) (v_xor_~res~0_BEFORE_RETURN_135 Int) (v_prenex_999 Int)) (or (and (= (mod v_xor_~res~0_BEFORE_RETURN_135 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_135 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_prenex_1000 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (<= (mod v_prenex_999 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (+ (mod v_prenex_999 4294967296) (- 4294967296)) main_~ret5~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_1000 Int) (v_xor_~res~0_BEFORE_RETURN_136 Int) (v_xor_~res~0_BEFORE_RETURN_135 Int) (v_prenex_999 Int)) (or (and (= (mod v_xor_~res~0_BEFORE_RETURN_135 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_xor_~res~0_BEFORE_RETURN_135 4294967296) 2147483647) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_prenex_1000 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (<= (mod v_prenex_999 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= (+ (mod v_prenex_999 4294967296) (- 4294967296)) main_~ret5~0)))))) [2019-10-06 23:01:47,512 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:47,512 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:48,171 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:48,172 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-06 23:01:48,173 INFO L442 AbstractCegarLoop]: Interpolant automaton has 70 states [2019-10-06 23:01:48,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2019-10-06 23:01:48,177 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1740, Invalid=3090, Unknown=0, NotChecked=0, Total=4830 [2019-10-06 23:01:48,177 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 70 states. [2019-10-06 23:01:51,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:01:51,723 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-06 23:01:51,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2019-10-06 23:01:51,724 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 67 [2019-10-06 23:01:51,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:01:51,726 INFO L225 Difference]: With dead ends: 104 [2019-10-06 23:01:51,726 INFO L226 Difference]: Without dead ends: 83 [2019-10-06 23:01:51,730 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3929 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=5099, Invalid=12723, Unknown=0, NotChecked=0, Total=17822 [2019-10-06 23:01:51,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-06 23:01:51,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-06 23:01:51,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-06 23:01:51,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-06 23:01:51,741 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-06 23:01:51,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:01:51,742 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-06 23:01:51,742 INFO L463 AbstractCegarLoop]: Interpolant automaton has 70 states. [2019-10-06 23:01:51,742 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-06 23:01:51,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-06 23:01:51,744 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:01:51,744 INFO L385 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:01:51,948 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:51,949 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:01:51,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:01:51,950 INFO L82 PathProgramCache]: Analyzing trace with hash -303923653, now seen corresponding path program 7 times [2019-10-06 23:01:51,950 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:01:51,950 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:51,951 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:51,951 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:01:51,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:01:52,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:53,328 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:01:53,329 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:01:53,329 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:01:53,329 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:01:53,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:01:53,599 INFO L256 TraceCheckSpWp]: Trace formula consists of 505 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-06 23:01:53,602 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:01:53,629 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:01:53,630 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:01:57,204 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:01:57,204 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:01:57,205 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:01:57,205 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:01:57,206 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:01:57,206 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:01:57,206 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:01:57,221 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:01:58,407 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:01:58,434 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:01:58,436 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:01:58,437 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:01:58,437 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 1000)) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|) (<= 1000 xor_~i~0)) [2019-10-06 23:01:58,437 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 23:01:58,437 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_prenex_1166 Int) (v_prenex_1165 Int) (v_xor_~res~0_BEFORE_RETURN_158 Int) (v_xor_~res~0_BEFORE_RETURN_157 Int)) (or (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1166 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1166 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (= (mod v_xor_~res~0_BEFORE_RETURN_157 4294967296) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_xor_~res~0_BEFORE_RETURN_157 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_158 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_158 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1165 4294967296) 2147483647))))) (exists ((v_prenex_1166 Int) (v_prenex_1165 Int) (v_xor_~res~0_BEFORE_RETURN_158 Int) (v_xor_~res~0_BEFORE_RETURN_157 Int)) (or (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_xor_~res~0_BEFORE_RETURN_158 4294967296) 2147483647) (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_158 4294967296)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1166 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1166 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (= (mod v_xor_~res~0_BEFORE_RETURN_157 4294967296) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_xor_~res~0_BEFORE_RETURN_157 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (= (+ (mod v_prenex_1165 4294967296) (- 4294967296)) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1165 4294967296) 2147483647)))))) [2019-10-06 23:01:58,437 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:01:58,438 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:01:58,438 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:01:58,438 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:01:58,438 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:58,438 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:58,438 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:01:58,439 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:01:58,439 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:01:58,439 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 23:01:58,439 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1166 Int) (v_xor_~res~0_BEFORE_RETURN_158 Int)) (or (and (not (< main_~i~1 1000)) (= |main_#t~ret5| (mod v_xor_~res~0_BEFORE_RETURN_158 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_158 4294967296) 2147483647)) (and (= (+ (mod v_prenex_1166 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 1000)) (not (<= (mod v_prenex_1166 4294967296) 2147483647))))) (exists ((v_prenex_1165 Int) (v_xor_~res~0_BEFORE_RETURN_157 Int)) (or (and (= |main_#t~ret5| (+ (mod v_prenex_1165 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (not (<= (mod v_prenex_1165 4294967296) 2147483647))) (and (= (mod v_xor_~res~0_BEFORE_RETURN_157 4294967296) |main_#t~ret5|) (not (< main_~i~1 1000)) (<= (mod v_xor_~res~0_BEFORE_RETURN_157 4294967296) 2147483647))))) [2019-10-06 23:01:58,439 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:01:58,439 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:01:58,440 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_161 Int) (v_xor_~res~0_BEFORE_RETURN_162 Int) (v_prenex_1194 Int) (v_prenex_1193 Int)) (or (and (<= (mod v_prenex_1193 4294967296) 2147483647) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_prenex_1194 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_161 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0))))) (and (exists ((v_xor_~res~0_BEFORE_RETURN_161 Int) (v_xor_~res~0_BEFORE_RETURN_162 Int) (v_prenex_1194 Int) (v_prenex_1193 Int)) (or (and (<= (mod v_prenex_1193 4294967296) 2147483647) (= (mod v_prenex_1193 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_162 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_162 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_prenex_1194 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1194 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_161 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_161 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 23:01:58,440 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:01:58,440 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:01:59,086 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:01:59,087 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 11] total 127 [2019-10-06 23:01:59,088 INFO L442 AbstractCegarLoop]: Interpolant automaton has 128 states [2019-10-06 23:01:59,090 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 128 interpolants. [2019-10-06 23:01:59,093 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6815, Invalid=9441, Unknown=0, NotChecked=0, Total=16256 [2019-10-06 23:01:59,094 INFO L87 Difference]: Start difference. First operand 83 states and 87 transitions. Second operand 128 states. [2019-10-06 23:02:09,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:02:09,119 INFO L93 Difference]: Finished difference Result 162 states and 227 transitions. [2019-10-06 23:02:09,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 127 states. [2019-10-06 23:02:09,120 INFO L78 Accepts]: Start accepts. Automaton has 128 states. Word has length 96 [2019-10-06 23:02:09,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:02:09,123 INFO L225 Difference]: With dead ends: 162 [2019-10-06 23:02:09,123 INFO L226 Difference]: Without dead ends: 141 [2019-10-06 23:02:09,129 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 471 GetRequests, 223 SyntacticMatches, 0 SemanticMatches, 248 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12078 ImplicationChecksByTransitivity, 14.7s TimeCoverageRelationStatistics Valid=20208, Invalid=42042, Unknown=0, NotChecked=0, Total=62250 [2019-10-06 23:02:09,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2019-10-06 23:02:09,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2019-10-06 23:02:09,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2019-10-06 23:02:09,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 145 transitions. [2019-10-06 23:02:09,145 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 145 transitions. Word has length 96 [2019-10-06 23:02:09,145 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:02:09,145 INFO L462 AbstractCegarLoop]: Abstraction has 141 states and 145 transitions. [2019-10-06 23:02:09,145 INFO L463 AbstractCegarLoop]: Interpolant automaton has 128 states. [2019-10-06 23:02:09,146 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 145 transitions. [2019-10-06 23:02:09,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2019-10-06 23:02:09,148 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:02:09,148 INFO L385 BasicCegarLoop]: trace histogram [114, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:02:09,352 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:09,353 INFO L410 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:02:09,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:02:09,353 INFO L82 PathProgramCache]: Analyzing trace with hash 1666919067, now seen corresponding path program 8 times [2019-10-06 23:02:09,353 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:02:09,354 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:09,354 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:09,354 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:09,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:02:09,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:02:14,480 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 0 proven. 6555 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-06 23:02:14,480 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:14,480 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:02:14,480 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:14,765 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-06 23:02:14,766 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:02:14,767 INFO L256 TraceCheckSpWp]: Trace formula consists of 141 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 23:02:14,770 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:02:15,045 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 23:02:15,045 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:02:15,332 INFO L134 CoverageAnalysis]: Checked inductivity of 6676 backedges. 52 proven. 10 refuted. 0 times theorem prover too weak. 6614 trivial. 0 not checked. [2019-10-06 23:02:15,333 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:02:15,334 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:02:15,334 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:02:15,335 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:02:15,335 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:02:15,335 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:02:15,354 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:02:16,641 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:02:16,669 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:02:16,671 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:02:16,672 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:02:16,672 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 1000)) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|) (<= 1000 xor_~i~0)) [2019-10-06 23:02:16,672 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 23:02:16,672 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_1359 Int) (v_xor_~res~0_BEFORE_RETURN_183 Int) (v_xor_~res~0_BEFORE_RETURN_184 Int) (v_prenex_1360 Int)) (or (and (= main_~ret~0 (mod v_prenex_1359 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1359 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_1360 4294967296)) (<= main_~ret~0 2147483647) (<= (mod v_prenex_1360 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_184 4294967296) 2147483647)) (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_184 4294967296) (- 4294967296)))) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)) main_~ret~0) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_183 4294967296) 2147483647))))) [2019-10-06 23:02:16,672 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:02:16,673 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:02:16,673 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:02:16,673 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:02:16,673 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:16,673 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:16,673 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:16,674 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:02:16,674 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:02:16,674 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 23:02:16,674 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1359 Int) (v_xor_~res~0_BEFORE_RETURN_183 Int)) (or (and (not (< main_~i~1 1000)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_183 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_183 4294967296) 2147483647))) (and (not (< main_~i~1 1000)) (= (mod v_prenex_1359 4294967296) |main_#t~ret5|) (<= (mod v_prenex_1359 4294967296) 2147483647)))) (exists ((v_xor_~res~0_BEFORE_RETURN_184 Int) (v_prenex_1360 Int)) (or (and (= (mod v_prenex_1360 4294967296) |main_#t~ret5|) (not (< main_~i~1 1000)) (<= (mod v_prenex_1360 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_184 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_184 4294967296) 2147483647)))))) [2019-10-06 23:02:16,675 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:02:16,675 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:02:16,675 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_xor_~res~0_BEFORE_RETURN_187 Int) (v_xor_~res~0_BEFORE_RETURN_188 Int)) (or (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_188 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_187 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_1388 4294967296) 2147483647)) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0))))) (and (exists ((v_prenex_1388 Int) (v_prenex_1387 Int) (v_xor_~res~0_BEFORE_RETURN_187 Int) (v_xor_~res~0_BEFORE_RETURN_188 Int)) (or (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_188 4294967296) 2147483647)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_188 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_187 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_187 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= (mod v_prenex_1388 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_prenex_1388 4294967296) 2147483647)) (and (= (mod v_prenex_1387 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= (mod v_prenex_1387 4294967296) 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-06 23:02:16,675 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:02:16,675 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:02:19,796 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:02:19,797 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [117, 7, 7, 11] total 137 [2019-10-06 23:02:19,798 INFO L442 AbstractCegarLoop]: Interpolant automaton has 138 states [2019-10-06 23:02:19,799 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 138 interpolants. [2019-10-06 23:02:19,800 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6880, Invalid=12025, Unknown=1, NotChecked=0, Total=18906 [2019-10-06 23:02:19,801 INFO L87 Difference]: Start difference. First operand 141 states and 145 transitions. Second operand 138 states. [2019-10-06 23:02:33,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:02:33,262 INFO L93 Difference]: Finished difference Result 169 states and 186 transitions. [2019-10-06 23:02:33,262 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 138 states. [2019-10-06 23:02:33,263 INFO L78 Accepts]: Start accepts. Automaton has 138 states. Word has length 154 [2019-10-06 23:02:33,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:02:33,264 INFO L225 Difference]: With dead ends: 169 [2019-10-06 23:02:33,264 INFO L226 Difference]: Without dead ends: 148 [2019-10-06 23:02:33,268 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 711 GetRequests, 442 SyntacticMatches, 0 SemanticMatches, 269 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12311 ImplicationChecksByTransitivity, 20.3s TimeCoverageRelationStatistics Valid=20694, Invalid=52475, Unknown=1, NotChecked=0, Total=73170 [2019-10-06 23:02:33,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2019-10-06 23:02:33,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 148. [2019-10-06 23:02:33,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2019-10-06 23:02:33,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 152 transitions. [2019-10-06 23:02:33,284 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 152 transitions. Word has length 154 [2019-10-06 23:02:33,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:02:33,284 INFO L462 AbstractCegarLoop]: Abstraction has 148 states and 152 transitions. [2019-10-06 23:02:33,284 INFO L463 AbstractCegarLoop]: Interpolant automaton has 138 states. [2019-10-06 23:02:33,285 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 152 transitions. [2019-10-06 23:02:33,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2019-10-06 23:02:33,287 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:02:33,287 INFO L385 BasicCegarLoop]: trace histogram [115, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:02:33,491 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:33,491 INFO L410 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:02:33,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:02:33,492 INFO L82 PathProgramCache]: Analyzing trace with hash -1390264614, now seen corresponding path program 9 times [2019-10-06 23:02:33,492 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:02:33,493 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:33,493 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:33,493 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:02:33,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:02:33,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:02:38,525 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 23:02:38,526 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:02:38,526 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:02:38,526 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:02:38,951 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 23:02:38,951 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:02:38,956 INFO L256 TraceCheckSpWp]: Trace formula consists of 913 conjuncts, 117 conjunts are in the unsatisfiable core [2019-10-06 23:02:38,961 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:02:39,004 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 23:02:39,005 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:02:53,551 INFO L134 CoverageAnalysis]: Checked inductivity of 7214 backedges. 0 proven. 6670 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 23:02:53,551 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:02:53,552 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:02:53,552 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:02:53,553 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:02:53,553 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:02:53,553 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:02:53,569 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:02:54,738 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:02:54,779 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:02:54,782 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:02:54,782 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:02:54,783 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 1000)) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|) (<= 1000 xor_~i~0)) [2019-10-06 23:02:54,783 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 23:02:54,783 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_1554 Int) (v_prenex_1553 Int) (v_xor_~res~0_BEFORE_RETURN_209 Int) (v_xor_~res~0_BEFORE_RETURN_210 Int)) (or (and (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1554 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (= (mod v_xor_~res~0_BEFORE_RETURN_209 4294967296) main_~ret~0) (<= (mod v_xor_~res~0_BEFORE_RETURN_209 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_prenex_1553 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1553 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_xor_~res~0_BEFORE_RETURN_210 4294967296) main_~ret~0) (<= main_~ret~0 2147483647)))) [2019-10-06 23:02:54,783 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:02:54,783 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:02:54,783 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:02:54,784 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:02:54,784 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:54,784 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-06 23:02:54,784 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:02:54,784 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:02:54,784 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:02:54,785 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 23:02:54,785 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1554 Int) (v_xor_~res~0_BEFORE_RETURN_210 Int)) (or (and (<= (mod v_xor_~res~0_BEFORE_RETURN_210 4294967296) 2147483647) (not (< main_~i~1 1000)) (= (mod v_xor_~res~0_BEFORE_RETURN_210 4294967296) |main_#t~ret5|)) (and (= (+ (mod v_prenex_1554 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 1000)) (not (<= (mod v_prenex_1554 4294967296) 2147483647))))) (exists ((v_prenex_1553 Int) (v_xor_~res~0_BEFORE_RETURN_209 Int)) (or (and (= (mod v_xor_~res~0_BEFORE_RETURN_209 4294967296) |main_#t~ret5|) (not (< main_~i~1 1000)) (<= (mod v_xor_~res~0_BEFORE_RETURN_209 4294967296) 2147483647)) (and (not (< main_~i~1 1000)) (not (<= (mod v_prenex_1553 4294967296) 2147483647)) (= (+ (mod v_prenex_1553 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-06 23:02:54,785 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:02:54,785 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:02:54,785 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_xor_~res~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int) (v_xor_~res~0_BEFORE_RETURN_213 Int)) (or (and (= main_~ret5~0 (mod v_prenex_1581 4294967296)) (<= (mod v_prenex_1581 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_prenex_1582 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_214 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_214 4294967296) (- 4294967296)) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_213 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_213 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_214 Int) (v_prenex_1582 Int) (v_prenex_1581 Int) (v_xor_~res~0_BEFORE_RETURN_213 Int)) (or (and (= main_~ret5~0 (mod v_prenex_1581 4294967296)) (<= (mod v_prenex_1581 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_prenex_1582 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (mod v_prenex_1582 4294967296)) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_214 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_214 4294967296) (- 4294967296)) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_213 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_213 4294967296) (- 4294967296)) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))))) [2019-10-06 23:02:54,786 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:02:54,786 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:02:55,945 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:02:55,947 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [118, 118, 118, 11] total 245 [2019-10-06 23:02:55,948 INFO L442 AbstractCegarLoop]: Interpolant automaton has 246 states [2019-10-06 23:02:55,953 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 246 interpolants. [2019-10-06 23:02:55,955 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27524, Invalid=32746, Unknown=0, NotChecked=0, Total=60270 [2019-10-06 23:02:55,956 INFO L87 Difference]: Start difference. First operand 148 states and 152 transitions. Second operand 246 states. [2019-10-06 23:03:33,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:03:33,424 INFO L93 Difference]: Finished difference Result 292 states and 416 transitions. [2019-10-06 23:03:33,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 245 states. [2019-10-06 23:03:33,424 INFO L78 Accepts]: Start accepts. Automaton has 246 states. Word has length 173 [2019-10-06 23:03:33,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:03:33,426 INFO L225 Difference]: With dead ends: 292 [2019-10-06 23:03:33,427 INFO L226 Difference]: Without dead ends: 265 [2019-10-06 23:03:33,435 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 879 GetRequests, 395 SyntacticMatches, 0 SemanticMatches, 484 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41637 ImplicationChecksByTransitivity, 53.8s TimeCoverageRelationStatistics Valid=82099, Invalid=153611, Unknown=0, NotChecked=0, Total=235710 [2019-10-06 23:03:33,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2019-10-06 23:03:33,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 265. [2019-10-06 23:03:33,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2019-10-06 23:03:33,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 269 transitions. [2019-10-06 23:03:33,459 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 269 transitions. Word has length 173 [2019-10-06 23:03:33,459 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:03:33,459 INFO L462 AbstractCegarLoop]: Abstraction has 265 states and 269 transitions. [2019-10-06 23:03:33,459 INFO L463 AbstractCegarLoop]: Interpolant automaton has 246 states. [2019-10-06 23:03:33,460 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 269 transitions. [2019-10-06 23:03:33,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2019-10-06 23:03:33,463 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:03:33,464 INFO L385 BasicCegarLoop]: trace histogram [232, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:03:33,669 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:03:33,670 INFO L410 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:03:33,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:03:33,670 INFO L82 PathProgramCache]: Analyzing trace with hash -376060421, now seen corresponding path program 10 times [2019-10-06 23:03:33,671 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:03:33,671 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:03:33,671 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:03:33,671 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:03:33,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:03:34,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:03:53,603 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 23:03:53,604 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:03:53,604 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:03:53,604 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:03:54,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:03:54,181 INFO L256 TraceCheckSpWp]: Trace formula consists of 1615 conjuncts, 234 conjunts are in the unsatisfiable core [2019-10-06 23:03:54,187 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:03:54,286 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 23:03:54,287 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:04:53,439 INFO L134 CoverageAnalysis]: Checked inductivity of 27572 backedges. 0 proven. 27028 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 23:04:53,440 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:04:53,441 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:04:53,441 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:04:53,442 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:04:53,442 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:04:53,442 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:04:53,477 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:04:54,547 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:04:54,567 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:04:54,570 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:04:54,570 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:04:54,570 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 1000)) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|) (<= 1000 xor_~i~0)) [2019-10-06 23:04:54,570 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 23:04:54,570 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_xor_~res~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int) (v_prenex_1747 Int) (v_xor_~res~0_BEFORE_RETURN_235 Int)) (or (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1748 4294967296) 2147483647) (<= main_~ret~0 2147483647) (= (mod v_prenex_1748 4294967296) main_~ret~0)) (and (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_1747 4294967296) 2147483647) (= main_~ret~0 (mod v_prenex_1747 4294967296)) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_236 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_236 4294967296) (- 4294967296)))) (and (= main_~ret~0 (+ (mod v_xor_~res~0_BEFORE_RETURN_235 4294967296) (- 4294967296))) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_235 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-06 23:04:54,570 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:04:54,571 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:04:54,571 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:04:54,571 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:04:54,571 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:04:54,571 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:04:54,571 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:04:54,571 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:04:54,572 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:04:54,572 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 23:04:54,572 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1747 Int) (v_xor_~res~0_BEFORE_RETURN_235 Int)) (or (and (not (< main_~i~1 1000)) (= |main_#t~ret5| (mod v_prenex_1747 4294967296)) (<= (mod v_prenex_1747 4294967296) 2147483647)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_235 4294967296) 2147483647)) (not (< main_~i~1 1000)) (= |main_#t~ret5| (+ (mod v_xor_~res~0_BEFORE_RETURN_235 4294967296) (- 4294967296)))))) (exists ((v_xor_~res~0_BEFORE_RETURN_236 Int) (v_prenex_1748 Int)) (or (and (= (+ (mod v_xor_~res~0_BEFORE_RETURN_236 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_236 4294967296) 2147483647)) (not (< main_~i~1 1000))) (and (not (< main_~i~1 1000)) (<= (mod v_prenex_1748 4294967296) 2147483647) (= (mod v_prenex_1748 4294967296) |main_#t~ret5|))))) [2019-10-06 23:04:54,572 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:04:54,572 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:04:54,573 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_xor_~res~0_BEFORE_RETURN_239 Int) (v_prenex_1776 Int) (v_prenex_1775 Int) (v_xor_~res~0_BEFORE_RETURN_240 Int)) (or (and (not (<= (mod v_prenex_1775 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1775 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= (mod v_xor_~res~0_BEFORE_RETURN_240 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_xor_~res~0_BEFORE_RETURN_240 4294967296) 2147483647)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_239 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= (mod v_xor_~res~0_BEFORE_RETURN_239 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1776 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1776 4294967296) (- 4294967296)) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_xor_~res~0_BEFORE_RETURN_239 Int) (v_prenex_1776 Int) (v_prenex_1775 Int) (v_xor_~res~0_BEFORE_RETURN_240 Int)) (or (and (not (<= (mod v_prenex_1775 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_prenex_1775 4294967296) (- 4294967296))) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= (mod v_xor_~res~0_BEFORE_RETURN_240 4294967296) main_~ret5~0) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (<= (mod v_xor_~res~0_BEFORE_RETURN_240 4294967296) 2147483647)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_239 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= (mod v_xor_~res~0_BEFORE_RETURN_239 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (not (<= (mod v_prenex_1776 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_prenex_1776 4294967296) (- 4294967296)) main_~ret5~0) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)))))) [2019-10-06 23:04:54,573 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:04:54,573 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:04:56,466 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:04:56,466 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [235, 235, 235, 11] total 479 [2019-10-06 23:04:56,468 INFO L442 AbstractCegarLoop]: Interpolant automaton has 480 states [2019-10-06 23:04:56,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 480 interpolants. [2019-10-06 23:04:56,483 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=109775, Invalid=120145, Unknown=0, NotChecked=0, Total=229920 [2019-10-06 23:04:56,483 INFO L87 Difference]: Start difference. First operand 265 states and 269 transitions. Second operand 480 states. [2019-10-06 23:07:14,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:07:14,251 INFO L93 Difference]: Finished difference Result 526 states and 767 transitions. [2019-10-06 23:07:14,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 479 states. [2019-10-06 23:07:14,251 INFO L78 Accepts]: Start accepts. Automaton has 480 states. Word has length 290 [2019-10-06 23:07:14,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:07:14,255 INFO L225 Difference]: With dead ends: 526 [2019-10-06 23:07:14,255 INFO L226 Difference]: Without dead ends: 499 [2019-10-06 23:07:14,280 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 1581 GetRequests, 629 SyntacticMatches, 0 SemanticMatches, 952 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151734 ImplicationChecksByTransitivity, 203.9s TimeCoverageRelationStatistics Valid=328384, Invalid=580778, Unknown=0, NotChecked=0, Total=909162 [2019-10-06 23:07:14,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 499 states. [2019-10-06 23:07:14,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 499 to 499. [2019-10-06 23:07:14,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 499 states. [2019-10-06 23:07:14,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 499 states to 499 states and 503 transitions. [2019-10-06 23:07:14,312 INFO L78 Accepts]: Start accepts. Automaton has 499 states and 503 transitions. Word has length 290 [2019-10-06 23:07:14,313 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:07:14,313 INFO L462 AbstractCegarLoop]: Abstraction has 499 states and 503 transitions. [2019-10-06 23:07:14,313 INFO L463 AbstractCegarLoop]: Interpolant automaton has 480 states. [2019-10-06 23:07:14,313 INFO L276 IsEmpty]: Start isEmpty. Operand 499 states and 503 transitions. [2019-10-06 23:07:14,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 525 [2019-10-06 23:07:14,324 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:07:14,325 INFO L385 BasicCegarLoop]: trace histogram [466, 30, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:07:14,530 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:07:14,531 INFO L410 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:07:14,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:07:14,531 INFO L82 PathProgramCache]: Analyzing trace with hash 1055125339, now seen corresponding path program 11 times [2019-10-06 23:07:14,532 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:07:14,532 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:07:14,532 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:07:14,532 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:07:14,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:07:16,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:08:33,798 INFO L134 CoverageAnalysis]: Checked inductivity of 109355 backedges. 0 proven. 108811 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2019-10-06 23:08:33,798 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:08:33,798 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:08:33,798 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:08:34,318 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2019-10-06 23:08:34,318 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:08:34,320 INFO L256 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 6 conjunts are in the unsatisfiable core [2019-10-06 23:08:34,329 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:08:35,812 INFO L134 CoverageAnalysis]: Checked inductivity of 109355 backedges. 246 proven. 10 refuted. 0 times theorem prover too weak. 109099 trivial. 0 not checked. [2019-10-06 23:08:35,813 INFO L322 TraceCheckSpWp]: Computing backward predicates... [2019-10-06 23:08:36,847 INFO L134 CoverageAnalysis]: Checked inductivity of 109355 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 109345 trivial. 0 not checked. [2019-10-06 23:08:36,848 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [2019-10-06 23:08:36,849 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-06 23:08:36,849 INFO L169 IcfgInterpreter]: Building call graph [2019-10-06 23:08:36,850 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-06 23:08:36,850 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-06 23:08:36,850 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-06 23:08:36,880 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-06 23:08:38,086 INFO L199 IcfgInterpreter]: Interpreting procedure xor with input of size 1 for LOIs [2019-10-06 23:08:38,110 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-06 23:08:38,120 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-06 23:08:38,121 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-06 23:08:38,121 INFO L193 IcfgInterpreter]: Reachable states at location xorEXIT satisfy 644#(and (not (< xor_~i~0 1000)) (<= 1 xor_~i~0) (= (ite (<= (mod xor_~res~0 4294967296) 2147483647) (mod xor_~res~0 4294967296) (+ (mod xor_~res~0 4294967296) (- 4294967296))) |xor_#res|) (<= 1000 xor_~i~0)) [2019-10-06 23:08:38,121 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (<= 1000 main_~i~1) (not (< main_~i~1 1000))) [2019-10-06 23:08:38,121 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_xor_~res~0_BEFORE_RETURN_262 Int) (v_xor_~res~0_BEFORE_RETURN_261 Int)) (or (and (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_261 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_261 4294967296) 2147483647)) (and (<= (mod v_prenex_1942 4294967296) 2147483647) (= (mod v_prenex_1942 4294967296) main_~ret~0) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (+ (mod v_prenex_1941 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_262 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_262 4294967296) (- 4294967296)) main_~ret~0)))) (exists ((v_prenex_1942 Int) (v_prenex_1941 Int) (v_xor_~res~0_BEFORE_RETURN_262 Int) (v_xor_~res~0_BEFORE_RETURN_261 Int)) (or (and (= (mod v_prenex_1942 4294967296) main_~ret~0) (<= (mod v_prenex_1942 4294967296) 2147483647) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (= main_~ret~0 (mod v_xor_~res~0_BEFORE_RETURN_261 4294967296)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (<= (mod v_xor_~res~0_BEFORE_RETURN_261 4294967296) 2147483647)) (and (= main_~ret~0 (+ (mod v_prenex_1941 4294967296) (- 4294967296))) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_xor_~res~0_BEFORE_RETURN_262 4294967296) 2147483647)) (not (< main_~i~1 1000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_xor_~res~0_BEFORE_RETURN_262 4294967296) (- 4294967296)) main_~ret~0))))) [2019-10-06 23:08:38,121 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-06 23:08:38,122 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-06 23:08:38,122 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 xor_~i~0) [2019-10-06 23:08:38,122 INFO L193 IcfgInterpreter]: Reachable states at location xorENTRY satisfy 601#true [2019-10-06 23:08:38,122 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:08:38,122 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:08:38,122 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-06 23:08:38,123 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-06 23:08:38,123 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-06 23:08:38,123 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 999)) (<= 999 main_~i~2) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) [2019-10-06 23:08:38,123 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_1941 Int) (v_xor_~res~0_BEFORE_RETURN_261 Int)) (or (and (not (< main_~i~1 1000)) (not (<= (mod v_prenex_1941 4294967296) 2147483647)) (= (+ (mod v_prenex_1941 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 1000)) (= |main_#t~ret5| (mod v_xor_~res~0_BEFORE_RETURN_261 4294967296)) (<= (mod v_xor_~res~0_BEFORE_RETURN_261 4294967296) 2147483647)))) (exists ((v_prenex_1942 Int) (v_xor_~res~0_BEFORE_RETURN_262 Int)) (or (and (not (< main_~i~1 1000)) (= |main_#t~ret5| (mod v_prenex_1942 4294967296)) (<= (mod v_prenex_1942 4294967296) 2147483647)) (and (= (+ (mod v_xor_~res~0_BEFORE_RETURN_262 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_xor_~res~0_BEFORE_RETURN_262 4294967296) 2147483647)) (not (< main_~i~1 1000)))))) [2019-10-06 23:08:38,123 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-06 23:08:38,123 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-06 23:08:38,124 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_1970 Int) (v_prenex_1969 Int) (v_xor_~res~0_BEFORE_RETURN_266 Int) (v_xor_~res~0_BEFORE_RETURN_265 Int)) (or (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_265 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_265 4294967296)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_prenex_1969 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1969 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_266 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_266 4294967296))))) (not (= main_~ret~0 main_~ret5~0))) (and (exists ((v_prenex_1970 Int) (v_prenex_1969 Int) (v_xor_~res~0_BEFORE_RETURN_266 Int) (v_xor_~res~0_BEFORE_RETURN_265 Int)) (or (and (not (<= (mod v_prenex_1970 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_prenex_1970 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_265 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_265 4294967296)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (= main_~ret5~0 (+ (mod v_prenex_1969 4294967296) (- 4294967296))) (not (<= (mod v_prenex_1969 4294967296) 2147483647)) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0)) (and (<= (mod v_xor_~res~0_BEFORE_RETURN_266 4294967296) 2147483647) (not (< main_~i~2 999)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 3996)) main_~temp~0) (= main_~ret5~0 (mod v_xor_~res~0_BEFORE_RETURN_266 4294967296))))) (not (= main_~ret~0 main_~ret2~0)))) [2019-10-06 23:08:38,124 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-06 23:08:38,124 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-06 23:08:41,840 INFO L211 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-06 23:08:41,841 INFO L224 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [469, 7, 7, 11] total 489 [2019-10-06 23:08:41,843 INFO L442 AbstractCegarLoop]: Interpolant automaton has 490 states [2019-10-06 23:08:41,853 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 490 interpolants. [2019-10-06 23:08:41,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=109840, Invalid=129770, Unknown=0, NotChecked=0, Total=239610 [2019-10-06 23:08:41,863 INFO L87 Difference]: Start difference. First operand 499 states and 503 transitions. Second operand 490 states. [2019-10-06 23:11:07,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-06 23:11:07,785 INFO L93 Difference]: Finished difference Result 533 states and 547 transitions. [2019-10-06 23:11:07,786 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 490 states. [2019-10-06 23:11:07,786 INFO L78 Accepts]: Start accepts. Automaton has 490 states. Word has length 524 [2019-10-06 23:11:07,787 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-06 23:11:07,790 INFO L225 Difference]: With dead ends: 533 [2019-10-06 23:11:07,790 INFO L226 Difference]: Without dead ends: 506 [2019-10-06 23:11:07,817 INFO L606 BasicCegarLoop]: 0 DeclaredPredicates, 2526 GetRequests, 1553 SyntacticMatches, 0 SemanticMatches, 973 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 131111 ImplicationChecksByTransitivity, 217.5s TimeCoverageRelationStatistics Valid=329534, Invalid=620116, Unknown=0, NotChecked=0, Total=949650 [2019-10-06 23:11:07,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 506 states. [2019-10-06 23:11:07,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 506 to 506. [2019-10-06 23:11:07,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 506 states. [2019-10-06 23:11:07,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 506 states to 506 states and 510 transitions. [2019-10-06 23:11:07,842 INFO L78 Accepts]: Start accepts. Automaton has 506 states and 510 transitions. Word has length 524 [2019-10-06 23:11:07,843 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-06 23:11:07,843 INFO L462 AbstractCegarLoop]: Abstraction has 506 states and 510 transitions. [2019-10-06 23:11:07,843 INFO L463 AbstractCegarLoop]: Interpolant automaton has 490 states. [2019-10-06 23:11:07,843 INFO L276 IsEmpty]: Start isEmpty. Operand 506 states and 510 transitions. [2019-10-06 23:11:07,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 532 [2019-10-06 23:11:07,847 INFO L377 BasicCegarLoop]: Found error trace [2019-10-06 23:11:07,847 INFO L385 BasicCegarLoop]: trace histogram [467, 30, 10, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-06 23:11:08,052 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:11:08,052 INFO L410 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-06 23:11:08,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-06 23:11:08,053 INFO L82 PathProgramCache]: Analyzing trace with hash 1259179194, now seen corresponding path program 12 times [2019-10-06 23:11:08,053 INFO L150 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-06 23:11:08,054 INFO L231 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:11:08,054 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:11:08,054 INFO L117 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-06 23:11:08,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-06 23:11:09,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-06 23:12:26,600 INFO L134 CoverageAnalysis]: Checked inductivity of 109867 backedges. 0 proven. 109278 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-10-06 23:12:26,601 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019-10-06 23:12:26,601 INFO L286 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019-10-06 23:12:26,601 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-06 23:12:27,549 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-06 23:12:27,549 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-06 23:12:27,576 INFO L256 TraceCheckSpWp]: Trace formula consists of 3049 conjuncts, 469 conjunts are in the unsatisfiable core [2019-10-06 23:12:27,589 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-06 23:12:27,890 INFO L134 CoverageAnalysis]: Checked inductivity of 109867 backedges. 0 proven. 109278 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-10-06 23:12:27,890 INFO L322 TraceCheckSpWp]: Computing backward predicates...