java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/array-crafted/bAnd3.i -------------------------------------------------------------------------------- This is Ultimate 0.1.24-f4eb214f-m [2019-10-13 21:30:35,389 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-13 21:30:35,392 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-13 21:30:35,410 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-13 21:30:35,411 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-13 21:30:35,413 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-13 21:30:35,415 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-13 21:30:35,424 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-13 21:30:35,429 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-13 21:30:35,431 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-13 21:30:35,433 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-13 21:30:35,434 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-13 21:30:35,434 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-13 21:30:35,436 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-13 21:30:35,437 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-13 21:30:35,437 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-13 21:30:35,438 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-13 21:30:35,439 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-13 21:30:35,440 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-13 21:30:35,442 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-13 21:30:35,444 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-13 21:30:35,445 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-13 21:30:35,446 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-13 21:30:35,446 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-13 21:30:35,448 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-10-13 21:30:35,455 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-13 21:30:35,456 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-13 21:30:35,457 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-13 21:30:35,458 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-13 21:30:35,472 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-13 21:30:35,472 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-13 21:30:35,473 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-13 21:30:35,474 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-13 21:30:35,474 INFO L138 SettingsManager]: * Use SBE=true [2019-10-13 21:30:35,474 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-13 21:30:35,474 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-13 21:30:35,475 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-13 21:30:35,475 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-13 21:30:35,475 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-13 21:30:35,475 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-13 21:30:35,475 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-13 21:30:35,475 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-13 21:30:35,476 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-13 21:30:35,476 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-13 21:30:35,476 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-13 21:30:35,476 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-13 21:30:35,476 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-13 21:30:35,477 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-13 21:30:35,477 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-13 21:30:35,477 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-13 21:30:35,477 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-13 21:30:35,478 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-13 21:30:35,478 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-13 21:30:35,478 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-13 21:30:35,479 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-13 21:30:35,479 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-13 21:30:35,479 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-13 21:30:35,479 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-13 21:30:35,784 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-13 21:30:35,797 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-13 21:30:35,800 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-13 21:30:35,801 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-13 21:30:35,802 INFO L275 PluginConnector]: CDTParser initialized [2019-10-13 21:30:35,803 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-crafted/bAnd3.i [2019-10-13 21:30:35,864 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/301f4a232/7dae29d601d54e8c81629b587af4a56b/FLAGdbc922320 [2019-10-13 21:30:36,306 INFO L306 CDTParser]: Found 1 translation units. [2019-10-13 21:30:36,307 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/array-crafted/bAnd3.i [2019-10-13 21:30:36,314 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/301f4a232/7dae29d601d54e8c81629b587af4a56b/FLAGdbc922320 [2019-10-13 21:30:36,658 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/301f4a232/7dae29d601d54e8c81629b587af4a56b [2019-10-13 21:30:36,667 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-13 21:30:36,669 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-13 21:30:36,670 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-13 21:30:36,670 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-13 21:30:36,673 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-13 21:30:36,674 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 09:30:36" (1/1) ... [2019-10-13 21:30:36,677 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@62a266f5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 09:30:36, skipping insertion in model container [2019-10-13 21:30:36,677 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.10 09:30:36" (1/1) ... [2019-10-13 21:30:36,684 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-13 21:30:36,701 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-13 21:30:36,902 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-13 21:30:36,916 INFO L188 MainTranslator]: Completed pre-run [2019-10-13 21:30:36,948 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-13 21:30:37,048 INFO L192 MainTranslator]: Completed translation [2019-10-13 21:30:37,048 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 09:30:37 WrapperNode [2019-10-13 21:30:37,048 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-13 21:30:37,049 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-13 21:30:37,049 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-13 21:30:37,049 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-13 21:30:37,059 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 09:30:37" (1/1) ... [2019-10-13 21:30:37,059 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 09:30:37" (1/1) ... [2019-10-13 21:30:37,067 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 09:30:37" (1/1) ... [2019-10-13 21:30:37,067 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 09:30:37" (1/1) ... [2019-10-13 21:30:37,077 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 09:30:37" (1/1) ... [2019-10-13 21:30:37,082 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 09:30:37" (1/1) ... [2019-10-13 21:30:37,084 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 09:30:37" (1/1) ... [2019-10-13 21:30:37,086 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-13 21:30:37,086 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-13 21:30:37,087 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-13 21:30:37,087 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-13 21:30:37,088 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 09:30:37" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-13 21:30:37,140 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-13 21:30:37,140 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-13 21:30:37,141 INFO L138 BoogieDeclarations]: Found implementation of procedure bAnd [2019-10-13 21:30:37,141 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-13 21:30:37,141 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-13 21:30:37,141 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-13 21:30:37,141 INFO L130 BoogieDeclarations]: Found specification of procedure bAnd [2019-10-13 21:30:37,142 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-10-13 21:30:37,142 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-13 21:30:37,142 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-10-13 21:30:37,142 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-10-13 21:30:37,142 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-10-13 21:30:37,142 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-13 21:30:37,143 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-13 21:30:37,537 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-13 21:30:37,537 INFO L284 CfgBuilder]: Removed 3 assume(true) statements. [2019-10-13 21:30:37,539 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 09:30:37 BoogieIcfgContainer [2019-10-13 21:30:37,539 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-13 21:30:37,540 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-13 21:30:37,540 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-13 21:30:37,543 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-13 21:30:37,543 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 13.10 09:30:36" (1/3) ... [2019-10-13 21:30:37,544 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@58f7c0e5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.10 09:30:37, skipping insertion in model container [2019-10-13 21:30:37,544 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.10 09:30:37" (2/3) ... [2019-10-13 21:30:37,545 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@58f7c0e5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.10 09:30:37, skipping insertion in model container [2019-10-13 21:30:37,545 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.10 09:30:37" (3/3) ... [2019-10-13 21:30:37,547 INFO L109 eAbstractionObserver]: Analyzing ICFG bAnd3.i [2019-10-13 21:30:37,561 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-13 21:30:37,569 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-13 21:30:37,581 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-13 21:30:37,607 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-13 21:30:37,607 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-13 21:30:37,607 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-13 21:30:37,607 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-13 21:30:37,607 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-13 21:30:37,608 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-13 21:30:37,608 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-13 21:30:37,608 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-13 21:30:37,625 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2019-10-13 21:30:37,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-10-13 21:30:37,631 INFO L372 BasicCegarLoop]: Found error trace [2019-10-13 21:30:37,632 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-13 21:30:37,634 INFO L410 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-13 21:30:37,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-13 21:30:37,639 INFO L82 PathProgramCache]: Analyzing trace with hash -1674969442, now seen corresponding path program 1 times [2019-10-13 21:30:37,646 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-13 21:30:37,646 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027210306] [2019-10-13 21:30:37,646 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:37,646 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:37,646 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-13 21:30:37,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:30:37,819 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-13 21:30:37,819 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027210306] [2019-10-13 21:30:37,822 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-13 21:30:37,823 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-13 21:30:37,823 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1290814456] [2019-10-13 21:30:37,828 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-13 21:30:37,828 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-13 21:30:37,841 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-13 21:30:37,841 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-13 21:30:37,843 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 3 states. [2019-10-13 21:30:37,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-13 21:30:37,878 INFO L93 Difference]: Finished difference Result 41 states and 51 transitions. [2019-10-13 21:30:37,878 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-13 21:30:37,880 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 24 [2019-10-13 21:30:37,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-13 21:30:37,889 INFO L225 Difference]: With dead ends: 41 [2019-10-13 21:30:37,890 INFO L226 Difference]: Without dead ends: 20 [2019-10-13 21:30:37,893 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-13 21:30:37,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-10-13 21:30:37,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-10-13 21:30:37,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-10-13 21:30:37,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2019-10-13 21:30:37,939 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 24 [2019-10-13 21:30:37,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-13 21:30:37,940 INFO L462 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2019-10-13 21:30:37,940 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-13 21:30:37,940 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2019-10-13 21:30:37,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-10-13 21:30:37,942 INFO L372 BasicCegarLoop]: Found error trace [2019-10-13 21:30:37,943 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-13 21:30:37,943 INFO L410 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-13 21:30:37,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-13 21:30:37,944 INFO L82 PathProgramCache]: Analyzing trace with hash -2035795135, now seen corresponding path program 1 times [2019-10-13 21:30:37,944 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-13 21:30:37,944 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794348232] [2019-10-13 21:30:37,945 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:37,945 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:37,945 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-13 21:30:37,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:30:38,049 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-13 21:30:38,050 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794348232] [2019-10-13 21:30:38,050 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1686587154] [2019-10-13 21:30:38,050 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:38,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:30:38,144 INFO L256 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 2 conjunts are in the unsatisfiable core [2019-10-13 21:30:38,153 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-13 21:30:38,202 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-13 21:30:38,203 INFO L321 TraceCheckSpWp]: Computing backward predicates... [2019-10-13 21:30:38,264 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-13 21:30:38,265 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-13 21:30:38,265 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 5 [2019-10-13 21:30:38,265 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366572315] [2019-10-13 21:30:38,267 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-13 21:30:38,268 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-13 21:30:38,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-13 21:30:38,268 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-13 21:30:38,269 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand 3 states. [2019-10-13 21:30:38,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-13 21:30:38,280 INFO L93 Difference]: Finished difference Result 33 states and 43 transitions. [2019-10-13 21:30:38,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-13 21:30:38,280 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-10-13 21:30:38,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-13 21:30:38,282 INFO L225 Difference]: With dead ends: 33 [2019-10-13 21:30:38,282 INFO L226 Difference]: Without dead ends: 21 [2019-10-13 21:30:38,283 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-10-13 21:30:38,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2019-10-13 21:30:38,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-10-13 21:30:38,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-10-13 21:30:38,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2019-10-13 21:30:38,290 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 25 [2019-10-13 21:30:38,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-13 21:30:38,292 INFO L462 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2019-10-13 21:30:38,294 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-13 21:30:38,294 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2019-10-13 21:30:38,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-10-13 21:30:38,298 INFO L372 BasicCegarLoop]: Found error trace [2019-10-13 21:30:38,298 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-13 21:30:38,502 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:38,502 INFO L410 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-13 21:30:38,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-13 21:30:38,503 INFO L82 PathProgramCache]: Analyzing trace with hash -629127273, now seen corresponding path program 1 times [2019-10-13 21:30:38,504 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-13 21:30:38,504 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351240646] [2019-10-13 21:30:38,504 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:38,505 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:38,505 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-13 21:30:38,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:30:38,592 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-13 21:30:38,593 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1351240646] [2019-10-13 21:30:38,593 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-13 21:30:38,593 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-13 21:30:38,594 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1405664243] [2019-10-13 21:30:38,594 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-13 21:30:38,595 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-13 21:30:38,595 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-13 21:30:38,595 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-13 21:30:38,595 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand 3 states. [2019-10-13 21:30:38,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-13 21:30:38,612 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2019-10-13 21:30:38,613 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-13 21:30:38,614 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-10-13 21:30:38,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-13 21:30:38,615 INFO L225 Difference]: With dead ends: 31 [2019-10-13 21:30:38,615 INFO L226 Difference]: Without dead ends: 22 [2019-10-13 21:30:38,616 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-13 21:30:38,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2019-10-13 21:30:38,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2019-10-13 21:30:38,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-10-13 21:30:38,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 26 transitions. [2019-10-13 21:30:38,627 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 26 transitions. Word has length 28 [2019-10-13 21:30:38,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-13 21:30:38,631 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 26 transitions. [2019-10-13 21:30:38,631 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-13 21:30:38,631 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 26 transitions. [2019-10-13 21:30:38,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-10-13 21:30:38,634 INFO L372 BasicCegarLoop]: Found error trace [2019-10-13 21:30:38,634 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-13 21:30:38,635 INFO L410 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-13 21:30:38,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-13 21:30:38,635 INFO L82 PathProgramCache]: Analyzing trace with hash -1942163656, now seen corresponding path program 1 times [2019-10-13 21:30:38,636 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-13 21:30:38,636 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937621688] [2019-10-13 21:30:38,636 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:38,636 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:38,637 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-13 21:30:38,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:30:38,744 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-13 21:30:38,745 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937621688] [2019-10-13 21:30:38,745 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [764321119] [2019-10-13 21:30:38,746 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:38,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:30:38,845 INFO L256 TraceCheckSpWp]: Trace formula consists of 136 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-13 21:30:38,848 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-13 21:30:38,864 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-13 21:30:38,864 INFO L321 TraceCheckSpWp]: Computing backward predicates... [2019-10-13 21:30:38,910 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-13 21:30:38,910 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1023074654] [2019-10-13 21:30:38,938 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-13 21:30:38,938 INFO L169 IcfgInterpreter]: Building call graph [2019-10-13 21:30:38,945 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-13 21:30:38,953 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-13 21:30:38,954 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-13 21:30:39,119 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-13 21:30:41,204 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-13 21:30:41,242 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-13 21:30:41,247 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-13 21:30:41,247 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-13 21:30:41,247 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-13 21:30:41,248 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-13 21:30:41,248 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_2 Int) (v_bAnd_~res~0_BEFORE_RETURN_1 Int) (v_prenex_2 Int) (v_prenex_1 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~0)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_2 Int) (v_bAnd_~res~0_BEFORE_RETURN_1 Int) (v_prenex_2 Int) (v_prenex_1 Int)) (or (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) main_~ret~0) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_1 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) main_~ret~0))))) [2019-10-13 21:30:41,248 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-13 21:30:41,248 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-13 21:30:41,249 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_29 Int) (v_bAnd_~res~0_BEFORE_RETURN_6 Int) (v_bAnd_~res~0_BEFORE_RETURN_5 Int) (v_prenex_30 Int)) (or (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (not (< main_~i~2 9999)) (<= (mod v_prenex_30 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_prenex_29 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= (mod v_prenex_29 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)))))) (and (exists ((v_prenex_29 Int) (v_bAnd_~res~0_BEFORE_RETURN_6 Int) (v_bAnd_~res~0_BEFORE_RETURN_5 Int) (v_prenex_30 Int)) (or (and (= main_~ret5~0 (mod v_prenex_30 4294967296)) (not (< main_~i~2 9999)) (<= (mod v_prenex_30 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_6 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (<= (mod v_prenex_29 4294967296) 2147483647) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= (mod v_prenex_29 4294967296) main_~ret5~0) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_5 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-13 21:30:41,249 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:41,249 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:41,250 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:41,250 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-13 21:30:41,250 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-13 21:30:41,250 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-13 21:30:41,250 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-13 21:30:41,251 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-13 21:30:41,251 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_1 Int) (v_prenex_1 Int)) (or (and (not (< main_~i~1 10000)) (= (+ (mod v_prenex_1 4294967296) (- 4294967296)) |main_#t~ret5|) (not (<= (mod v_prenex_1 4294967296) 2147483647))) (and (<= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_1 4294967296) |main_#t~ret5|)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_2 Int) (v_prenex_2 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_2 4294967296) |main_#t~ret5|)) (and (not (<= (mod v_prenex_2 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (+ (mod v_prenex_2 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-13 21:30:41,251 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-13 21:30:41,251 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-13 21:30:41,252 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-13 21:30:41,252 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-13 21:30:41,654 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-13 21:30:41,654 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 11] total 17 [2019-10-13 21:30:41,654 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1831224877] [2019-10-13 21:30:41,656 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-10-13 21:30:41,657 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-13 21:30:41,658 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-10-13 21:30:41,659 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=256, Unknown=0, NotChecked=0, Total=306 [2019-10-13 21:30:41,659 INFO L87 Difference]: Start difference. First operand 22 states and 26 transitions. Second operand 18 states. [2019-10-13 21:30:42,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-13 21:30:42,364 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-10-13 21:30:42,364 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-10-13 21:30:42,364 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2019-10-13 21:30:42,364 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-13 21:30:42,365 INFO L225 Difference]: With dead ends: 40 [2019-10-13 21:30:42,365 INFO L226 Difference]: Without dead ends: 25 [2019-10-13 21:30:42,368 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=133, Invalid=737, Unknown=0, NotChecked=0, Total=870 [2019-10-13 21:30:42,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-10-13 21:30:42,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-10-13 21:30:42,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-10-13 21:30:42,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2019-10-13 21:30:42,378 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 29 [2019-10-13 21:30:42,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-13 21:30:42,379 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2019-10-13 21:30:42,379 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-10-13 21:30:42,379 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2019-10-13 21:30:42,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-10-13 21:30:42,381 INFO L372 BasicCegarLoop]: Found error trace [2019-10-13 21:30:42,382 INFO L380 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-13 21:30:42,594 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:42,594 INFO L410 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-13 21:30:42,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-13 21:30:42,594 INFO L82 PathProgramCache]: Analyzing trace with hash 143191253, now seen corresponding path program 2 times [2019-10-13 21:30:42,595 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-13 21:30:42,595 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604342798] [2019-10-13 21:30:42,595 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:42,595 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:42,595 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-13 21:30:42,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:30:42,715 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2019-10-13 21:30:42,716 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604342798] [2019-10-13 21:30:42,716 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [211577419] [2019-10-13 21:30:42,716 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:42,801 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-10-13 21:30:42,801 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-13 21:30:42,802 INFO L256 TraceCheckSpWp]: Trace formula consists of 106 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-13 21:30:42,804 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-13 21:30:42,821 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-13 21:30:42,821 INFO L321 TraceCheckSpWp]: Computing backward predicates... [2019-10-13 21:30:42,854 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 10 proven. 1 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-10-13 21:30:42,855 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [907715221] [2019-10-13 21:30:42,857 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-13 21:30:42,857 INFO L169 IcfgInterpreter]: Building call graph [2019-10-13 21:30:42,858 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-13 21:30:42,863 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-13 21:30:42,864 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-13 21:30:42,903 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-13 21:30:44,474 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-13 21:30:44,504 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-13 21:30:44,508 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-13 21:30:44,508 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-13 21:30:44,508 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-13 21:30:44,509 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-13 21:30:44,509 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_27 Int) (v_prenex_196 Int) (v_bAnd_~res~0_BEFORE_RETURN_28 Int) (v_prenex_195 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_195 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_195 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296))) (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) main_~ret~0)))) [2019-10-13 21:30:44,509 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-13 21:30:44,509 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-13 21:30:44,510 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_prenex_223 Int) (v_bAnd_~res~0_BEFORE_RETURN_32 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_31 Int) (v_prenex_224 Int) (v_prenex_223 Int) (v_bAnd_~res~0_BEFORE_RETURN_32 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_223 4294967296) 2147483647) (= (mod v_prenex_223 4294967296) main_~ret5~0)) (and (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) 2147483647)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_32 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_31 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_224 4294967296) 2147483647) (= main_~ret5~0 (mod v_prenex_224 4294967296))))))) [2019-10-13 21:30:44,510 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:44,510 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:44,510 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:44,510 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-13 21:30:44,511 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-13 21:30:44,511 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-13 21:30:44,511 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-13 21:30:44,511 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-13 21:30:44,511 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_bAnd_~res~0_BEFORE_RETURN_27 Int) (v_prenex_195 Int)) (or (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_27 4294967296) 2147483647)) (and (= (+ (mod v_prenex_195 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 10000)) (not (<= (mod v_prenex_195 4294967296) 2147483647))))) (exists ((v_prenex_196 Int) (v_bAnd_~res~0_BEFORE_RETURN_28 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_196 4294967296) 2147483647)) (= (+ (mod v_prenex_196 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296) 2147483647) (= (mod v_bAnd_~res~0_BEFORE_RETURN_28 4294967296) |main_#t~ret5|))))) [2019-10-13 21:30:44,512 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-13 21:30:44,512 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-13 21:30:44,512 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-13 21:30:44,512 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-13 21:30:44,883 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-13 21:30:44,883 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 11] total 21 [2019-10-13 21:30:44,883 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [28160601] [2019-10-13 21:30:44,884 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-10-13 21:30:44,884 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-13 21:30:44,885 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-10-13 21:30:44,885 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=398, Unknown=0, NotChecked=0, Total=462 [2019-10-13 21:30:44,885 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand 22 states. [2019-10-13 21:30:45,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-13 21:30:45,845 INFO L93 Difference]: Finished difference Result 44 states and 58 transitions. [2019-10-13 21:30:45,845 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-10-13 21:30:45,845 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 32 [2019-10-13 21:30:45,845 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-13 21:30:45,846 INFO L225 Difference]: With dead ends: 44 [2019-10-13 21:30:45,847 INFO L226 Difference]: Without dead ends: 29 [2019-10-13 21:30:45,849 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=210, Invalid=1272, Unknown=0, NotChecked=0, Total=1482 [2019-10-13 21:30:45,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-10-13 21:30:45,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-10-13 21:30:45,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-10-13 21:30:45,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2019-10-13 21:30:45,864 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 32 [2019-10-13 21:30:45,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-13 21:30:45,864 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2019-10-13 21:30:45,864 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-10-13 21:30:45,864 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2019-10-13 21:30:45,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-10-13 21:30:45,867 INFO L372 BasicCegarLoop]: Found error trace [2019-10-13 21:30:45,868 INFO L380 BasicCegarLoop]: trace histogram [12, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-13 21:30:46,071 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:46,072 INFO L410 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-13 21:30:46,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-13 21:30:46,072 INFO L82 PathProgramCache]: Analyzing trace with hash 766317228, now seen corresponding path program 3 times [2019-10-13 21:30:46,073 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-13 21:30:46,073 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659954803] [2019-10-13 21:30:46,073 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:46,074 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:46,074 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-13 21:30:46,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:30:46,186 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-13 21:30:46,186 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659954803] [2019-10-13 21:30:46,186 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [904716462] [2019-10-13 21:30:46,187 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:46,303 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-13 21:30:46,304 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-13 21:30:46,305 INFO L256 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 7 conjunts are in the unsatisfiable core [2019-10-13 21:30:46,308 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-13 21:30:46,325 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-13 21:30:46,326 INFO L321 TraceCheckSpWp]: Computing backward predicates... [2019-10-13 21:30:46,434 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-13 21:30:46,434 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [250098890] [2019-10-13 21:30:46,436 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-13 21:30:46,438 INFO L169 IcfgInterpreter]: Building call graph [2019-10-13 21:30:46,439 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-13 21:30:46,439 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-13 21:30:46,440 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-13 21:30:46,459 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-13 21:30:47,749 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-13 21:30:47,770 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-13 21:30:47,773 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-13 21:30:47,773 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-13 21:30:47,774 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-13 21:30:47,774 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-13 21:30:47,774 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_bAnd_~res~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int) (v_prenex_390 Int) (v_bAnd_~res~0_BEFORE_RETURN_54 Int)) (or (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) main_~ret~0) (<= main_~ret~0 2147483647) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= (+ (mod v_prenex_390 4294967296) (- 4294967296)) main_~ret~0) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) 2147483647)) (<= main_~ret~0 2147483647) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (= (mod v_prenex_389 4294967296) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_prenex_389 4294967296) 2147483647) (<= main_~ret~0 2147483647)))) [2019-10-13 21:30:47,774 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-13 21:30:47,774 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-13 21:30:47,775 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_58 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_bAnd_~res~0_BEFORE_RETURN_57 Int)) (or (and (not (< main_~i~2 9999)) (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) (- 4294967296)))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_418 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_418 4294967296) 2147483647)) (and (not (< main_~i~2 9999)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) 2147483647))))) (not (= main_~ret~0 main_~ret2~0))) (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_58 Int) (v_prenex_417 Int) (v_prenex_418 Int) (v_bAnd_~res~0_BEFORE_RETURN_57 Int)) (or (and (not (< main_~i~2 9999)) (= (mod v_prenex_417 4294967296) main_~ret5~0) (<= (mod v_prenex_417 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) 2147483647)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_58 4294967296) (- 4294967296)))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_418 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_418 4294967296) 2147483647)) (and (not (< main_~i~2 9999)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) (- 4294967296)) main_~ret5~0) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_57 4294967296) 2147483647))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-13 21:30:47,775 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:47,775 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:47,775 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:47,776 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-13 21:30:47,776 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-13 21:30:47,776 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-13 21:30:47,776 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-13 21:30:47,776 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-13 21:30:47,776 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_390 Int) (v_bAnd_~res~0_BEFORE_RETURN_54 Int)) (or (and (not (< main_~i~1 10000)) (= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) |main_#t~ret5|) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_54 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_390 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_prenex_390 4294967296) (- 4294967296)))))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_53 Int) (v_prenex_389 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) 2147483647)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_53 4294967296) (- 4294967296)))) (and (not (< main_~i~1 10000)) (<= (mod v_prenex_389 4294967296) 2147483647) (= (mod v_prenex_389 4294967296) |main_#t~ret5|))))) [2019-10-13 21:30:47,777 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-13 21:30:47,777 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-13 21:30:47,777 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-13 21:30:47,777 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-13 21:30:48,116 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-13 21:30:48,116 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 11] total 25 [2019-10-13 21:30:48,116 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537967215] [2019-10-13 21:30:48,119 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-10-13 21:30:48,120 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-13 21:30:48,120 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-10-13 21:30:48,121 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=516, Unknown=0, NotChecked=0, Total=650 [2019-10-13 21:30:48,121 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand 26 states. [2019-10-13 21:30:49,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-13 21:30:49,055 INFO L93 Difference]: Finished difference Result 54 states and 68 transitions. [2019-10-13 21:30:49,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-10-13 21:30:49,055 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 42 [2019-10-13 21:30:49,056 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-13 21:30:49,056 INFO L225 Difference]: With dead ends: 54 [2019-10-13 21:30:49,056 INFO L226 Difference]: Without dead ends: 36 [2019-10-13 21:30:49,058 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 112 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2019-10-13 21:30:49,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-10-13 21:30:49,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2019-10-13 21:30:49,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-10-13 21:30:49,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 40 transitions. [2019-10-13 21:30:49,065 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 40 transitions. Word has length 42 [2019-10-13 21:30:49,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-13 21:30:49,065 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 40 transitions. [2019-10-13 21:30:49,065 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-10-13 21:30:49,066 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 40 transitions. [2019-10-13 21:30:49,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-10-13 21:30:49,067 INFO L372 BasicCegarLoop]: Found error trace [2019-10-13 21:30:49,067 INFO L380 BasicCegarLoop]: trace histogram [12, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-13 21:30:49,270 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:49,271 INFO L410 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-13 21:30:49,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-13 21:30:49,272 INFO L82 PathProgramCache]: Analyzing trace with hash 615727983, now seen corresponding path program 4 times [2019-10-13 21:30:49,272 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-13 21:30:49,272 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141174744] [2019-10-13 21:30:49,273 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:49,273 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:49,273 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-13 21:30:49,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:30:49,447 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-13 21:30:49,447 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141174744] [2019-10-13 21:30:49,447 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1018146601] [2019-10-13 21:30:49,448 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:49,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:30:49,594 INFO L256 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 14 conjunts are in the unsatisfiable core [2019-10-13 21:30:49,597 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-13 21:30:49,611 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-13 21:30:49,611 INFO L321 TraceCheckSpWp]: Computing backward predicates... [2019-10-13 21:30:49,861 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-13 21:30:49,861 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [172021526] [2019-10-13 21:30:49,878 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-13 21:30:49,878 INFO L169 IcfgInterpreter]: Building call graph [2019-10-13 21:30:49,879 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-13 21:30:49,879 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-13 21:30:49,879 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-13 21:30:49,907 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-13 21:30:51,385 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-13 21:30:51,440 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-13 21:30:51,444 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-13 21:30:51,445 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-13 21:30:51,445 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-13 21:30:51,445 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-13 21:30:51,446 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_583 Int) (v_prenex_584 Int) (v_bAnd_~res~0_BEFORE_RETURN_80 Int) (v_bAnd_~res~0_BEFORE_RETURN_79 Int)) (or (and (not (< main_~i~1 10000)) (= main_~ret~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) 2147483647))) (and (not (< main_~i~1 10000)) (<= (mod v_prenex_583 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_prenex_583 4294967296)) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (mod v_prenex_584 4294967296) main_~ret~0) (<= (mod v_prenex_584 4294967296) 2147483647)) (and (not (< main_~i~1 10000)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) main_~ret~0) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-13 21:30:51,446 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-13 21:30:51,446 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-13 21:30:51,447 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_bAnd_~res~0_BEFORE_RETURN_83 Int) (v_bAnd_~res~0_BEFORE_RETURN_84 Int)) (or (and (not (< main_~i~2 9999)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) 2147483647)) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_611 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647))))) (not (= main_~ret~0 main_~ret5~0))) (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_611 Int) (v_prenex_612 Int) (v_bAnd_~res~0_BEFORE_RETURN_83 Int) (v_bAnd_~res~0_BEFORE_RETURN_84 Int)) (or (and (not (< main_~i~2 9999)) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) (- 4294967296))) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_83 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648))) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_84 4294967296) 2147483647)) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_611 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= main_~ret5~0 (mod v_prenex_611 4294967296))) (and (= (+ (mod v_prenex_612 4294967296) (- 4294967296)) main_~ret5~0) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_prenex_612 4294967296) 2147483647))))))) [2019-10-13 21:30:51,447 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:51,447 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:51,448 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:51,448 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-13 21:30:51,448 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-13 21:30:51,449 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-13 21:30:51,449 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-13 21:30:51,449 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-13 21:30:51,450 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_583 Int) (v_bAnd_~res~0_BEFORE_RETURN_79 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_prenex_583 4294967296) 2147483647) (= |main_#t~ret5| (mod v_prenex_583 4294967296))) (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (+ (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) (- 4294967296))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_79 4294967296) 2147483647))))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_80 Int) (v_prenex_584 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_80 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (= |main_#t~ret5| (mod v_prenex_584 4294967296)) (<= (mod v_prenex_584 4294967296) 2147483647))))) [2019-10-13 21:30:51,450 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-13 21:30:51,450 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-13 21:30:51,450 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-13 21:30:51,451 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-13 21:30:52,023 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-13 21:30:52,023 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 11] total 39 [2019-10-13 21:30:52,024 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [92638659] [2019-10-13 21:30:52,025 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-10-13 21:30:52,025 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-13 21:30:52,025 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-10-13 21:30:52,026 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=1125, Unknown=0, NotChecked=0, Total=1560 [2019-10-13 21:30:52,026 INFO L87 Difference]: Start difference. First operand 36 states and 40 transitions. Second operand 40 states. [2019-10-13 21:30:53,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-13 21:30:53,556 INFO L93 Difference]: Finished difference Result 68 states and 89 transitions. [2019-10-13 21:30:53,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-10-13 21:30:53,556 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 49 [2019-10-13 21:30:53,557 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-13 21:30:53,557 INFO L225 Difference]: With dead ends: 68 [2019-10-13 21:30:53,558 INFO L226 Difference]: Without dead ends: 50 [2019-10-13 21:30:53,560 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1364 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1244, Invalid=4158, Unknown=0, NotChecked=0, Total=5402 [2019-10-13 21:30:53,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-10-13 21:30:53,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2019-10-13 21:30:53,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-10-13 21:30:53,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2019-10-13 21:30:53,567 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 49 [2019-10-13 21:30:53,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-13 21:30:53,568 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2019-10-13 21:30:53,568 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-10-13 21:30:53,568 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2019-10-13 21:30:53,569 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-10-13 21:30:53,570 INFO L372 BasicCegarLoop]: Found error trace [2019-10-13 21:30:53,570 INFO L380 BasicCegarLoop]: trace histogram [26, 12, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-13 21:30:53,772 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:53,773 INFO L410 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-13 21:30:53,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-13 21:30:53,774 INFO L82 PathProgramCache]: Analyzing trace with hash 2121294031, now seen corresponding path program 5 times [2019-10-13 21:30:53,774 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-13 21:30:53,775 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745734885] [2019-10-13 21:30:53,775 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:53,775 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:53,775 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-13 21:30:53,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:30:54,208 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2019-10-13 21:30:54,208 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745734885] [2019-10-13 21:30:54,208 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2045891624] [2019-10-13 21:30:54,209 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:54,391 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-10-13 21:30:54,392 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-13 21:30:54,393 INFO L256 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-13 21:30:54,407 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-13 21:30:54,452 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 54 proven. 1 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2019-10-13 21:30:54,452 INFO L321 TraceCheckSpWp]: Computing backward predicates... [2019-10-13 21:30:54,509 INFO L134 CoverageAnalysis]: Checked inductivity of 463 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 462 trivial. 0 not checked. [2019-10-13 21:30:54,510 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [626988147] [2019-10-13 21:30:54,511 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-13 21:30:54,511 INFO L169 IcfgInterpreter]: Building call graph [2019-10-13 21:30:54,512 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-13 21:30:54,512 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-13 21:30:54,512 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-13 21:30:54,534 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-13 21:30:55,701 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-13 21:30:55,732 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-13 21:30:55,734 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-13 21:30:55,735 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-13 21:30:55,735 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-13 21:30:55,735 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-13 21:30:55,735 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(exists ((v_prenex_777 Int) (v_bAnd_~res~0_BEFORE_RETURN_106 Int) (v_bAnd_~res~0_BEFORE_RETURN_105 Int) (v_prenex_778 Int)) (or (and (not (<= (mod v_prenex_778 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) main_~ret~0)) (and (<= (mod v_prenex_777 4294967296) 2147483647) (not (< main_~i~1 10000)) (= main_~ret~0 (mod v_prenex_777 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) 2147483647)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) (- 4294967296)) main_~ret~0) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) [2019-10-13 21:30:55,736 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-13 21:30:55,736 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-13 21:30:55,736 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_prenex_806 Int) (v_prenex_805 Int) (v_bAnd_~res~0_BEFORE_RETURN_109 Int) (v_bAnd_~res~0_BEFORE_RETURN_110 Int)) (or (and (= main_~ret5~0 (mod v_prenex_805 4294967296)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (not (< main_~i~2 9999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) 2147483647)))))) (and (exists ((v_prenex_806 Int) (v_prenex_805 Int) (v_bAnd_~res~0_BEFORE_RETURN_109 Int) (v_bAnd_~res~0_BEFORE_RETURN_110 Int)) (or (and (= main_~ret5~0 (mod v_prenex_805 4294967296)) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_805 4294967296) 2147483647)) (and (not (< main_~i~2 9999)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) 2147483647)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_110 4294967296) (- 4294967296))) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~ret5~0 (mod v_prenex_806 4294967296)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (<= (mod v_prenex_806 4294967296) 2147483647)) (and (= main_~ret5~0 (+ (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) (- 4294967296))) (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_109 4294967296) 2147483647))))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-13 21:30:55,736 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:55,737 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0) (= 0 (select |old(#valid)| 0))) [2019-10-13 21:30:55,737 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:30:55,737 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-13 21:30:55,737 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-13 21:30:55,737 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-13 21:30:55,737 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-13 21:30:55,738 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-13 21:30:55,738 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_777 Int) (v_bAnd_~res~0_BEFORE_RETURN_105 Int)) (or (and (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) (- 4294967296)) |main_#t~ret5|) (not (< main_~i~1 10000)) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_105 4294967296) 2147483647))) (and (<= (mod v_prenex_777 4294967296) 2147483647) (not (< main_~i~1 10000)) (= (mod v_prenex_777 4294967296) |main_#t~ret5|)))) (exists ((v_bAnd_~res~0_BEFORE_RETURN_106 Int) (v_prenex_778 Int)) (or (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_778 4294967296) 2147483647)) (= (+ (mod v_prenex_778 4294967296) (- 4294967296)) |main_#t~ret5|)) (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296) 2147483647) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_106 4294967296)))))) [2019-10-13 21:30:55,740 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-13 21:30:55,740 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-13 21:30:55,740 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-13 21:30:55,740 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-13 21:30:56,285 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-13 21:30:56,285 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 4, 4, 11] total 43 [2019-10-13 21:30:56,285 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1540451103] [2019-10-13 21:30:56,287 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2019-10-13 21:30:56,287 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-13 21:30:56,288 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-10-13 21:30:56,288 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=449, Invalid=1443, Unknown=0, NotChecked=0, Total=1892 [2019-10-13 21:30:56,288 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 44 states. [2019-10-13 21:30:58,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-13 21:30:58,470 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2019-10-13 21:30:58,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-10-13 21:30:58,470 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 63 [2019-10-13 21:30:58,471 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-13 21:30:58,471 INFO L225 Difference]: With dead ends: 72 [2019-10-13 21:30:58,472 INFO L226 Difference]: Without dead ends: 54 [2019-10-13 21:30:58,474 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1350 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1349, Invalid=5457, Unknown=0, NotChecked=0, Total=6806 [2019-10-13 21:30:58,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-10-13 21:30:58,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2019-10-13 21:30:58,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-10-13 21:30:58,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2019-10-13 21:30:58,483 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 63 [2019-10-13 21:30:58,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-13 21:30:58,483 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2019-10-13 21:30:58,483 INFO L463 AbstractCegarLoop]: Interpolant automaton has 44 states. [2019-10-13 21:30:58,483 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2019-10-13 21:30:58,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-10-13 21:30:58,485 INFO L372 BasicCegarLoop]: Found error trace [2019-10-13 21:30:58,485 INFO L380 BasicCegarLoop]: trace histogram [27, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-13 21:30:58,689 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:58,689 INFO L410 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-13 21:30:58,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-13 21:30:58,690 INFO L82 PathProgramCache]: Analyzing trace with hash -1728770399, now seen corresponding path program 6 times [2019-10-13 21:30:58,690 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-13 21:30:58,690 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315735629] [2019-10-13 21:30:58,691 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:58,691 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:30:58,691 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-13 21:30:58,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:30:59,132 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-13 21:30:59,132 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1315735629] [2019-10-13 21:30:59,132 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1919065954] [2019-10-13 21:30:59,132 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:30:59,348 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-10-13 21:30:59,348 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-10-13 21:30:59,351 INFO L256 TraceCheckSpWp]: Trace formula consists of 331 conjuncts, 29 conjunts are in the unsatisfiable core [2019-10-13 21:30:59,355 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-13 21:30:59,385 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-13 21:30:59,385 INFO L321 TraceCheckSpWp]: Computing backward predicates... [2019-10-13 21:31:00,319 INFO L134 CoverageAnalysis]: Checked inductivity of 499 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-13 21:31:00,320 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [558800413] [2019-10-13 21:31:00,321 INFO L162 IcfgInterpreter]: Started Sifa with 19 locations of interest [2019-10-13 21:31:00,321 INFO L169 IcfgInterpreter]: Building call graph [2019-10-13 21:31:00,322 INFO L174 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2019-10-13 21:31:00,322 INFO L179 IcfgInterpreter]: Starting interpretation [2019-10-13 21:31:00,322 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2019-10-13 21:31:00,337 INFO L199 IcfgInterpreter]: Interpreting procedure main with input of size 21 for LOIs [2019-10-13 21:31:01,685 INFO L199 IcfgInterpreter]: Interpreting procedure bAnd with input of size 1 for LOIs [2019-10-13 21:31:01,710 INFO L199 IcfgInterpreter]: Interpreting procedure ULTIMATE.init with input of size 10 for LOIs [2019-10-13 21:31:01,713 INFO L183 IcfgInterpreter]: Interpretation finished [2019-10-13 21:31:01,713 INFO L191 IcfgInterpreter]: Final predicates for locations of interest are: [2019-10-13 21:31:01,714 INFO L193 IcfgInterpreter]: Reachable states at location bAndENTRY satisfy 601#true [2019-10-13 21:31:01,714 INFO L193 IcfgInterpreter]: Reachable states at location L26-4 satisfy 73#(and (not (< main_~i~1 10000)) (<= 10000 main_~i~1)) [2019-10-13 21:31:01,714 INFO L193 IcfgInterpreter]: Reachable states at location L33 satisfy 592#(or (exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_bAnd_~res~0_BEFORE_RETURN_131 Int) (v_bAnd_~res~0_BEFORE_RETURN_132 Int)) (or (and (= main_~ret~0 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (not (< main_~i~1 10000)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) main_~ret~0) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296) 2147483647) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)))) (exists ((v_prenex_972 Int) (v_prenex_971 Int) (v_bAnd_~res~0_BEFORE_RETURN_131 Int) (v_bAnd_~res~0_BEFORE_RETURN_132 Int)) (or (and (= main_~ret~0 (+ (mod v_prenex_972 4294967296) (- 4294967296))) (not (< main_~i~1 10000)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (< main_~i~1 10000)) (= main_~ret~0 (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296) 2147483647) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= main_~ret~0 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (= main_~ret~0 (+ (mod v_prenex_971 4294967296) (- 4294967296))) (<= main_~ret~0 2147483647)) (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) main_~ret~0) (not (< main_~i~1 10000)) (<= 0 (+ main_~ret~0 2147483648)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 4))) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) 2147483647) (<= main_~ret~0 2147483647))))) [2019-10-13 21:31:01,714 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initENTRY satisfy 648#(and (= |old(#NULL.base)| |#NULL.base|) (= |#valid| |old(#valid)|) (= |#NULL.offset| |old(#NULL.offset)|)) [2019-10-13 21:31:01,714 INFO L193 IcfgInterpreter]: Reachable states at location L26-3 satisfy 68#true [2019-10-13 21:31:01,715 INFO L193 IcfgInterpreter]: Reachable states at location mainErr0ASSERT_VIOLATIONERROR_FUNCTION satisfy 234#(or (and (not (= main_~ret~0 main_~ret2~0)) (exists ((v_bAnd_~res~0_BEFORE_RETURN_135 Int) (v_bAnd_~res~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 9999)) (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_1000 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0))))) (and (exists ((v_bAnd_~res~0_BEFORE_RETURN_135 Int) (v_bAnd_~res~0_BEFORE_RETURN_136 Int) (v_prenex_1000 Int) (v_prenex_999 Int)) (or (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) 2147483647)) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_135 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 9999)) (= (mod v_prenex_999 4294967296) main_~ret5~0) (<= (mod v_prenex_999 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648))) (and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (not (<= (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) 2147483647)) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (+ (mod v_bAnd_~res~0_BEFORE_RETURN_136 4294967296) (- 4294967296)) main_~ret5~0)) (and (not (< main_~i~2 9999)) (<= (mod v_prenex_1000 4294967296) 2147483647) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= main_~ret5~0 2147483647) (<= 0 (+ main_~ret5~0 2147483648)) (= (mod v_prenex_1000 4294967296) main_~ret5~0)))) (not (= main_~ret~0 main_~ret5~0)))) [2019-10-13 21:31:01,715 INFO L193 IcfgInterpreter]: Reachable states at location L-1 satisfy 23#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= 0 (select |#valid| 0)) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:31:01,715 INFO L193 IcfgInterpreter]: Reachable states at location mainENTRY satisfy 33#(and (= 0 |#NULL.base|) (<= |#NULL.base| 0) (= |#valid| |old(#valid)|) (<= 0 |#NULL.base|) (= |#memory_int| |old(#memory_int)|) (= |#NULL.offset| 0) (= |old(#length)| |#length|) (= 0 (select |old(#valid)| 0)) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:31:01,715 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.initEXIT satisfy 653#(and (= |#valid| (store |old(#valid)| 0 0)) (= 0 |#NULL.base|) (<= |#NULL.base| 0) (<= 0 |#NULL.base|) (= |#NULL.offset| 0) (<= 0 |#NULL.offset|) (<= |#NULL.offset| 0)) [2019-10-13 21:31:01,715 INFO L193 IcfgInterpreter]: Reachable states at location L39-1 satisfy 479#true [2019-10-13 21:31:01,716 INFO L193 IcfgInterpreter]: Reachable states at location L12-3 satisfy 639#(<= 1 bAnd_~i~0) [2019-10-13 21:31:01,716 INFO L193 IcfgInterpreter]: Reachable states at location ULTIMATE.startENTRY satisfy 6#true [2019-10-13 21:31:01,716 INFO L193 IcfgInterpreter]: Reachable states at location L39 satisfy 522#(and (not (< main_~i~2 9999)) (= main_~temp~0 (select (select |#memory_int| |main_~#x~0.base|) (+ |main_~#x~0.offset| 39996))) (<= 9999 main_~i~2)) [2019-10-13 21:31:01,716 INFO L193 IcfgInterpreter]: Reachable states at location bAndEXIT satisfy 644#(and (= |bAnd_#res| (ite (<= (mod bAnd_~res~0 4294967296) 2147483647) (mod bAnd_~res~0 4294967296) (+ (mod bAnd_~res~0 4294967296) (- 4294967296)))) (<= 1 bAnd_~i~0) (<= 10000 bAnd_~i~0) (not (< bAnd_~i~0 10000))) [2019-10-13 21:31:01,717 INFO L193 IcfgInterpreter]: Reachable states at location L30 satisfy 120#(or (exists ((v_prenex_971 Int) (v_bAnd_~res~0_BEFORE_RETURN_131 Int)) (or (and (= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) |main_#t~ret5|) (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_131 4294967296) 2147483647)) (and (not (<= (mod v_prenex_971 4294967296) 2147483647)) (not (< main_~i~1 10000)) (= (+ (mod v_prenex_971 4294967296) (- 4294967296)) |main_#t~ret5|)))) (exists ((v_prenex_972 Int) (v_bAnd_~res~0_BEFORE_RETURN_132 Int)) (or (and (not (< main_~i~1 10000)) (<= (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296) 2147483647) (= |main_#t~ret5| (mod v_bAnd_~res~0_BEFORE_RETURN_132 4294967296))) (and (not (< main_~i~1 10000)) (not (<= (mod v_prenex_972 4294967296) 2147483647)) (= (+ (mod v_prenex_972 4294967296) (- 4294967296)) |main_#t~ret5|))))) [2019-10-13 21:31:01,717 INFO L193 IcfgInterpreter]: Reachable states at location L41 satisfy 424#true [2019-10-13 21:31:01,717 INFO L193 IcfgInterpreter]: Reachable states at location L42 satisfy 313#true [2019-10-13 21:31:01,717 INFO L193 IcfgInterpreter]: Reachable states at location L33-1 satisfy 587#true [2019-10-13 21:31:01,718 INFO L193 IcfgInterpreter]: Reachable states at location L35-3 satisfy 560#true [2019-10-13 21:31:02,186 INFO L223 tionRefinementEngine]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2019-10-13 21:31:02,187 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 11] total 69 [2019-10-13 21:31:02,187 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [802123495] [2019-10-13 21:31:02,188 INFO L442 AbstractCegarLoop]: Interpolant automaton has 70 states [2019-10-13 21:31:02,188 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-13 21:31:02,189 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2019-10-13 21:31:02,191 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1740, Invalid=3090, Unknown=0, NotChecked=0, Total=4830 [2019-10-13 21:31:02,191 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 70 states. [2019-10-13 21:31:07,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-13 21:31:07,439 INFO L93 Difference]: Finished difference Result 104 states and 140 transitions. [2019-10-13 21:31:07,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2019-10-13 21:31:07,439 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 67 [2019-10-13 21:31:07,440 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-13 21:31:07,441 INFO L225 Difference]: With dead ends: 104 [2019-10-13 21:31:07,441 INFO L226 Difference]: Without dead ends: 83 [2019-10-13 21:31:07,446 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3929 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=5099, Invalid=12723, Unknown=0, NotChecked=0, Total=17822 [2019-10-13 21:31:07,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-10-13 21:31:07,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-10-13 21:31:07,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-10-13 21:31:07,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 87 transitions. [2019-10-13 21:31:07,457 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 87 transitions. Word has length 67 [2019-10-13 21:31:07,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-13 21:31:07,457 INFO L462 AbstractCegarLoop]: Abstraction has 83 states and 87 transitions. [2019-10-13 21:31:07,458 INFO L463 AbstractCegarLoop]: Interpolant automaton has 70 states. [2019-10-13 21:31:07,458 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 87 transitions. [2019-10-13 21:31:07,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-10-13 21:31:07,459 INFO L372 BasicCegarLoop]: Found error trace [2019-10-13 21:31:07,459 INFO L380 BasicCegarLoop]: trace histogram [56, 12, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-13 21:31:07,663 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:31:07,664 INFO L410 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-13 21:31:07,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-13 21:31:07,664 INFO L82 PathProgramCache]: Analyzing trace with hash 1695588190, now seen corresponding path program 7 times [2019-10-13 21:31:07,665 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-13 21:31:07,665 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870960644] [2019-10-13 21:31:07,665 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:31:07,666 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-13 21:31:07,666 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-13 21:31:07,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:31:09,068 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-13 21:31:09,068 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [870960644] [2019-10-13 21:31:09,069 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1115956307] [2019-10-13 21:31:09,069 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-13 21:31:09,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-13 21:31:09,342 INFO L256 TraceCheckSpWp]: Trace formula consists of 505 conjuncts, 58 conjunts are in the unsatisfiable core [2019-10-13 21:31:09,345 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-13 21:31:09,367 INFO L134 CoverageAnalysis]: Checked inductivity of 1717 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 121 trivial. 0 not checked. [2019-10-13 21:31:09,368 INFO L321 TraceCheckSpWp]: Computing backward predicates...