java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --abstractinterpretationv2.abstract.domain IntervalDomain --traceabstraction.trace.refinement.strategy TAIPAN --traceabstraction.abstract.interpretation.mode USE_PREDICATES -i ../../../trunk/examples/svcomp/systemc/transmitter.02.cil.c -------------------------------------------------------------------------------- This is Ultimate 0.1.24-13a467a-m [2019-10-15 01:28:45,669 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-15 01:28:45,673 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-15 01:28:45,691 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-15 01:28:45,692 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-15 01:28:45,694 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-15 01:28:45,696 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-15 01:28:45,708 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-15 01:28:45,709 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-15 01:28:45,710 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-15 01:28:45,711 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-15 01:28:45,712 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-15 01:28:45,712 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-15 01:28:45,713 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-15 01:28:45,714 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-15 01:28:45,715 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-15 01:28:45,716 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-15 01:28:45,717 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-15 01:28:45,719 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-15 01:28:45,720 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-15 01:28:45,722 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-15 01:28:45,723 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-15 01:28:45,724 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-15 01:28:45,724 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-15 01:28:45,727 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-10-15 01:28:45,727 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-10-15 01:28:45,727 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-10-15 01:28:45,728 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-10-15 01:28:45,728 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-10-15 01:28:45,729 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-10-15 01:28:45,729 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-15 01:28:45,730 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-15 01:28:45,731 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-15 01:28:45,732 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-15 01:28:45,733 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-15 01:28:45,733 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-15 01:28:45,733 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-15 01:28:45,734 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-15 01:28:45,734 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-15 01:28:45,735 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-15 01:28:45,735 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-15 01:28:45,736 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-15 01:28:45,749 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-15 01:28:45,750 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-15 01:28:45,751 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-15 01:28:45,751 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-15 01:28:45,751 INFO L138 SettingsManager]: * Use SBE=true [2019-10-15 01:28:45,752 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-15 01:28:45,752 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-15 01:28:45,752 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-15 01:28:45,752 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-15 01:28:45,752 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-15 01:28:45,753 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-15 01:28:45,753 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-15 01:28:45,753 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-15 01:28:45,753 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-15 01:28:45,753 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-15 01:28:45,753 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-15 01:28:45,754 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-15 01:28:45,754 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-15 01:28:45,754 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-15 01:28:45,754 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-15 01:28:45,754 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-15 01:28:45,755 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-15 01:28:45,755 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-15 01:28:45,755 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-15 01:28:45,755 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-15 01:28:45,756 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-15 01:28:45,756 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-15 01:28:45,756 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-15 01:28:45,756 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: Abstract domain -> IntervalDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Abstract interpretation Mode -> USE_PREDICATES [2019-10-15 01:28:46,017 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-15 01:28:46,037 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-15 01:28:46,040 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-15 01:28:46,042 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-15 01:28:46,042 INFO L275 PluginConnector]: CDTParser initialized [2019-10-15 01:28:46,043 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/systemc/transmitter.02.cil.c [2019-10-15 01:28:46,113 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f9874a64e/e5ea73b8d6614ad399761223adef85d9/FLAGe5985084b [2019-10-15 01:28:46,608 INFO L306 CDTParser]: Found 1 translation units. [2019-10-15 01:28:46,609 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/systemc/transmitter.02.cil.c [2019-10-15 01:28:46,619 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f9874a64e/e5ea73b8d6614ad399761223adef85d9/FLAGe5985084b [2019-10-15 01:28:47,006 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f9874a64e/e5ea73b8d6614ad399761223adef85d9 [2019-10-15 01:28:47,018 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-15 01:28:47,020 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-15 01:28:47,021 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-15 01:28:47,022 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-15 01:28:47,025 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-15 01:28:47,026 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 01:28:47" (1/1) ... [2019-10-15 01:28:47,030 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@25622116 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:28:47, skipping insertion in model container [2019-10-15 01:28:47,030 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 01:28:47" (1/1) ... [2019-10-15 01:28:47,039 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-15 01:28:47,074 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-15 01:28:47,365 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-15 01:28:47,381 INFO L188 MainTranslator]: Completed pre-run [2019-10-15 01:28:47,511 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-15 01:28:47,532 INFO L192 MainTranslator]: Completed translation [2019-10-15 01:28:47,533 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:28:47 WrapperNode [2019-10-15 01:28:47,533 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-15 01:28:47,534 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-15 01:28:47,534 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-15 01:28:47,534 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-15 01:28:47,546 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:28:47" (1/1) ... [2019-10-15 01:28:47,547 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:28:47" (1/1) ... [2019-10-15 01:28:47,554 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:28:47" (1/1) ... [2019-10-15 01:28:47,554 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:28:47" (1/1) ... [2019-10-15 01:28:47,564 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:28:47" (1/1) ... [2019-10-15 01:28:47,577 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:28:47" (1/1) ... [2019-10-15 01:28:47,580 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:28:47" (1/1) ... [2019-10-15 01:28:47,584 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-15 01:28:47,584 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-15 01:28:47,584 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-15 01:28:47,585 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-15 01:28:47,585 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:28:47" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-15 01:28:47,639 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-15 01:28:47,639 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-15 01:28:47,639 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2019-10-15 01:28:47,639 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2019-10-15 01:28:47,640 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2019-10-15 01:28:47,640 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2019-10-15 01:28:47,640 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2019-10-15 01:28:47,640 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2019-10-15 01:28:47,642 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2019-10-15 01:28:47,644 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2019-10-15 01:28:47,645 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2019-10-15 01:28:47,645 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2019-10-15 01:28:47,645 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2019-10-15 01:28:47,646 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2019-10-15 01:28:47,646 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2019-10-15 01:28:47,646 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2019-10-15 01:28:47,647 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2019-10-15 01:28:47,647 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2019-10-15 01:28:47,647 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2019-10-15 01:28:47,647 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2019-10-15 01:28:47,647 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2019-10-15 01:28:47,647 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2019-10-15 01:28:47,648 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-15 01:28:47,648 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-15 01:28:47,648 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-15 01:28:47,648 INFO L130 BoogieDeclarations]: Found specification of procedure error [2019-10-15 01:28:47,648 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2019-10-15 01:28:47,649 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2019-10-15 01:28:47,649 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2019-10-15 01:28:47,649 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2019-10-15 01:28:47,649 INFO L130 BoogieDeclarations]: Found specification of procedure master [2019-10-15 01:28:47,649 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2019-10-15 01:28:47,649 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2019-10-15 01:28:47,650 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2019-10-15 01:28:47,650 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2019-10-15 01:28:47,650 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2019-10-15 01:28:47,650 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2019-10-15 01:28:47,650 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2019-10-15 01:28:47,650 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2019-10-15 01:28:47,650 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2019-10-15 01:28:47,651 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2019-10-15 01:28:47,651 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2019-10-15 01:28:47,651 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2019-10-15 01:28:47,651 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2019-10-15 01:28:47,651 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2019-10-15 01:28:47,651 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-15 01:28:47,652 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-15 01:28:47,652 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-15 01:28:48,275 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-15 01:28:48,276 INFO L284 CfgBuilder]: Removed 6 assume(true) statements. [2019-10-15 01:28:48,277 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 01:28:48 BoogieIcfgContainer [2019-10-15 01:28:48,278 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-15 01:28:48,279 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-15 01:28:48,279 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-15 01:28:48,282 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-15 01:28:48,283 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 15.10 01:28:47" (1/3) ... [2019-10-15 01:28:48,284 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@45781c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.10 01:28:48, skipping insertion in model container [2019-10-15 01:28:48,284 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 01:28:47" (2/3) ... [2019-10-15 01:28:48,284 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@45781c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.10 01:28:48, skipping insertion in model container [2019-10-15 01:28:48,285 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 01:28:48" (3/3) ... [2019-10-15 01:28:48,286 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.02.cil.c [2019-10-15 01:28:48,298 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-15 01:28:48,318 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-15 01:28:48,330 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-15 01:28:48,368 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-15 01:28:48,368 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-15 01:28:48,369 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-15 01:28:48,369 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-15 01:28:48,369 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-15 01:28:48,369 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-15 01:28:48,370 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-15 01:28:48,370 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-15 01:28:48,404 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states. [2019-10-15 01:28:48,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:48,416 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:48,418 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:48,420 INFO L410 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:48,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:48,426 INFO L82 PathProgramCache]: Analyzing trace with hash 1996614335, now seen corresponding path program 1 times [2019-10-15 01:28:48,436 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:48,437 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1557061511] [2019-10-15 01:28:48,437 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:48,438 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:48,438 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:48,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:48,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:48,726 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1557061511] [2019-10-15 01:28:48,727 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:48,728 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-15 01:28:48,728 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [954613543] [2019-10-15 01:28:48,733 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-15 01:28:48,735 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:48,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-15 01:28:48,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-15 01:28:48,753 INFO L87 Difference]: Start difference. First operand 169 states. Second operand 4 states. [2019-10-15 01:28:49,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:49,059 INFO L93 Difference]: Finished difference Result 320 states and 454 transitions. [2019-10-15 01:28:49,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-15 01:28:49,061 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 90 [2019-10-15 01:28:49,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:49,075 INFO L225 Difference]: With dead ends: 320 [2019-10-15 01:28:49,075 INFO L226 Difference]: Without dead ends: 160 [2019-10-15 01:28:49,081 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-15 01:28:49,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2019-10-15 01:28:49,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 160. [2019-10-15 01:28:49,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2019-10-15 01:28:49,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 212 transitions. [2019-10-15 01:28:49,160 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 212 transitions. Word has length 90 [2019-10-15 01:28:49,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:49,162 INFO L462 AbstractCegarLoop]: Abstraction has 160 states and 212 transitions. [2019-10-15 01:28:49,162 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-15 01:28:49,162 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 212 transitions. [2019-10-15 01:28:49,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:49,166 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:49,166 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:49,167 INFO L410 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:49,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:49,167 INFO L82 PathProgramCache]: Analyzing trace with hash -387310403, now seen corresponding path program 1 times [2019-10-15 01:28:49,167 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:49,168 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878897348] [2019-10-15 01:28:49,168 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:49,168 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:49,168 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:49,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:49,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:49,353 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [878897348] [2019-10-15 01:28:49,354 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:49,354 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-15 01:28:49,354 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1365966069] [2019-10-15 01:28:49,359 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-15 01:28:49,359 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:49,359 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-15 01:28:49,359 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-15 01:28:49,360 INFO L87 Difference]: Start difference. First operand 160 states and 212 transitions. Second operand 5 states. [2019-10-15 01:28:49,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:49,836 INFO L93 Difference]: Finished difference Result 328 states and 450 transitions. [2019-10-15 01:28:49,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-15 01:28:49,837 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2019-10-15 01:28:49,838 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:49,841 INFO L225 Difference]: With dead ends: 328 [2019-10-15 01:28:49,841 INFO L226 Difference]: Without dead ends: 188 [2019-10-15 01:28:49,843 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-15 01:28:49,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2019-10-15 01:28:49,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 160. [2019-10-15 01:28:49,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2019-10-15 01:28:49,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 211 transitions. [2019-10-15 01:28:49,885 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 211 transitions. Word has length 90 [2019-10-15 01:28:49,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:49,889 INFO L462 AbstractCegarLoop]: Abstraction has 160 states and 211 transitions. [2019-10-15 01:28:49,889 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-15 01:28:49,889 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 211 transitions. [2019-10-15 01:28:49,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:49,894 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:49,895 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:49,896 INFO L410 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:49,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:49,896 INFO L82 PathProgramCache]: Analyzing trace with hash 566629755, now seen corresponding path program 1 times [2019-10-15 01:28:49,897 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:49,897 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023726005] [2019-10-15 01:28:49,897 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:49,898 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:49,898 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:49,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:50,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:50,061 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023726005] [2019-10-15 01:28:50,061 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:50,061 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-15 01:28:50,062 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264299410] [2019-10-15 01:28:50,063 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-15 01:28:50,063 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:50,063 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-15 01:28:50,064 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-15 01:28:50,064 INFO L87 Difference]: Start difference. First operand 160 states and 211 transitions. Second operand 5 states. [2019-10-15 01:28:50,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:50,538 INFO L93 Difference]: Finished difference Result 328 states and 449 transitions. [2019-10-15 01:28:50,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-15 01:28:50,539 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2019-10-15 01:28:50,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:50,547 INFO L225 Difference]: With dead ends: 328 [2019-10-15 01:28:50,547 INFO L226 Difference]: Without dead ends: 188 [2019-10-15 01:28:50,549 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-15 01:28:50,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2019-10-15 01:28:50,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 160. [2019-10-15 01:28:50,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2019-10-15 01:28:50,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 210 transitions. [2019-10-15 01:28:50,594 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 210 transitions. Word has length 90 [2019-10-15 01:28:50,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:50,595 INFO L462 AbstractCegarLoop]: Abstraction has 160 states and 210 transitions. [2019-10-15 01:28:50,595 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-15 01:28:50,595 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 210 transitions. [2019-10-15 01:28:50,600 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:50,600 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:50,601 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:50,601 INFO L410 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:50,601 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:50,601 INFO L82 PathProgramCache]: Analyzing trace with hash -649523971, now seen corresponding path program 1 times [2019-10-15 01:28:50,602 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:50,602 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579281828] [2019-10-15 01:28:50,607 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:50,607 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:50,607 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:50,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:50,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:50,727 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579281828] [2019-10-15 01:28:50,728 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:50,728 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-15 01:28:50,728 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1689460043] [2019-10-15 01:28:50,729 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-15 01:28:50,729 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:50,729 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-15 01:28:50,729 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-15 01:28:50,730 INFO L87 Difference]: Start difference. First operand 160 states and 210 transitions. Second operand 5 states. [2019-10-15 01:28:51,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:51,130 INFO L93 Difference]: Finished difference Result 326 states and 443 transitions. [2019-10-15 01:28:51,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-15 01:28:51,130 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2019-10-15 01:28:51,131 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:51,133 INFO L225 Difference]: With dead ends: 326 [2019-10-15 01:28:51,133 INFO L226 Difference]: Without dead ends: 186 [2019-10-15 01:28:51,134 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-15 01:28:51,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2019-10-15 01:28:51,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 160. [2019-10-15 01:28:51,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2019-10-15 01:28:51,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 209 transitions. [2019-10-15 01:28:51,155 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 209 transitions. Word has length 90 [2019-10-15 01:28:51,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:51,155 INFO L462 AbstractCegarLoop]: Abstraction has 160 states and 209 transitions. [2019-10-15 01:28:51,155 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-15 01:28:51,156 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 209 transitions. [2019-10-15 01:28:51,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:51,157 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:51,158 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:51,158 INFO L410 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:51,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:51,158 INFO L82 PathProgramCache]: Analyzing trace with hash -1381491397, now seen corresponding path program 1 times [2019-10-15 01:28:51,159 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:51,159 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1924863677] [2019-10-15 01:28:51,159 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:51,159 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:51,159 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:51,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:51,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:51,223 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1924863677] [2019-10-15 01:28:51,223 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:51,224 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-15 01:28:51,224 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [615936094] [2019-10-15 01:28:51,224 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-15 01:28:51,225 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:51,225 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-15 01:28:51,225 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-15 01:28:51,225 INFO L87 Difference]: Start difference. First operand 160 states and 209 transitions. Second operand 5 states. [2019-10-15 01:28:51,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:51,592 INFO L93 Difference]: Finished difference Result 341 states and 465 transitions. [2019-10-15 01:28:51,593 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-15 01:28:51,594 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2019-10-15 01:28:51,594 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:51,596 INFO L225 Difference]: With dead ends: 341 [2019-10-15 01:28:51,597 INFO L226 Difference]: Without dead ends: 201 [2019-10-15 01:28:51,598 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-15 01:28:51,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2019-10-15 01:28:51,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 160. [2019-10-15 01:28:51,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2019-10-15 01:28:51,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 208 transitions. [2019-10-15 01:28:51,632 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 208 transitions. Word has length 90 [2019-10-15 01:28:51,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:51,632 INFO L462 AbstractCegarLoop]: Abstraction has 160 states and 208 transitions. [2019-10-15 01:28:51,633 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-15 01:28:51,633 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 208 transitions. [2019-10-15 01:28:51,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:51,634 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:51,634 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:51,635 INFO L410 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:51,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:51,635 INFO L82 PathProgramCache]: Analyzing trace with hash -1435884295, now seen corresponding path program 1 times [2019-10-15 01:28:51,635 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:51,636 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316925201] [2019-10-15 01:28:51,636 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:51,636 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:51,636 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:51,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:51,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:51,724 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316925201] [2019-10-15 01:28:51,725 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:51,725 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-15 01:28:51,725 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904437668] [2019-10-15 01:28:51,726 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-15 01:28:51,726 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:51,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-15 01:28:51,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-15 01:28:51,727 INFO L87 Difference]: Start difference. First operand 160 states and 208 transitions. Second operand 6 states. [2019-10-15 01:28:51,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:51,766 INFO L93 Difference]: Finished difference Result 312 states and 420 transitions. [2019-10-15 01:28:51,767 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-15 01:28:51,767 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 90 [2019-10-15 01:28:51,767 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:51,769 INFO L225 Difference]: With dead ends: 312 [2019-10-15 01:28:51,769 INFO L226 Difference]: Without dead ends: 173 [2019-10-15 01:28:51,770 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2019-10-15 01:28:51,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2019-10-15 01:28:51,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 165. [2019-10-15 01:28:51,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2019-10-15 01:28:51,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 213 transitions. [2019-10-15 01:28:51,787 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 213 transitions. Word has length 90 [2019-10-15 01:28:51,787 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:51,787 INFO L462 AbstractCegarLoop]: Abstraction has 165 states and 213 transitions. [2019-10-15 01:28:51,788 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-15 01:28:51,788 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 213 transitions. [2019-10-15 01:28:51,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:51,789 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:51,789 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:51,789 INFO L410 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:51,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:51,790 INFO L82 PathProgramCache]: Analyzing trace with hash 830496891, now seen corresponding path program 1 times [2019-10-15 01:28:51,790 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:51,790 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79703296] [2019-10-15 01:28:51,791 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:51,791 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:51,791 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:51,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:51,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:51,871 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [79703296] [2019-10-15 01:28:51,871 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:51,871 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-15 01:28:51,872 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1889605742] [2019-10-15 01:28:51,873 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-15 01:28:51,873 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:51,873 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-15 01:28:51,874 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-15 01:28:51,874 INFO L87 Difference]: Start difference. First operand 165 states and 213 transitions. Second operand 6 states. [2019-10-15 01:28:51,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:51,918 INFO L93 Difference]: Finished difference Result 319 states and 425 transitions. [2019-10-15 01:28:51,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-15 01:28:51,918 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 90 [2019-10-15 01:28:51,919 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:51,921 INFO L225 Difference]: With dead ends: 319 [2019-10-15 01:28:51,921 INFO L226 Difference]: Without dead ends: 175 [2019-10-15 01:28:51,922 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2019-10-15 01:28:51,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2019-10-15 01:28:51,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 170. [2019-10-15 01:28:51,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2019-10-15 01:28:51,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 218 transitions. [2019-10-15 01:28:51,946 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 218 transitions. Word has length 90 [2019-10-15 01:28:51,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:51,947 INFO L462 AbstractCegarLoop]: Abstraction has 170 states and 218 transitions. [2019-10-15 01:28:51,947 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-15 01:28:51,947 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 218 transitions. [2019-10-15 01:28:51,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:51,949 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:51,949 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:51,949 INFO L410 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:51,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:51,950 INFO L82 PathProgramCache]: Analyzing trace with hash 1078643385, now seen corresponding path program 1 times [2019-10-15 01:28:51,950 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:51,951 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387935804] [2019-10-15 01:28:51,951 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:51,951 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:51,951 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:51,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:52,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:52,031 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387935804] [2019-10-15 01:28:52,031 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:52,031 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-10-15 01:28:52,031 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [170432651] [2019-10-15 01:28:52,032 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-15 01:28:52,033 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:52,033 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-15 01:28:52,033 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-15 01:28:52,033 INFO L87 Difference]: Start difference. First operand 170 states and 218 transitions. Second operand 6 states. [2019-10-15 01:28:52,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:52,073 INFO L93 Difference]: Finished difference Result 326 states and 430 transitions. [2019-10-15 01:28:52,073 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-15 01:28:52,074 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 90 [2019-10-15 01:28:52,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:52,077 INFO L225 Difference]: With dead ends: 326 [2019-10-15 01:28:52,077 INFO L226 Difference]: Without dead ends: 177 [2019-10-15 01:28:52,079 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2019-10-15 01:28:52,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2019-10-15 01:28:52,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 175. [2019-10-15 01:28:52,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2019-10-15 01:28:52,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 223 transitions. [2019-10-15 01:28:52,097 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 223 transitions. Word has length 90 [2019-10-15 01:28:52,099 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:52,099 INFO L462 AbstractCegarLoop]: Abstraction has 175 states and 223 transitions. [2019-10-15 01:28:52,099 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-15 01:28:52,099 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 223 transitions. [2019-10-15 01:28:52,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:52,100 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:52,101 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:52,101 INFO L410 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:52,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:52,101 INFO L82 PathProgramCache]: Analyzing trace with hash 1006256827, now seen corresponding path program 1 times [2019-10-15 01:28:52,102 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:52,102 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867645128] [2019-10-15 01:28:52,103 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:52,104 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:52,104 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:52,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:52,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:52,180 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867645128] [2019-10-15 01:28:52,180 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:52,181 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-15 01:28:52,181 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [623992721] [2019-10-15 01:28:52,182 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-15 01:28:52,182 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:52,182 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-15 01:28:52,182 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-15 01:28:52,183 INFO L87 Difference]: Start difference. First operand 175 states and 223 transitions. Second operand 5 states. [2019-10-15 01:28:52,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:52,824 INFO L93 Difference]: Finished difference Result 428 states and 564 transitions. [2019-10-15 01:28:52,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-10-15 01:28:52,824 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2019-10-15 01:28:52,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:52,827 INFO L225 Difference]: With dead ends: 428 [2019-10-15 01:28:52,827 INFO L226 Difference]: Without dead ends: 274 [2019-10-15 01:28:52,828 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2019-10-15 01:28:52,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states. [2019-10-15 01:28:52,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 226. [2019-10-15 01:28:52,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2019-10-15 01:28:52,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 286 transitions. [2019-10-15 01:28:52,875 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 286 transitions. Word has length 90 [2019-10-15 01:28:52,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:52,876 INFO L462 AbstractCegarLoop]: Abstraction has 226 states and 286 transitions. [2019-10-15 01:28:52,876 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-15 01:28:52,876 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 286 transitions. [2019-10-15 01:28:52,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:52,877 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:52,877 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:52,878 INFO L410 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:52,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:52,878 INFO L82 PathProgramCache]: Analyzing trace with hash -1902507075, now seen corresponding path program 1 times [2019-10-15 01:28:52,878 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:52,879 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1582822131] [2019-10-15 01:28:52,879 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:52,879 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:52,879 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:52,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:52,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:52,932 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1582822131] [2019-10-15 01:28:52,933 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:52,933 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-15 01:28:52,933 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1273191404] [2019-10-15 01:28:52,933 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-15 01:28:52,934 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:52,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-15 01:28:52,934 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-15 01:28:52,934 INFO L87 Difference]: Start difference. First operand 226 states and 286 transitions. Second operand 5 states. [2019-10-15 01:28:53,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:53,219 INFO L93 Difference]: Finished difference Result 430 states and 549 transitions. [2019-10-15 01:28:53,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-15 01:28:53,220 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2019-10-15 01:28:53,220 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:53,222 INFO L225 Difference]: With dead ends: 430 [2019-10-15 01:28:53,222 INFO L226 Difference]: Without dead ends: 226 [2019-10-15 01:28:53,223 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-15 01:28:53,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2019-10-15 01:28:53,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 226. [2019-10-15 01:28:53,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2019-10-15 01:28:53,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 283 transitions. [2019-10-15 01:28:53,242 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 283 transitions. Word has length 90 [2019-10-15 01:28:53,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:53,242 INFO L462 AbstractCegarLoop]: Abstraction has 226 states and 283 transitions. [2019-10-15 01:28:53,243 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-15 01:28:53,243 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 283 transitions. [2019-10-15 01:28:53,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:53,244 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:53,244 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:53,244 INFO L410 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:53,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:53,245 INFO L82 PathProgramCache]: Analyzing trace with hash 1882987131, now seen corresponding path program 1 times [2019-10-15 01:28:53,245 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:53,245 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105497265] [2019-10-15 01:28:53,245 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:53,246 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:53,246 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:53,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:53,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:53,318 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2105497265] [2019-10-15 01:28:53,318 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:53,318 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-15 01:28:53,319 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [4545076] [2019-10-15 01:28:53,319 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-15 01:28:53,319 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:53,320 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-15 01:28:53,320 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-15 01:28:53,321 INFO L87 Difference]: Start difference. First operand 226 states and 283 transitions. Second operand 5 states. [2019-10-15 01:28:53,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:53,661 INFO L93 Difference]: Finished difference Result 430 states and 543 transitions. [2019-10-15 01:28:53,661 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-15 01:28:53,661 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2019-10-15 01:28:53,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:53,663 INFO L225 Difference]: With dead ends: 430 [2019-10-15 01:28:53,663 INFO L226 Difference]: Without dead ends: 226 [2019-10-15 01:28:53,664 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-15 01:28:53,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2019-10-15 01:28:53,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 226. [2019-10-15 01:28:53,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2019-10-15 01:28:53,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 280 transitions. [2019-10-15 01:28:53,696 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 280 transitions. Word has length 90 [2019-10-15 01:28:53,697 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:53,697 INFO L462 AbstractCegarLoop]: Abstraction has 226 states and 280 transitions. [2019-10-15 01:28:53,697 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-15 01:28:53,697 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 280 transitions. [2019-10-15 01:28:53,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:53,698 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:53,699 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:53,699 INFO L410 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:53,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:53,699 INFO L82 PathProgramCache]: Analyzing trace with hash -488752131, now seen corresponding path program 1 times [2019-10-15 01:28:53,700 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:53,700 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767229527] [2019-10-15 01:28:53,700 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:53,700 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:53,700 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:53,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:53,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:53,777 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1767229527] [2019-10-15 01:28:53,777 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:53,778 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-15 01:28:53,778 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953876226] [2019-10-15 01:28:53,778 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-15 01:28:53,779 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:53,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-15 01:28:53,779 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-15 01:28:53,779 INFO L87 Difference]: Start difference. First operand 226 states and 280 transitions. Second operand 5 states. [2019-10-15 01:28:54,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:54,282 INFO L93 Difference]: Finished difference Result 540 states and 719 transitions. [2019-10-15 01:28:54,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-10-15 01:28:54,283 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2019-10-15 01:28:54,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:54,289 INFO L225 Difference]: With dead ends: 540 [2019-10-15 01:28:54,290 INFO L226 Difference]: Without dead ends: 335 [2019-10-15 01:28:54,291 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2019-10-15 01:28:54,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 335 states. [2019-10-15 01:28:54,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 335 to 276. [2019-10-15 01:28:54,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 276 states. [2019-10-15 01:28:54,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276 states to 276 states and 342 transitions. [2019-10-15 01:28:54,340 INFO L78 Accepts]: Start accepts. Automaton has 276 states and 342 transitions. Word has length 90 [2019-10-15 01:28:54,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:54,340 INFO L462 AbstractCegarLoop]: Abstraction has 276 states and 342 transitions. [2019-10-15 01:28:54,341 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-15 01:28:54,341 INFO L276 IsEmpty]: Start isEmpty. Operand 276 states and 342 transitions. [2019-10-15 01:28:54,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:54,343 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:54,343 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:54,344 INFO L410 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:54,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:54,344 INFO L82 PathProgramCache]: Analyzing trace with hash -426712517, now seen corresponding path program 1 times [2019-10-15 01:28:54,345 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:54,345 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740457453] [2019-10-15 01:28:54,345 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:54,345 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:54,346 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:54,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:54,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:54,437 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740457453] [2019-10-15 01:28:54,437 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:54,438 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-15 01:28:54,438 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962359651] [2019-10-15 01:28:54,439 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-15 01:28:54,440 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:54,440 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-15 01:28:54,441 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-15 01:28:54,441 INFO L87 Difference]: Start difference. First operand 276 states and 342 transitions. Second operand 5 states. [2019-10-15 01:28:54,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:54,939 INFO L93 Difference]: Finished difference Result 600 states and 798 transitions. [2019-10-15 01:28:54,940 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-10-15 01:28:54,940 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2019-10-15 01:28:54,940 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:54,943 INFO L225 Difference]: With dead ends: 600 [2019-10-15 01:28:54,943 INFO L226 Difference]: Without dead ends: 346 [2019-10-15 01:28:54,945 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-10-15 01:28:54,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346 states. [2019-10-15 01:28:54,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346 to 301. [2019-10-15 01:28:54,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 301 states. [2019-10-15 01:28:54,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 301 states to 301 states and 363 transitions. [2019-10-15 01:28:54,971 INFO L78 Accepts]: Start accepts. Automaton has 301 states and 363 transitions. Word has length 90 [2019-10-15 01:28:54,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:54,972 INFO L462 AbstractCegarLoop]: Abstraction has 301 states and 363 transitions. [2019-10-15 01:28:54,972 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-15 01:28:54,972 INFO L276 IsEmpty]: Start isEmpty. Operand 301 states and 363 transitions. [2019-10-15 01:28:54,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-10-15 01:28:54,973 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:54,973 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:54,974 INFO L410 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:54,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:54,974 INFO L82 PathProgramCache]: Analyzing trace with hash -286163907, now seen corresponding path program 1 times [2019-10-15 01:28:54,974 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:54,974 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894892164] [2019-10-15 01:28:54,974 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:54,975 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:54,975 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:54,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:55,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:55,009 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894892164] [2019-10-15 01:28:55,009 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:55,010 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-15 01:28:55,010 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742010678] [2019-10-15 01:28:55,010 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-15 01:28:55,011 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:55,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-15 01:28:55,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 01:28:55,011 INFO L87 Difference]: Start difference. First operand 301 states and 363 transitions. Second operand 3 states. [2019-10-15 01:28:55,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:55,071 INFO L93 Difference]: Finished difference Result 847 states and 1025 transitions. [2019-10-15 01:28:55,071 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-15 01:28:55,071 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 90 [2019-10-15 01:28:55,072 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:55,076 INFO L225 Difference]: With dead ends: 847 [2019-10-15 01:28:55,076 INFO L226 Difference]: Without dead ends: 570 [2019-10-15 01:28:55,078 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 01:28:55,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 570 states. [2019-10-15 01:28:55,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 570 to 565. [2019-10-15 01:28:55,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 565 states. [2019-10-15 01:28:55,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 565 states to 565 states and 685 transitions. [2019-10-15 01:28:55,126 INFO L78 Accepts]: Start accepts. Automaton has 565 states and 685 transitions. Word has length 90 [2019-10-15 01:28:55,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:55,127 INFO L462 AbstractCegarLoop]: Abstraction has 565 states and 685 transitions. [2019-10-15 01:28:55,127 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-15 01:28:55,127 INFO L276 IsEmpty]: Start isEmpty. Operand 565 states and 685 transitions. [2019-10-15 01:28:55,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2019-10-15 01:28:55,129 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:55,129 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:55,129 INFO L410 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:55,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:55,130 INFO L82 PathProgramCache]: Analyzing trace with hash 1417763379, now seen corresponding path program 1 times [2019-10-15 01:28:55,130 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:55,130 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148592920] [2019-10-15 01:28:55,130 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:55,130 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:55,130 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:55,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:55,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 01:28:55,172 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1148592920] [2019-10-15 01:28:55,172 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:55,172 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-15 01:28:55,173 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884268548] [2019-10-15 01:28:55,173 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-15 01:28:55,173 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:55,174 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-15 01:28:55,174 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 01:28:55,174 INFO L87 Difference]: Start difference. First operand 565 states and 685 transitions. Second operand 3 states. [2019-10-15 01:28:55,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:55,274 INFO L93 Difference]: Finished difference Result 1592 states and 1999 transitions. [2019-10-15 01:28:55,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-15 01:28:55,275 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 91 [2019-10-15 01:28:55,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:55,283 INFO L225 Difference]: With dead ends: 1592 [2019-10-15 01:28:55,283 INFO L226 Difference]: Without dead ends: 1056 [2019-10-15 01:28:55,286 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 01:28:55,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1056 states. [2019-10-15 01:28:55,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1056 to 1054. [2019-10-15 01:28:55,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1054 states. [2019-10-15 01:28:55,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1054 states to 1054 states and 1295 transitions. [2019-10-15 01:28:55,375 INFO L78 Accepts]: Start accepts. Automaton has 1054 states and 1295 transitions. Word has length 91 [2019-10-15 01:28:55,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:55,376 INFO L462 AbstractCegarLoop]: Abstraction has 1054 states and 1295 transitions. [2019-10-15 01:28:55,376 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-15 01:28:55,376 INFO L276 IsEmpty]: Start isEmpty. Operand 1054 states and 1295 transitions. [2019-10-15 01:28:55,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2019-10-15 01:28:55,379 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:55,380 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:55,380 INFO L410 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:55,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:55,380 INFO L82 PathProgramCache]: Analyzing trace with hash 1387972843, now seen corresponding path program 1 times [2019-10-15 01:28:55,381 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:55,381 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955834797] [2019-10-15 01:28:55,381 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:55,381 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:55,381 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:55,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:55,435 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2019-10-15 01:28:55,437 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955834797] [2019-10-15 01:28:55,438 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:55,438 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-15 01:28:55,438 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2116456725] [2019-10-15 01:28:55,439 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-15 01:28:55,442 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:55,443 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-15 01:28:55,443 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-15 01:28:55,443 INFO L87 Difference]: Start difference. First operand 1054 states and 1295 transitions. Second operand 4 states. [2019-10-15 01:28:55,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:55,621 INFO L93 Difference]: Finished difference Result 2075 states and 2537 transitions. [2019-10-15 01:28:55,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-15 01:28:55,622 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 111 [2019-10-15 01:28:55,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:55,630 INFO L225 Difference]: With dead ends: 2075 [2019-10-15 01:28:55,630 INFO L226 Difference]: Without dead ends: 1045 [2019-10-15 01:28:55,635 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-15 01:28:55,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1045 states. [2019-10-15 01:28:55,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1045 to 1045. [2019-10-15 01:28:55,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1045 states. [2019-10-15 01:28:55,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1045 states to 1045 states and 1276 transitions. [2019-10-15 01:28:55,727 INFO L78 Accepts]: Start accepts. Automaton has 1045 states and 1276 transitions. Word has length 111 [2019-10-15 01:28:55,727 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:55,727 INFO L462 AbstractCegarLoop]: Abstraction has 1045 states and 1276 transitions. [2019-10-15 01:28:55,727 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-15 01:28:55,728 INFO L276 IsEmpty]: Start isEmpty. Operand 1045 states and 1276 transitions. [2019-10-15 01:28:55,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2019-10-15 01:28:55,730 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:55,730 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:55,731 INFO L410 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:55,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:55,731 INFO L82 PathProgramCache]: Analyzing trace with hash 687816872, now seen corresponding path program 1 times [2019-10-15 01:28:55,731 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:55,732 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53460538] [2019-10-15 01:28:55,732 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:55,732 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:55,732 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:55,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:55,792 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2019-10-15 01:28:55,793 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53460538] [2019-10-15 01:28:55,793 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:55,793 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-10-15 01:28:55,793 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208604263] [2019-10-15 01:28:55,794 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-10-15 01:28:55,794 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:55,794 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-10-15 01:28:55,794 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-10-15 01:28:55,795 INFO L87 Difference]: Start difference. First operand 1045 states and 1276 transitions. Second operand 5 states. [2019-10-15 01:28:56,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:56,263 INFO L93 Difference]: Finished difference Result 2084 states and 2669 transitions. [2019-10-15 01:28:56,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-10-15 01:28:56,264 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 112 [2019-10-15 01:28:56,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:56,274 INFO L225 Difference]: With dead ends: 2084 [2019-10-15 01:28:56,275 INFO L226 Difference]: Without dead ends: 1060 [2019-10-15 01:28:56,280 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-10-15 01:28:56,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1060 states. [2019-10-15 01:28:56,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1060 to 924. [2019-10-15 01:28:56,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 924 states. [2019-10-15 01:28:56,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1116 transitions. [2019-10-15 01:28:56,437 INFO L78 Accepts]: Start accepts. Automaton has 924 states and 1116 transitions. Word has length 112 [2019-10-15 01:28:56,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:56,437 INFO L462 AbstractCegarLoop]: Abstraction has 924 states and 1116 transitions. [2019-10-15 01:28:56,437 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-10-15 01:28:56,438 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1116 transitions. [2019-10-15 01:28:56,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2019-10-15 01:28:56,439 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:56,440 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:56,440 INFO L410 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:56,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:56,440 INFO L82 PathProgramCache]: Analyzing trace with hash 36587625, now seen corresponding path program 1 times [2019-10-15 01:28:56,440 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:56,441 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [446333086] [2019-10-15 01:28:56,441 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:56,441 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:56,441 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:56,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:56,480 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-10-15 01:28:56,481 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [446333086] [2019-10-15 01:28:56,481 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:56,481 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-15 01:28:56,482 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312115508] [2019-10-15 01:28:56,482 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-15 01:28:56,482 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:56,482 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-15 01:28:56,483 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 01:28:56,483 INFO L87 Difference]: Start difference. First operand 924 states and 1116 transitions. Second operand 3 states. [2019-10-15 01:28:56,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:56,630 INFO L93 Difference]: Finished difference Result 2706 states and 3330 transitions. [2019-10-15 01:28:56,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-15 01:28:56,631 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 111 [2019-10-15 01:28:56,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:56,641 INFO L225 Difference]: With dead ends: 2706 [2019-10-15 01:28:56,641 INFO L226 Difference]: Without dead ends: 1363 [2019-10-15 01:28:56,647 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 01:28:56,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1363 states. [2019-10-15 01:28:56,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1363 to 1363. [2019-10-15 01:28:56,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1363 states. [2019-10-15 01:28:56,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1363 states to 1363 states and 1646 transitions. [2019-10-15 01:28:56,763 INFO L78 Accepts]: Start accepts. Automaton has 1363 states and 1646 transitions. Word has length 111 [2019-10-15 01:28:56,764 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:56,764 INFO L462 AbstractCegarLoop]: Abstraction has 1363 states and 1646 transitions. [2019-10-15 01:28:56,764 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-15 01:28:56,764 INFO L276 IsEmpty]: Start isEmpty. Operand 1363 states and 1646 transitions. [2019-10-15 01:28:56,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2019-10-15 01:28:56,767 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:56,767 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:56,768 INFO L410 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:56,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:56,768 INFO L82 PathProgramCache]: Analyzing trace with hash -1178118941, now seen corresponding path program 1 times [2019-10-15 01:28:56,768 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:56,768 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1357845522] [2019-10-15 01:28:56,769 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:56,769 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:56,769 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:56,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:56,824 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2019-10-15 01:28:56,824 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1357845522] [2019-10-15 01:28:56,825 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:56,825 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-15 01:28:56,826 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108555692] [2019-10-15 01:28:56,827 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-15 01:28:56,827 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:56,828 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-15 01:28:56,828 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 01:28:56,828 INFO L87 Difference]: Start difference. First operand 1363 states and 1646 transitions. Second operand 3 states. [2019-10-15 01:28:57,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:57,054 INFO L93 Difference]: Finished difference Result 3766 states and 4721 transitions. [2019-10-15 01:28:57,054 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-15 01:28:57,055 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 155 [2019-10-15 01:28:57,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:57,077 INFO L225 Difference]: With dead ends: 3766 [2019-10-15 01:28:57,078 INFO L226 Difference]: Without dead ends: 2425 [2019-10-15 01:28:57,088 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 01:28:57,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2425 states. [2019-10-15 01:28:57,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2425 to 2422. [2019-10-15 01:28:57,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2422 states. [2019-10-15 01:28:57,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2422 states to 2422 states and 3006 transitions. [2019-10-15 01:28:57,379 INFO L78 Accepts]: Start accepts. Automaton has 2422 states and 3006 transitions. Word has length 155 [2019-10-15 01:28:57,383 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:57,383 INFO L462 AbstractCegarLoop]: Abstraction has 2422 states and 3006 transitions. [2019-10-15 01:28:57,383 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-15 01:28:57,383 INFO L276 IsEmpty]: Start isEmpty. Operand 2422 states and 3006 transitions. [2019-10-15 01:28:57,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2019-10-15 01:28:57,392 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:57,392 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:57,393 INFO L410 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:57,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:57,393 INFO L82 PathProgramCache]: Analyzing trace with hash -390866386, now seen corresponding path program 1 times [2019-10-15 01:28:57,394 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:57,394 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911991934] [2019-10-15 01:28:57,394 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:57,394 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:57,395 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:57,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:57,552 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2019-10-15 01:28:57,552 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911991934] [2019-10-15 01:28:57,553 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [233566594] [2019-10-15 01:28:57,553 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-15 01:28:57,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:57,720 INFO L256 TraceCheckSpWp]: Trace formula consists of 657 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-15 01:28:57,750 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-15 01:28:57,800 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 33 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2019-10-15 01:28:57,800 INFO L321 TraceCheckSpWp]: Computing backward predicates... [2019-10-15 01:28:58,063 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2019-10-15 01:28:58,064 INFO L223 tionRefinementEngine]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2019-10-15 01:28:58,064 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [6] total 7 [2019-10-15 01:28:58,064 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550195760] [2019-10-15 01:28:58,065 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-15 01:28:58,065 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:58,066 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-15 01:28:58,066 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2019-10-15 01:28:58,066 INFO L87 Difference]: Start difference. First operand 2422 states and 3006 transitions. Second operand 4 states. [2019-10-15 01:28:58,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:58,610 INFO L93 Difference]: Finished difference Result 6179 states and 8106 transitions. [2019-10-15 01:28:58,611 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-15 01:28:58,611 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 156 [2019-10-15 01:28:58,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:58,633 INFO L225 Difference]: With dead ends: 6179 [2019-10-15 01:28:58,634 INFO L226 Difference]: Without dead ends: 3093 [2019-10-15 01:28:58,653 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 313 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2019-10-15 01:28:58,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3093 states. [2019-10-15 01:28:58,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3093 to 3081. [2019-10-15 01:28:58,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3081 states. [2019-10-15 01:28:58,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3081 states to 3081 states and 3765 transitions. [2019-10-15 01:28:58,932 INFO L78 Accepts]: Start accepts. Automaton has 3081 states and 3765 transitions. Word has length 156 [2019-10-15 01:28:58,933 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:58,933 INFO L462 AbstractCegarLoop]: Abstraction has 3081 states and 3765 transitions. [2019-10-15 01:28:58,933 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-15 01:28:58,933 INFO L276 IsEmpty]: Start isEmpty. Operand 3081 states and 3765 transitions. [2019-10-15 01:28:58,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 208 [2019-10-15 01:28:58,944 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:58,944 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:59,146 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-15 01:28:59,147 INFO L410 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:59,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:59,147 INFO L82 PathProgramCache]: Analyzing trace with hash -1382123670, now seen corresponding path program 1 times [2019-10-15 01:28:59,148 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:59,148 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414062486] [2019-10-15 01:28:59,148 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:59,148 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:59,148 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:59,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 01:28:59,307 INFO L134 CoverageAnalysis]: Checked inductivity of 114 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2019-10-15 01:28:59,308 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1414062486] [2019-10-15 01:28:59,308 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 01:28:59,308 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-15 01:28:59,308 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992122279] [2019-10-15 01:28:59,309 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-15 01:28:59,309 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy TAIPAN [2019-10-15 01:28:59,310 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-15 01:28:59,310 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-15 01:28:59,310 INFO L87 Difference]: Start difference. First operand 3081 states and 3765 transitions. Second operand 4 states. [2019-10-15 01:28:59,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 01:28:59,692 INFO L93 Difference]: Finished difference Result 6169 states and 7745 transitions. [2019-10-15 01:28:59,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-15 01:28:59,693 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 207 [2019-10-15 01:28:59,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 01:28:59,705 INFO L225 Difference]: With dead ends: 6169 [2019-10-15 01:28:59,706 INFO L226 Difference]: Without dead ends: 1660 [2019-10-15 01:28:59,729 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-15 01:28:59,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1660 states. [2019-10-15 01:28:59,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1660 to 1631. [2019-10-15 01:28:59,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1631 states. [2019-10-15 01:28:59,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1631 states to 1631 states and 1819 transitions. [2019-10-15 01:28:59,857 INFO L78 Accepts]: Start accepts. Automaton has 1631 states and 1819 transitions. Word has length 207 [2019-10-15 01:28:59,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 01:28:59,858 INFO L462 AbstractCegarLoop]: Abstraction has 1631 states and 1819 transitions. [2019-10-15 01:28:59,858 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-15 01:28:59,858 INFO L276 IsEmpty]: Start isEmpty. Operand 1631 states and 1819 transitions. [2019-10-15 01:28:59,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 209 [2019-10-15 01:28:59,863 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 01:28:59,864 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 01:28:59,864 INFO L410 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 01:28:59,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 01:28:59,864 INFO L82 PathProgramCache]: Analyzing trace with hash 89354437, now seen corresponding path program 1 times [2019-10-15 01:28:59,865 INFO L157 tionRefinementEngine]: Executing refinement strategy TAIPAN [2019-10-15 01:28:59,865 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389556481] [2019-10-15 01:28:59,865 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:59,865 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 01:28:59,865 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 01:28:59,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-15 01:28:59,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-15 01:29:00,050 INFO L168 tionRefinementEngine]: Strategy TAIPAN found a feasible trace [2019-10-15 01:29:00,052 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-10-15 01:29:00,271 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 15.10 01:29:00 BoogieIcfgContainer [2019-10-15 01:29:00,271 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-10-15 01:29:00,275 INFO L168 Benchmark]: Toolchain (without parser) took 13253.95 ms. Allocated memory was 137.4 MB in the beginning and 494.9 MB in the end (delta: 357.6 MB). Free memory was 101.7 MB in the beginning and 141.3 MB in the end (delta: -39.6 MB). Peak memory consumption was 318.0 MB. Max. memory is 7.1 GB. [2019-10-15 01:29:00,276 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 137.4 MB. Free memory is still 120.2 MB. There was no memory consumed. Max. memory is 7.1 GB. [2019-10-15 01:29:00,276 INFO L168 Benchmark]: CACSL2BoogieTranslator took 512.10 ms. Allocated memory was 137.4 MB in the beginning and 201.9 MB in the end (delta: 64.5 MB). Free memory was 101.3 MB in the beginning and 178.4 MB in the end (delta: -77.2 MB). Peak memory consumption was 24.7 MB. Max. memory is 7.1 GB. [2019-10-15 01:29:00,282 INFO L168 Benchmark]: Boogie Preprocessor took 49.88 ms. Allocated memory is still 201.9 MB. Free memory was 178.4 MB in the beginning and 175.2 MB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 7.1 GB. [2019-10-15 01:29:00,284 INFO L168 Benchmark]: RCFGBuilder took 693.60 ms. Allocated memory is still 201.9 MB. Free memory was 175.2 MB in the beginning and 140.2 MB in the end (delta: 35.0 MB). Peak memory consumption was 35.0 MB. Max. memory is 7.1 GB. [2019-10-15 01:29:00,285 INFO L168 Benchmark]: TraceAbstraction took 11992.41 ms. Allocated memory was 201.9 MB in the beginning and 494.9 MB in the end (delta: 293.1 MB). Free memory was 140.2 MB in the beginning and 141.3 MB in the end (delta: -1.1 MB). Peak memory consumption was 292.0 MB. Max. memory is 7.1 GB. [2019-10-15 01:29:00,295 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 137.4 MB. Free memory is still 120.2 MB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 512.10 ms. Allocated memory was 137.4 MB in the beginning and 201.9 MB in the end (delta: 64.5 MB). Free memory was 101.3 MB in the beginning and 178.4 MB in the end (delta: -77.2 MB). Peak memory consumption was 24.7 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 49.88 ms. Allocated memory is still 201.9 MB. Free memory was 178.4 MB in the beginning and 175.2 MB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 7.1 GB. * RCFGBuilder took 693.60 ms. Allocated memory is still 201.9 MB. Free memory was 175.2 MB in the beginning and 140.2 MB in the end (delta: 35.0 MB). Peak memory consumption was 35.0 MB. Max. memory is 7.1 GB. * TraceAbstraction took 11992.41 ms. Allocated memory was 201.9 MB in the beginning and 494.9 MB in the end (delta: 293.1 MB). Free memory was 140.2 MB in the beginning and 141.3 MB in the end (delta: -1.1 MB). Peak memory consumption was 292.0 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int m_i ; [L22] int t1_i ; [L23] int t2_i ; [L24] int M_E = 2; [L25] int T1_E = 2; [L26] int T2_E = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; VAL [\old(E_1)=16, \old(E_2)=5, \old(M_E)=13, \old(m_i)=7, \old(m_pc)=11, \old(m_st)=12, \old(T1_E)=3, \old(t1_i)=15, \old(t1_pc)=8, \old(t1_st)=4, \old(T2_E)=14, \old(t2_i)=6, \old(t2_pc)=9, \old(t2_st)=10, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L563] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L567] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L477] m_i = 1 [L478] t1_i = 1 [L479] t2_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L567] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L568] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L504] int kernel_st ; [L505] int tmp ; [L506] int tmp___0 ; [L510] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L511] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L211] COND TRUE m_i == 1 [L212] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L216] COND TRUE t1_i == 1 [L217] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L221] COND TRUE t2_i == 1 [L222] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L324] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L329] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L334] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L514] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L158] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L165] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L177] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L184] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L196] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0] [L514] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L357] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L362] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L367] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L518] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L521] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L522] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L257] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L231] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L252] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L78] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L89] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L91] t1_pc = 1 [L92] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L291] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L113] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L124] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L126] t2_pc = 1 [L127] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L305] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L231] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L252] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L264] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND TRUE \read(tmp_ndt_1) [L276] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L277] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L37] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L48] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L51] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND TRUE E_1 == 1 [L167] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND TRUE \read(tmp___0) [L404] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1, tmp___1=0] [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L53] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L56] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L58] m_pc = 1 [L59] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L277] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L78] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L81] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L97] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L98] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L147] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND TRUE E_2 == 1 [L186] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND TRUE \read(tmp___1) [L412] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=0, tmp___0=0, tmp___1=1] [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L98] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L99] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L89] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L91] t1_pc = 1 [L92] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L291] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L113] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L116] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L132] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 23 procedures, 169 locations, 1 error locations. Result: UNSAFE, OverallTime: 11.9s, OverallIterations: 22, TraceHistogramMax: 3, AutomataDifference: 6.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4770 SDtfs, 4888 SDslu, 4804 SDs, 0 SdLazy, 2984 SolverSat, 1202 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 473 GetRequests, 389 SyntacticMatches, 9 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3081occurred in iteration=20, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 1.6s AutomataMinimizationTime, 21 MinimizatonAttempts, 477 StatesRemovedByMinimization, 16 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 1.5s InterpolantComputationTime, 2567 NumberOfCodeBlocks, 2567 NumberOfCodeBlocksAsserted, 23 NumberOfCheckSat, 2492 ConstructedInterpolants, 0 QuantifiedInterpolants, 412020 SizeOfPredicates, 0 NumberOfNonLiveVariables, 657 ConjunctsInSsa, 3 ConjunctsInUnsatCore, 23 InterpolantComputations, 22 PerfectInterpolantSequences, 334/345 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...