java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf --traceabstraction.trace.refinement.strategy SIFA_TAIPAN --sifa.abstract.domain CompoundDomain --rcfgbuilder.size.of.a.code.block LoopFreeBlock --sifa.call.summarizer TopInputCallSummarizer --sifa.fluid SizeLimitFluid --sifa.simplification.technique SIMPLIFY_QUICK -i ../../../trunk/examples/svcomp/systemc/transmitter.02.cil.c -------------------------------------------------------------------------------- This is Ultimate 0.1.24-13a467a-m [2019-10-15 03:32:12,620 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-10-15 03:32:12,623 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-10-15 03:32:12,634 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-10-15 03:32:12,635 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-10-15 03:32:12,636 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-10-15 03:32:12,637 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-10-15 03:32:12,639 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-10-15 03:32:12,640 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-10-15 03:32:12,641 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-10-15 03:32:12,642 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-10-15 03:32:12,643 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-10-15 03:32:12,643 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-10-15 03:32:12,644 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-10-15 03:32:12,645 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-10-15 03:32:12,646 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-10-15 03:32:12,647 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-10-15 03:32:12,648 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-10-15 03:32:12,650 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-10-15 03:32:12,651 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-10-15 03:32:12,653 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-10-15 03:32:12,654 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-10-15 03:32:12,655 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-10-15 03:32:12,655 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-10-15 03:32:12,657 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-10-15 03:32:12,657 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-10-15 03:32:12,658 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-10-15 03:32:12,658 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-10-15 03:32:12,659 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-10-15 03:32:12,660 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-10-15 03:32:12,660 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-10-15 03:32:12,661 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-10-15 03:32:12,662 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-10-15 03:32:12,662 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-10-15 03:32:12,663 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-10-15 03:32:12,663 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-10-15 03:32:12,664 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-10-15 03:32:12,664 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-10-15 03:32:12,665 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-10-15 03:32:12,665 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-10-15 03:32:12,666 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-10-15 03:32:12,667 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2019-10-15 03:32:12,681 INFO L113 SettingsManager]: Loading preferences was successful [2019-10-15 03:32:12,681 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-10-15 03:32:12,682 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-10-15 03:32:12,682 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-10-15 03:32:12,682 INFO L138 SettingsManager]: * Use SBE=true [2019-10-15 03:32:12,683 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-10-15 03:32:12,683 INFO L138 SettingsManager]: * sizeof long=4 [2019-10-15 03:32:12,683 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-10-15 03:32:12,683 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-10-15 03:32:12,683 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-10-15 03:32:12,684 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-10-15 03:32:12,684 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-10-15 03:32:12,684 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-10-15 03:32:12,684 INFO L138 SettingsManager]: * sizeof long double=12 [2019-10-15 03:32:12,684 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-10-15 03:32:12,684 INFO L138 SettingsManager]: * Use constant arrays=true [2019-10-15 03:32:12,685 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-10-15 03:32:12,685 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-10-15 03:32:12,685 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-10-15 03:32:12,685 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-10-15 03:32:12,685 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-10-15 03:32:12,686 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-15 03:32:12,686 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-10-15 03:32:12,686 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-10-15 03:32:12,686 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-10-15 03:32:12,687 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-10-15 03:32:12,687 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-10-15 03:32:12,687 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-10-15 03:32:12,687 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Trace refinement strategy -> SIFA_TAIPAN Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Abstract Domain -> CompoundDomain Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> LoopFreeBlock Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Call Summarizer -> TopInputCallSummarizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Fluid -> SizeLimitFluid Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.sifa: Simplification Technique -> SIMPLIFY_QUICK [2019-10-15 03:32:12,973 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-10-15 03:32:12,991 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-10-15 03:32:12,994 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-10-15 03:32:12,996 INFO L271 PluginConnector]: Initializing CDTParser... [2019-10-15 03:32:12,996 INFO L275 PluginConnector]: CDTParser initialized [2019-10-15 03:32:12,997 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/systemc/transmitter.02.cil.c [2019-10-15 03:32:13,069 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/be3d78c1b/abdcfcf2b4314b268ea364a91ff810ed/FLAGbc71c265a [2019-10-15 03:32:13,530 INFO L306 CDTParser]: Found 1 translation units. [2019-10-15 03:32:13,531 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/systemc/transmitter.02.cil.c [2019-10-15 03:32:13,542 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/be3d78c1b/abdcfcf2b4314b268ea364a91ff810ed/FLAGbc71c265a [2019-10-15 03:32:13,897 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/be3d78c1b/abdcfcf2b4314b268ea364a91ff810ed [2019-10-15 03:32:13,907 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-10-15 03:32:13,909 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-10-15 03:32:13,910 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-10-15 03:32:13,910 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-10-15 03:32:13,913 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-10-15 03:32:13,914 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 03:32:13" (1/1) ... [2019-10-15 03:32:13,917 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1b2e1afb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 03:32:13, skipping insertion in model container [2019-10-15 03:32:13,917 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.10 03:32:13" (1/1) ... [2019-10-15 03:32:13,924 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-10-15 03:32:13,971 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-10-15 03:32:14,202 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-15 03:32:14,209 INFO L188 MainTranslator]: Completed pre-run [2019-10-15 03:32:14,338 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-10-15 03:32:14,359 INFO L192 MainTranslator]: Completed translation [2019-10-15 03:32:14,360 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 03:32:14 WrapperNode [2019-10-15 03:32:14,360 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-10-15 03:32:14,361 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-10-15 03:32:14,361 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-10-15 03:32:14,361 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-10-15 03:32:14,372 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 03:32:14" (1/1) ... [2019-10-15 03:32:14,372 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 03:32:14" (1/1) ... [2019-10-15 03:32:14,378 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 03:32:14" (1/1) ... [2019-10-15 03:32:14,379 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 03:32:14" (1/1) ... [2019-10-15 03:32:14,388 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 03:32:14" (1/1) ... [2019-10-15 03:32:14,398 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 03:32:14" (1/1) ... [2019-10-15 03:32:14,401 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 03:32:14" (1/1) ... [2019-10-15 03:32:14,404 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-10-15 03:32:14,405 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-10-15 03:32:14,405 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-10-15 03:32:14,405 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-10-15 03:32:14,406 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 03:32:14" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-10-15 03:32:14,456 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-10-15 03:32:14,456 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-10-15 03:32:14,457 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2019-10-15 03:32:14,457 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2019-10-15 03:32:14,457 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2019-10-15 03:32:14,457 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2019-10-15 03:32:14,457 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2019-10-15 03:32:14,457 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2019-10-15 03:32:14,458 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2019-10-15 03:32:14,458 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2019-10-15 03:32:14,458 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2019-10-15 03:32:14,458 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2019-10-15 03:32:14,458 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2019-10-15 03:32:14,458 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2019-10-15 03:32:14,459 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2019-10-15 03:32:14,459 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2019-10-15 03:32:14,459 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2019-10-15 03:32:14,459 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2019-10-15 03:32:14,459 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2019-10-15 03:32:14,460 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2019-10-15 03:32:14,460 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2019-10-15 03:32:14,460 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2019-10-15 03:32:14,460 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-10-15 03:32:14,460 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2019-10-15 03:32:14,460 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2019-10-15 03:32:14,461 INFO L130 BoogieDeclarations]: Found specification of procedure error [2019-10-15 03:32:14,461 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2019-10-15 03:32:14,461 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2019-10-15 03:32:14,461 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2019-10-15 03:32:14,461 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2019-10-15 03:32:14,461 INFO L130 BoogieDeclarations]: Found specification of procedure master [2019-10-15 03:32:14,462 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2019-10-15 03:32:14,462 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2019-10-15 03:32:14,462 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2019-10-15 03:32:14,462 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2019-10-15 03:32:14,462 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2019-10-15 03:32:14,463 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2019-10-15 03:32:14,463 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2019-10-15 03:32:14,463 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2019-10-15 03:32:14,463 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2019-10-15 03:32:14,463 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2019-10-15 03:32:14,463 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2019-10-15 03:32:14,464 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2019-10-15 03:32:14,464 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2019-10-15 03:32:14,464 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2019-10-15 03:32:14,464 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-10-15 03:32:14,464 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-10-15 03:32:14,464 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-10-15 03:32:15,290 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-10-15 03:32:15,290 INFO L284 CfgBuilder]: Removed 6 assume(true) statements. [2019-10-15 03:32:15,292 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 03:32:15 BoogieIcfgContainer [2019-10-15 03:32:15,292 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-10-15 03:32:15,293 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-10-15 03:32:15,294 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-10-15 03:32:15,297 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-10-15 03:32:15,297 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 15.10 03:32:13" (1/3) ... [2019-10-15 03:32:15,298 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4b29bad4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.10 03:32:15, skipping insertion in model container [2019-10-15 03:32:15,298 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.10 03:32:14" (2/3) ... [2019-10-15 03:32:15,299 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4b29bad4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.10 03:32:15, skipping insertion in model container [2019-10-15 03:32:15,299 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.10 03:32:15" (3/3) ... [2019-10-15 03:32:15,301 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.02.cil.c [2019-10-15 03:32:15,311 INFO L152 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-10-15 03:32:15,320 INFO L164 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-10-15 03:32:15,331 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-10-15 03:32:15,359 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-10-15 03:32:15,359 INFO L374 AbstractCegarLoop]: Hoare is true [2019-10-15 03:32:15,359 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-10-15 03:32:15,360 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-10-15 03:32:15,360 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-10-15 03:32:15,360 INFO L378 AbstractCegarLoop]: Difference is false [2019-10-15 03:32:15,360 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-10-15 03:32:15,360 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-10-15 03:32:15,383 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states. [2019-10-15 03:32:15,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-10-15 03:32:15,393 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:15,394 INFO L380 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:15,396 INFO L410 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:15,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:15,402 INFO L82 PathProgramCache]: Analyzing trace with hash -1953432145, now seen corresponding path program 1 times [2019-10-15 03:32:15,412 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:15,412 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985836254] [2019-10-15 03:32:15,413 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:15,413 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:15,413 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:15,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:15,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-10-15 03:32:15,765 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985836254] [2019-10-15 03:32:15,767 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 03:32:15,767 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-15 03:32:15,768 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116168796] [2019-10-15 03:32:15,773 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-15 03:32:15,774 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:15,804 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-15 03:32:15,805 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 03:32:15,807 INFO L87 Difference]: Start difference. First operand 123 states. Second operand 3 states. [2019-10-15 03:32:15,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:15,920 INFO L93 Difference]: Finished difference Result 328 states and 445 transitions. [2019-10-15 03:32:15,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-15 03:32:15,922 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2019-10-15 03:32:15,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:15,938 INFO L225 Difference]: With dead ends: 328 [2019-10-15 03:32:15,938 INFO L226 Difference]: Without dead ends: 209 [2019-10-15 03:32:15,943 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 03:32:15,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2019-10-15 03:32:16,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 209. [2019-10-15 03:32:16,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209 states. [2019-10-15 03:32:16,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209 states to 209 states and 270 transitions. [2019-10-15 03:32:16,016 INFO L78 Accepts]: Start accepts. Automaton has 209 states and 270 transitions. Word has length 64 [2019-10-15 03:32:16,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:16,017 INFO L462 AbstractCegarLoop]: Abstraction has 209 states and 270 transitions. [2019-10-15 03:32:16,017 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-15 03:32:16,017 INFO L276 IsEmpty]: Start isEmpty. Operand 209 states and 270 transitions. [2019-10-15 03:32:16,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2019-10-15 03:32:16,022 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:16,022 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:16,023 INFO L410 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:16,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:16,023 INFO L82 PathProgramCache]: Analyzing trace with hash 244655769, now seen corresponding path program 1 times [2019-10-15 03:32:16,023 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:16,024 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905383615] [2019-10-15 03:32:16,024 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:16,024 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:16,024 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:16,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:16,122 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-10-15 03:32:16,122 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905383615] [2019-10-15 03:32:16,123 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 03:32:16,123 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-15 03:32:16,123 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1750522034] [2019-10-15 03:32:16,126 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-15 03:32:16,126 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:16,127 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-15 03:32:16,127 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-10-15 03:32:16,127 INFO L87 Difference]: Start difference. First operand 209 states and 270 transitions. Second operand 4 states. [2019-10-15 03:32:16,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:16,290 INFO L93 Difference]: Finished difference Result 590 states and 792 transitions. [2019-10-15 03:32:16,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-15 03:32:16,290 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 78 [2019-10-15 03:32:16,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:16,297 INFO L225 Difference]: With dead ends: 590 [2019-10-15 03:32:16,297 INFO L226 Difference]: Without dead ends: 398 [2019-10-15 03:32:16,301 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-10-15 03:32:16,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 398 states. [2019-10-15 03:32:16,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 398 to 327. [2019-10-15 03:32:16,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 327 states. [2019-10-15 03:32:16,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 441 transitions. [2019-10-15 03:32:16,378 INFO L78 Accepts]: Start accepts. Automaton has 327 states and 441 transitions. Word has length 78 [2019-10-15 03:32:16,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:16,381 INFO L462 AbstractCegarLoop]: Abstraction has 327 states and 441 transitions. [2019-10-15 03:32:16,382 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-15 03:32:16,382 INFO L276 IsEmpty]: Start isEmpty. Operand 327 states and 441 transitions. [2019-10-15 03:32:16,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2019-10-15 03:32:16,394 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:16,395 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:16,395 INFO L410 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:16,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:16,396 INFO L82 PathProgramCache]: Analyzing trace with hash -2111280734, now seen corresponding path program 1 times [2019-10-15 03:32:16,396 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:16,396 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [630241085] [2019-10-15 03:32:16,396 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:16,396 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:16,397 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:16,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:16,559 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-10-15 03:32:16,559 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [630241085] [2019-10-15 03:32:16,560 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 03:32:16,560 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-15 03:32:16,561 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066790455] [2019-10-15 03:32:16,562 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-15 03:32:16,562 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:16,562 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-15 03:32:16,563 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 03:32:16,563 INFO L87 Difference]: Start difference. First operand 327 states and 441 transitions. Second operand 3 states. [2019-10-15 03:32:16,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:16,647 INFO L93 Difference]: Finished difference Result 835 states and 1143 transitions. [2019-10-15 03:32:16,647 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-15 03:32:16,647 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 112 [2019-10-15 03:32:16,648 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:16,657 INFO L225 Difference]: With dead ends: 835 [2019-10-15 03:32:16,657 INFO L226 Difference]: Without dead ends: 525 [2019-10-15 03:32:16,660 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 03:32:16,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 525 states. [2019-10-15 03:32:16,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 525 to 417. [2019-10-15 03:32:16,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 417 states. [2019-10-15 03:32:16,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 417 states to 417 states and 572 transitions. [2019-10-15 03:32:16,736 INFO L78 Accepts]: Start accepts. Automaton has 417 states and 572 transitions. Word has length 112 [2019-10-15 03:32:16,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:16,739 INFO L462 AbstractCegarLoop]: Abstraction has 417 states and 572 transitions. [2019-10-15 03:32:16,739 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-15 03:32:16,739 INFO L276 IsEmpty]: Start isEmpty. Operand 417 states and 572 transitions. [2019-10-15 03:32:16,745 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-10-15 03:32:16,745 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:16,745 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:16,746 INFO L410 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:16,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:16,746 INFO L82 PathProgramCache]: Analyzing trace with hash 77978997, now seen corresponding path program 1 times [2019-10-15 03:32:16,746 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:16,747 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257986616] [2019-10-15 03:32:16,747 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:16,747 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:16,747 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:16,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:16,932 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 4 proven. 7 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-10-15 03:32:16,932 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257986616] [2019-10-15 03:32:16,933 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [382628789] [2019-10-15 03:32:16,933 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-15 03:32:17,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:17,088 INFO L256 TraceCheckSpWp]: Trace formula consists of 599 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-15 03:32:17,102 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-15 03:32:17,134 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2019-10-15 03:32:17,135 INFO L321 TraceCheckSpWp]: Computing backward predicates... [2019-10-15 03:32:17,282 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-10-15 03:32:17,283 INFO L223 tionRefinementEngine]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2019-10-15 03:32:17,283 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [5] total 6 [2019-10-15 03:32:17,283 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127906624] [2019-10-15 03:32:17,284 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-15 03:32:17,285 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:17,285 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-15 03:32:17,285 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-15 03:32:17,285 INFO L87 Difference]: Start difference. First operand 417 states and 572 transitions. Second operand 4 states. [2019-10-15 03:32:17,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:17,543 INFO L93 Difference]: Finished difference Result 1202 states and 1771 transitions. [2019-10-15 03:32:17,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-15 03:32:17,543 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 113 [2019-10-15 03:32:17,544 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:17,551 INFO L225 Difference]: With dead ends: 1202 [2019-10-15 03:32:17,551 INFO L226 Difference]: Without dead ends: 801 [2019-10-15 03:32:17,554 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 231 GetRequests, 227 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-15 03:32:17,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 801 states. [2019-10-15 03:32:17,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 801 to 780. [2019-10-15 03:32:17,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 780 states. [2019-10-15 03:32:17,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 780 states to 780 states and 1056 transitions. [2019-10-15 03:32:17,646 INFO L78 Accepts]: Start accepts. Automaton has 780 states and 1056 transitions. Word has length 113 [2019-10-15 03:32:17,647 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:17,647 INFO L462 AbstractCegarLoop]: Abstraction has 780 states and 1056 transitions. [2019-10-15 03:32:17,648 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-15 03:32:17,648 INFO L276 IsEmpty]: Start isEmpty. Operand 780 states and 1056 transitions. [2019-10-15 03:32:17,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-10-15 03:32:17,653 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:17,653 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:17,860 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-15 03:32:17,860 INFO L410 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:17,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:17,861 INFO L82 PathProgramCache]: Analyzing trace with hash 8310746, now seen corresponding path program 1 times [2019-10-15 03:32:17,862 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:17,862 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631173525] [2019-10-15 03:32:17,862 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:17,863 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:17,863 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:17,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:17,921 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-10-15 03:32:17,922 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631173525] [2019-10-15 03:32:17,922 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 03:32:17,922 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-10-15 03:32:17,923 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74567214] [2019-10-15 03:32:17,923 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-10-15 03:32:17,923 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:17,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-10-15 03:32:17,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 03:32:17,924 INFO L87 Difference]: Start difference. First operand 780 states and 1056 transitions. Second operand 3 states. [2019-10-15 03:32:18,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:18,015 INFO L93 Difference]: Finished difference Result 1950 states and 2661 transitions. [2019-10-15 03:32:18,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-10-15 03:32:18,016 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-10-15 03:32:18,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:18,025 INFO L225 Difference]: With dead ends: 1950 [2019-10-15 03:32:18,025 INFO L226 Difference]: Without dead ends: 1187 [2019-10-15 03:32:18,030 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-10-15 03:32:18,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1187 states. [2019-10-15 03:32:18,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1187 to 1039. [2019-10-15 03:32:18,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1039 states. [2019-10-15 03:32:18,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1039 states to 1039 states and 1391 transitions. [2019-10-15 03:32:18,105 INFO L78 Accepts]: Start accepts. Automaton has 1039 states and 1391 transitions. Word has length 113 [2019-10-15 03:32:18,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:18,106 INFO L462 AbstractCegarLoop]: Abstraction has 1039 states and 1391 transitions. [2019-10-15 03:32:18,106 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-10-15 03:32:18,106 INFO L276 IsEmpty]: Start isEmpty. Operand 1039 states and 1391 transitions. [2019-10-15 03:32:18,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2019-10-15 03:32:18,109 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:18,110 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:18,110 INFO L410 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:18,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:18,110 INFO L82 PathProgramCache]: Analyzing trace with hash -1572067527, now seen corresponding path program 1 times [2019-10-15 03:32:18,111 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:18,111 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054849819] [2019-10-15 03:32:18,111 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:18,111 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:18,111 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:18,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:18,284 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-10-15 03:32:18,285 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054849819] [2019-10-15 03:32:18,285 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 03:32:18,286 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-10-15 03:32:18,287 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799680779] [2019-10-15 03:32:18,287 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-10-15 03:32:18,288 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:18,288 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-10-15 03:32:18,288 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2019-10-15 03:32:18,289 INFO L87 Difference]: Start difference. First operand 1039 states and 1391 transitions. Second operand 8 states. [2019-10-15 03:32:19,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:19,219 INFO L93 Difference]: Finished difference Result 2672 states and 3689 transitions. [2019-10-15 03:32:19,220 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-10-15 03:32:19,220 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 115 [2019-10-15 03:32:19,221 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:19,235 INFO L225 Difference]: With dead ends: 2672 [2019-10-15 03:32:19,235 INFO L226 Difference]: Without dead ends: 1650 [2019-10-15 03:32:19,242 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=122, Unknown=0, NotChecked=0, Total=182 [2019-10-15 03:32:19,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1650 states. [2019-10-15 03:32:19,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1650 to 1630. [2019-10-15 03:32:19,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1630 states. [2019-10-15 03:32:19,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1630 states to 1630 states and 2235 transitions. [2019-10-15 03:32:19,373 INFO L78 Accepts]: Start accepts. Automaton has 1630 states and 2235 transitions. Word has length 115 [2019-10-15 03:32:19,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:19,373 INFO L462 AbstractCegarLoop]: Abstraction has 1630 states and 2235 transitions. [2019-10-15 03:32:19,374 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-10-15 03:32:19,374 INFO L276 IsEmpty]: Start isEmpty. Operand 1630 states and 2235 transitions. [2019-10-15 03:32:19,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2019-10-15 03:32:19,378 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:19,378 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:19,378 INFO L410 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:19,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:19,379 INFO L82 PathProgramCache]: Analyzing trace with hash -846455608, now seen corresponding path program 1 times [2019-10-15 03:32:19,379 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:19,379 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901533556] [2019-10-15 03:32:19,379 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:19,380 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:19,380 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:19,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:19,450 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2019-10-15 03:32:19,451 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901533556] [2019-10-15 03:32:19,451 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 03:32:19,451 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-15 03:32:19,451 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [401666589] [2019-10-15 03:32:19,452 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-15 03:32:19,452 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:19,452 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-15 03:32:19,453 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-15 03:32:19,453 INFO L87 Difference]: Start difference. First operand 1630 states and 2235 transitions. Second operand 4 states. [2019-10-15 03:32:19,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:19,774 INFO L93 Difference]: Finished difference Result 3660 states and 5105 transitions. [2019-10-15 03:32:19,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-15 03:32:19,775 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 114 [2019-10-15 03:32:19,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:19,788 INFO L225 Difference]: With dead ends: 3660 [2019-10-15 03:32:19,788 INFO L226 Difference]: Without dead ends: 2047 [2019-10-15 03:32:19,798 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-15 03:32:19,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states. [2019-10-15 03:32:19,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2013. [2019-10-15 03:32:19,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2013 states. [2019-10-15 03:32:19,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2013 states to 2013 states and 2682 transitions. [2019-10-15 03:32:19,940 INFO L78 Accepts]: Start accepts. Automaton has 2013 states and 2682 transitions. Word has length 114 [2019-10-15 03:32:19,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:19,941 INFO L462 AbstractCegarLoop]: Abstraction has 2013 states and 2682 transitions. [2019-10-15 03:32:19,941 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-15 03:32:19,941 INFO L276 IsEmpty]: Start isEmpty. Operand 2013 states and 2682 transitions. [2019-10-15 03:32:19,946 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2019-10-15 03:32:19,946 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:19,946 INFO L380 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:19,946 INFO L410 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:19,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:19,947 INFO L82 PathProgramCache]: Analyzing trace with hash -1944182159, now seen corresponding path program 1 times [2019-10-15 03:32:19,947 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:19,947 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672725747] [2019-10-15 03:32:19,947 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:19,948 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:19,948 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:19,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:20,049 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2019-10-15 03:32:20,049 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [672725747] [2019-10-15 03:32:20,049 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 03:32:20,050 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-10-15 03:32:20,050 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [793391338] [2019-10-15 03:32:20,050 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-10-15 03:32:20,051 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:20,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-10-15 03:32:20,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-10-15 03:32:20,051 INFO L87 Difference]: Start difference. First operand 2013 states and 2682 transitions. Second operand 9 states. [2019-10-15 03:32:21,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:21,360 INFO L93 Difference]: Finished difference Result 6608 states and 9241 transitions. [2019-10-15 03:32:21,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-10-15 03:32:21,361 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 115 [2019-10-15 03:32:21,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:21,386 INFO L225 Difference]: With dead ends: 6608 [2019-10-15 03:32:21,386 INFO L226 Difference]: Without dead ends: 3156 [2019-10-15 03:32:21,411 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=107, Invalid=235, Unknown=0, NotChecked=0, Total=342 [2019-10-15 03:32:21,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3156 states. [2019-10-15 03:32:21,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3156 to 2761. [2019-10-15 03:32:21,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2761 states. [2019-10-15 03:32:21,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2761 states to 2761 states and 3668 transitions. [2019-10-15 03:32:21,665 INFO L78 Accepts]: Start accepts. Automaton has 2761 states and 3668 transitions. Word has length 115 [2019-10-15 03:32:21,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:21,666 INFO L462 AbstractCegarLoop]: Abstraction has 2761 states and 3668 transitions. [2019-10-15 03:32:21,666 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-10-15 03:32:21,666 INFO L276 IsEmpty]: Start isEmpty. Operand 2761 states and 3668 transitions. [2019-10-15 03:32:21,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2019-10-15 03:32:21,675 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:21,676 INFO L380 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:21,676 INFO L410 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:21,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:21,677 INFO L82 PathProgramCache]: Analyzing trace with hash -453819748, now seen corresponding path program 1 times [2019-10-15 03:32:21,677 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:21,678 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640568622] [2019-10-15 03:32:21,678 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:21,678 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:21,678 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:21,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:21,936 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2019-10-15 03:32:21,936 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640568622] [2019-10-15 03:32:21,937 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1299917231] [2019-10-15 03:32:21,937 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-15 03:32:22,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:22,075 INFO L256 TraceCheckSpWp]: Trace formula consists of 692 conjuncts, 21 conjunts are in the unsatisfiable core [2019-10-15 03:32:22,083 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-15 03:32:22,249 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 63 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-15 03:32:22,250 INFO L321 TraceCheckSpWp]: Computing backward predicates... [2019-10-15 03:32:22,445 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-15 03:32:22,550 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-15 03:32:22,551 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-15 03:32:22,572 INFO L319 QuantifierPusher]: Applying distributivity, recursing on 2 terms [2019-10-15 03:32:22,620 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 21 proven. 8 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2019-10-15 03:32:22,621 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-15 03:32:22,621 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [9, 8] total 22 [2019-10-15 03:32:22,621 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [388739179] [2019-10-15 03:32:22,623 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-10-15 03:32:22,623 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:22,624 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-10-15 03:32:22,624 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=392, Unknown=0, NotChecked=0, Total=462 [2019-10-15 03:32:22,624 INFO L87 Difference]: Start difference. First operand 2761 states and 3668 transitions. Second operand 11 states. [2019-10-15 03:32:24,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:24,648 INFO L93 Difference]: Finished difference Result 9966 states and 15069 transitions. [2019-10-15 03:32:24,649 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-10-15 03:32:24,649 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 138 [2019-10-15 03:32:24,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:24,708 INFO L225 Difference]: With dead ends: 9966 [2019-10-15 03:32:24,708 INFO L226 Difference]: Without dead ends: 7222 [2019-10-15 03:32:24,742 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 309 GetRequests, 275 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 205 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=225, Invalid=1035, Unknown=0, NotChecked=0, Total=1260 [2019-10-15 03:32:24,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7222 states. [2019-10-15 03:32:25,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7222 to 6601. [2019-10-15 03:32:25,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6601 states. [2019-10-15 03:32:25,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6601 states to 6601 states and 9255 transitions. [2019-10-15 03:32:25,477 INFO L78 Accepts]: Start accepts. Automaton has 6601 states and 9255 transitions. Word has length 138 [2019-10-15 03:32:25,477 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:25,477 INFO L462 AbstractCegarLoop]: Abstraction has 6601 states and 9255 transitions. [2019-10-15 03:32:25,477 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-10-15 03:32:25,478 INFO L276 IsEmpty]: Start isEmpty. Operand 6601 states and 9255 transitions. [2019-10-15 03:32:25,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-10-15 03:32:25,493 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:25,494 INFO L380 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:25,700 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-15 03:32:25,700 INFO L410 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:25,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:25,701 INFO L82 PathProgramCache]: Analyzing trace with hash -539214046, now seen corresponding path program 1 times [2019-10-15 03:32:25,701 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:25,702 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236965069] [2019-10-15 03:32:25,702 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:25,702 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:25,702 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:25,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:25,866 INFO L134 CoverageAnalysis]: Checked inductivity of 70 backedges. 19 proven. 11 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2019-10-15 03:32:25,869 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236965069] [2019-10-15 03:32:25,870 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [418337644] [2019-10-15 03:32:25,870 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-15 03:32:26,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:26,140 INFO L256 TraceCheckSpWp]: Trace formula consists of 706 conjuncts, 11 conjunts are in the unsatisfiable core [2019-10-15 03:32:26,153 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-15 03:32:26,271 INFO L134 CoverageAnalysis]: Checked inductivity of 70 backedges. 64 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-15 03:32:26,271 INFO L321 TraceCheckSpWp]: Computing backward predicates... [2019-10-15 03:32:26,744 INFO L134 CoverageAnalysis]: Checked inductivity of 70 backedges. 23 proven. 3 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2019-10-15 03:32:26,744 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-10-15 03:32:26,744 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11, 6] total 18 [2019-10-15 03:32:26,745 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [371491802] [2019-10-15 03:32:26,745 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-10-15 03:32:26,745 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:26,746 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-10-15 03:32:26,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=257, Unknown=0, NotChecked=0, Total=306 [2019-10-15 03:32:26,746 INFO L87 Difference]: Start difference. First operand 6601 states and 9255 transitions. Second operand 6 states. [2019-10-15 03:32:27,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:27,186 INFO L93 Difference]: Finished difference Result 12357 states and 17356 transitions. [2019-10-15 03:32:27,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-10-15 03:32:27,187 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 140 [2019-10-15 03:32:27,187 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:27,229 INFO L225 Difference]: With dead ends: 12357 [2019-10-15 03:32:27,230 INFO L226 Difference]: Without dead ends: 5773 [2019-10-15 03:32:27,270 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 295 GetRequests, 276 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 74 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2019-10-15 03:32:27,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5773 states. [2019-10-15 03:32:27,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5773 to 5192. [2019-10-15 03:32:27,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5192 states. [2019-10-15 03:32:27,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5192 states to 5192 states and 7011 transitions. [2019-10-15 03:32:27,890 INFO L78 Accepts]: Start accepts. Automaton has 5192 states and 7011 transitions. Word has length 140 [2019-10-15 03:32:27,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:27,890 INFO L462 AbstractCegarLoop]: Abstraction has 5192 states and 7011 transitions. [2019-10-15 03:32:27,890 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-10-15 03:32:27,891 INFO L276 IsEmpty]: Start isEmpty. Operand 5192 states and 7011 transitions. [2019-10-15 03:32:27,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2019-10-15 03:32:27,901 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:27,901 INFO L380 BasicCegarLoop]: trace histogram [5, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:28,106 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-15 03:32:28,108 INFO L410 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:28,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:28,108 INFO L82 PathProgramCache]: Analyzing trace with hash -1561917984, now seen corresponding path program 1 times [2019-10-15 03:32:28,108 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:28,108 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40417302] [2019-10-15 03:32:28,109 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:28,109 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:28,109 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:28,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:28,243 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 17 proven. 13 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-10-15 03:32:28,244 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40417302] [2019-10-15 03:32:28,244 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [259180651] [2019-10-15 03:32:28,244 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-15 03:32:28,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:28,456 INFO L256 TraceCheckSpWp]: Trace formula consists of 730 conjuncts, 3 conjunts are in the unsatisfiable core [2019-10-15 03:32:28,460 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2019-10-15 03:32:28,503 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 63 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-10-15 03:32:28,503 INFO L321 TraceCheckSpWp]: Computing backward predicates... [2019-10-15 03:32:28,638 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2019-10-15 03:32:28,638 INFO L223 tionRefinementEngine]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2019-10-15 03:32:28,639 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [3, 4] imperfect sequences [5] total 6 [2019-10-15 03:32:28,639 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [818346113] [2019-10-15 03:32:28,640 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-15 03:32:28,641 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:28,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-15 03:32:28,641 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-15 03:32:28,641 INFO L87 Difference]: Start difference. First operand 5192 states and 7011 transitions. Second operand 4 states. [2019-10-15 03:32:29,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:29,319 INFO L93 Difference]: Finished difference Result 10440 states and 14542 transitions. [2019-10-15 03:32:29,319 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-15 03:32:29,320 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 145 [2019-10-15 03:32:29,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:29,380 INFO L225 Difference]: With dead ends: 10440 [2019-10-15 03:32:29,380 INFO L226 Difference]: Without dead ends: 5266 [2019-10-15 03:32:29,406 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 296 GetRequests, 292 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-10-15 03:32:29,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5266 states. [2019-10-15 03:32:29,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5266 to 5178. [2019-10-15 03:32:29,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5178 states. [2019-10-15 03:32:29,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5178 states to 5178 states and 6465 transitions. [2019-10-15 03:32:29,828 INFO L78 Accepts]: Start accepts. Automaton has 5178 states and 6465 transitions. Word has length 145 [2019-10-15 03:32:29,829 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:29,829 INFO L462 AbstractCegarLoop]: Abstraction has 5178 states and 6465 transitions. [2019-10-15 03:32:29,829 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-15 03:32:29,829 INFO L276 IsEmpty]: Start isEmpty. Operand 5178 states and 6465 transitions. [2019-10-15 03:32:29,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2019-10-15 03:32:29,835 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:29,835 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:30,040 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-10-15 03:32:30,040 INFO L410 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:30,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:30,041 INFO L82 PathProgramCache]: Analyzing trace with hash 2009742356, now seen corresponding path program 1 times [2019-10-15 03:32:30,041 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:30,041 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904810560] [2019-10-15 03:32:30,041 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:30,041 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:30,041 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:30,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:30,139 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 62 trivial. 0 not checked. [2019-10-15 03:32:30,139 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904810560] [2019-10-15 03:32:30,139 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 03:32:30,140 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-10-15 03:32:30,140 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449254405] [2019-10-15 03:32:30,143 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-10-15 03:32:30,144 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:30,144 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-10-15 03:32:30,144 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-15 03:32:30,144 INFO L87 Difference]: Start difference. First operand 5178 states and 6465 transitions. Second operand 4 states. [2019-10-15 03:32:30,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:30,528 INFO L93 Difference]: Finished difference Result 7774 states and 10194 transitions. [2019-10-15 03:32:30,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-10-15 03:32:30,529 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 154 [2019-10-15 03:32:30,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:30,568 INFO L225 Difference]: With dead ends: 7774 [2019-10-15 03:32:30,568 INFO L226 Difference]: Without dead ends: 5158 [2019-10-15 03:32:30,580 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-10-15 03:32:30,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5158 states. [2019-10-15 03:32:31,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5158 to 5158. [2019-10-15 03:32:31,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5158 states. [2019-10-15 03:32:31,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5158 states to 5158 states and 6396 transitions. [2019-10-15 03:32:31,416 INFO L78 Accepts]: Start accepts. Automaton has 5158 states and 6396 transitions. Word has length 154 [2019-10-15 03:32:31,418 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:31,418 INFO L462 AbstractCegarLoop]: Abstraction has 5158 states and 6396 transitions. [2019-10-15 03:32:31,418 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-10-15 03:32:31,418 INFO L276 IsEmpty]: Start isEmpty. Operand 5158 states and 6396 transitions. [2019-10-15 03:32:31,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2019-10-15 03:32:31,425 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:31,425 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:31,426 INFO L410 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:31,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:31,426 INFO L82 PathProgramCache]: Analyzing trace with hash -2109454516, now seen corresponding path program 1 times [2019-10-15 03:32:31,426 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:31,426 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274621071] [2019-10-15 03:32:31,427 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:31,427 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:31,427 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:31,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-10-15 03:32:31,575 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 24 proven. 0 refuted. 0 times theorem prover too weak. 62 trivial. 0 not checked. [2019-10-15 03:32:31,576 INFO L342 tionRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1274621071] [2019-10-15 03:32:31,576 INFO L223 tionRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-10-15 03:32:31,576 INFO L236 tionRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-10-15 03:32:31,576 INFO L342 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [642546669] [2019-10-15 03:32:31,577 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-10-15 03:32:31,577 INFO L137 tionRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-10-15 03:32:31,577 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-10-15 03:32:31,578 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2019-10-15 03:32:31,578 INFO L87 Difference]: Start difference. First operand 5158 states and 6396 transitions. Second operand 7 states. [2019-10-15 03:32:32,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-10-15 03:32:32,675 INFO L93 Difference]: Finished difference Result 12608 states and 15612 transitions. [2019-10-15 03:32:32,675 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-10-15 03:32:32,676 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 155 [2019-10-15 03:32:32,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-10-15 03:32:32,726 INFO L225 Difference]: With dead ends: 12608 [2019-10-15 03:32:32,726 INFO L226 Difference]: Without dead ends: 7905 [2019-10-15 03:32:32,739 INFO L600 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 7 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2019-10-15 03:32:32,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7905 states. [2019-10-15 03:32:33,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7905 to 7823. [2019-10-15 03:32:33,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7823 states. [2019-10-15 03:32:33,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7823 states to 7823 states and 9470 transitions. [2019-10-15 03:32:33,255 INFO L78 Accepts]: Start accepts. Automaton has 7823 states and 9470 transitions. Word has length 155 [2019-10-15 03:32:33,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-10-15 03:32:33,255 INFO L462 AbstractCegarLoop]: Abstraction has 7823 states and 9470 transitions. [2019-10-15 03:32:33,255 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-10-15 03:32:33,255 INFO L276 IsEmpty]: Start isEmpty. Operand 7823 states and 9470 transitions. [2019-10-15 03:32:33,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2019-10-15 03:32:33,260 INFO L372 BasicCegarLoop]: Found error trace [2019-10-15 03:32:33,261 INFO L380 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-10-15 03:32:33,261 INFO L410 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-10-15 03:32:33,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-10-15 03:32:33,262 INFO L82 PathProgramCache]: Analyzing trace with hash 1752141364, now seen corresponding path program 1 times [2019-10-15 03:32:33,262 INFO L157 tionRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-10-15 03:32:33,262 INFO L342 tionRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145159852] [2019-10-15 03:32:33,262 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:33,262 INFO L116 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-10-15 03:32:33,262 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-10-15 03:32:33,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-15 03:32:33,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-10-15 03:32:33,394 INFO L168 tionRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2019-10-15 03:32:33,394 INFO L445 BasicCegarLoop]: Counterexample might be feasible [2019-10-15 03:32:33,579 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 15.10 03:32:33 BoogieIcfgContainer [2019-10-15 03:32:33,579 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-10-15 03:32:33,588 INFO L168 Benchmark]: Toolchain (without parser) took 19672.67 ms. Allocated memory was 135.8 MB in the beginning and 838.3 MB in the end (delta: 702.5 MB). Free memory was 99.3 MB in the beginning and 449.5 MB in the end (delta: -350.1 MB). Peak memory consumption was 352.4 MB. Max. memory is 7.1 GB. [2019-10-15 03:32:33,588 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 135.8 MB. Free memory was 117.8 MB in the beginning and 117.6 MB in the end (delta: 210.0 kB). Peak memory consumption was 210.0 kB. Max. memory is 7.1 GB. [2019-10-15 03:32:33,589 INFO L168 Benchmark]: CACSL2BoogieTranslator took 450.65 ms. Allocated memory was 135.8 MB in the beginning and 199.2 MB in the end (delta: 63.4 MB). Free memory was 98.9 MB in the beginning and 175.2 MB in the end (delta: -76.3 MB). Peak memory consumption was 24.9 MB. Max. memory is 7.1 GB. [2019-10-15 03:32:33,590 INFO L168 Benchmark]: Boogie Preprocessor took 43.75 ms. Allocated memory is still 199.2 MB. Free memory was 175.2 MB in the beginning and 173.1 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 7.1 GB. [2019-10-15 03:32:33,591 INFO L168 Benchmark]: RCFGBuilder took 887.65 ms. Allocated memory is still 199.2 MB. Free memory was 173.1 MB in the beginning and 107.6 MB in the end (delta: 65.5 MB). Peak memory consumption was 65.5 MB. Max. memory is 7.1 GB. [2019-10-15 03:32:33,593 INFO L168 Benchmark]: TraceAbstraction took 18285.89 ms. Allocated memory was 199.2 MB in the beginning and 838.3 MB in the end (delta: 639.1 MB). Free memory was 107.6 MB in the beginning and 461.8 MB in the end (delta: -354.2 MB). Peak memory consumption was 284.9 MB. Max. memory is 7.1 GB. [2019-10-15 03:32:33,602 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 135.8 MB. Free memory was 117.8 MB in the beginning and 117.6 MB in the end (delta: 210.0 kB). Peak memory consumption was 210.0 kB. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 450.65 ms. Allocated memory was 135.8 MB in the beginning and 199.2 MB in the end (delta: 63.4 MB). Free memory was 98.9 MB in the beginning and 175.2 MB in the end (delta: -76.3 MB). Peak memory consumption was 24.9 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 43.75 ms. Allocated memory is still 199.2 MB. Free memory was 175.2 MB in the beginning and 173.1 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 7.1 GB. * RCFGBuilder took 887.65 ms. Allocated memory is still 199.2 MB. Free memory was 173.1 MB in the beginning and 107.6 MB in the end (delta: 65.5 MB). Peak memory consumption was 65.5 MB. Max. memory is 7.1 GB. * TraceAbstraction took 18285.89 ms. Allocated memory was 199.2 MB in the beginning and 838.3 MB in the end (delta: 639.1 MB). Free memory was 107.6 MB in the beginning and 461.8 MB in the end (delta: -354.2 MB). Peak memory consumption was 284.9 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int m_i ; [L22] int t1_i ; [L23] int t2_i ; [L24] int M_E = 2; [L25] int T1_E = 2; [L26] int T2_E = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; [L563] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L567] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L477] m_i = 1 [L478] t1_i = 1 [L479] t2_i = 1 [L567] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L568] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L504] int kernel_st ; [L505] int tmp ; [L506] int tmp___0 ; [L510] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L511] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L211] COND TRUE m_i == 1 [L212] m_st = 0 [L216] COND TRUE t1_i == 1 [L217] t1_st = 0 [L221] COND TRUE t2_i == 1 [L222] t2_st = 0 [L512] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L324] COND FALSE !(M_E == 0) [L329] COND FALSE !(T1_E == 0) [L334] COND FALSE !(T2_E == 0) [L339] COND FALSE !(E_1 == 0) [L344] COND FALSE !(E_2 == 0) [L513] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L514] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L158] return (__retres1); [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L165] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L177] return (__retres1); [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L184] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L196] return (__retres1); [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE !(\read(tmp___1)) [L514] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L357] COND FALSE !(M_E == 1) [L362] COND FALSE !(T1_E == 1) [L367] COND FALSE !(T2_E == 1) [L372] COND FALSE !(E_1 == 1) [L377] COND FALSE !(E_2 == 1) [L515] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L518] COND TRUE 1 [L521] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L522] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L257] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L231] int __retres1 ; [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 [L252] return (__retres1); [L264] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L78] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L89] COND TRUE 1 [L91] t1_pc = 1 [L92] t1_st = 2 [L291] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L113] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L124] COND TRUE 1 [L126] t2_pc = 1 [L127] t2_st = 2 [L305] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L231] int __retres1 ; [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 [L252] return (__retres1); [L264] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND TRUE \read(tmp_ndt_1) [L276] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L277] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L37] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L48] COND TRUE 1 [L51] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] return (__retres1); [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND TRUE E_1 == 1 [L167] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] return (__retres1); [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND TRUE \read(tmp___0) [L404] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] return (__retres1); [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE !(\read(tmp___1)) [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L53] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L56] COND TRUE 1 [L58] m_pc = 1 [L59] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L277] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L78] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L81] COND TRUE t1_pc == 1 [L97] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L98] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L147] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] return (__retres1); [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] return (__retres1); [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND TRUE E_2 == 1 [L186] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] return (__retres1); [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND TRUE \read(tmp___1) [L412] t2_st = 0 [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L98] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L99] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L89] COND TRUE 1 [L91] t1_pc = 1 [L92] t1_st = 2 [L291] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L113] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L116] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L132] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 23 procedures, 123 locations, 1 error locations. Result: UNSAFE, OverallTime: 18.2s, OverallIterations: 14, TraceHistogramMax: 5, AutomataDifference: 8.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2847 SDtfs, 3005 SDslu, 3676 SDs, 0 SdLazy, 3148 SolverSat, 1079 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1218 GetRequests, 1109 SyntacticMatches, 2 SemanticMatches, 107 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 319 ImplicationChecksByTransitivity, 1.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=7823occurred in iteration=13, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 4.0s AutomataMinimizationTime, 13 MinimizatonAttempts, 2169 StatesRemovedByMinimization, 11 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.3s SsaConstructionTime, 0.7s SatisfiabilityAnalysisTime, 2.7s InterpolantComputationTime, 2248 NumberOfCodeBlocks, 2248 NumberOfCodeBlocksAsserted, 18 NumberOfCheckSat, 2607 ConstructedInterpolants, 0 QuantifiedInterpolants, 543576 SizeOfPredicates, 10 NumberOfNonLiveVariables, 2727 ConjunctsInSsa, 38 ConjunctsInUnsatCore, 21 InterpolantComputations, 15 PerfectInterpolantSequences, 1041/1086 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...