/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml -s ../../../trunk/examples/settings/default/taipan/svcomp-Reach-32bit-Taipan_Default.epf -i ../../../trunk/examples/svcomp/systemc/transmitter.04.cil.c -------------------------------------------------------------------------------- This is Ultimate 0.1.24-6598664 [2019-11-24 06:06:10,531 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-24 06:06:10,534 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-24 06:06:10,551 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-24 06:06:10,552 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-24 06:06:10,554 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-24 06:06:10,556 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-24 06:06:10,567 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-24 06:06:10,569 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-24 06:06:10,570 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-24 06:06:10,570 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-24 06:06:10,572 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... 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[2019-11-24 06:06:10,605 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-24 06:06:10,609 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-24 06:06:10,610 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-24 06:06:10,611 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/taipan/svcomp-Reach-32bit-Taipan_Default.epf [2019-11-24 06:06:10,636 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-24 06:06:10,636 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-24 06:06:10,637 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-11-24 06:06:10,638 INFO L138 SettingsManager]: * User list type=DISABLED [2019-11-24 06:06:10,638 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-11-24 06:06:10,638 INFO L138 SettingsManager]: * Explicit value domain=true [2019-11-24 06:06:10,638 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-11-24 06:06:10,639 INFO L138 SettingsManager]: * Octagon Domain=false [2019-11-24 06:06:10,639 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2019-11-24 06:06:10,639 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-11-24 06:06:10,640 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2019-11-24 06:06:10,641 INFO L138 SettingsManager]: * Interval Domain=false [2019-11-24 06:06:10,641 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2019-11-24 06:06:10,642 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2019-11-24 06:06:10,642 INFO L138 SettingsManager]: * Simplification Technique=SIMPLIFY_QUICK [2019-11-24 06:06:10,643 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-24 06:06:10,644 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-24 06:06:10,644 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-24 06:06:10,644 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-24 06:06:10,644 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-24 06:06:10,644 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-24 06:06:10,644 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-24 06:06:10,645 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-24 06:06:10,645 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-24 06:06:10,645 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-24 06:06:10,645 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-24 06:06:10,646 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-24 06:06:10,646 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-24 06:06:10,647 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-24 06:06:10,647 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-24 06:06:10,647 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-24 06:06:10,648 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-24 06:06:10,648 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-24 06:06:10,648 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2019-11-24 06:06:10,649 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-24 06:06:10,649 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-24 06:06:10,649 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-11-24 06:06:10,650 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-11-24 06:06:10,970 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-24 06:06:10,983 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-24 06:06:10,987 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-24 06:06:10,988 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-24 06:06:10,989 INFO L275 PluginConnector]: CDTParser initialized [2019-11-24 06:06:10,990 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/systemc/transmitter.04.cil.c [2019-11-24 06:06:11,052 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7d836b118/8334a167da434808ba12e989ea132999/FLAG29d7e026a [2019-11-24 06:06:11,558 INFO L306 CDTParser]: Found 1 translation units. [2019-11-24 06:06:11,560 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/systemc/transmitter.04.cil.c [2019-11-24 06:06:11,580 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7d836b118/8334a167da434808ba12e989ea132999/FLAG29d7e026a [2019-11-24 06:06:11,924 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7d836b118/8334a167da434808ba12e989ea132999 [2019-11-24 06:06:11,934 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-24 06:06:11,936 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2019-11-24 06:06:11,937 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-24 06:06:11,937 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-24 06:06:11,940 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-24 06:06:11,941 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 06:06:11" (1/1) ... [2019-11-24 06:06:11,945 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@52a73aee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:11, skipping insertion in model container [2019-11-24 06:06:11,946 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 06:06:11" (1/1) ... [2019-11-24 06:06:11,954 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-24 06:06:12,013 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-24 06:06:12,261 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-24 06:06:12,271 INFO L203 MainTranslator]: Completed pre-run [2019-11-24 06:06:12,409 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-24 06:06:12,441 INFO L208 MainTranslator]: Completed translation [2019-11-24 06:06:12,442 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:12 WrapperNode [2019-11-24 06:06:12,442 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-24 06:06:12,443 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-24 06:06:12,443 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-24 06:06:12,443 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-24 06:06:12,452 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:12" (1/1) ... [2019-11-24 06:06:12,460 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:12" (1/1) ... [2019-11-24 06:06:12,529 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-24 06:06:12,530 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-24 06:06:12,530 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-24 06:06:12,530 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-24 06:06:12,539 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:12" (1/1) ... [2019-11-24 06:06:12,539 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:12" (1/1) ... [2019-11-24 06:06:12,545 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:12" (1/1) ... [2019-11-24 06:06:12,546 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:12" (1/1) ... [2019-11-24 06:06:12,562 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:12" (1/1) ... [2019-11-24 06:06:12,603 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:12" (1/1) ... [2019-11-24 06:06:12,613 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:12" (1/1) ... [2019-11-24 06:06:12,628 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-24 06:06:12,629 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-24 06:06:12,629 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-24 06:06:12,629 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-24 06:06:12,630 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:12" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-24 06:06:12,714 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-24 06:06:12,718 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-24 06:06:15,314 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-24 06:06:15,315 INFO L284 CfgBuilder]: Removed 148 assume(true) statements. [2019-11-24 06:06:15,316 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 06:06:15 BoogieIcfgContainer [2019-11-24 06:06:15,317 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-24 06:06:15,318 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-24 06:06:15,318 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-24 06:06:15,321 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-24 06:06:15,322 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.11 06:06:11" (1/3) ... [2019-11-24 06:06:15,323 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@35fa048 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 06:06:15, skipping insertion in model container [2019-11-24 06:06:15,323 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 06:06:12" (2/3) ... [2019-11-24 06:06:15,324 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@35fa048 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 06:06:15, skipping insertion in model container [2019-11-24 06:06:15,324 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 06:06:15" (3/3) ... [2019-11-24 06:06:15,326 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.04.cil.c [2019-11-24 06:06:15,335 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-24 06:06:15,343 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-24 06:06:15,354 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-24 06:06:15,388 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-24 06:06:15,388 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-24 06:06:15,389 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-24 06:06:15,389 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-24 06:06:15,389 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-24 06:06:15,389 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-24 06:06:15,389 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-24 06:06:15,389 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-24 06:06:15,409 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states. [2019-11-24 06:06:15,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-11-24 06:06:15,416 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:15,417 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:15,417 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:15,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:15,423 INFO L82 PathProgramCache]: Analyzing trace with hash -321320626, now seen corresponding path program 1 times [2019-11-24 06:06:15,431 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:15,432 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589356022] [2019-11-24 06:06:15,432 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:15,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:15,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:15,640 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1589356022] [2019-11-24 06:06:15,640 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:15,641 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-24 06:06:15,643 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357033838] [2019-11-24 06:06:15,648 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:15,648 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:15,662 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:15,663 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:15,665 INFO L87 Difference]: Start difference. First operand 178 states. Second operand 3 states. [2019-11-24 06:06:15,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:15,828 INFO L93 Difference]: Finished difference Result 481 states and 740 transitions. [2019-11-24 06:06:15,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:15,830 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-11-24 06:06:15,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:15,859 INFO L225 Difference]: With dead ends: 481 [2019-11-24 06:06:15,859 INFO L226 Difference]: Without dead ends: 305 [2019-11-24 06:06:15,867 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:15,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 305 states. [2019-11-24 06:06:15,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 305 to 302. [2019-11-24 06:06:15,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 302 states. [2019-11-24 06:06:15,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 452 transitions. [2019-11-24 06:06:15,973 INFO L78 Accepts]: Start accepts. Automaton has 302 states and 452 transitions. Word has length 28 [2019-11-24 06:06:15,973 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:15,973 INFO L462 AbstractCegarLoop]: Abstraction has 302 states and 452 transitions. [2019-11-24 06:06:15,973 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:15,974 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 452 transitions. [2019-11-24 06:06:15,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-11-24 06:06:15,975 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:15,975 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:15,976 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:15,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:15,976 INFO L82 PathProgramCache]: Analyzing trace with hash -1911715603, now seen corresponding path program 1 times [2019-11-24 06:06:15,976 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:15,977 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044081239] [2019-11-24 06:06:15,977 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:16,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:16,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:16,056 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2044081239] [2019-11-24 06:06:16,056 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:16,056 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-24 06:06:16,057 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051571254] [2019-11-24 06:06:16,058 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:16,058 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:16,059 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:16,059 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:16,059 INFO L87 Difference]: Start difference. First operand 302 states and 452 transitions. Second operand 3 states. [2019-11-24 06:06:16,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:16,128 INFO L93 Difference]: Finished difference Result 824 states and 1233 transitions. [2019-11-24 06:06:16,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:16,129 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-11-24 06:06:16,129 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:16,132 INFO L225 Difference]: With dead ends: 824 [2019-11-24 06:06:16,132 INFO L226 Difference]: Without dead ends: 535 [2019-11-24 06:06:16,135 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:16,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 535 states. [2019-11-24 06:06:16,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 535 to 531. [2019-11-24 06:06:16,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 531 states. [2019-11-24 06:06:16,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 531 states to 531 states and 784 transitions. [2019-11-24 06:06:16,159 INFO L78 Accepts]: Start accepts. Automaton has 531 states and 784 transitions. Word has length 28 [2019-11-24 06:06:16,159 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:16,159 INFO L462 AbstractCegarLoop]: Abstraction has 531 states and 784 transitions. [2019-11-24 06:06:16,159 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:16,160 INFO L276 IsEmpty]: Start isEmpty. Operand 531 states and 784 transitions. [2019-11-24 06:06:16,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-11-24 06:06:16,161 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:16,161 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:16,162 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:16,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:16,162 INFO L82 PathProgramCache]: Analyzing trace with hash -771363892, now seen corresponding path program 1 times [2019-11-24 06:06:16,162 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:16,163 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968184764] [2019-11-24 06:06:16,163 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:16,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:16,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:16,229 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [968184764] [2019-11-24 06:06:16,229 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:16,230 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-24 06:06:16,230 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [525664795] [2019-11-24 06:06:16,230 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:16,230 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:16,231 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:16,231 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:16,231 INFO L87 Difference]: Start difference. First operand 531 states and 784 transitions. Second operand 3 states. [2019-11-24 06:06:16,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:16,336 INFO L93 Difference]: Finished difference Result 1531 states and 2255 transitions. [2019-11-24 06:06:16,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:16,337 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-11-24 06:06:16,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:16,342 INFO L225 Difference]: With dead ends: 1531 [2019-11-24 06:06:16,343 INFO L226 Difference]: Without dead ends: 1016 [2019-11-24 06:06:16,345 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:16,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1016 states. [2019-11-24 06:06:16,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1016 to 1012. [2019-11-24 06:06:16,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1012 states. [2019-11-24 06:06:16,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1012 states to 1012 states and 1463 transitions. [2019-11-24 06:06:16,378 INFO L78 Accepts]: Start accepts. Automaton has 1012 states and 1463 transitions. Word has length 28 [2019-11-24 06:06:16,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:16,379 INFO L462 AbstractCegarLoop]: Abstraction has 1012 states and 1463 transitions. [2019-11-24 06:06:16,379 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:16,379 INFO L276 IsEmpty]: Start isEmpty. Operand 1012 states and 1463 transitions. [2019-11-24 06:06:16,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-11-24 06:06:16,383 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:16,383 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:16,384 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:16,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:16,384 INFO L82 PathProgramCache]: Analyzing trace with hash -430432055, now seen corresponding path program 1 times [2019-11-24 06:06:16,384 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:16,385 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040031064] [2019-11-24 06:06:16,385 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:16,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:16,453 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:16,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040031064] [2019-11-24 06:06:16,453 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:16,454 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-24 06:06:16,454 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [652721778] [2019-11-24 06:06:16,454 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-24 06:06:16,455 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:16,455 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-24 06:06:16,455 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-24 06:06:16,455 INFO L87 Difference]: Start difference. First operand 1012 states and 1463 transitions. Second operand 4 states. [2019-11-24 06:06:16,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:16,596 INFO L93 Difference]: Finished difference Result 3196 states and 4662 transitions. [2019-11-24 06:06:16,596 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-24 06:06:16,596 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 38 [2019-11-24 06:06:16,597 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:16,607 INFO L225 Difference]: With dead ends: 3196 [2019-11-24 06:06:16,607 INFO L226 Difference]: Without dead ends: 2202 [2019-11-24 06:06:16,610 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-24 06:06:16,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2202 states. [2019-11-24 06:06:16,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2202 to 1188. [2019-11-24 06:06:16,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1188 states. [2019-11-24 06:06:16,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1188 states to 1188 states and 1767 transitions. [2019-11-24 06:06:16,658 INFO L78 Accepts]: Start accepts. Automaton has 1188 states and 1767 transitions. Word has length 38 [2019-11-24 06:06:16,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:16,658 INFO L462 AbstractCegarLoop]: Abstraction has 1188 states and 1767 transitions. [2019-11-24 06:06:16,658 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-24 06:06:16,658 INFO L276 IsEmpty]: Start isEmpty. Operand 1188 states and 1767 transitions. [2019-11-24 06:06:16,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-24 06:06:16,662 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:16,663 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:16,663 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:16,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:16,663 INFO L82 PathProgramCache]: Analyzing trace with hash 807646039, now seen corresponding path program 1 times [2019-11-24 06:06:16,663 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:16,664 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133831008] [2019-11-24 06:06:16,664 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:16,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:16,720 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:16,721 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2133831008] [2019-11-24 06:06:16,721 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:16,721 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-24 06:06:16,722 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [67409376] [2019-11-24 06:06:16,722 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:16,722 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:16,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:16,723 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:16,723 INFO L87 Difference]: Start difference. First operand 1188 states and 1767 transitions. Second operand 3 states. [2019-11-24 06:06:16,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:16,816 INFO L93 Difference]: Finished difference Result 2784 states and 4217 transitions. [2019-11-24 06:06:16,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:16,816 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 57 [2019-11-24 06:06:16,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:16,825 INFO L225 Difference]: With dead ends: 2784 [2019-11-24 06:06:16,825 INFO L226 Difference]: Without dead ends: 1614 [2019-11-24 06:06:16,828 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:16,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1614 states. [2019-11-24 06:06:16,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1614 to 1500. [2019-11-24 06:06:16,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1500 states. [2019-11-24 06:06:16,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1500 states to 1500 states and 2295 transitions. [2019-11-24 06:06:16,915 INFO L78 Accepts]: Start accepts. Automaton has 1500 states and 2295 transitions. Word has length 57 [2019-11-24 06:06:16,915 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:16,916 INFO L462 AbstractCegarLoop]: Abstraction has 1500 states and 2295 transitions. [2019-11-24 06:06:16,916 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:16,916 INFO L276 IsEmpty]: Start isEmpty. Operand 1500 states and 2295 transitions. [2019-11-24 06:06:16,920 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-24 06:06:16,920 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:16,920 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:16,921 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:16,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:16,921 INFO L82 PathProgramCache]: Analyzing trace with hash 1836899025, now seen corresponding path program 1 times [2019-11-24 06:06:16,921 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:16,922 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926549907] [2019-11-24 06:06:16,922 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:16,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:16,982 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:16,983 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926549907] [2019-11-24 06:06:16,983 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:16,983 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-24 06:06:16,984 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810325471] [2019-11-24 06:06:16,985 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:16,985 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:16,985 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:16,985 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:16,986 INFO L87 Difference]: Start difference. First operand 1500 states and 2295 transitions. Second operand 3 states. [2019-11-24 06:06:17,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:17,163 INFO L93 Difference]: Finished difference Result 3846 states and 5955 transitions. [2019-11-24 06:06:17,164 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:17,164 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 57 [2019-11-24 06:06:17,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:17,182 INFO L225 Difference]: With dead ends: 3846 [2019-11-24 06:06:17,182 INFO L226 Difference]: Without dead ends: 2364 [2019-11-24 06:06:17,186 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:17,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2364 states. [2019-11-24 06:06:17,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2364 to 2060. [2019-11-24 06:06:17,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2060 states. [2019-11-24 06:06:17,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2060 states to 2060 states and 3223 transitions. [2019-11-24 06:06:17,354 INFO L78 Accepts]: Start accepts. Automaton has 2060 states and 3223 transitions. Word has length 57 [2019-11-24 06:06:17,356 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:17,357 INFO L462 AbstractCegarLoop]: Abstraction has 2060 states and 3223 transitions. [2019-11-24 06:06:17,357 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:17,357 INFO L276 IsEmpty]: Start isEmpty. Operand 2060 states and 3223 transitions. [2019-11-24 06:06:17,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-24 06:06:17,366 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:17,367 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:17,367 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:17,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:17,375 INFO L82 PathProgramCache]: Analyzing trace with hash 179970460, now seen corresponding path program 1 times [2019-11-24 06:06:17,375 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:17,376 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702593842] [2019-11-24 06:06:17,384 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:17,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:17,496 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:17,497 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702593842] [2019-11-24 06:06:17,497 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:17,497 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-24 06:06:17,498 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854777233] [2019-11-24 06:06:17,500 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:17,501 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:17,501 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:17,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:17,503 INFO L87 Difference]: Start difference. First operand 2060 states and 3223 transitions. Second operand 3 states. [2019-11-24 06:06:17,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:17,653 INFO L93 Difference]: Finished difference Result 3108 states and 4886 transitions. [2019-11-24 06:06:17,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:17,654 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 58 [2019-11-24 06:06:17,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:17,669 INFO L225 Difference]: With dead ends: 3108 [2019-11-24 06:06:17,669 INFO L226 Difference]: Without dead ends: 2060 [2019-11-24 06:06:17,672 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:17,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2060 states. [2019-11-24 06:06:17,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2060 to 2030. [2019-11-24 06:06:17,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2030 states. [2019-11-24 06:06:17,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2030 states to 2030 states and 3141 transitions. [2019-11-24 06:06:17,843 INFO L78 Accepts]: Start accepts. Automaton has 2030 states and 3141 transitions. Word has length 58 [2019-11-24 06:06:17,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:17,846 INFO L462 AbstractCegarLoop]: Abstraction has 2030 states and 3141 transitions. [2019-11-24 06:06:17,846 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:17,846 INFO L276 IsEmpty]: Start isEmpty. Operand 2030 states and 3141 transitions. [2019-11-24 06:06:17,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-24 06:06:17,852 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:17,853 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:17,853 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:17,853 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:17,853 INFO L82 PathProgramCache]: Analyzing trace with hash 1468164989, now seen corresponding path program 1 times [2019-11-24 06:06:17,854 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:17,854 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812710352] [2019-11-24 06:06:17,855 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:17,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:17,929 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2019-11-24 06:06:17,930 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1812710352] [2019-11-24 06:06:17,930 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:17,931 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-24 06:06:17,931 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1048932650] [2019-11-24 06:06:17,932 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:17,932 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:17,932 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:17,933 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:17,933 INFO L87 Difference]: Start difference. First operand 2030 states and 3141 transitions. Second operand 3 states. [2019-11-24 06:06:18,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:18,049 INFO L93 Difference]: Finished difference Result 3032 states and 4706 transitions. [2019-11-24 06:06:18,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:18,049 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 58 [2019-11-24 06:06:18,050 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:18,060 INFO L225 Difference]: With dead ends: 3032 [2019-11-24 06:06:18,060 INFO L226 Difference]: Without dead ends: 2030 [2019-11-24 06:06:18,062 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:18,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2030 states. [2019-11-24 06:06:18,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2030 to 2030. [2019-11-24 06:06:18,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2030 states. [2019-11-24 06:06:18,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2030 states to 2030 states and 3123 transitions. [2019-11-24 06:06:18,164 INFO L78 Accepts]: Start accepts. Automaton has 2030 states and 3123 transitions. Word has length 58 [2019-11-24 06:06:18,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:18,164 INFO L462 AbstractCegarLoop]: Abstraction has 2030 states and 3123 transitions. [2019-11-24 06:06:18,165 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:18,165 INFO L276 IsEmpty]: Start isEmpty. Operand 2030 states and 3123 transitions. [2019-11-24 06:06:18,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-11-24 06:06:18,170 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:18,170 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:18,170 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:18,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:18,171 INFO L82 PathProgramCache]: Analyzing trace with hash -1056359343, now seen corresponding path program 1 times [2019-11-24 06:06:18,171 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:18,171 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909696886] [2019-11-24 06:06:18,171 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:18,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:18,235 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:18,235 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909696886] [2019-11-24 06:06:18,236 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:18,236 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-24 06:06:18,236 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [632150] [2019-11-24 06:06:18,236 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-24 06:06:18,237 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:18,237 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-24 06:06:18,237 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-24 06:06:18,237 INFO L87 Difference]: Start difference. First operand 2030 states and 3123 transitions. Second operand 5 states. [2019-11-24 06:06:18,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:18,738 INFO L93 Difference]: Finished difference Result 6738 states and 10336 transitions. [2019-11-24 06:06:18,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-24 06:06:18,739 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 59 [2019-11-24 06:06:18,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:18,758 INFO L225 Difference]: With dead ends: 6738 [2019-11-24 06:06:18,759 INFO L226 Difference]: Without dead ends: 3322 [2019-11-24 06:06:18,766 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2019-11-24 06:06:18,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3322 states. [2019-11-24 06:06:18,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3322 to 1821. [2019-11-24 06:06:18,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1821 states. [2019-11-24 06:06:18,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1821 states to 1821 states and 2680 transitions. [2019-11-24 06:06:18,942 INFO L78 Accepts]: Start accepts. Automaton has 1821 states and 2680 transitions. Word has length 59 [2019-11-24 06:06:18,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:18,943 INFO L462 AbstractCegarLoop]: Abstraction has 1821 states and 2680 transitions. [2019-11-24 06:06:18,944 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-24 06:06:18,944 INFO L276 IsEmpty]: Start isEmpty. Operand 1821 states and 2680 transitions. [2019-11-24 06:06:18,950 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-11-24 06:06:18,950 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:18,951 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:18,951 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:18,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:18,952 INFO L82 PathProgramCache]: Analyzing trace with hash 1291449910, now seen corresponding path program 1 times [2019-11-24 06:06:18,952 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:18,952 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659493419] [2019-11-24 06:06:18,953 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:18,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:19,018 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:19,019 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659493419] [2019-11-24 06:06:19,020 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:19,020 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-24 06:06:19,020 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [703110123] [2019-11-24 06:06:19,021 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-24 06:06:19,021 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:19,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-24 06:06:19,022 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-24 06:06:19,022 INFO L87 Difference]: Start difference. First operand 1821 states and 2680 transitions. Second operand 4 states. [2019-11-24 06:06:19,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:19,382 INFO L93 Difference]: Finished difference Result 5544 states and 8292 transitions. [2019-11-24 06:06:19,383 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-24 06:06:19,383 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 60 [2019-11-24 06:06:19,383 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:19,403 INFO L225 Difference]: With dead ends: 5544 [2019-11-24 06:06:19,404 INFO L226 Difference]: Without dead ends: 3741 [2019-11-24 06:06:19,408 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-24 06:06:19,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3741 states. [2019-11-24 06:06:19,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3741 to 2457. [2019-11-24 06:06:19,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2457 states. [2019-11-24 06:06:19,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2457 states to 2457 states and 3688 transitions. [2019-11-24 06:06:19,639 INFO L78 Accepts]: Start accepts. Automaton has 2457 states and 3688 transitions. Word has length 60 [2019-11-24 06:06:19,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:19,639 INFO L462 AbstractCegarLoop]: Abstraction has 2457 states and 3688 transitions. [2019-11-24 06:06:19,640 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-24 06:06:19,640 INFO L276 IsEmpty]: Start isEmpty. Operand 2457 states and 3688 transitions. [2019-11-24 06:06:19,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2019-11-24 06:06:19,645 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:19,645 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:19,645 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:19,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:19,646 INFO L82 PathProgramCache]: Analyzing trace with hash 766995459, now seen corresponding path program 1 times [2019-11-24 06:06:19,646 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:19,646 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954721998] [2019-11-24 06:06:19,646 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:19,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:19,703 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2019-11-24 06:06:19,703 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [954721998] [2019-11-24 06:06:19,704 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:19,704 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-24 06:06:19,704 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451413319] [2019-11-24 06:06:19,704 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:19,705 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:19,705 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:19,705 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:19,705 INFO L87 Difference]: Start difference. First operand 2457 states and 3688 transitions. Second operand 3 states. [2019-11-24 06:06:19,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:19,855 INFO L93 Difference]: Finished difference Result 3987 states and 6013 transitions. [2019-11-24 06:06:19,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:19,855 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2019-11-24 06:06:19,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:19,866 INFO L225 Difference]: With dead ends: 3987 [2019-11-24 06:06:19,867 INFO L226 Difference]: Without dead ends: 2457 [2019-11-24 06:06:19,869 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:19,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2457 states. [2019-11-24 06:06:19,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2457 to 2457. [2019-11-24 06:06:19,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2457 states. [2019-11-24 06:06:20,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2457 states to 2457 states and 3661 transitions. [2019-11-24 06:06:20,002 INFO L78 Accepts]: Start accepts. Automaton has 2457 states and 3661 transitions. Word has length 81 [2019-11-24 06:06:20,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:20,002 INFO L462 AbstractCegarLoop]: Abstraction has 2457 states and 3661 transitions. [2019-11-24 06:06:20,002 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:20,002 INFO L276 IsEmpty]: Start isEmpty. Operand 2457 states and 3661 transitions. [2019-11-24 06:06:20,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2019-11-24 06:06:20,007 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:20,007 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:20,008 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:20,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:20,008 INFO L82 PathProgramCache]: Analyzing trace with hash 530250019, now seen corresponding path program 1 times [2019-11-24 06:06:20,008 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:20,009 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016370241] [2019-11-24 06:06:20,009 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:20,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:20,053 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:20,054 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2016370241] [2019-11-24 06:06:20,054 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:20,054 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-24 06:06:20,054 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1715592985] [2019-11-24 06:06:20,055 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:20,055 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:20,055 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:20,056 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:20,056 INFO L87 Difference]: Start difference. First operand 2457 states and 3661 transitions. Second operand 3 states. [2019-11-24 06:06:20,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:20,242 INFO L93 Difference]: Finished difference Result 3985 states and 5957 transitions. [2019-11-24 06:06:20,242 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:20,243 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2019-11-24 06:06:20,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:20,266 INFO L225 Difference]: With dead ends: 3985 [2019-11-24 06:06:20,266 INFO L226 Difference]: Without dead ends: 2455 [2019-11-24 06:06:20,269 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:20,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2455 states. [2019-11-24 06:06:20,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2455 to 2415. [2019-11-24 06:06:20,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2415 states. [2019-11-24 06:06:20,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2415 states to 2415 states and 3538 transitions. [2019-11-24 06:06:20,400 INFO L78 Accepts]: Start accepts. Automaton has 2415 states and 3538 transitions. Word has length 81 [2019-11-24 06:06:20,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:20,400 INFO L462 AbstractCegarLoop]: Abstraction has 2415 states and 3538 transitions. [2019-11-24 06:06:20,400 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:20,400 INFO L276 IsEmpty]: Start isEmpty. Operand 2415 states and 3538 transitions. [2019-11-24 06:06:20,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2019-11-24 06:06:20,405 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:20,405 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:20,406 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:20,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:20,406 INFO L82 PathProgramCache]: Analyzing trace with hash 2039038588, now seen corresponding path program 1 times [2019-11-24 06:06:20,406 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:20,406 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1450397341] [2019-11-24 06:06:20,407 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:20,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:20,444 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-24 06:06:20,445 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1450397341] [2019-11-24 06:06:20,445 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:20,445 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-24 06:06:20,445 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812657787] [2019-11-24 06:06:20,446 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:20,446 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:20,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:20,447 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:20,447 INFO L87 Difference]: Start difference. First operand 2415 states and 3538 transitions. Second operand 3 states. [2019-11-24 06:06:20,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:20,696 INFO L93 Difference]: Finished difference Result 6949 states and 10173 transitions. [2019-11-24 06:06:20,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:20,696 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 82 [2019-11-24 06:06:20,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:20,710 INFO L225 Difference]: With dead ends: 6949 [2019-11-24 06:06:20,710 INFO L226 Difference]: Without dead ends: 4543 [2019-11-24 06:06:20,715 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:20,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4543 states. [2019-11-24 06:06:20,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4543 to 4499. [2019-11-24 06:06:20,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4499 states. [2019-11-24 06:06:20,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4499 states to 4499 states and 6522 transitions. [2019-11-24 06:06:20,998 INFO L78 Accepts]: Start accepts. Automaton has 4499 states and 6522 transitions. Word has length 82 [2019-11-24 06:06:20,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:20,998 INFO L462 AbstractCegarLoop]: Abstraction has 4499 states and 6522 transitions. [2019-11-24 06:06:20,998 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:20,999 INFO L276 IsEmpty]: Start isEmpty. Operand 4499 states and 6522 transitions. [2019-11-24 06:06:21,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2019-11-24 06:06:21,007 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:21,008 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:21,008 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:21,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:21,008 INFO L82 PathProgramCache]: Analyzing trace with hash -544802934, now seen corresponding path program 1 times [2019-11-24 06:06:21,008 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:21,009 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742961026] [2019-11-24 06:06:21,009 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:21,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:21,074 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:21,074 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [742961026] [2019-11-24 06:06:21,074 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:21,074 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-24 06:06:21,075 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1961957580] [2019-11-24 06:06:21,075 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-24 06:06:21,075 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:21,075 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-24 06:06:21,076 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-24 06:06:21,076 INFO L87 Difference]: Start difference. First operand 4499 states and 6522 transitions. Second operand 5 states. [2019-11-24 06:06:21,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:21,679 INFO L93 Difference]: Finished difference Result 13233 states and 19204 transitions. [2019-11-24 06:06:21,679 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-24 06:06:21,680 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 83 [2019-11-24 06:06:21,680 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:21,693 INFO L225 Difference]: With dead ends: 13233 [2019-11-24 06:06:21,693 INFO L226 Difference]: Without dead ends: 6639 [2019-11-24 06:06:21,703 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2019-11-24 06:06:21,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6639 states. [2019-11-24 06:06:21,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6639 to 3797. [2019-11-24 06:06:21,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3797 states. [2019-11-24 06:06:21,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3797 states to 3797 states and 5292 transitions. [2019-11-24 06:06:21,906 INFO L78 Accepts]: Start accepts. Automaton has 3797 states and 5292 transitions. Word has length 83 [2019-11-24 06:06:21,907 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:21,907 INFO L462 AbstractCegarLoop]: Abstraction has 3797 states and 5292 transitions. [2019-11-24 06:06:21,907 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-24 06:06:21,907 INFO L276 IsEmpty]: Start isEmpty. Operand 3797 states and 5292 transitions. [2019-11-24 06:06:21,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2019-11-24 06:06:21,915 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:21,915 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:21,915 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:21,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:21,916 INFO L82 PathProgramCache]: Analyzing trace with hash -1745744671, now seen corresponding path program 1 times [2019-11-24 06:06:21,916 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:21,916 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899011399] [2019-11-24 06:06:21,916 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:21,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:21,969 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:21,970 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899011399] [2019-11-24 06:06:21,970 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:21,970 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-24 06:06:21,971 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461617125] [2019-11-24 06:06:21,971 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:21,971 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:21,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:21,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:21,972 INFO L87 Difference]: Start difference. First operand 3797 states and 5292 transitions. Second operand 3 states. [2019-11-24 06:06:22,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:22,185 INFO L93 Difference]: Finished difference Result 6493 states and 9097 transitions. [2019-11-24 06:06:22,185 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:22,185 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 106 [2019-11-24 06:06:22,185 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:22,193 INFO L225 Difference]: With dead ends: 6493 [2019-11-24 06:06:22,193 INFO L226 Difference]: Without dead ends: 3797 [2019-11-24 06:06:22,200 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:22,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3797 states. [2019-11-24 06:06:22,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3797 to 3757. [2019-11-24 06:06:22,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3757 states. [2019-11-24 06:06:22,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3757 states to 3757 states and 5110 transitions. [2019-11-24 06:06:22,407 INFO L78 Accepts]: Start accepts. Automaton has 3757 states and 5110 transitions. Word has length 106 [2019-11-24 06:06:22,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:22,408 INFO L462 AbstractCegarLoop]: Abstraction has 3757 states and 5110 transitions. [2019-11-24 06:06:22,408 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:22,408 INFO L276 IsEmpty]: Start isEmpty. Operand 3757 states and 5110 transitions. [2019-11-24 06:06:22,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2019-11-24 06:06:22,416 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:22,416 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:22,416 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:22,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:22,417 INFO L82 PathProgramCache]: Analyzing trace with hash -1015864797, now seen corresponding path program 1 times [2019-11-24 06:06:22,417 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:22,417 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566999423] [2019-11-24 06:06:22,418 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:22,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:22,521 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2019-11-24 06:06:22,521 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1566999423] [2019-11-24 06:06:22,521 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:22,522 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-24 06:06:22,522 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [367294655] [2019-11-24 06:06:22,522 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:22,522 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:22,523 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:22,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:22,523 INFO L87 Difference]: Start difference. First operand 3757 states and 5110 transitions. Second operand 3 states. [2019-11-24 06:06:22,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:22,709 INFO L93 Difference]: Finished difference Result 6405 states and 8725 transitions. [2019-11-24 06:06:22,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:22,709 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 106 [2019-11-24 06:06:22,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:22,717 INFO L225 Difference]: With dead ends: 6405 [2019-11-24 06:06:22,717 INFO L226 Difference]: Without dead ends: 3757 [2019-11-24 06:06:22,722 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:22,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3757 states. [2019-11-24 06:06:22,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3757 to 3757. [2019-11-24 06:06:22,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3757 states. [2019-11-24 06:06:22,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3757 states to 3757 states and 5040 transitions. [2019-11-24 06:06:22,901 INFO L78 Accepts]: Start accepts. Automaton has 3757 states and 5040 transitions. Word has length 106 [2019-11-24 06:06:22,902 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:22,902 INFO L462 AbstractCegarLoop]: Abstraction has 3757 states and 5040 transitions. [2019-11-24 06:06:22,902 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:22,902 INFO L276 IsEmpty]: Start isEmpty. Operand 3757 states and 5040 transitions. [2019-11-24 06:06:22,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2019-11-24 06:06:22,909 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:22,909 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:22,909 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:22,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:22,910 INFO L82 PathProgramCache]: Analyzing trace with hash 1598475233, now seen corresponding path program 1 times [2019-11-24 06:06:22,910 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:22,910 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907498795] [2019-11-24 06:06:22,911 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:22,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:22,971 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-24 06:06:22,972 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [907498795] [2019-11-24 06:06:22,972 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:22,972 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-24 06:06:22,973 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [870898500] [2019-11-24 06:06:22,973 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:22,973 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:22,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:22,974 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:22,974 INFO L87 Difference]: Start difference. First operand 3757 states and 5040 transitions. Second operand 3 states. [2019-11-24 06:06:23,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:23,333 INFO L93 Difference]: Finished difference Result 10808 states and 14581 transitions. [2019-11-24 06:06:23,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:23,334 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 109 [2019-11-24 06:06:23,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:23,347 INFO L225 Difference]: With dead ends: 10808 [2019-11-24 06:06:23,348 INFO L226 Difference]: Without dead ends: 7055 [2019-11-24 06:06:23,353 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:23,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7055 states. [2019-11-24 06:06:23,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7055 to 7051. [2019-11-24 06:06:23,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7051 states. [2019-11-24 06:06:23,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7051 states to 7051 states and 9461 transitions. [2019-11-24 06:06:23,684 INFO L78 Accepts]: Start accepts. Automaton has 7051 states and 9461 transitions. Word has length 109 [2019-11-24 06:06:23,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:23,684 INFO L462 AbstractCegarLoop]: Abstraction has 7051 states and 9461 transitions. [2019-11-24 06:06:23,685 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:23,685 INFO L276 IsEmpty]: Start isEmpty. Operand 7051 states and 9461 transitions. [2019-11-24 06:06:23,694 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2019-11-24 06:06:23,694 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:23,695 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:23,695 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:23,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:23,695 INFO L82 PathProgramCache]: Analyzing trace with hash 1504978467, now seen corresponding path program 1 times [2019-11-24 06:06:23,695 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:23,696 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835583298] [2019-11-24 06:06:23,696 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:23,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:23,741 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2019-11-24 06:06:23,742 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1835583298] [2019-11-24 06:06:23,742 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:23,742 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-24 06:06:23,742 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [603281943] [2019-11-24 06:06:23,743 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:23,743 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:23,743 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:23,748 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:23,748 INFO L87 Difference]: Start difference. First operand 7051 states and 9461 transitions. Second operand 3 states. [2019-11-24 06:06:24,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:24,302 INFO L93 Difference]: Finished difference Result 20801 states and 27875 transitions. [2019-11-24 06:06:24,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:24,303 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 109 [2019-11-24 06:06:24,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:24,330 INFO L225 Difference]: With dead ends: 20801 [2019-11-24 06:06:24,331 INFO L226 Difference]: Without dead ends: 13767 [2019-11-24 06:06:24,341 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:24,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13767 states. [2019-11-24 06:06:24,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13767 to 12927. [2019-11-24 06:06:24,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12927 states. [2019-11-24 06:06:24,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12927 states to 12927 states and 17213 transitions. [2019-11-24 06:06:24,968 INFO L78 Accepts]: Start accepts. Automaton has 12927 states and 17213 transitions. Word has length 109 [2019-11-24 06:06:24,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:24,969 INFO L462 AbstractCegarLoop]: Abstraction has 12927 states and 17213 transitions. [2019-11-24 06:06:24,969 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:24,969 INFO L276 IsEmpty]: Start isEmpty. Operand 12927 states and 17213 transitions. [2019-11-24 06:06:24,985 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-24 06:06:24,986 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:24,986 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:24,986 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:24,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:24,987 INFO L82 PathProgramCache]: Analyzing trace with hash 1980777405, now seen corresponding path program 1 times [2019-11-24 06:06:24,987 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:24,987 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376299614] [2019-11-24 06:06:24,988 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:25,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:25,039 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:25,039 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376299614] [2019-11-24 06:06:25,039 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:25,040 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-24 06:06:25,040 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1293830385] [2019-11-24 06:06:25,041 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-24 06:06:25,041 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:25,042 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-24 06:06:25,042 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-24 06:06:25,042 INFO L87 Difference]: Start difference. First operand 12927 states and 17213 transitions. Second operand 4 states. [2019-11-24 06:06:26,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:26,005 INFO L93 Difference]: Finished difference Result 36137 states and 49181 transitions. [2019-11-24 06:06:26,008 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-24 06:06:26,009 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 110 [2019-11-24 06:06:26,009 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:26,056 INFO L225 Difference]: With dead ends: 36137 [2019-11-24 06:06:26,056 INFO L226 Difference]: Without dead ends: 23241 [2019-11-24 06:06:26,072 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-24 06:06:26,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23241 states. [2019-11-24 06:06:27,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23241 to 17759. [2019-11-24 06:06:27,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17759 states. [2019-11-24 06:06:27,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17759 states to 17759 states and 24125 transitions. [2019-11-24 06:06:27,641 INFO L78 Accepts]: Start accepts. Automaton has 17759 states and 24125 transitions. Word has length 110 [2019-11-24 06:06:27,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:27,641 INFO L462 AbstractCegarLoop]: Abstraction has 17759 states and 24125 transitions. [2019-11-24 06:06:27,642 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-24 06:06:27,642 INFO L276 IsEmpty]: Start isEmpty. Operand 17759 states and 24125 transitions. [2019-11-24 06:06:27,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2019-11-24 06:06:27,664 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:27,665 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:27,665 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:27,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:27,665 INFO L82 PathProgramCache]: Analyzing trace with hash 953352303, now seen corresponding path program 1 times [2019-11-24 06:06:27,665 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:27,666 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40026984] [2019-11-24 06:06:27,666 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:27,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:27,738 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:27,738 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40026984] [2019-11-24 06:06:27,739 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:27,739 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-24 06:06:27,739 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1802138502] [2019-11-24 06:06:27,740 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-24 06:06:27,740 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:27,740 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-24 06:06:27,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-24 06:06:27,741 INFO L87 Difference]: Start difference. First operand 17759 states and 24125 transitions. Second operand 4 states. [2019-11-24 06:06:28,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:28,769 INFO L93 Difference]: Finished difference Result 42677 states and 58003 transitions. [2019-11-24 06:06:28,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-24 06:06:28,770 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 111 [2019-11-24 06:06:28,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:28,802 INFO L225 Difference]: With dead ends: 42677 [2019-11-24 06:06:28,802 INFO L226 Difference]: Without dead ends: 18677 [2019-11-24 06:06:28,823 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-24 06:06:28,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18677 states. [2019-11-24 06:06:29,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18677 to 14071. [2019-11-24 06:06:29,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14071 states. [2019-11-24 06:06:29,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14071 states to 14071 states and 18373 transitions. [2019-11-24 06:06:29,540 INFO L78 Accepts]: Start accepts. Automaton has 14071 states and 18373 transitions. Word has length 111 [2019-11-24 06:06:29,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:29,541 INFO L462 AbstractCegarLoop]: Abstraction has 14071 states and 18373 transitions. [2019-11-24 06:06:29,541 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-24 06:06:29,541 INFO L276 IsEmpty]: Start isEmpty. Operand 14071 states and 18373 transitions. [2019-11-24 06:06:29,554 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-24 06:06:29,554 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:29,554 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:29,554 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:29,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:29,555 INFO L82 PathProgramCache]: Analyzing trace with hash -471155920, now seen corresponding path program 1 times [2019-11-24 06:06:29,555 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:29,555 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838012670] [2019-11-24 06:06:29,555 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:29,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:29,610 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-24 06:06:29,611 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [838012670] [2019-11-24 06:06:29,611 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:29,611 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-24 06:06:29,611 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184497102] [2019-11-24 06:06:29,612 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-24 06:06:29,612 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:29,612 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-24 06:06:29,612 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:29,612 INFO L87 Difference]: Start difference. First operand 14071 states and 18373 transitions. Second operand 3 states. [2019-11-24 06:06:30,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:30,099 INFO L93 Difference]: Finished difference Result 24871 states and 32610 transitions. [2019-11-24 06:06:30,099 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-24 06:06:30,099 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 135 [2019-11-24 06:06:30,099 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:30,117 INFO L225 Difference]: With dead ends: 24871 [2019-11-24 06:06:30,117 INFO L226 Difference]: Without dead ends: 14055 [2019-11-24 06:06:30,130 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-24 06:06:30,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14055 states. [2019-11-24 06:06:30,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14055 to 13863. [2019-11-24 06:06:30,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13863 states. [2019-11-24 06:06:30,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13863 states to 13863 states and 17549 transitions. [2019-11-24 06:06:30,822 INFO L78 Accepts]: Start accepts. Automaton has 13863 states and 17549 transitions. Word has length 135 [2019-11-24 06:06:30,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:30,822 INFO L462 AbstractCegarLoop]: Abstraction has 13863 states and 17549 transitions. [2019-11-24 06:06:30,822 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-24 06:06:30,822 INFO L276 IsEmpty]: Start isEmpty. Operand 13863 states and 17549 transitions. [2019-11-24 06:06:30,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-24 06:06:30,832 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:30,832 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:30,833 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:30,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:30,833 INFO L82 PathProgramCache]: Analyzing trace with hash -137745167, now seen corresponding path program 1 times [2019-11-24 06:06:30,833 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:30,834 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825101277] [2019-11-24 06:06:30,834 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:30,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-24 06:06:30,911 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-24 06:06:30,912 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1825101277] [2019-11-24 06:06:30,912 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-24 06:06:30,913 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-24 06:06:30,913 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303779177] [2019-11-24 06:06:30,913 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-24 06:06:30,913 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-24 06:06:30,914 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-24 06:06:30,914 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-24 06:06:30,914 INFO L87 Difference]: Start difference. First operand 13863 states and 17549 transitions. Second operand 4 states. [2019-11-24 06:06:31,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-24 06:06:31,458 INFO L93 Difference]: Finished difference Result 24399 states and 30906 transitions. [2019-11-24 06:06:31,460 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-24 06:06:31,460 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2019-11-24 06:06:31,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-24 06:06:31,476 INFO L225 Difference]: With dead ends: 24399 [2019-11-24 06:06:31,476 INFO L226 Difference]: Without dead ends: 13823 [2019-11-24 06:06:31,488 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-24 06:06:31,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13823 states. [2019-11-24 06:06:32,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13823 to 13823. [2019-11-24 06:06:32,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13823 states. [2019-11-24 06:06:32,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13823 states to 13823 states and 17213 transitions. [2019-11-24 06:06:32,121 INFO L78 Accepts]: Start accepts. Automaton has 13823 states and 17213 transitions. Word has length 135 [2019-11-24 06:06:32,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-24 06:06:32,121 INFO L462 AbstractCegarLoop]: Abstraction has 13823 states and 17213 transitions. [2019-11-24 06:06:32,121 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-24 06:06:32,121 INFO L276 IsEmpty]: Start isEmpty. Operand 13823 states and 17213 transitions. [2019-11-24 06:06:32,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2019-11-24 06:06:32,130 INFO L402 BasicCegarLoop]: Found error trace [2019-11-24 06:06:32,130 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-24 06:06:32,130 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-24 06:06:32,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-24 06:06:32,130 INFO L82 PathProgramCache]: Analyzing trace with hash -1009703305, now seen corresponding path program 1 times [2019-11-24 06:06:32,130 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-24 06:06:32,131 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416721724] [2019-11-24 06:06:32,131 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-24 06:06:32,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-24 06:06:32,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-24 06:06:32,274 INFO L174 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2019-11-24 06:06:32,274 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-24 06:06:32,467 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.11 06:06:32 BoogieIcfgContainer [2019-11-24 06:06:32,467 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-24 06:06:32,472 INFO L168 Benchmark]: Toolchain (without parser) took 20533.68 ms. Allocated memory was 141.0 MB in the beginning and 1.3 GB in the end (delta: 1.2 GB). Free memory was 104.3 MB in the beginning and 647.4 MB in the end (delta: -543.1 MB). Peak memory consumption was 647.0 MB. Max. memory is 7.1 GB. [2019-11-24 06:06:32,473 INFO L168 Benchmark]: CDTParser took 0.25 ms. Allocated memory is still 141.0 MB. Free memory was 123.0 MB in the beginning and 122.8 MB in the end (delta: 209.9 kB). Peak memory consumption was 209.9 kB. Max. memory is 7.1 GB. [2019-11-24 06:06:32,473 INFO L168 Benchmark]: CACSL2BoogieTranslator took 505.71 ms. Allocated memory was 141.0 MB in the beginning and 203.4 MB in the end (delta: 62.4 MB). Free memory was 104.1 MB in the beginning and 178.6 MB in the end (delta: -74.6 MB). Peak memory consumption was 27.4 MB. Max. memory is 7.1 GB. [2019-11-24 06:06:32,474 INFO L168 Benchmark]: Boogie Procedure Inliner took 86.45 ms. Allocated memory is still 203.4 MB. Free memory was 178.6 MB in the beginning and 174.2 MB in the end (delta: 4.4 MB). Peak memory consumption was 4.4 MB. Max. memory is 7.1 GB. [2019-11-24 06:06:32,474 INFO L168 Benchmark]: Boogie Preprocessor took 98.71 ms. Allocated memory is still 203.4 MB. Free memory was 174.2 MB in the beginning and 170.4 MB in the end (delta: 3.8 MB). Peak memory consumption was 3.8 MB. Max. memory is 7.1 GB. [2019-11-24 06:06:32,475 INFO L168 Benchmark]: RCFGBuilder took 2688.27 ms. Allocated memory was 203.4 MB in the beginning and 244.3 MB in the end (delta: 40.9 MB). Free memory was 170.4 MB in the beginning and 162.9 MB in the end (delta: 7.6 MB). Peak memory consumption was 114.5 MB. Max. memory is 7.1 GB. [2019-11-24 06:06:32,480 INFO L168 Benchmark]: TraceAbstraction took 17149.53 ms. Allocated memory was 244.3 MB in the beginning and 1.3 GB in the end (delta: 1.1 GB). Free memory was 162.9 MB in the beginning and 647.4 MB in the end (delta: -484.6 MB). Peak memory consumption was 602.3 MB. Max. memory is 7.1 GB. [2019-11-24 06:06:32,484 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25 ms. Allocated memory is still 141.0 MB. Free memory was 123.0 MB in the beginning and 122.8 MB in the end (delta: 209.9 kB). Peak memory consumption was 209.9 kB. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 505.71 ms. Allocated memory was 141.0 MB in the beginning and 203.4 MB in the end (delta: 62.4 MB). Free memory was 104.1 MB in the beginning and 178.6 MB in the end (delta: -74.6 MB). Peak memory consumption was 27.4 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 86.45 ms. Allocated memory is still 203.4 MB. Free memory was 178.6 MB in the beginning and 174.2 MB in the end (delta: 4.4 MB). Peak memory consumption was 4.4 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 98.71 ms. Allocated memory is still 203.4 MB. Free memory was 174.2 MB in the beginning and 170.4 MB in the end (delta: 3.8 MB). Peak memory consumption was 3.8 MB. Max. memory is 7.1 GB. * RCFGBuilder took 2688.27 ms. Allocated memory was 203.4 MB in the beginning and 244.3 MB in the end (delta: 40.9 MB). Free memory was 170.4 MB in the beginning and 162.9 MB in the end (delta: 7.6 MB). Peak memory consumption was 114.5 MB. Max. memory is 7.1 GB. * TraceAbstraction took 17149.53 ms. Allocated memory was 244.3 MB in the beginning and 1.3 GB in the end (delta: 1.1 GB). Free memory was 162.9 MB in the beginning and 647.4 MB in the end (delta: -484.6 MB). Peak memory consumption was 602.3 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L811] int __retres1 ; [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 [L331] COND TRUE m_i == 1 [L332] m_st = 0 [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 [L492] COND FALSE !(M_E == 0) [L497] COND FALSE !(T1_E == 0) [L502] COND FALSE !(T2_E == 0) [L507] COND FALSE !(T3_E == 0) [L512] COND FALSE !(T4_E == 0) [L517] COND FALSE !(E_1 == 0) [L522] COND FALSE !(E_2 == 0) [L527] COND FALSE !(E_3 == 0) [L532] COND FALSE !(E_4 == 0) [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L228] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L247] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L266] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L285] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L304] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L545] COND FALSE !(M_E == 1) [L550] COND FALSE !(T1_E == 1) [L555] COND FALSE !(T2_E == 1) [L560] COND FALSE !(T3_E == 1) [L565] COND FALSE !(T4_E == 1) [L570] COND FALSE !(E_1 == 1) [L575] COND FALSE !(E_2 == 1) [L580] COND FALSE !(E_3 == 1) [L585] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L766] COND TRUE 1 [L769] kernel_st = 1 [L397] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L401] COND TRUE 1 [L361] int __retres1 ; [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 [L392] return (__retres1); [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L90] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L101] COND TRUE 1 [L103] t1_pc = 1 [L104] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L125] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L136] COND TRUE 1 [L138] t2_pc = 1 [L139] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L160] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L171] COND TRUE 1 [L173] t3_pc = 1 [L174] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L195] COND TRUE t4_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L206] COND TRUE 1 [L208] t4_pc = 1 [L209] t4_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L401] COND TRUE 1 [L361] int __retres1 ; [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 [L392] return (__retres1); [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND TRUE \read(tmp_ndt_1) [L416] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L49] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L60] COND TRUE 1 [L63] E_1 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND TRUE E_1 == 1 [L249] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND TRUE \read(tmp___0) [L614] t1_st = 0 [L263] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L65] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L68] COND TRUE 1 [L70] m_pc = 1 [L71] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L90] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L93] COND TRUE t1_pc == 1 [L109] E_2 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND TRUE E_2 == 1 [L268] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND TRUE \read(tmp___1) [L622] t2_st = 0 [L282] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L111] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L101] COND TRUE 1 [L103] t1_pc = 1 [L104] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L125] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L128] COND TRUE t2_pc == 1 [L144] E_3 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND TRUE E_3 == 1 [L287] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND TRUE \read(tmp___2) [L630] t3_st = 0 [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L146] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L136] COND TRUE 1 [L138] t2_pc = 1 [L139] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L163] COND TRUE t3_pc == 1 [L179] E_4 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND TRUE E_4 == 1 [L306] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND TRUE \read(tmp___3) [L638] t4_st = 0 [L181] E_4 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L171] COND TRUE 1 [L173] t3_pc = 1 [L174] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L195] COND FALSE !(t4_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L198] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L11] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 178 locations, 1 error locations. Result: UNSAFE, OverallTime: 17.0s, OverallIterations: 23, TraceHistogramMax: 3, AutomataDifference: 7.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 7914 SDtfs, 5120 SDslu, 6535 SDs, 0 SdLazy, 686 SolverSat, 195 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 79 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=17759occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 6.8s AutomataMinimizationTime, 22 MinimizatonAttempts, 18348 StatesRemovedByMinimization, 18 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 0.8s InterpolantComputationTime, 1858 NumberOfCodeBlocks, 1858 NumberOfCodeBlocksAsserted, 23 NumberOfCheckSat, 1697 ConstructedInterpolants, 0 QuantifiedInterpolants, 257147 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 22 InterpolantComputations, 22 PerfectInterpolantSequences, 265/265 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...