/usr/bin/java -Xmx16000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml -s ../../../trunk/examples/settings/automizer/concurrent/svcomp-Reach-32bit-Automizer_Default-noMmResRef-Sleep-NoLbe-Delay.epf -i ../../../trunk/examples/svcomp/pthread-wmm/safe000_power.opt.i -------------------------------------------------------------------------------- This is Ultimate 0.2.0-6f57305 [2021-01-26 22:47:50,513 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-01-26 22:47:50,518 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-01-26 22:47:50,572 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-01-26 22:47:50,573 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-01-26 22:47:50,577 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-01-26 22:47:50,581 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-01-26 22:47:50,588 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-01-26 22:47:50,592 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-01-26 22:47:50,598 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-01-26 22:47:50,599 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-01-26 22:47:50,601 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-01-26 22:47:50,601 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-01-26 22:47:50,604 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-01-26 22:47:50,606 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-01-26 22:47:50,608 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-01-26 22:47:50,609 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-01-26 22:47:50,613 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-01-26 22:47:50,621 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-01-26 22:47:50,630 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-01-26 22:47:50,632 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-01-26 22:47:50,633 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-01-26 22:47:50,635 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-01-26 22:47:50,637 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-01-26 22:47:50,646 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2021-01-26 22:47:50,651 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-01-26 22:47:50,652 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-01-26 22:47:50,655 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-01-26 22:47:50,656 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-01-26 22:47:50,657 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-01-26 22:47:50,657 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-01-26 22:47:50,658 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-01-26 22:47:50,659 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-01-26 22:47:50,659 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-01-26 22:47:50,660 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-01-26 22:47:50,661 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-01-26 22:47:50,662 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/concurrent/svcomp-Reach-32bit-Automizer_Default-noMmResRef-Sleep-NoLbe-Delay.epf [2021-01-26 22:47:50,710 INFO L113 SettingsManager]: Loading preferences was successful [2021-01-26 22:47:50,711 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-01-26 22:47:50,715 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-01-26 22:47:50,715 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-01-26 22:47:50,715 INFO L138 SettingsManager]: * Use SBE=true [2021-01-26 22:47:50,715 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-01-26 22:47:50,716 INFO L138 SettingsManager]: * sizeof long=4 [2021-01-26 22:47:50,716 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-01-26 22:47:50,716 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-01-26 22:47:50,717 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-01-26 22:47:50,718 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-01-26 22:47:50,719 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-01-26 22:47:50,719 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-01-26 22:47:50,719 INFO L138 SettingsManager]: * sizeof long double=12 [2021-01-26 22:47:50,719 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-01-26 22:47:50,720 INFO L138 SettingsManager]: * Use constant arrays=true [2021-01-26 22:47:50,720 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-01-26 22:47:50,720 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-01-26 22:47:50,720 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-01-26 22:47:50,721 INFO L138 SettingsManager]: * To the following directory=./dump/ [2021-01-26 22:47:50,721 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-01-26 22:47:50,721 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-01-26 22:47:50,722 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-01-26 22:47:50,722 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-01-26 22:47:50,722 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-01-26 22:47:50,723 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-01-26 22:47:50,723 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-01-26 22:47:50,723 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2021-01-26 22:47:50,723 INFO L138 SettingsManager]: * Lazy Petri-NFA conversion=true [2021-01-26 22:47:50,724 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=SLEEP_SET_FA [2021-01-26 22:47:50,724 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-01-26 22:47:50,724 INFO L138 SettingsManager]: * Minimization of abstraction=NONE [2021-01-26 22:47:50,725 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2021-01-26 22:47:50,725 INFO L138 SettingsManager]: * Sleep set reduction in concurrent analysis=DELAY_SET WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2021-01-26 22:47:51,138 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-01-26 22:47:51,169 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-01-26 22:47:51,172 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-01-26 22:47:51,174 INFO L271 PluginConnector]: Initializing CDTParser... [2021-01-26 22:47:51,174 INFO L275 PluginConnector]: CDTParser initialized [2021-01-26 22:47:51,175 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/pthread-wmm/safe000_power.opt.i [2021-01-26 22:47:51,259 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/44dce03d5/1f200a58e7364c06963aeebe02478b22/FLAGdeb96f987 [2021-01-26 22:47:52,002 INFO L306 CDTParser]: Found 1 translation units. [2021-01-26 22:47:52,002 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/pthread-wmm/safe000_power.opt.i [2021-01-26 22:47:52,020 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/44dce03d5/1f200a58e7364c06963aeebe02478b22/FLAGdeb96f987 [2021-01-26 22:47:52,224 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/44dce03d5/1f200a58e7364c06963aeebe02478b22 [2021-01-26 22:47:52,228 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-01-26 22:47:52,240 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2021-01-26 22:47:52,245 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-01-26 22:47:52,245 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-01-26 22:47:52,249 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-01-26 22:47:52,250 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.01 10:47:52" (1/1) ... [2021-01-26 22:47:52,258 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@ebb1280 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:52, skipping insertion in model container [2021-01-26 22:47:52,258 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.01 10:47:52" (1/1) ... [2021-01-26 22:47:52,267 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-01-26 22:47:52,345 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-01-26 22:47:52,863 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-01-26 22:47:52,877 INFO L203 MainTranslator]: Completed pre-run [2021-01-26 22:47:52,962 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-01-26 22:47:53,060 INFO L208 MainTranslator]: Completed translation [2021-01-26 22:47:53,061 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:53 WrapperNode [2021-01-26 22:47:53,061 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-01-26 22:47:53,063 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-01-26 22:47:53,063 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-01-26 22:47:53,063 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-01-26 22:47:53,071 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:53" (1/1) ... [2021-01-26 22:47:53,092 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:53" (1/1) ... [2021-01-26 22:47:53,123 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-01-26 22:47:53,124 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-01-26 22:47:53,124 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-01-26 22:47:53,124 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-01-26 22:47:53,134 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:53" (1/1) ... [2021-01-26 22:47:53,134 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:53" (1/1) ... [2021-01-26 22:47:53,140 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:53" (1/1) ... [2021-01-26 22:47:53,140 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:53" (1/1) ... [2021-01-26 22:47:53,160 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:53" (1/1) ... [2021-01-26 22:47:53,168 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:53" (1/1) ... [2021-01-26 22:47:53,173 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:53" (1/1) ... [2021-01-26 22:47:53,180 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-01-26 22:47:53,181 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-01-26 22:47:53,181 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-01-26 22:47:53,181 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-01-26 22:47:53,182 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:53" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-01-26 22:47:53,273 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-01-26 22:47:53,275 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-01-26 22:47:53,275 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2021-01-26 22:47:53,276 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-01-26 22:47:53,276 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-01-26 22:47:53,277 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2021-01-26 22:47:53,277 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2021-01-26 22:47:53,277 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2021-01-26 22:47:53,277 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2021-01-26 22:47:53,277 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2021-01-26 22:47:53,277 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2021-01-26 22:47:53,277 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-01-26 22:47:53,278 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2021-01-26 22:47:53,278 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-01-26 22:47:53,278 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-01-26 22:47:53,280 WARN L208 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2021-01-26 22:47:56,392 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-01-26 22:47:56,392 INFO L298 CfgBuilder]: Removed 14 assume(true) statements. [2021-01-26 22:47:56,394 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.01 10:47:56 BoogieIcfgContainer [2021-01-26 22:47:56,394 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-01-26 22:47:56,396 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-01-26 22:47:56,396 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-01-26 22:47:56,399 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-01-26 22:47:56,399 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 26.01 10:47:52" (1/3) ... [2021-01-26 22:47:56,400 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4cfdc546 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.01 10:47:56, skipping insertion in model container [2021-01-26 22:47:56,400 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 10:47:53" (2/3) ... [2021-01-26 22:47:56,401 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4cfdc546 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.01 10:47:56, skipping insertion in model container [2021-01-26 22:47:56,401 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.01 10:47:56" (3/3) ... [2021-01-26 22:47:56,402 INFO L111 eAbstractionObserver]: Analyzing ICFG safe000_power.opt.i [2021-01-26 22:47:56,417 WARN L168 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2021-01-26 22:47:56,418 INFO L179 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-01-26 22:47:56,421 INFO L191 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2021-01-26 22:47:56,422 INFO L351 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2021-01-26 22:47:56,466 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,467 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,467 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,467 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,467 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,467 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,468 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,468 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,468 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,468 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,468 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,468 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,469 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,469 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,469 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,469 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,469 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,469 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,469 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,470 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,470 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,470 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,470 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,470 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,470 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,471 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,471 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,471 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,471 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,471 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,472 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,472 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,472 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,472 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,472 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,472 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,472 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,473 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,473 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,473 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,473 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,474 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,474 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,474 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,474 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,474 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,475 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,475 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,475 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,475 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,476 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,476 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,476 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,476 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,476 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,476 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,476 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,477 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,477 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,477 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,477 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,477 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,477 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,477 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,478 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,478 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,478 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,478 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,478 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,478 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,478 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,479 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,479 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,479 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,479 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,479 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,479 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,479 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,480 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,480 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,480 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,480 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,480 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,480 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,481 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,481 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,481 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,481 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,481 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,481 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,481 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,482 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,482 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,482 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,482 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,482 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,482 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,482 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,482 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,483 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,483 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,483 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,483 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,483 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,483 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,484 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,484 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,484 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,484 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,484 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,484 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,484 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,485 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,485 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,485 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,485 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,485 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,485 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,485 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,485 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,486 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,486 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,486 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,486 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,486 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,486 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,486 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,486 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,487 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,487 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,487 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,487 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,487 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,487 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,487 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,487 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,488 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,488 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,488 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,488 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,488 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,488 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,488 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,488 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,489 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,489 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,493 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,493 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,493 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,493 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,493 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,493 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,493 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,494 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,494 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,494 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,494 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,494 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,494 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,494 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,494 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,495 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,495 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,495 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,495 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,495 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,495 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,495 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,495 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,496 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,496 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,496 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,496 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,496 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,496 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,496 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,496 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,496 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,497 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,497 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,497 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,497 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,497 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,497 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,497 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,499 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,499 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,499 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,499 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,499 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,499 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,499 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,499 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,502 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,502 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,502 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,502 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,502 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,502 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,502 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,504 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,508 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,508 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,509 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,509 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,509 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,509 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,509 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,509 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,509 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,510 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,510 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,510 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,510 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,511 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,511 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,511 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,511 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,511 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,512 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,512 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,512 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,512 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,513 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,513 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,513 WARN L313 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,513 WARN L313 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,513 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,513 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,513 WARN L313 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,514 WARN L313 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,514 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,514 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,514 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,514 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,514 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite71| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,514 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite70| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,514 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite74| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,515 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite73| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,515 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite72| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,515 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,515 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,516 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,516 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,516 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite71| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,516 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite70| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,516 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite74| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,516 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite73| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,516 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite72| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,517 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,517 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,517 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,517 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,520 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,520 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,520 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,520 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,520 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,520 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,521 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,521 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,521 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,521 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,521 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,521 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,521 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,522 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,522 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,528 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,528 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,528 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,528 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,528 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,529 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,529 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,529 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,529 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,529 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,529 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,530 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,530 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,530 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,530 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,530 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,530 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,530 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,531 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,531 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,531 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,531 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,531 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,531 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,532 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,532 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,532 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,532 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,532 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,532 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,532 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,533 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,533 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,533 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,533 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,533 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,533 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,534 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,534 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,534 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,534 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,534 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,534 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,534 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,535 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,535 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,535 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,535 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,535 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,535 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,535 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,536 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,536 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,536 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,536 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,536 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,536 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,537 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,537 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~mem59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,537 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,539 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite69| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,539 WARN L313 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,539 WARN L313 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,539 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~mem68| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,539 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite74| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,539 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite73| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,540 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite72| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,540 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,540 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite70| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,540 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite71| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,540 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 22:47:56,541 INFO L149 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2021-01-26 22:47:56,555 INFO L253 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2021-01-26 22:47:56,579 INFO L377 AbstractCegarLoop]: Interprodecural is true [2021-01-26 22:47:56,579 INFO L378 AbstractCegarLoop]: Hoare is true [2021-01-26 22:47:56,579 INFO L379 AbstractCegarLoop]: Compute interpolants for FPandBP [2021-01-26 22:47:56,579 INFO L380 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2021-01-26 22:47:56,579 INFO L381 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-01-26 22:47:56,580 INFO L382 AbstractCegarLoop]: Difference is false [2021-01-26 22:47:56,580 INFO L383 AbstractCegarLoop]: Minimize is NONE [2021-01-26 22:47:56,580 INFO L387 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== Size of Word is: 59 and size of Sequence is : 60[2021-01-26 22:47:56,608 INFO L164 SleepSetCegar]: Size of mCounterexample is: 60 [2021-01-26 22:47:56,608 INFO L165 SleepSetCegar]: [132#[ULTIMATE.startENTRY]don't care, 134#[L-1]don't care, 136#[L-1-1]don't care, 138#[L17]don't care, 140#[L17-1]don't care, 142#[L17-2]don't care, 144#[L17-3]don't care, 146#[L17-4]don't care, 148#[L711]don't care, 150#[L713]don't care, 152#[L714]don't care, 154#[L715]don't care, 156#[L716]don't care, 158#[L717]don't care, 160#[L718]don't care, 162#[L719]don't care, 164#[L720]don't care, 166#[L721]don't care, 168#[L722]don't care, 170#[L723]don't care, 172#[L724]don't care, 174#[L725]don't care, 176#[L726]don't care, 178#[L727]don't care, 180#[L728]don't care, 182#[L729]don't care, 184#[L731]don't care, 186#[L732]don't care, 188#[L733]don't care, 190#[L735]don't care, 192#[L735-1]don't care, 194#[L735-2]don't care, 196#[L737]don't care, 198#[L738]don't care, 200#[L739]don't care, 202#[L740]don't care, 204#[L741]don't care, 206#[L742]don't care, 208#[L743]don't care, 210#[L744]don't care, 212#[L745]don't care, 214#[L746]don't care, 216#[L747]don't care, 218#[L748]don't care, 220#[L749]don't care, 222#[L750]don't care, 224#[L751]don't care, 226#[L753]don't care, 228#[L754]don't care, 230#[L755]don't care, 232#[L756]don't care, 234#[L-1-2]don't care, 236#[L-1-3]don't care, 238#[L853]don't care, 240#[L853-1]don't care, 242#[L854]don't care, 244#[P0ENTRY, L854-1]don't care, 246#[L854-1, L759]don't care, 252#[L854-1, L761]don't care, 254#[L854-1, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]don't care] [2021-01-26 22:47:56,608 INFO L429 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 22:47:56,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 22:47:56,614 INFO L82 PathProgramCache]: Analyzing trace with hash 454458663, now seen corresponding path program 1 times [2021-01-26 22:47:56,624 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 22:47:56,624 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071551202] [2021-01-26 22:47:56,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 22:47:56,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 22:47:56,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 22:47:56,965 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1071551202] [2021-01-26 22:47:56,967 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 22:47:56,967 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-26 22:47:56,968 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951319076] [2021-01-26 22:47:56,978 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-26 22:47:56,978 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 22:47:56,996 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-26 22:47:57,001 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-26 22:47:57,004 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 22:47:57,006 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 3 states, 2 states have (on average 29.5) internal successors, (59), 3 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 22:47:57,040 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check Size of Word is: 100 and size of Sequence is : 101[2021-01-26 22:47:57,126 INFO L164 SleepSetCegar]: Size of mCounterexample is: 101 [2021-01-26 22:47:57,127 INFO L165 SleepSetCegar]: [262#[ULTIMATE.startENTRY]true, 263#[L-1]true, 264#[L-1-1]true, 265#[L17]true, 266#[L17-1]true, 267#[L17-2]true, 268#[L17-3]true, 269#[L17-4]true, 270#[L711]true, 271#[L713]true, 272#[L714]true, 273#[L715]true, 274#[L716]true, 275#[L717]true, 276#[L718]true, 277#[L719]true, 278#[L720]true, 279#[L721]true, 280#[L722]true, 281#[L723]true, 282#[L724]true, 283#[L725]true, 284#[L726]true, 285#[L727]true, 286#[L728]true, 287#[L729]true, 288#[L731]true, 289#[L732]true, 290#[L733]true, 291#[L735]true, 292#[L735-1]true, 293#[L735-2]true, 294#[L737]true, 295#[L738]true, 296#[L739]true, 297#[L740]true, 298#[L741]true, 299#[L742]true, 300#[L743]true, 301#[L744]true, 302#[L745]true, 303#[L746]true, 304#[L747]true, 305#[L748]true, 306#[L749]true, 307#[L750](= ~x$w_buff0_used~0 0), 308#[L751](= ~x$w_buff0_used~0 0), 309#[L753](= ~x$w_buff0_used~0 0), 310#[L754](= ~x$w_buff0_used~0 0), 311#[L755](= ~x$w_buff0_used~0 0), 312#[L756](= ~x$w_buff0_used~0 0), 313#[L-1-2](= ~x$w_buff0_used~0 0), 314#[L-1-3](= ~x$w_buff0_used~0 0), 315#[L853](= ~x$w_buff0_used~0 0), 316#[L853-1](= ~x$w_buff0_used~0 0), 317#[L854](= ~x$w_buff0_used~0 0), 318#[P0ENTRY, L854-1](= ~x$w_buff0_used~0 0), 319#[L854-1, L759](= ~x$w_buff0_used~0 0), 322#[L854-1, L761](= ~x$w_buff0_used~0 0), 325#[L773, L854-1]true, 331#[L854-1, L780]true, 337#[L854-1, L783]true, 343#[L854-1, P0FINAL]true, 348#[L854-1, P0EXIT]true, 352#[L855, P0EXIT]true, 355#[L855-1, P0EXIT]true, 358#[L856, P0EXIT]true, 361#[L856-1, P1ENTRY, P0EXIT]true, 367#[P1ENTRY, P0EXIT, L857]true, 372#[P0EXIT, L857, L788]true, 379#[L806, P0EXIT, L857]true, 385#[L809, P0EXIT, L857]true, 390#[L816, P0EXIT, L857]true, 396#[L819, P0EXIT, L857]true, 402#[P1FINAL, P0EXIT, L857]true, 408#[P1EXIT, P0EXIT, L857]true, 412#[L857-1, P1EXIT, P0EXIT]true, 415#[P1EXIT, L858, P0EXIT]true, 418#[P1EXIT, L858-1, P0EXIT, P2ENTRY]true, 423#[P1EXIT, P0EXIT, L859, P2ENTRY]true, 429#[P1EXIT, L861, P0EXIT, P2ENTRY]true, 435#[P1EXIT, L862, P0EXIT, P2ENTRY]true, 441#[P1EXIT, L2, P0EXIT, P2ENTRY]true, 447#[P1EXIT, P0EXIT, P2ENTRY, L3]true, 456#[P1EXIT, L2-1, P0EXIT, P2ENTRY]true, 503#[P1EXIT, L869, P0EXIT, P2ENTRY]true, 509#[P1EXIT, L874, P0EXIT, P2ENTRY]true, 516#[L824, P1EXIT, L874, P0EXIT]true, 522#[P1EXIT, L826, L874, P0EXIT]true, 528#[P1EXIT, L874, L829, P0EXIT]true, 534#[L836, P1EXIT, L874, P0EXIT]true, 540#[P1EXIT, L839, L874, P0EXIT]true, 545#[P1EXIT, L874, P2FINAL, P0EXIT]true, 552#[P2EXIT, P1EXIT, L874, P0EXIT]true, 555#[P2EXIT, L875, P1EXIT, P0EXIT]true, 558#[P2EXIT, P1EXIT, L18, P0EXIT]true, 561#[P2EXIT, L18-1, P1EXIT, P0EXIT]true, 566#[P2EXIT, L18-2, P1EXIT, P0EXIT]true, 570#[P2EXIT, P1EXIT, L17-5, P0EXIT]true, 575#[P2EXIT, L17-7, P1EXIT, P0EXIT]true, 581#[P2EXIT, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1EXIT, P0EXIT]true] [2021-01-26 22:47:57,127 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-01-26 22:47:57,127 INFO L429 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 22:47:57,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 22:47:57,128 INFO L82 PathProgramCache]: Analyzing trace with hash 500615883, now seen corresponding path program 1 times [2021-01-26 22:47:57,128 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 22:47:57,128 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611728523] [2021-01-26 22:47:57,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 22:47:57,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 22:47:57,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 22:47:57,821 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611728523] [2021-01-26 22:47:57,821 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 22:47:57,821 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2021-01-26 22:47:57,822 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [807244328] [2021-01-26 22:47:57,826 INFO L461 AbstractCegarLoop]: Interpolant automaton has 7 states [2021-01-26 22:47:57,826 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 22:47:57,827 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-01-26 22:47:57,827 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2021-01-26 22:47:57,827 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 22:47:57,827 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 22:47:58,016 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:02,096 WARN L146 IndependenceRelation]: Expensive independence query (3794 ms) for statements [1364] L829-->L836: Formula: (let ((.cse5 (= (mod v_~x$w_buff0_used~0_416 256) 0)) (.cse4 (= (mod v_~x$r_buff1_thd3~0_56 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_332 256) 0)) (.cse14 (= 0 (mod v_~x$r_buff0_thd3~0_62 256))) (.cse16 (= (mod v_~x$w_buff0_used~0_417 256) 0))) (let ((.cse11 (not .cse16)) (.cse6 (or .cse14 .cse16)) (.cse8 (not .cse15)) (.cse3 (not .cse4)) (.cse9 (or .cse15 .cse4)) (.cse13 (or .cse14 .cse5)) (.cse0 (not .cse5)) (.cse12 (not .cse14)) (.cse10 (select |v_#memory_int_258| |v_~#x~0.base_162|))) (and (let ((.cse2 (= (mod v_~x$w_buff1_used~0_331 256) 0)) (.cse1 (= (mod v_~x$r_buff0_thd3~0_61 256) 0))) (or (and (= v_~x$r_buff1_thd3~0_55 0) (or (and .cse0 (not .cse1)) (and (not .cse2) .cse3))) (and (= v_~x$r_buff1_thd3~0_56 v_~x$r_buff1_thd3~0_55) (or .cse2 .cse4) (or .cse5 .cse1)))) (let ((.cse7 (= |v_P2_#t~mem68_38| |v_P2Thread1of1ForFork2_#t~mem68_1|))) (or (and (= |v_P2_#t~ite69_39| |v_P2_#t~ite70_33|) .cse6 (or (and .cse7 (= |v_P2_#t~ite69_39| v_~x$w_buff1~0_86) .cse3 .cse8) (and .cse9 (= |v_P2_#t~ite69_39| |v_P2_#t~mem68_38|) (= |v_P2_#t~mem68_38| (select .cse10 |v_~#x~0.offset_162|))))) (and (= |v_P2_#t~ite69_39| |v_P2Thread1of1ForFork2_#t~ite69_1|) .cse7 .cse11 (= |v_P2_#t~ite70_33| v_~x$w_buff0~0_115) .cse12))) (or (and .cse11 (= v_~x$w_buff0_used~0_416 0) .cse12) (and .cse6 (= v_~x$w_buff0_used~0_417 v_~x$w_buff0_used~0_416))) (or (and (= v_~x$w_buff1_used~0_331 0) (or (and .cse0 .cse12) (and .cse8 .cse3))) (and .cse9 .cse13 (= v_~x$w_buff1_used~0_332 v_~x$w_buff1_used~0_331))) (or (and .cse13 (= v_~x$r_buff0_thd3~0_62 v_~x$r_buff0_thd3~0_61)) (and .cse0 (= v_~x$r_buff0_thd3~0_61 0) .cse12)) (= (store |v_#memory_int_258| |v_~#x~0.base_162| (store .cse10 |v_~#x~0.offset_162| |v_P2_#t~ite70_33|)) |v_#memory_int_257|)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_115, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_1|, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_1|, #memory_int=|v_#memory_int_258|, ~#x~0.base=|v_~#x~0.base_162|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_56, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_332, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_62, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_417} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_115, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_2|, P2Thread1of1ForFork2_#t~ite73=|v_P2Thread1of1ForFork2_#t~ite73_1|, P2Thread1of1ForFork2_#t~ite72=|v_P2Thread1of1ForFork2_#t~ite72_1|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_55, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_331, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_1|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_61, P2Thread1of1ForFork2_#t~ite71=|v_P2Thread1of1ForFork2_#t~ite71_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_416, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_2|, P2Thread1of1ForFork2_#t~ite74=|v_P2Thread1of1ForFork2_#t~ite74_1|, #memory_int=|v_#memory_int_257|, ~#x~0.base=|v_~#x~0.base_162|} AuxVars[|v_P2_#t~ite70_33|, |v_P2_#t~mem68_38|, |v_P2_#t~ite69_39|] AssignedVars[P2Thread1of1ForFork2_#t~ite69, P2Thread1of1ForFork2_#t~mem68, P2Thread1of1ForFork2_#t~ite74, P2Thread1of1ForFork2_#t~ite73, P2Thread1of1ForFork2_#t~ite72, #memory_int, ~x$r_buff1_thd3~0, ~x$w_buff1_used~0, P2Thread1of1ForFork2_#t~ite70, ~x$r_buff0_thd3~0, P2Thread1of1ForFork2_#t~ite71, ~x$w_buff0_used~0] and [1340] L2-1-->L869: Formula: (let ((.cse13 (= (mod v_~x$w_buff0_used~0_454 256) 0)) (.cse12 (= (mod v_~x$r_buff1_thd0~0_64 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_374 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd0~0_68 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_455 256) 0))) (let ((.cse3 (not .cse16)) (.cse4 (or .cse16 .cse14)) (.cse7 (not .cse15)) (.cse1 (not .cse14)) (.cse8 (or .cse15 .cse12)) (.cse0 (or .cse13 .cse14)) (.cse9 (select |v_#memory_int_282| |v_~#x~0.base_178|)) (.cse2 (not .cse13)) (.cse6 (not .cse12))) (and (or (and .cse0 (= v_~x$r_buff0_thd0~0_68 v_~x$r_buff0_thd0~0_67)) (and .cse1 .cse2 (= v_~x$r_buff0_thd0~0_67 0))) (or (and (= v_~x$w_buff0_used~0_454 0) .cse1 .cse3) (and .cse4 (= v_~x$w_buff0_used~0_455 v_~x$w_buff0_used~0_454))) (let ((.cse5 (= |v_ULTIMATE.start_main_#t~mem78_23| |v_ULTIMATE.start_main_#t~mem78_27|))) (or (and .cse1 (= v_~x$w_buff0~0_125 |v_ULTIMATE.start_main_#t~ite80_32|) (= |v_ULTIMATE.start_main_#t~ite79_22| |v_ULTIMATE.start_main_#t~ite79_26|) .cse3 .cse5) (and (or (and .cse6 .cse7 .cse5 (= |v_ULTIMATE.start_main_#t~ite79_26| v_~x$w_buff1~0_98)) (and .cse8 (= |v_ULTIMATE.start_main_#t~mem78_27| (select .cse9 |v_~#x~0.offset_178|)) (= |v_ULTIMATE.start_main_#t~mem78_27| |v_ULTIMATE.start_main_#t~ite79_26|))) (= |v_ULTIMATE.start_main_#t~ite79_26| |v_ULTIMATE.start_main_#t~ite80_32|) .cse4))) (or (and (or (and .cse6 .cse7) (and .cse1 .cse2)) (= v_~x$w_buff1_used~0_373 0)) (and .cse8 .cse0 (= v_~x$w_buff1_used~0_374 v_~x$w_buff1_used~0_373))) (= (store |v_#memory_int_282| |v_~#x~0.base_178| (store .cse9 |v_~#x~0.offset_178| |v_ULTIMATE.start_main_#t~ite80_32|)) |v_#memory_int_281|) (let ((.cse11 (= (mod v_~x$w_buff1_used~0_373 256) 0)) (.cse10 (= (mod v_~x$r_buff0_thd0~0_67 256) 0))) (or (and (or (and .cse2 (not .cse10)) (and .cse6 (not .cse11))) (= v_~x$r_buff1_thd0~0_63 0)) (and (or .cse11 .cse12) (or .cse13 .cse10) (= v_~x$r_buff1_thd0~0_64 v_~x$r_buff1_thd0~0_63))))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_68, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_23|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, #memory_int=|v_#memory_int_282|, ~#x~0.base=|v_~#x~0.base_178|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_374, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_22|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_64, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_455} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_67, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_21|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_373, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_20|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_63, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_454, ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_26|, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_32|, ULTIMATE.start_main_#t~ite82=|v_ULTIMATE.start_main_#t~ite82_28|, ULTIMATE.start_main_#t~ite81=|v_ULTIMATE.start_main_#t~ite81_36|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_28|, #memory_int=|v_#memory_int_281|, ~#x~0.base=|v_~#x~0.base_178|} AuxVars[|v_ULTIMATE.start_main_#t~ite79_26|, |v_ULTIMATE.start_main_#t~ite80_32|, |v_ULTIMATE.start_main_#t~mem78_27|] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem78, ULTIMATE.start_main_#t~ite84, ULTIMATE.start_main_#t~ite83, ULTIMATE.start_main_#t~ite82, ULTIMATE.start_main_#t~ite81, ULTIMATE.start_main_#t~ite80, #memory_int, ~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite79, ~x$r_buff1_thd0~0, ~x$w_buff0_used~0] under condition null [2021-01-26 22:48:04,802 WARN L146 IndependenceRelation]: Expensive independence query (2525 ms) for statements [1256] L857-1-->L858: Formula: (= |v_#memory_int_28| (store |v_#memory_int_29| |v_ULTIMATE.start_main_~#t1782~0.base_5| (store (select |v_#memory_int_29| |v_ULTIMATE.start_main_~#t1782~0.base_5|) |v_ULTIMATE.start_main_~#t1782~0.offset_5| 2))) InVars {#memory_int=|v_#memory_int_29|, ULTIMATE.start_main_~#t1782~0.base=|v_ULTIMATE.start_main_~#t1782~0.base_5|, ULTIMATE.start_main_~#t1782~0.offset=|v_ULTIMATE.start_main_~#t1782~0.offset_5|} OutVars{#memory_int=|v_#memory_int_28|, ULTIMATE.start_main_~#t1782~0.base=|v_ULTIMATE.start_main_~#t1782~0.base_5|, ULTIMATE.start_main_~#t1782~0.offset=|v_ULTIMATE.start_main_~#t1782~0.offset_5|} AuxVars[] AssignedVars[#memory_int] and [1357] L809-->L816: Formula: (let ((.cse4 (= (mod v_~x$w_buff0_used~0_502 256) 0)) (.cse5 (= (mod v_~x$r_buff1_thd2~0_258 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_422 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd2~0_292 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_503 256) 0))) (let ((.cse13 (not .cse16)) (.cse8 (or .cse14 .cse16)) (.cse9 (select |v_#memory_int_296| |v_~#x~0.base_186|)) (.cse12 (not .cse15)) (.cse7 (not .cse5)) (.cse1 (not .cse4)) (.cse2 (not .cse14)) (.cse10 (or .cse5 .cse15)) (.cse0 (or .cse14 .cse4))) (and (or (and (= v_~x$r_buff0_thd2~0_291 v_~x$r_buff0_thd2~0_292) .cse0) (and .cse1 (= v_~x$r_buff0_thd2~0_291 0) .cse2)) (let ((.cse6 (= (mod v_~x$w_buff1_used~0_421 256) 0)) (.cse3 (= (mod v_~x$r_buff0_thd2~0_291 256) 0))) (or (and (or .cse3 .cse4) (= v_~x$r_buff1_thd2~0_258 v_~x$r_buff1_thd2~0_257) (or .cse5 .cse6)) (and (= v_~x$r_buff1_thd2~0_257 0) (or (and (not .cse6) .cse7) (and .cse1 (not .cse3)))))) (let ((.cse11 (= |v_P1_#t~mem61_50| |v_P1Thread1of1ForFork1_#t~mem61_1|))) (or (and .cse8 (or (and (= |v_P1_#t~ite62_49| |v_P1_#t~mem61_50|) (= (select .cse9 |v_~#x~0.offset_186|) |v_P1_#t~mem61_50|) .cse10) (and (= |v_P1_#t~ite62_49| v_~x$w_buff1~0_126) .cse11 .cse12 .cse7)) (= |v_P1_#t~ite62_49| |v_P1_#t~ite63_43|)) (and .cse13 .cse11 (= |v_P1_#t~ite62_49| |v_P1Thread1of1ForFork1_#t~ite62_1|) .cse2 (= |v_P1_#t~ite63_43| v_~x$w_buff0~0_133)))) (or (and .cse13 (= v_~x$w_buff0_used~0_502 0) .cse2) (and (= v_~x$w_buff0_used~0_503 v_~x$w_buff0_used~0_502) .cse8)) (= (store |v_#memory_int_296| |v_~#x~0.base_186| (store .cse9 |v_~#x~0.offset_186| |v_P1_#t~ite63_43|)) |v_#memory_int_295|) (or (and (= v_~x$w_buff1_used~0_421 0) (or (and .cse12 .cse7) (and .cse1 .cse2))) (and .cse10 (= v_~x$w_buff1_used~0_422 v_~x$w_buff1_used~0_421) .cse0))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_133, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_1|, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, #memory_int=|v_#memory_int_296|, ~#x~0.base=|v_~#x~0.base_186|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_422, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_258, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_292, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_503} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_133, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_257, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_421, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_291, P1Thread1of1ForFork1_#t~ite65=|v_P1Thread1of1ForFork1_#t~ite65_1|, P1Thread1of1ForFork1_#t~ite66=|v_P1Thread1of1ForFork1_#t~ite66_1|, P1Thread1of1ForFork1_#t~ite67=|v_P1Thread1of1ForFork1_#t~ite67_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_502, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_2|, P1Thread1of1ForFork1_#t~ite63=|v_P1Thread1of1ForFork1_#t~ite63_1|, P1Thread1of1ForFork1_#t~ite64=|v_P1Thread1of1ForFork1_#t~ite64_1|, #memory_int=|v_#memory_int_295|, ~#x~0.base=|v_~#x~0.base_186|} AuxVars[|v_P1_#t~ite62_49|, |v_P1_#t~mem61_50|, |v_P1_#t~ite63_43|] AssignedVars[P1Thread1of1ForFork1_#t~ite62, P1Thread1of1ForFork1_#t~ite63, P1Thread1of1ForFork1_#t~ite64, #memory_int, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, P1Thread1of1ForFork1_#t~mem61, ~x$r_buff0_thd2~0, P1Thread1of1ForFork1_#t~ite65, P1Thread1of1ForFork1_#t~ite66, P1Thread1of1ForFork1_#t~ite67, ~x$w_buff0_used~0] under condition null [2021-01-26 22:48:08,871 WARN L146 IndependenceRelation]: Expensive independence query (4065 ms) for statements [1364] L829-->L836: Formula: (let ((.cse5 (= (mod v_~x$w_buff0_used~0_416 256) 0)) (.cse4 (= (mod v_~x$r_buff1_thd3~0_56 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_332 256) 0)) (.cse14 (= 0 (mod v_~x$r_buff0_thd3~0_62 256))) (.cse16 (= (mod v_~x$w_buff0_used~0_417 256) 0))) (let ((.cse11 (not .cse16)) (.cse6 (or .cse14 .cse16)) (.cse8 (not .cse15)) (.cse3 (not .cse4)) (.cse9 (or .cse15 .cse4)) (.cse13 (or .cse14 .cse5)) (.cse0 (not .cse5)) (.cse12 (not .cse14)) (.cse10 (select |v_#memory_int_258| |v_~#x~0.base_162|))) (and (let ((.cse2 (= (mod v_~x$w_buff1_used~0_331 256) 0)) (.cse1 (= (mod v_~x$r_buff0_thd3~0_61 256) 0))) (or (and (= v_~x$r_buff1_thd3~0_55 0) (or (and .cse0 (not .cse1)) (and (not .cse2) .cse3))) (and (= v_~x$r_buff1_thd3~0_56 v_~x$r_buff1_thd3~0_55) (or .cse2 .cse4) (or .cse5 .cse1)))) (let ((.cse7 (= |v_P2_#t~mem68_38| |v_P2Thread1of1ForFork2_#t~mem68_1|))) (or (and (= |v_P2_#t~ite69_39| |v_P2_#t~ite70_33|) .cse6 (or (and .cse7 (= |v_P2_#t~ite69_39| v_~x$w_buff1~0_86) .cse3 .cse8) (and .cse9 (= |v_P2_#t~ite69_39| |v_P2_#t~mem68_38|) (= |v_P2_#t~mem68_38| (select .cse10 |v_~#x~0.offset_162|))))) (and (= |v_P2_#t~ite69_39| |v_P2Thread1of1ForFork2_#t~ite69_1|) .cse7 .cse11 (= |v_P2_#t~ite70_33| v_~x$w_buff0~0_115) .cse12))) (or (and .cse11 (= v_~x$w_buff0_used~0_416 0) .cse12) (and .cse6 (= v_~x$w_buff0_used~0_417 v_~x$w_buff0_used~0_416))) (or (and (= v_~x$w_buff1_used~0_331 0) (or (and .cse0 .cse12) (and .cse8 .cse3))) (and .cse9 .cse13 (= v_~x$w_buff1_used~0_332 v_~x$w_buff1_used~0_331))) (or (and .cse13 (= v_~x$r_buff0_thd3~0_62 v_~x$r_buff0_thd3~0_61)) (and .cse0 (= v_~x$r_buff0_thd3~0_61 0) .cse12)) (= (store |v_#memory_int_258| |v_~#x~0.base_162| (store .cse10 |v_~#x~0.offset_162| |v_P2_#t~ite70_33|)) |v_#memory_int_257|)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_115, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_1|, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_1|, #memory_int=|v_#memory_int_258|, ~#x~0.base=|v_~#x~0.base_162|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_56, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_332, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_62, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_417} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_115, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_2|, P2Thread1of1ForFork2_#t~ite73=|v_P2Thread1of1ForFork2_#t~ite73_1|, P2Thread1of1ForFork2_#t~ite72=|v_P2Thread1of1ForFork2_#t~ite72_1|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_55, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_331, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_1|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_61, P2Thread1of1ForFork2_#t~ite71=|v_P2Thread1of1ForFork2_#t~ite71_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_416, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_2|, P2Thread1of1ForFork2_#t~ite74=|v_P2Thread1of1ForFork2_#t~ite74_1|, #memory_int=|v_#memory_int_257|, ~#x~0.base=|v_~#x~0.base_162|} AuxVars[|v_P2_#t~ite70_33|, |v_P2_#t~mem68_38|, |v_P2_#t~ite69_39|] AssignedVars[P2Thread1of1ForFork2_#t~ite69, P2Thread1of1ForFork2_#t~mem68, P2Thread1of1ForFork2_#t~ite74, P2Thread1of1ForFork2_#t~ite73, P2Thread1of1ForFork2_#t~ite72, #memory_int, ~x$r_buff1_thd3~0, ~x$w_buff1_used~0, P2Thread1of1ForFork2_#t~ite70, ~x$r_buff0_thd3~0, P2Thread1of1ForFork2_#t~ite71, ~x$w_buff0_used~0] and [1357] L809-->L816: Formula: (let ((.cse4 (= (mod v_~x$w_buff0_used~0_502 256) 0)) (.cse5 (= (mod v_~x$r_buff1_thd2~0_258 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_422 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd2~0_292 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_503 256) 0))) (let ((.cse13 (not .cse16)) (.cse8 (or .cse14 .cse16)) (.cse9 (select |v_#memory_int_296| |v_~#x~0.base_186|)) (.cse12 (not .cse15)) (.cse7 (not .cse5)) (.cse1 (not .cse4)) (.cse2 (not .cse14)) (.cse10 (or .cse5 .cse15)) (.cse0 (or .cse14 .cse4))) (and (or (and (= v_~x$r_buff0_thd2~0_291 v_~x$r_buff0_thd2~0_292) .cse0) (and .cse1 (= v_~x$r_buff0_thd2~0_291 0) .cse2)) (let ((.cse6 (= (mod v_~x$w_buff1_used~0_421 256) 0)) (.cse3 (= (mod v_~x$r_buff0_thd2~0_291 256) 0))) (or (and (or .cse3 .cse4) (= v_~x$r_buff1_thd2~0_258 v_~x$r_buff1_thd2~0_257) (or .cse5 .cse6)) (and (= v_~x$r_buff1_thd2~0_257 0) (or (and (not .cse6) .cse7) (and .cse1 (not .cse3)))))) (let ((.cse11 (= |v_P1_#t~mem61_50| |v_P1Thread1of1ForFork1_#t~mem61_1|))) (or (and .cse8 (or (and (= |v_P1_#t~ite62_49| |v_P1_#t~mem61_50|) (= (select .cse9 |v_~#x~0.offset_186|) |v_P1_#t~mem61_50|) .cse10) (and (= |v_P1_#t~ite62_49| v_~x$w_buff1~0_126) .cse11 .cse12 .cse7)) (= |v_P1_#t~ite62_49| |v_P1_#t~ite63_43|)) (and .cse13 .cse11 (= |v_P1_#t~ite62_49| |v_P1Thread1of1ForFork1_#t~ite62_1|) .cse2 (= |v_P1_#t~ite63_43| v_~x$w_buff0~0_133)))) (or (and .cse13 (= v_~x$w_buff0_used~0_502 0) .cse2) (and (= v_~x$w_buff0_used~0_503 v_~x$w_buff0_used~0_502) .cse8)) (= (store |v_#memory_int_296| |v_~#x~0.base_186| (store .cse9 |v_~#x~0.offset_186| |v_P1_#t~ite63_43|)) |v_#memory_int_295|) (or (and (= v_~x$w_buff1_used~0_421 0) (or (and .cse12 .cse7) (and .cse1 .cse2))) (and .cse10 (= v_~x$w_buff1_used~0_422 v_~x$w_buff1_used~0_421) .cse0))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_133, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_1|, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, #memory_int=|v_#memory_int_296|, ~#x~0.base=|v_~#x~0.base_186|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_422, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_258, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_292, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_503} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_133, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_257, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_421, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_291, P1Thread1of1ForFork1_#t~ite65=|v_P1Thread1of1ForFork1_#t~ite65_1|, P1Thread1of1ForFork1_#t~ite66=|v_P1Thread1of1ForFork1_#t~ite66_1|, P1Thread1of1ForFork1_#t~ite67=|v_P1Thread1of1ForFork1_#t~ite67_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_502, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_2|, P1Thread1of1ForFork1_#t~ite63=|v_P1Thread1of1ForFork1_#t~ite63_1|, P1Thread1of1ForFork1_#t~ite64=|v_P1Thread1of1ForFork1_#t~ite64_1|, #memory_int=|v_#memory_int_295|, ~#x~0.base=|v_~#x~0.base_186|} AuxVars[|v_P1_#t~ite62_49|, |v_P1_#t~mem61_50|, |v_P1_#t~ite63_43|] AssignedVars[P1Thread1of1ForFork1_#t~ite62, P1Thread1of1ForFork1_#t~ite63, P1Thread1of1ForFork1_#t~ite64, #memory_int, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, P1Thread1of1ForFork1_#t~mem61, ~x$r_buff0_thd2~0, P1Thread1of1ForFork1_#t~ite65, P1Thread1of1ForFork1_#t~ite66, P1Thread1of1ForFork1_#t~ite67, ~x$w_buff0_used~0] under condition null [2021-01-26 22:48:12,975 WARN L146 IndependenceRelation]: Expensive independence query (4101 ms) for statements [1340] L2-1-->L869: Formula: (let ((.cse13 (= (mod v_~x$w_buff0_used~0_454 256) 0)) (.cse12 (= (mod v_~x$r_buff1_thd0~0_64 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_374 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd0~0_68 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_455 256) 0))) (let ((.cse3 (not .cse16)) (.cse4 (or .cse16 .cse14)) (.cse7 (not .cse15)) (.cse1 (not .cse14)) (.cse8 (or .cse15 .cse12)) (.cse0 (or .cse13 .cse14)) (.cse9 (select |v_#memory_int_282| |v_~#x~0.base_178|)) (.cse2 (not .cse13)) (.cse6 (not .cse12))) (and (or (and .cse0 (= v_~x$r_buff0_thd0~0_68 v_~x$r_buff0_thd0~0_67)) (and .cse1 .cse2 (= v_~x$r_buff0_thd0~0_67 0))) (or (and (= v_~x$w_buff0_used~0_454 0) .cse1 .cse3) (and .cse4 (= v_~x$w_buff0_used~0_455 v_~x$w_buff0_used~0_454))) (let ((.cse5 (= |v_ULTIMATE.start_main_#t~mem78_23| |v_ULTIMATE.start_main_#t~mem78_27|))) (or (and .cse1 (= v_~x$w_buff0~0_125 |v_ULTIMATE.start_main_#t~ite80_32|) (= |v_ULTIMATE.start_main_#t~ite79_22| |v_ULTIMATE.start_main_#t~ite79_26|) .cse3 .cse5) (and (or (and .cse6 .cse7 .cse5 (= |v_ULTIMATE.start_main_#t~ite79_26| v_~x$w_buff1~0_98)) (and .cse8 (= |v_ULTIMATE.start_main_#t~mem78_27| (select .cse9 |v_~#x~0.offset_178|)) (= |v_ULTIMATE.start_main_#t~mem78_27| |v_ULTIMATE.start_main_#t~ite79_26|))) (= |v_ULTIMATE.start_main_#t~ite79_26| |v_ULTIMATE.start_main_#t~ite80_32|) .cse4))) (or (and (or (and .cse6 .cse7) (and .cse1 .cse2)) (= v_~x$w_buff1_used~0_373 0)) (and .cse8 .cse0 (= v_~x$w_buff1_used~0_374 v_~x$w_buff1_used~0_373))) (= (store |v_#memory_int_282| |v_~#x~0.base_178| (store .cse9 |v_~#x~0.offset_178| |v_ULTIMATE.start_main_#t~ite80_32|)) |v_#memory_int_281|) (let ((.cse11 (= (mod v_~x$w_buff1_used~0_373 256) 0)) (.cse10 (= (mod v_~x$r_buff0_thd0~0_67 256) 0))) (or (and (or (and .cse2 (not .cse10)) (and .cse6 (not .cse11))) (= v_~x$r_buff1_thd0~0_63 0)) (and (or .cse11 .cse12) (or .cse13 .cse10) (= v_~x$r_buff1_thd0~0_64 v_~x$r_buff1_thd0~0_63))))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_68, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_23|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, #memory_int=|v_#memory_int_282|, ~#x~0.base=|v_~#x~0.base_178|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_374, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_22|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_64, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_455} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_67, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_21|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_373, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_20|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_63, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_454, ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_26|, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_32|, ULTIMATE.start_main_#t~ite82=|v_ULTIMATE.start_main_#t~ite82_28|, ULTIMATE.start_main_#t~ite81=|v_ULTIMATE.start_main_#t~ite81_36|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_28|, #memory_int=|v_#memory_int_281|, ~#x~0.base=|v_~#x~0.base_178|} AuxVars[|v_ULTIMATE.start_main_#t~ite79_26|, |v_ULTIMATE.start_main_#t~ite80_32|, |v_ULTIMATE.start_main_#t~mem78_27|] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem78, ULTIMATE.start_main_#t~ite84, ULTIMATE.start_main_#t~ite83, ULTIMATE.start_main_#t~ite82, ULTIMATE.start_main_#t~ite81, ULTIMATE.start_main_#t~ite80, #memory_int, ~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite79, ~x$r_buff1_thd0~0, ~x$w_buff0_used~0] and [1357] L809-->L816: Formula: (let ((.cse4 (= (mod v_~x$w_buff0_used~0_502 256) 0)) (.cse5 (= (mod v_~x$r_buff1_thd2~0_258 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_422 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd2~0_292 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_503 256) 0))) (let ((.cse13 (not .cse16)) (.cse8 (or .cse14 .cse16)) (.cse9 (select |v_#memory_int_296| |v_~#x~0.base_186|)) (.cse12 (not .cse15)) (.cse7 (not .cse5)) (.cse1 (not .cse4)) (.cse2 (not .cse14)) (.cse10 (or .cse5 .cse15)) (.cse0 (or .cse14 .cse4))) (and (or (and (= v_~x$r_buff0_thd2~0_291 v_~x$r_buff0_thd2~0_292) .cse0) (and .cse1 (= v_~x$r_buff0_thd2~0_291 0) .cse2)) (let ((.cse6 (= (mod v_~x$w_buff1_used~0_421 256) 0)) (.cse3 (= (mod v_~x$r_buff0_thd2~0_291 256) 0))) (or (and (or .cse3 .cse4) (= v_~x$r_buff1_thd2~0_258 v_~x$r_buff1_thd2~0_257) (or .cse5 .cse6)) (and (= v_~x$r_buff1_thd2~0_257 0) (or (and (not .cse6) .cse7) (and .cse1 (not .cse3)))))) (let ((.cse11 (= |v_P1_#t~mem61_50| |v_P1Thread1of1ForFork1_#t~mem61_1|))) (or (and .cse8 (or (and (= |v_P1_#t~ite62_49| |v_P1_#t~mem61_50|) (= (select .cse9 |v_~#x~0.offset_186|) |v_P1_#t~mem61_50|) .cse10) (and (= |v_P1_#t~ite62_49| v_~x$w_buff1~0_126) .cse11 .cse12 .cse7)) (= |v_P1_#t~ite62_49| |v_P1_#t~ite63_43|)) (and .cse13 .cse11 (= |v_P1_#t~ite62_49| |v_P1Thread1of1ForFork1_#t~ite62_1|) .cse2 (= |v_P1_#t~ite63_43| v_~x$w_buff0~0_133)))) (or (and .cse13 (= v_~x$w_buff0_used~0_502 0) .cse2) (and (= v_~x$w_buff0_used~0_503 v_~x$w_buff0_used~0_502) .cse8)) (= (store |v_#memory_int_296| |v_~#x~0.base_186| (store .cse9 |v_~#x~0.offset_186| |v_P1_#t~ite63_43|)) |v_#memory_int_295|) (or (and (= v_~x$w_buff1_used~0_421 0) (or (and .cse12 .cse7) (and .cse1 .cse2))) (and .cse10 (= v_~x$w_buff1_used~0_422 v_~x$w_buff1_used~0_421) .cse0))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_133, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_1|, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, #memory_int=|v_#memory_int_296|, ~#x~0.base=|v_~#x~0.base_186|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_422, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_258, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_292, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_503} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_133, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_257, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_421, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_291, P1Thread1of1ForFork1_#t~ite65=|v_P1Thread1of1ForFork1_#t~ite65_1|, P1Thread1of1ForFork1_#t~ite66=|v_P1Thread1of1ForFork1_#t~ite66_1|, P1Thread1of1ForFork1_#t~ite67=|v_P1Thread1of1ForFork1_#t~ite67_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_502, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_2|, P1Thread1of1ForFork1_#t~ite63=|v_P1Thread1of1ForFork1_#t~ite63_1|, P1Thread1of1ForFork1_#t~ite64=|v_P1Thread1of1ForFork1_#t~ite64_1|, #memory_int=|v_#memory_int_295|, ~#x~0.base=|v_~#x~0.base_186|} AuxVars[|v_P1_#t~ite62_49|, |v_P1_#t~mem61_50|, |v_P1_#t~ite63_43|] AssignedVars[P1Thread1of1ForFork1_#t~ite62, P1Thread1of1ForFork1_#t~ite63, P1Thread1of1ForFork1_#t~ite64, #memory_int, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, P1Thread1of1ForFork1_#t~mem61, ~x$r_buff0_thd2~0, P1Thread1of1ForFork1_#t~ite65, P1Thread1of1ForFork1_#t~ite66, P1Thread1of1ForFork1_#t~ite67, ~x$w_buff0_used~0] under condition null [2021-01-26 22:48:13,165 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:13,177 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:13,286 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:13,376 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:18,785 WARN L146 IndependenceRelation]: Expensive independence query (2966 ms) for statements [1235] L855-1-->L856: Formula: (= |v_#memory_int_26| (store |v_#memory_int_27| |v_ULTIMATE.start_main_~#t1781~0.base_5| (store (select |v_#memory_int_27| |v_ULTIMATE.start_main_~#t1781~0.base_5|) |v_ULTIMATE.start_main_~#t1781~0.offset_5| 1))) InVars {#memory_int=|v_#memory_int_27|, ULTIMATE.start_main_~#t1781~0.base=|v_ULTIMATE.start_main_~#t1781~0.base_5|, ULTIMATE.start_main_~#t1781~0.offset=|v_ULTIMATE.start_main_~#t1781~0.offset_5|} OutVars{#memory_int=|v_#memory_int_26|, ULTIMATE.start_main_~#t1781~0.base=|v_ULTIMATE.start_main_~#t1781~0.base_5|, ULTIMATE.start_main_~#t1781~0.offset=|v_ULTIMATE.start_main_~#t1781~0.offset_5|} AuxVars[] AssignedVars[#memory_int] and [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] under condition null [2021-01-26 22:48:23,068 WARN L146 IndependenceRelation]: Expensive independence query (3983 ms) for statements [1357] L809-->L816: Formula: (let ((.cse4 (= (mod v_~x$w_buff0_used~0_502 256) 0)) (.cse5 (= (mod v_~x$r_buff1_thd2~0_258 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_422 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd2~0_292 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_503 256) 0))) (let ((.cse13 (not .cse16)) (.cse8 (or .cse14 .cse16)) (.cse9 (select |v_#memory_int_296| |v_~#x~0.base_186|)) (.cse12 (not .cse15)) (.cse7 (not .cse5)) (.cse1 (not .cse4)) (.cse2 (not .cse14)) (.cse10 (or .cse5 .cse15)) (.cse0 (or .cse14 .cse4))) (and (or (and (= v_~x$r_buff0_thd2~0_291 v_~x$r_buff0_thd2~0_292) .cse0) (and .cse1 (= v_~x$r_buff0_thd2~0_291 0) .cse2)) (let ((.cse6 (= (mod v_~x$w_buff1_used~0_421 256) 0)) (.cse3 (= (mod v_~x$r_buff0_thd2~0_291 256) 0))) (or (and (or .cse3 .cse4) (= v_~x$r_buff1_thd2~0_258 v_~x$r_buff1_thd2~0_257) (or .cse5 .cse6)) (and (= v_~x$r_buff1_thd2~0_257 0) (or (and (not .cse6) .cse7) (and .cse1 (not .cse3)))))) (let ((.cse11 (= |v_P1_#t~mem61_50| |v_P1Thread1of1ForFork1_#t~mem61_1|))) (or (and .cse8 (or (and (= |v_P1_#t~ite62_49| |v_P1_#t~mem61_50|) (= (select .cse9 |v_~#x~0.offset_186|) |v_P1_#t~mem61_50|) .cse10) (and (= |v_P1_#t~ite62_49| v_~x$w_buff1~0_126) .cse11 .cse12 .cse7)) (= |v_P1_#t~ite62_49| |v_P1_#t~ite63_43|)) (and .cse13 .cse11 (= |v_P1_#t~ite62_49| |v_P1Thread1of1ForFork1_#t~ite62_1|) .cse2 (= |v_P1_#t~ite63_43| v_~x$w_buff0~0_133)))) (or (and .cse13 (= v_~x$w_buff0_used~0_502 0) .cse2) (and (= v_~x$w_buff0_used~0_503 v_~x$w_buff0_used~0_502) .cse8)) (= (store |v_#memory_int_296| |v_~#x~0.base_186| (store .cse9 |v_~#x~0.offset_186| |v_P1_#t~ite63_43|)) |v_#memory_int_295|) (or (and (= v_~x$w_buff1_used~0_421 0) (or (and .cse12 .cse7) (and .cse1 .cse2))) (and .cse10 (= v_~x$w_buff1_used~0_422 v_~x$w_buff1_used~0_421) .cse0))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_133, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_1|, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, #memory_int=|v_#memory_int_296|, ~#x~0.base=|v_~#x~0.base_186|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_422, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_258, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_292, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_503} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_133, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_257, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_421, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_291, P1Thread1of1ForFork1_#t~ite65=|v_P1Thread1of1ForFork1_#t~ite65_1|, P1Thread1of1ForFork1_#t~ite66=|v_P1Thread1of1ForFork1_#t~ite66_1|, P1Thread1of1ForFork1_#t~ite67=|v_P1Thread1of1ForFork1_#t~ite67_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_502, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_2|, P1Thread1of1ForFork1_#t~ite63=|v_P1Thread1of1ForFork1_#t~ite63_1|, P1Thread1of1ForFork1_#t~ite64=|v_P1Thread1of1ForFork1_#t~ite64_1|, #memory_int=|v_#memory_int_295|, ~#x~0.base=|v_~#x~0.base_186|} AuxVars[|v_P1_#t~ite62_49|, |v_P1_#t~mem61_50|, |v_P1_#t~ite63_43|] AssignedVars[P1Thread1of1ForFork1_#t~ite62, P1Thread1of1ForFork1_#t~ite63, P1Thread1of1ForFork1_#t~ite64, #memory_int, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, P1Thread1of1ForFork1_#t~mem61, ~x$r_buff0_thd2~0, P1Thread1of1ForFork1_#t~ite65, P1Thread1of1ForFork1_#t~ite66, P1Thread1of1ForFork1_#t~ite67, ~x$w_buff0_used~0] and [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] under condition null [2021-01-26 22:48:25,567 WARN L146 IndependenceRelation]: Expensive independence query (2497 ms) for statements [1256] L857-1-->L858: Formula: (= |v_#memory_int_28| (store |v_#memory_int_29| |v_ULTIMATE.start_main_~#t1782~0.base_5| (store (select |v_#memory_int_29| |v_ULTIMATE.start_main_~#t1782~0.base_5|) |v_ULTIMATE.start_main_~#t1782~0.offset_5| 2))) InVars {#memory_int=|v_#memory_int_29|, ULTIMATE.start_main_~#t1782~0.base=|v_ULTIMATE.start_main_~#t1782~0.base_5|, ULTIMATE.start_main_~#t1782~0.offset=|v_ULTIMATE.start_main_~#t1782~0.offset_5|} OutVars{#memory_int=|v_#memory_int_28|, ULTIMATE.start_main_~#t1782~0.base=|v_ULTIMATE.start_main_~#t1782~0.base_5|, ULTIMATE.start_main_~#t1782~0.offset=|v_ULTIMATE.start_main_~#t1782~0.offset_5|} AuxVars[] AssignedVars[#memory_int] and [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] under condition null [2021-01-26 22:48:29,521 WARN L146 IndependenceRelation]: Expensive independence query (3951 ms) for statements [1364] L829-->L836: Formula: (let ((.cse5 (= (mod v_~x$w_buff0_used~0_416 256) 0)) (.cse4 (= (mod v_~x$r_buff1_thd3~0_56 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_332 256) 0)) (.cse14 (= 0 (mod v_~x$r_buff0_thd3~0_62 256))) (.cse16 (= (mod v_~x$w_buff0_used~0_417 256) 0))) (let ((.cse11 (not .cse16)) (.cse6 (or .cse14 .cse16)) (.cse8 (not .cse15)) (.cse3 (not .cse4)) (.cse9 (or .cse15 .cse4)) (.cse13 (or .cse14 .cse5)) (.cse0 (not .cse5)) (.cse12 (not .cse14)) (.cse10 (select |v_#memory_int_258| |v_~#x~0.base_162|))) (and (let ((.cse2 (= (mod v_~x$w_buff1_used~0_331 256) 0)) (.cse1 (= (mod v_~x$r_buff0_thd3~0_61 256) 0))) (or (and (= v_~x$r_buff1_thd3~0_55 0) (or (and .cse0 (not .cse1)) (and (not .cse2) .cse3))) (and (= v_~x$r_buff1_thd3~0_56 v_~x$r_buff1_thd3~0_55) (or .cse2 .cse4) (or .cse5 .cse1)))) (let ((.cse7 (= |v_P2_#t~mem68_38| |v_P2Thread1of1ForFork2_#t~mem68_1|))) (or (and (= |v_P2_#t~ite69_39| |v_P2_#t~ite70_33|) .cse6 (or (and .cse7 (= |v_P2_#t~ite69_39| v_~x$w_buff1~0_86) .cse3 .cse8) (and .cse9 (= |v_P2_#t~ite69_39| |v_P2_#t~mem68_38|) (= |v_P2_#t~mem68_38| (select .cse10 |v_~#x~0.offset_162|))))) (and (= |v_P2_#t~ite69_39| |v_P2Thread1of1ForFork2_#t~ite69_1|) .cse7 .cse11 (= |v_P2_#t~ite70_33| v_~x$w_buff0~0_115) .cse12))) (or (and .cse11 (= v_~x$w_buff0_used~0_416 0) .cse12) (and .cse6 (= v_~x$w_buff0_used~0_417 v_~x$w_buff0_used~0_416))) (or (and (= v_~x$w_buff1_used~0_331 0) (or (and .cse0 .cse12) (and .cse8 .cse3))) (and .cse9 .cse13 (= v_~x$w_buff1_used~0_332 v_~x$w_buff1_used~0_331))) (or (and .cse13 (= v_~x$r_buff0_thd3~0_62 v_~x$r_buff0_thd3~0_61)) (and .cse0 (= v_~x$r_buff0_thd3~0_61 0) .cse12)) (= (store |v_#memory_int_258| |v_~#x~0.base_162| (store .cse10 |v_~#x~0.offset_162| |v_P2_#t~ite70_33|)) |v_#memory_int_257|)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_115, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_1|, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_1|, #memory_int=|v_#memory_int_258|, ~#x~0.base=|v_~#x~0.base_162|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_56, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_332, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_62, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_417} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_115, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_2|, P2Thread1of1ForFork2_#t~ite73=|v_P2Thread1of1ForFork2_#t~ite73_1|, P2Thread1of1ForFork2_#t~ite72=|v_P2Thread1of1ForFork2_#t~ite72_1|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_55, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_331, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_1|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_61, P2Thread1of1ForFork2_#t~ite71=|v_P2Thread1of1ForFork2_#t~ite71_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_416, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_2|, P2Thread1of1ForFork2_#t~ite74=|v_P2Thread1of1ForFork2_#t~ite74_1|, #memory_int=|v_#memory_int_257|, ~#x~0.base=|v_~#x~0.base_162|} AuxVars[|v_P2_#t~ite70_33|, |v_P2_#t~mem68_38|, |v_P2_#t~ite69_39|] AssignedVars[P2Thread1of1ForFork2_#t~ite69, P2Thread1of1ForFork2_#t~mem68, P2Thread1of1ForFork2_#t~ite74, P2Thread1of1ForFork2_#t~ite73, P2Thread1of1ForFork2_#t~ite72, #memory_int, ~x$r_buff1_thd3~0, ~x$w_buff1_used~0, P2Thread1of1ForFork2_#t~ite70, ~x$r_buff0_thd3~0, P2Thread1of1ForFork2_#t~ite71, ~x$w_buff0_used~0] and [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] under condition null [2021-01-26 22:48:33,494 WARN L146 IndependenceRelation]: Expensive independence query (3970 ms) for statements [1340] L2-1-->L869: Formula: (let ((.cse13 (= (mod v_~x$w_buff0_used~0_454 256) 0)) (.cse12 (= (mod v_~x$r_buff1_thd0~0_64 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_374 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd0~0_68 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_455 256) 0))) (let ((.cse3 (not .cse16)) (.cse4 (or .cse16 .cse14)) (.cse7 (not .cse15)) (.cse1 (not .cse14)) (.cse8 (or .cse15 .cse12)) (.cse0 (or .cse13 .cse14)) (.cse9 (select |v_#memory_int_282| |v_~#x~0.base_178|)) (.cse2 (not .cse13)) (.cse6 (not .cse12))) (and (or (and .cse0 (= v_~x$r_buff0_thd0~0_68 v_~x$r_buff0_thd0~0_67)) (and .cse1 .cse2 (= v_~x$r_buff0_thd0~0_67 0))) (or (and (= v_~x$w_buff0_used~0_454 0) .cse1 .cse3) (and .cse4 (= v_~x$w_buff0_used~0_455 v_~x$w_buff0_used~0_454))) (let ((.cse5 (= |v_ULTIMATE.start_main_#t~mem78_23| |v_ULTIMATE.start_main_#t~mem78_27|))) (or (and .cse1 (= v_~x$w_buff0~0_125 |v_ULTIMATE.start_main_#t~ite80_32|) (= |v_ULTIMATE.start_main_#t~ite79_22| |v_ULTIMATE.start_main_#t~ite79_26|) .cse3 .cse5) (and (or (and .cse6 .cse7 .cse5 (= |v_ULTIMATE.start_main_#t~ite79_26| v_~x$w_buff1~0_98)) (and .cse8 (= |v_ULTIMATE.start_main_#t~mem78_27| (select .cse9 |v_~#x~0.offset_178|)) (= |v_ULTIMATE.start_main_#t~mem78_27| |v_ULTIMATE.start_main_#t~ite79_26|))) (= |v_ULTIMATE.start_main_#t~ite79_26| |v_ULTIMATE.start_main_#t~ite80_32|) .cse4))) (or (and (or (and .cse6 .cse7) (and .cse1 .cse2)) (= v_~x$w_buff1_used~0_373 0)) (and .cse8 .cse0 (= v_~x$w_buff1_used~0_374 v_~x$w_buff1_used~0_373))) (= (store |v_#memory_int_282| |v_~#x~0.base_178| (store .cse9 |v_~#x~0.offset_178| |v_ULTIMATE.start_main_#t~ite80_32|)) |v_#memory_int_281|) (let ((.cse11 (= (mod v_~x$w_buff1_used~0_373 256) 0)) (.cse10 (= (mod v_~x$r_buff0_thd0~0_67 256) 0))) (or (and (or (and .cse2 (not .cse10)) (and .cse6 (not .cse11))) (= v_~x$r_buff1_thd0~0_63 0)) (and (or .cse11 .cse12) (or .cse13 .cse10) (= v_~x$r_buff1_thd0~0_64 v_~x$r_buff1_thd0~0_63))))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_68, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_23|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, #memory_int=|v_#memory_int_282|, ~#x~0.base=|v_~#x~0.base_178|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_374, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_22|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_64, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_455} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_67, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_21|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_373, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_20|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_63, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_454, ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_26|, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_32|, ULTIMATE.start_main_#t~ite82=|v_ULTIMATE.start_main_#t~ite82_28|, ULTIMATE.start_main_#t~ite81=|v_ULTIMATE.start_main_#t~ite81_36|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_28|, #memory_int=|v_#memory_int_281|, ~#x~0.base=|v_~#x~0.base_178|} AuxVars[|v_ULTIMATE.start_main_#t~ite79_26|, |v_ULTIMATE.start_main_#t~ite80_32|, |v_ULTIMATE.start_main_#t~mem78_27|] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem78, ULTIMATE.start_main_#t~ite84, ULTIMATE.start_main_#t~ite83, ULTIMATE.start_main_#t~ite82, ULTIMATE.start_main_#t~ite81, ULTIMATE.start_main_#t~ite80, #memory_int, ~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite79, ~x$r_buff1_thd0~0, ~x$w_buff0_used~0] and [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] under condition null [2021-01-26 22:48:34,024 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:34,720 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:34,904 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:35,080 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:36,375 WARN L146 IndependenceRelation]: Expensive independence query (1209 ms) for statements [1340] L2-1-->L869: Formula: (let ((.cse13 (= (mod v_~x$w_buff0_used~0_454 256) 0)) (.cse12 (= (mod v_~x$r_buff1_thd0~0_64 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_374 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd0~0_68 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_455 256) 0))) (let ((.cse3 (not .cse16)) (.cse4 (or .cse16 .cse14)) (.cse7 (not .cse15)) (.cse1 (not .cse14)) (.cse8 (or .cse15 .cse12)) (.cse0 (or .cse13 .cse14)) (.cse9 (select |v_#memory_int_282| |v_~#x~0.base_178|)) (.cse2 (not .cse13)) (.cse6 (not .cse12))) (and (or (and .cse0 (= v_~x$r_buff0_thd0~0_68 v_~x$r_buff0_thd0~0_67)) (and .cse1 .cse2 (= v_~x$r_buff0_thd0~0_67 0))) (or (and (= v_~x$w_buff0_used~0_454 0) .cse1 .cse3) (and .cse4 (= v_~x$w_buff0_used~0_455 v_~x$w_buff0_used~0_454))) (let ((.cse5 (= |v_ULTIMATE.start_main_#t~mem78_23| |v_ULTIMATE.start_main_#t~mem78_27|))) (or (and .cse1 (= v_~x$w_buff0~0_125 |v_ULTIMATE.start_main_#t~ite80_32|) (= |v_ULTIMATE.start_main_#t~ite79_22| |v_ULTIMATE.start_main_#t~ite79_26|) .cse3 .cse5) (and (or (and .cse6 .cse7 .cse5 (= |v_ULTIMATE.start_main_#t~ite79_26| v_~x$w_buff1~0_98)) (and .cse8 (= |v_ULTIMATE.start_main_#t~mem78_27| (select .cse9 |v_~#x~0.offset_178|)) (= |v_ULTIMATE.start_main_#t~mem78_27| |v_ULTIMATE.start_main_#t~ite79_26|))) (= |v_ULTIMATE.start_main_#t~ite79_26| |v_ULTIMATE.start_main_#t~ite80_32|) .cse4))) (or (and (or (and .cse6 .cse7) (and .cse1 .cse2)) (= v_~x$w_buff1_used~0_373 0)) (and .cse8 .cse0 (= v_~x$w_buff1_used~0_374 v_~x$w_buff1_used~0_373))) (= (store |v_#memory_int_282| |v_~#x~0.base_178| (store .cse9 |v_~#x~0.offset_178| |v_ULTIMATE.start_main_#t~ite80_32|)) |v_#memory_int_281|) (let ((.cse11 (= (mod v_~x$w_buff1_used~0_373 256) 0)) (.cse10 (= (mod v_~x$r_buff0_thd0~0_67 256) 0))) (or (and (or (and .cse2 (not .cse10)) (and .cse6 (not .cse11))) (= v_~x$r_buff1_thd0~0_63 0)) (and (or .cse11 .cse12) (or .cse13 .cse10) (= v_~x$r_buff1_thd0~0_64 v_~x$r_buff1_thd0~0_63))))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_68, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_23|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, #memory_int=|v_#memory_int_282|, ~#x~0.base=|v_~#x~0.base_178|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_374, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_22|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_64, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_455} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_67, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_21|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_373, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_20|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_63, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_454, ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_26|, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_32|, ULTIMATE.start_main_#t~ite82=|v_ULTIMATE.start_main_#t~ite82_28|, ULTIMATE.start_main_#t~ite81=|v_ULTIMATE.start_main_#t~ite81_36|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_28|, #memory_int=|v_#memory_int_281|, ~#x~0.base=|v_~#x~0.base_178|} AuxVars[|v_ULTIMATE.start_main_#t~ite79_26|, |v_ULTIMATE.start_main_#t~ite80_32|, |v_ULTIMATE.start_main_#t~mem78_27|] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem78, ULTIMATE.start_main_#t~ite84, ULTIMATE.start_main_#t~ite83, ULTIMATE.start_main_#t~ite82, ULTIMATE.start_main_#t~ite81, ULTIMATE.start_main_#t~ite80, #memory_int, ~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite79, ~x$r_buff1_thd0~0, ~x$w_buff0_used~0] and [1349] L761-->L773: Formula: (and (= |v_P0Thread1of1ForFork0_reach_error_#t~nondet2.base_3| |v_P0Thread1of1ForFork0_reach_error_#t~nondet2.base_4|) (= v_~x$w_buff0_used~0_Out_3 1) (= (ite (not (and (not (= (mod v_~x$w_buff0_used~0_Out_3 256) 0)) (not (= (mod v_~x$w_buff1_used~0_Out_3 256) 0)))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_3|) (= v_~x$r_buff0_thd1~0_Out_1 1) (= v_~x$w_buff1~0_Out_3 v_~x$w_buff0~0_In_35) (= v_~x$r_buff1_thd2~0_Out_1 v_~x$r_buff0_thd2~0_In_79) (= |v_P0Thread1of1ForFork0_reach_error_#t~nondet2.offset_3| |v_P0Thread1of1ForFork0_reach_error_#t~nondet2.offset_4|) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_3 0)) (= v_~x$w_buff1_used~0_Out_3 v_~x$w_buff0_used~0_In_109) (= v_~x$r_buff1_thd1~0_Out_1 v_~x$r_buff0_thd1~0_In_11) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_3 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_3|) (= v_~x$r_buff0_thd3~0_In_11 v_~x$r_buff1_thd3~0_Out_1) (= v_~x$r_buff1_thd0~0_Out_1 v_~x$r_buff0_thd0~0_In_11) (= v_~x$w_buff0~0_Out_3 1)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_In_35, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_In_11, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_In_11, P0Thread1of1ForFork0_reach_error_#t~nondet2.offset=|v_P0Thread1of1ForFork0_reach_error_#t~nondet2.offset_3|, P0Thread1of1ForFork0_reach_error_#t~nondet2.base=|v_P0Thread1of1ForFork0_reach_error_#t~nondet2.base_3|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_In_11, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_In_79, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_In_109} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_Out_3, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_In_11, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_Out_1, ~x$w_buff1~0=v_~x$w_buff1~0_Out_3, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_Out_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_Out_1, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_Out_3, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_Out_1, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_In_11, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_In_79, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_Out_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_Out_3, P0Thread1of1ForFork0_reach_error_#t~nondet2.offset=|v_P0Thread1of1ForFork0_reach_error_#t~nondet2.offset_4|, P0Thread1of1ForFork0_reach_error_#t~nondet2.base=|v_P0Thread1of1ForFork0_reach_error_#t~nondet2.base_4|, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_3, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_3|} AuxVars[] AssignedVars[~x$w_buff0~0, ~x$r_buff0_thd1~0, ~x$w_buff1~0, ~x$r_buff1_thd3~0, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$r_buff1_thd0~0, ~x$w_buff0_used~0, P0Thread1of1ForFork0_reach_error_#t~nondet2.offset, P0Thread1of1ForFork0_reach_error_#t~nondet2.base, P0Thread1of1ForFork0___VERIFIER_assert_~expression, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression] under condition null [2021-01-26 22:48:38,963 WARN L146 IndependenceRelation]: Expensive independence query (2271 ms) for statements [1256] L857-1-->L858: Formula: (= |v_#memory_int_28| (store |v_#memory_int_29| |v_ULTIMATE.start_main_~#t1782~0.base_5| (store (select |v_#memory_int_29| |v_ULTIMATE.start_main_~#t1782~0.base_5|) |v_ULTIMATE.start_main_~#t1782~0.offset_5| 2))) InVars {#memory_int=|v_#memory_int_29|, ULTIMATE.start_main_~#t1782~0.base=|v_ULTIMATE.start_main_~#t1782~0.base_5|, ULTIMATE.start_main_~#t1782~0.offset=|v_ULTIMATE.start_main_~#t1782~0.offset_5|} OutVars{#memory_int=|v_#memory_int_28|, ULTIMATE.start_main_~#t1782~0.base=|v_ULTIMATE.start_main_~#t1782~0.base_5|, ULTIMATE.start_main_~#t1782~0.offset=|v_ULTIMATE.start_main_~#t1782~0.offset_5|} AuxVars[] AssignedVars[#memory_int] and [1357] L809-->L816: Formula: (let ((.cse4 (= (mod v_~x$w_buff0_used~0_502 256) 0)) (.cse5 (= (mod v_~x$r_buff1_thd2~0_258 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_422 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd2~0_292 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_503 256) 0))) (let ((.cse13 (not .cse16)) (.cse8 (or .cse14 .cse16)) (.cse9 (select |v_#memory_int_296| |v_~#x~0.base_186|)) (.cse12 (not .cse15)) (.cse7 (not .cse5)) (.cse1 (not .cse4)) (.cse2 (not .cse14)) (.cse10 (or .cse5 .cse15)) (.cse0 (or .cse14 .cse4))) (and (or (and (= v_~x$r_buff0_thd2~0_291 v_~x$r_buff0_thd2~0_292) .cse0) (and .cse1 (= v_~x$r_buff0_thd2~0_291 0) .cse2)) (let ((.cse6 (= (mod v_~x$w_buff1_used~0_421 256) 0)) (.cse3 (= (mod v_~x$r_buff0_thd2~0_291 256) 0))) (or (and (or .cse3 .cse4) (= v_~x$r_buff1_thd2~0_258 v_~x$r_buff1_thd2~0_257) (or .cse5 .cse6)) (and (= v_~x$r_buff1_thd2~0_257 0) (or (and (not .cse6) .cse7) (and .cse1 (not .cse3)))))) (let ((.cse11 (= |v_P1_#t~mem61_50| |v_P1Thread1of1ForFork1_#t~mem61_1|))) (or (and .cse8 (or (and (= |v_P1_#t~ite62_49| |v_P1_#t~mem61_50|) (= (select .cse9 |v_~#x~0.offset_186|) |v_P1_#t~mem61_50|) .cse10) (and (= |v_P1_#t~ite62_49| v_~x$w_buff1~0_126) .cse11 .cse12 .cse7)) (= |v_P1_#t~ite62_49| |v_P1_#t~ite63_43|)) (and .cse13 .cse11 (= |v_P1_#t~ite62_49| |v_P1Thread1of1ForFork1_#t~ite62_1|) .cse2 (= |v_P1_#t~ite63_43| v_~x$w_buff0~0_133)))) (or (and .cse13 (= v_~x$w_buff0_used~0_502 0) .cse2) (and (= v_~x$w_buff0_used~0_503 v_~x$w_buff0_used~0_502) .cse8)) (= (store |v_#memory_int_296| |v_~#x~0.base_186| (store .cse9 |v_~#x~0.offset_186| |v_P1_#t~ite63_43|)) |v_#memory_int_295|) (or (and (= v_~x$w_buff1_used~0_421 0) (or (and .cse12 .cse7) (and .cse1 .cse2))) (and .cse10 (= v_~x$w_buff1_used~0_422 v_~x$w_buff1_used~0_421) .cse0))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_133, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_1|, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, #memory_int=|v_#memory_int_296|, ~#x~0.base=|v_~#x~0.base_186|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_422, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_258, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_292, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_503} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_133, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_257, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_421, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_291, P1Thread1of1ForFork1_#t~ite65=|v_P1Thread1of1ForFork1_#t~ite65_1|, P1Thread1of1ForFork1_#t~ite66=|v_P1Thread1of1ForFork1_#t~ite66_1|, P1Thread1of1ForFork1_#t~ite67=|v_P1Thread1of1ForFork1_#t~ite67_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_502, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_2|, P1Thread1of1ForFork1_#t~ite63=|v_P1Thread1of1ForFork1_#t~ite63_1|, P1Thread1of1ForFork1_#t~ite64=|v_P1Thread1of1ForFork1_#t~ite64_1|, #memory_int=|v_#memory_int_295|, ~#x~0.base=|v_~#x~0.base_186|} AuxVars[|v_P1_#t~ite62_49|, |v_P1_#t~mem61_50|, |v_P1_#t~ite63_43|] AssignedVars[P1Thread1of1ForFork1_#t~ite62, P1Thread1of1ForFork1_#t~ite63, P1Thread1of1ForFork1_#t~ite64, #memory_int, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, P1Thread1of1ForFork1_#t~mem61, ~x$r_buff0_thd2~0, P1Thread1of1ForFork1_#t~ite65, P1Thread1of1ForFork1_#t~ite66, P1Thread1of1ForFork1_#t~ite67, ~x$w_buff0_used~0] under condition 261#(= ~x$w_buff0_used~0 0) Size of Word is: 100 and size of Sequence is : 101[2021-01-26 22:48:40,149 INFO L164 SleepSetCegar]: Size of mCounterexample is: 101 [2021-01-26 22:48:40,150 INFO L165 SleepSetCegar]: [591#[ULTIMATE.startENTRY]true, 593#[L-1]true, 595#[L-1-1]true, 597#[L17]true, 599#[L17-1]true, 601#[L17-2]true, 603#[L17-3]true, 605#[L17-4]true, 607#[L711]true, 609#[L713](= ~__unbuffered_p0_EAX~0 0), 611#[L714](= ~__unbuffered_p0_EAX~0 0), 613#[L715](= ~__unbuffered_p0_EAX~0 0), 615#[L716](= ~__unbuffered_p0_EAX~0 0), 617#[L717](= ~__unbuffered_p0_EAX~0 0), 619#[L718](= ~__unbuffered_p0_EAX~0 0), 621#[L719](= ~__unbuffered_p0_EAX~0 0), 623#[L720](= ~__unbuffered_p0_EAX~0 0), 625#[L721](= ~__unbuffered_p0_EAX~0 0), 627#[L722](= ~__unbuffered_p0_EAX~0 0), 629#[L723](= ~__unbuffered_p0_EAX~0 0), 631#[L724](= ~__unbuffered_p0_EAX~0 0), 633#[L725](= ~__unbuffered_p0_EAX~0 0), 635#[L726](= ~__unbuffered_p0_EAX~0 0), 637#[L727](= ~__unbuffered_p0_EAX~0 0), 639#[L728](= ~__unbuffered_p0_EAX~0 0), 641#[L729](= ~__unbuffered_p0_EAX~0 0), 643#[L731](= ~__unbuffered_p0_EAX~0 0), 645#[L732](= ~__unbuffered_p0_EAX~0 0), 647#[L733](= ~__unbuffered_p0_EAX~0 0), 649#[L735](= ~__unbuffered_p0_EAX~0 0), 651#[L735-1](= ~__unbuffered_p0_EAX~0 0), 653#[L735-2](= ~__unbuffered_p0_EAX~0 0), 655#[L737](= ~__unbuffered_p0_EAX~0 0), 657#[L738](= ~__unbuffered_p0_EAX~0 0), 659#[L739](= ~__unbuffered_p0_EAX~0 0), 661#[L740](= ~__unbuffered_p0_EAX~0 0), 663#[L741](= ~__unbuffered_p0_EAX~0 0), 665#[L742](= ~__unbuffered_p0_EAX~0 0), 667#[L743](= ~__unbuffered_p0_EAX~0 0), 669#[L744](= ~__unbuffered_p0_EAX~0 0), 671#[L745](= ~__unbuffered_p0_EAX~0 0), 673#[L746](= ~__unbuffered_p0_EAX~0 0), 675#[L747](= ~__unbuffered_p0_EAX~0 0), 677#[L748](= ~__unbuffered_p0_EAX~0 0), 679#[L749](= ~__unbuffered_p0_EAX~0 0), 681#[L750](and (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 683#[L751](and (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 685#[L753](and (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 689#[L754](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 691#[L755](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 693#[L756](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 695#[L-1-2](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 697#[L-1-3](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 699#[L853](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 701#[L853-1](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 703#[L854](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 705#[P0ENTRY, L854-1](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 707#[L854-1, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 711#[L855, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56326#[L855-1, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56331#[L856, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56336#[L856-1, P1ENTRY, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56346#[P1ENTRY, L759, L857](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56354#[L759, L857, L788](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56366#[L806, L759, L857](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56376#[L759, L809, L857](and (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56386#[L761, L809, L857](= ~x$w_buff0_used~0 0), 56396#[L773, L809, L857]true, 56400#[L780, L809, L857]true, 56406#[L783, L809, L857]true, 56414#[L809, L857, P0FINAL]true, 56416#[L809, P0EXIT, L857]true, 56422#[L816, P0EXIT, L857]true, 56426#[L819, P0EXIT, L857]true, 56430#[P1FINAL, P0EXIT, L857]true, 56434#[P1EXIT, P0EXIT, L857]true, 56438#[L857-1, P1EXIT, P0EXIT]true, 56440#[P1EXIT, L858, P0EXIT]true, 56442#[P1EXIT, L858-1, P0EXIT, P2ENTRY]true, 56444#[P1EXIT, P0EXIT, L859, P2ENTRY]true, 56448#[P1EXIT, L861, P0EXIT, P2ENTRY]true, 56452#[P1EXIT, L862, P0EXIT, P2ENTRY]true, 56456#[P1EXIT, L2, P0EXIT, P2ENTRY]true, 56460#[P1EXIT, P0EXIT, P2ENTRY, L3]true, 56466#[P1EXIT, L2-1, P0EXIT, P2ENTRY]true, 56484#[P1EXIT, L869, P0EXIT, P2ENTRY]true, 56488#[P1EXIT, L874, P0EXIT, P2ENTRY]true, 56494#[L824, P1EXIT, L874, P0EXIT]true, 56498#[P1EXIT, L826, L874, P0EXIT]true, 56502#[P1EXIT, L874, L829, P0EXIT]true, 56506#[L836, P1EXIT, L874, P0EXIT]true, 56510#[P1EXIT, L839, L874, P0EXIT]true, 56512#[P1EXIT, L874, P2FINAL, P0EXIT]true, 56518#[P2EXIT, P1EXIT, L874, P0EXIT]true, 56520#[P2EXIT, L875, P1EXIT, P0EXIT]true, 56522#[P2EXIT, P1EXIT, L18, P0EXIT]true, 56524#[P2EXIT, L18-1, P1EXIT, P0EXIT]true, 56526#[P2EXIT, L18-2, P1EXIT, P0EXIT]true, 56530#[P2EXIT, P1EXIT, L17-5, P0EXIT]true, 56532#[P2EXIT, L17-7, P1EXIT, P0EXIT]true, 56536#[P2EXIT, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1EXIT, P0EXIT]true] [2021-01-26 22:48:40,150 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-01-26 22:48:40,150 INFO L429 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 22:48:40,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 22:48:40,151 INFO L82 PathProgramCache]: Analyzing trace with hash -1574428725, now seen corresponding path program 2 times [2021-01-26 22:48:40,152 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 22:48:40,152 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682965123] [2021-01-26 22:48:40,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 22:48:40,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 22:48:40,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 22:48:40,624 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1682965123] [2021-01-26 22:48:40,624 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 22:48:40,624 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2021-01-26 22:48:40,625 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [862673160] [2021-01-26 22:48:40,628 INFO L461 AbstractCegarLoop]: Interpolant automaton has 6 states [2021-01-26 22:48:40,628 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 22:48:40,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-01-26 22:48:40,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2021-01-26 22:48:40,629 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 22:48:40,630 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 6 states, 6 states have (on average 16.666666666666668) internal successors, (100), 6 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 22:48:40,894 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:41,102 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:43,669 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check Size of Word is: 100 and size of Sequence is : 101[2021-01-26 22:48:43,731 INFO L164 SleepSetCegar]: Size of mCounterexample is: 101 [2021-01-26 22:48:43,732 INFO L165 SleepSetCegar]: [56546#[ULTIMATE.startENTRY]true, 56548#[L-1]true, 56550#[L-1-1]true, 56552#[L17]true, 56554#[L17-1]true, 56556#[L17-2]true, 56558#[L17-3]true, 56560#[L17-4]true, 56562#[L711]true, 56564#[L713](= ~__unbuffered_p0_EAX~0 0), 56566#[L714](= ~__unbuffered_p0_EAX~0 0), 56568#[L715](= ~__unbuffered_p0_EAX~0 0), 56570#[L716](= ~__unbuffered_p0_EAX~0 0), 56572#[L717](= ~__unbuffered_p0_EAX~0 0), 56574#[L718](= ~__unbuffered_p0_EAX~0 0), 56576#[L719](= ~__unbuffered_p0_EAX~0 0), 56578#[L720](= ~__unbuffered_p0_EAX~0 0), 56580#[L721](= ~__unbuffered_p0_EAX~0 0), 56582#[L722](= ~__unbuffered_p0_EAX~0 0), 56584#[L723](= ~__unbuffered_p0_EAX~0 0), 56586#[L724](= ~__unbuffered_p0_EAX~0 0), 56588#[L725](= ~__unbuffered_p0_EAX~0 0), 56590#[L726](= ~__unbuffered_p0_EAX~0 0), 56592#[L727](= ~__unbuffered_p0_EAX~0 0), 56594#[L728](= ~__unbuffered_p0_EAX~0 0), 56596#[L729](= ~__unbuffered_p0_EAX~0 0), 56598#[L731](= ~__unbuffered_p0_EAX~0 0), 56600#[L732](= ~__unbuffered_p0_EAX~0 0), 56602#[L733](= ~__unbuffered_p0_EAX~0 0), 56604#[L735](= ~__unbuffered_p0_EAX~0 0), 56606#[L735-1](= ~__unbuffered_p0_EAX~0 0), 56608#[L735-2](= ~__unbuffered_p0_EAX~0 0), 56610#[L737](= ~__unbuffered_p0_EAX~0 0), 56612#[L738](= ~__unbuffered_p0_EAX~0 0), 56614#[L739](= ~__unbuffered_p0_EAX~0 0), 56616#[L740](= ~__unbuffered_p0_EAX~0 0), 56618#[L741](= ~__unbuffered_p0_EAX~0 0), 56620#[L742](= ~__unbuffered_p0_EAX~0 0), 56622#[L743](= ~__unbuffered_p0_EAX~0 0), 56624#[L744](= ~__unbuffered_p0_EAX~0 0), 56626#[L745](= ~__unbuffered_p0_EAX~0 0), 56628#[L746](= ~__unbuffered_p0_EAX~0 0), 56630#[L747](= ~__unbuffered_p0_EAX~0 0), 56632#[L748](= ~__unbuffered_p0_EAX~0 0), 56634#[L749](= ~__unbuffered_p0_EAX~0 0), 56636#[L750](and (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56638#[L751](and (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56640#[L753](and (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56642#[L754](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56644#[L755](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56646#[L756](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56648#[L-1-2](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56650#[L-1-3](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56652#[L853](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56654#[L853-1](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56656#[L854](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56658#[P0ENTRY, L854-1](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56660#[L854-1, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 56664#[L855, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 100710#[L855-1, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 100712#[L856, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 100714#[L856-1, P1ENTRY, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 100718#[P1ENTRY, L759, L857](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 100720#[L759, L857, L788](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 100726#[L806, L759, L857](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 100730#[L759, L809, L857](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 100734#[L761, L809, L857](and (= ~y~0 1) (= ~x$w_buff0_used~0 0)), 100744#[L773, L809, L857](= ~y~0 1), 100748#[L780, L809, L857](= ~y~0 1), 100754#[L783, L809, L857](= ~y~0 1), 100762#[L809, L857, P0FINAL](= ~y~0 1), 100764#[L809, P0EXIT, L857](= ~y~0 1), 100770#[L816, P0EXIT, L857](= ~y~0 1), 100774#[L819, P0EXIT, L857](= ~y~0 1), 100778#[P1FINAL, P0EXIT, L857](= ~y~0 1), 100782#[P1EXIT, P0EXIT, L857](= ~y~0 1), 100786#[L857-1, P1EXIT, P0EXIT](= ~y~0 1), 100788#[P1EXIT, L858, P0EXIT](= ~y~0 1), 100790#[P1EXIT, L858-1, P0EXIT, P2ENTRY](= ~y~0 1), 100792#[P1EXIT, P0EXIT, L859, P2ENTRY](= ~y~0 1), 100796#[P1EXIT, L861, P0EXIT, P2ENTRY](= ~y~0 1), 100800#[P1EXIT, L862, P0EXIT, P2ENTRY](= ~y~0 1), 100804#[P1EXIT, L2, P0EXIT, P2ENTRY](= ~y~0 1), 100808#[P1EXIT, P0EXIT, P2ENTRY, L3](= ~y~0 1), 100814#[P1EXIT, L2-1, P0EXIT, P2ENTRY](= ~y~0 1), 100832#[P1EXIT, L869, P0EXIT, P2ENTRY](= ~y~0 1), 100838#[L824, P1EXIT, L869, P0EXIT](= ~y~0 1), 101280#[P1EXIT, L826, L869, P0EXIT](= ~y~0 1), 101284#[P1EXIT, L869, L829, P0EXIT]true, 101288#[P1EXIT, L874, L829, P0EXIT]true, 101294#[L836, P1EXIT, L874, P0EXIT]true, 101298#[P1EXIT, L839, L874, P0EXIT]true, 101300#[P1EXIT, L874, P2FINAL, P0EXIT]true, 101306#[P2EXIT, P1EXIT, L874, P0EXIT]true, 101308#[P2EXIT, L875, P1EXIT, P0EXIT]true, 101310#[P2EXIT, P1EXIT, L18, P0EXIT]true, 101312#[P2EXIT, L18-1, P1EXIT, P0EXIT]true, 101314#[P2EXIT, L18-2, P1EXIT, P0EXIT]true, 101318#[P2EXIT, P1EXIT, L17-5, P0EXIT]true, 101320#[P2EXIT, L17-7, P1EXIT, P0EXIT]true, 101324#[P2EXIT, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1EXIT, P0EXIT]true] [2021-01-26 22:48:43,732 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2021-01-26 22:48:43,732 INFO L429 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 22:48:43,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 22:48:43,733 INFO L82 PathProgramCache]: Analyzing trace with hash 2084520435, now seen corresponding path program 3 times [2021-01-26 22:48:43,733 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 22:48:43,734 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50595827] [2021-01-26 22:48:43,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 22:48:43,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 22:48:44,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 22:48:44,072 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [50595827] [2021-01-26 22:48:44,072 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 22:48:44,072 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2021-01-26 22:48:44,073 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1364780933] [2021-01-26 22:48:44,073 INFO L461 AbstractCegarLoop]: Interpolant automaton has 7 states [2021-01-26 22:48:44,076 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 22:48:44,078 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-01-26 22:48:44,079 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2021-01-26 22:48:44,079 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 22:48:44,079 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 22:48:46,133 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:46,167 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:47,537 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check Size of Word is: 100 and size of Sequence is : 101[2021-01-26 22:48:47,690 INFO L164 SleepSetCegar]: Size of mCounterexample is: 101 [2021-01-26 22:48:47,691 INFO L165 SleepSetCegar]: [101335#[ULTIMATE.startENTRY]true, 101337#[L-1]true, 101339#[L-1-1]true, 101341#[L17]true, 101343#[L17-1]true, 101345#[L17-2]true, 101347#[L17-3]true, 101349#[L17-4]true, 101351#[L711]true, 101353#[L713](= ~__unbuffered_p0_EAX~0 0), 101355#[L714](= ~__unbuffered_p0_EAX~0 0), 101357#[L715](= ~__unbuffered_p0_EAX~0 0), 101359#[L716](= ~__unbuffered_p0_EAX~0 0), 101361#[L717](= ~__unbuffered_p0_EAX~0 0), 101363#[L718](= ~__unbuffered_p0_EAX~0 0), 101365#[L719](= ~__unbuffered_p0_EAX~0 0), 101367#[L720](= ~__unbuffered_p0_EAX~0 0), 101369#[L721](= ~__unbuffered_p0_EAX~0 0), 101371#[L722](= ~__unbuffered_p0_EAX~0 0), 101373#[L723](= ~__unbuffered_p0_EAX~0 0), 101375#[L724](= ~__unbuffered_p0_EAX~0 0), 101377#[L725](= ~__unbuffered_p0_EAX~0 0), 101379#[L726](= ~__unbuffered_p0_EAX~0 0), 101381#[L727](= ~__unbuffered_p0_EAX~0 0), 101383#[L728](= ~__unbuffered_p0_EAX~0 0), 101385#[L729](= ~__unbuffered_p0_EAX~0 0), 101387#[L731](= ~__unbuffered_p0_EAX~0 0), 101389#[L732](= ~__unbuffered_p0_EAX~0 0), 101391#[L733](= ~__unbuffered_p0_EAX~0 0), 101393#[L735](= ~__unbuffered_p0_EAX~0 0), 101395#[L735-1](= ~__unbuffered_p0_EAX~0 0), 101397#[L735-2](= ~__unbuffered_p0_EAX~0 0), 101399#[L737](= ~__unbuffered_p0_EAX~0 0), 101401#[L738](= ~__unbuffered_p0_EAX~0 0), 101403#[L739](= ~__unbuffered_p0_EAX~0 0), 101405#[L740](= ~__unbuffered_p0_EAX~0 0), 101407#[L741](= ~__unbuffered_p0_EAX~0 0), 101409#[L742](= ~__unbuffered_p0_EAX~0 0), 101411#[L743](= ~__unbuffered_p0_EAX~0 0), 101413#[L744](= ~__unbuffered_p0_EAX~0 0), 101415#[L745](= ~__unbuffered_p0_EAX~0 0), 101417#[L746](= ~__unbuffered_p0_EAX~0 0), 101419#[L747](= ~__unbuffered_p0_EAX~0 0), 101421#[L748](= ~__unbuffered_p0_EAX~0 0), 101423#[L749](= ~__unbuffered_p0_EAX~0 0), 101425#[L750](and (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101427#[L751](and (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101429#[L753](and (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101431#[L754](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101433#[L755](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101435#[L756](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101437#[L-1-2](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101439#[L-1-3](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101441#[L853](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101443#[L853-1](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101445#[L854](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101447#[P0ENTRY, L854-1](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101449#[L854-1, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 101453#[L855, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 145499#[L855-1, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 145501#[L856, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 145503#[L856-1, P1ENTRY, L759](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 145507#[P1ENTRY, L759, L857](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 145509#[L759, L857, L788](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 145515#[L806, L759, L857](and (= ~y~0 0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 145519#[L759, L809, L857](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 145521#[L816, L759, L857](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 193981#[L819, L759, L857](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 193999#[L759, P1FINAL, L857](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 194017#[P1EXIT, L759, L857](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 194028#[L857-1, P1EXIT, L759](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 194037#[P1EXIT, L759, L858](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 194046#[P1EXIT, L858-1, L759, P2ENTRY](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 194062#[P1EXIT, L759, L859, P2ENTRY](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 194080#[P1EXIT, L861, L759, P2ENTRY](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 194098#[P1EXIT, L862, L759, P2ENTRY](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 194116#[P1EXIT, L2, L759, P2ENTRY](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 194134#[P1EXIT, L759, P2ENTRY, L3](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 194161#[P1EXIT, L2-1, L759, P2ENTRY](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 194380#[P1EXIT, L759, L869, P2ENTRY](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 194400#[L824, P1EXIT, L759, L869](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 198676#[P1EXIT, L826, L759, L869](and (= ~y~0 1) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 198685#[P1EXIT, L759, L869, L829](and (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 198698#[L761, P1EXIT, L869, L829](= ~x$w_buff0_used~0 0), 198704#[L761, P1EXIT, L874, L829](= ~x$w_buff0_used~0 0), 198718#[L773, P1EXIT, L874, L829]true, 198726#[P1EXIT, L874, L829, L780]true, 198734#[L783, P1EXIT, L874, L829]true, 198744#[P1EXIT, L874, L829, P0FINAL]true, 198750#[P1EXIT, L874, L829, P0EXIT]true, 198756#[L836, P1EXIT, L874, P0EXIT]true, 198760#[P1EXIT, L839, L874, P0EXIT]true, 198762#[P1EXIT, L874, P2FINAL, P0EXIT]true, 198768#[P2EXIT, P1EXIT, L874, P0EXIT]true, 198770#[P2EXIT, L875, P1EXIT, P0EXIT]true, 198772#[P2EXIT, P1EXIT, L18, P0EXIT]true, 198774#[P2EXIT, L18-1, P1EXIT, P0EXIT]true, 198776#[P2EXIT, L18-2, P1EXIT, P0EXIT]true, 198780#[P2EXIT, P1EXIT, L17-5, P0EXIT]true, 198782#[P2EXIT, L17-7, P1EXIT, P0EXIT]true, 198786#[P2EXIT, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1EXIT, P0EXIT]true] [2021-01-26 22:48:47,691 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2021-01-26 22:48:47,692 INFO L429 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 22:48:47,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 22:48:47,692 INFO L82 PathProgramCache]: Analyzing trace with hash 1481152777, now seen corresponding path program 4 times [2021-01-26 22:48:47,692 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 22:48:47,693 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889536596] [2021-01-26 22:48:47,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 22:48:47,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 22:48:48,621 WARN L193 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 29 [2021-01-26 22:48:49,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 22:48:49,044 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889536596] [2021-01-26 22:48:49,044 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 22:48:49,045 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2021-01-26 22:48:49,045 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [538214091] [2021-01-26 22:48:49,045 INFO L461 AbstractCegarLoop]: Interpolant automaton has 21 states [2021-01-26 22:48:49,046 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 22:48:49,046 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-01-26 22:48:49,047 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=86, Invalid=334, Unknown=0, NotChecked=0, Total=420 [2021-01-26 22:48:49,047 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 22:48:49,048 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 21 states, 21 states have (on average 4.761904761904762) internal successors, (100), 21 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 22:48:49,159 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:49,425 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:48:53,530 WARN L146 IndependenceRelation]: Expensive independence query (4013 ms) for statements [1364] L829-->L836: Formula: (let ((.cse5 (= (mod v_~x$w_buff0_used~0_416 256) 0)) (.cse4 (= (mod v_~x$r_buff1_thd3~0_56 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_332 256) 0)) (.cse14 (= 0 (mod v_~x$r_buff0_thd3~0_62 256))) (.cse16 (= (mod v_~x$w_buff0_used~0_417 256) 0))) (let ((.cse11 (not .cse16)) (.cse6 (or .cse14 .cse16)) (.cse8 (not .cse15)) (.cse3 (not .cse4)) (.cse9 (or .cse15 .cse4)) (.cse13 (or .cse14 .cse5)) (.cse0 (not .cse5)) (.cse12 (not .cse14)) (.cse10 (select |v_#memory_int_258| |v_~#x~0.base_162|))) (and (let ((.cse2 (= (mod v_~x$w_buff1_used~0_331 256) 0)) (.cse1 (= (mod v_~x$r_buff0_thd3~0_61 256) 0))) (or (and (= v_~x$r_buff1_thd3~0_55 0) (or (and .cse0 (not .cse1)) (and (not .cse2) .cse3))) (and (= v_~x$r_buff1_thd3~0_56 v_~x$r_buff1_thd3~0_55) (or .cse2 .cse4) (or .cse5 .cse1)))) (let ((.cse7 (= |v_P2_#t~mem68_38| |v_P2Thread1of1ForFork2_#t~mem68_1|))) (or (and (= |v_P2_#t~ite69_39| |v_P2_#t~ite70_33|) .cse6 (or (and .cse7 (= |v_P2_#t~ite69_39| v_~x$w_buff1~0_86) .cse3 .cse8) (and .cse9 (= |v_P2_#t~ite69_39| |v_P2_#t~mem68_38|) (= |v_P2_#t~mem68_38| (select .cse10 |v_~#x~0.offset_162|))))) (and (= |v_P2_#t~ite69_39| |v_P2Thread1of1ForFork2_#t~ite69_1|) .cse7 .cse11 (= |v_P2_#t~ite70_33| v_~x$w_buff0~0_115) .cse12))) (or (and .cse11 (= v_~x$w_buff0_used~0_416 0) .cse12) (and .cse6 (= v_~x$w_buff0_used~0_417 v_~x$w_buff0_used~0_416))) (or (and (= v_~x$w_buff1_used~0_331 0) (or (and .cse0 .cse12) (and .cse8 .cse3))) (and .cse9 .cse13 (= v_~x$w_buff1_used~0_332 v_~x$w_buff1_used~0_331))) (or (and .cse13 (= v_~x$r_buff0_thd3~0_62 v_~x$r_buff0_thd3~0_61)) (and .cse0 (= v_~x$r_buff0_thd3~0_61 0) .cse12)) (= (store |v_#memory_int_258| |v_~#x~0.base_162| (store .cse10 |v_~#x~0.offset_162| |v_P2_#t~ite70_33|)) |v_#memory_int_257|)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_115, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_1|, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_1|, #memory_int=|v_#memory_int_258|, ~#x~0.base=|v_~#x~0.base_162|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_56, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_332, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_62, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_417} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_115, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_2|, P2Thread1of1ForFork2_#t~ite73=|v_P2Thread1of1ForFork2_#t~ite73_1|, P2Thread1of1ForFork2_#t~ite72=|v_P2Thread1of1ForFork2_#t~ite72_1|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_55, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_331, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_1|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_61, P2Thread1of1ForFork2_#t~ite71=|v_P2Thread1of1ForFork2_#t~ite71_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_416, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_2|, P2Thread1of1ForFork2_#t~ite74=|v_P2Thread1of1ForFork2_#t~ite74_1|, #memory_int=|v_#memory_int_257|, ~#x~0.base=|v_~#x~0.base_162|} AuxVars[|v_P2_#t~ite70_33|, |v_P2_#t~mem68_38|, |v_P2_#t~ite69_39|] AssignedVars[P2Thread1of1ForFork2_#t~ite69, P2Thread1of1ForFork2_#t~mem68, P2Thread1of1ForFork2_#t~ite74, P2Thread1of1ForFork2_#t~ite73, P2Thread1of1ForFork2_#t~ite72, #memory_int, ~x$r_buff1_thd3~0, ~x$w_buff1_used~0, P2Thread1of1ForFork2_#t~ite70, ~x$r_buff0_thd3~0, P2Thread1of1ForFork2_#t~ite71, ~x$w_buff0_used~0] and [1340] L2-1-->L869: Formula: (let ((.cse13 (= (mod v_~x$w_buff0_used~0_454 256) 0)) (.cse12 (= (mod v_~x$r_buff1_thd0~0_64 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_374 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd0~0_68 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_455 256) 0))) (let ((.cse3 (not .cse16)) (.cse4 (or .cse16 .cse14)) (.cse7 (not .cse15)) (.cse1 (not .cse14)) (.cse8 (or .cse15 .cse12)) (.cse0 (or .cse13 .cse14)) (.cse9 (select |v_#memory_int_282| |v_~#x~0.base_178|)) (.cse2 (not .cse13)) (.cse6 (not .cse12))) (and (or (and .cse0 (= v_~x$r_buff0_thd0~0_68 v_~x$r_buff0_thd0~0_67)) (and .cse1 .cse2 (= v_~x$r_buff0_thd0~0_67 0))) (or (and (= v_~x$w_buff0_used~0_454 0) .cse1 .cse3) (and .cse4 (= v_~x$w_buff0_used~0_455 v_~x$w_buff0_used~0_454))) (let ((.cse5 (= |v_ULTIMATE.start_main_#t~mem78_23| |v_ULTIMATE.start_main_#t~mem78_27|))) (or (and .cse1 (= v_~x$w_buff0~0_125 |v_ULTIMATE.start_main_#t~ite80_32|) (= |v_ULTIMATE.start_main_#t~ite79_22| |v_ULTIMATE.start_main_#t~ite79_26|) .cse3 .cse5) (and (or (and .cse6 .cse7 .cse5 (= |v_ULTIMATE.start_main_#t~ite79_26| v_~x$w_buff1~0_98)) (and .cse8 (= |v_ULTIMATE.start_main_#t~mem78_27| (select .cse9 |v_~#x~0.offset_178|)) (= |v_ULTIMATE.start_main_#t~mem78_27| |v_ULTIMATE.start_main_#t~ite79_26|))) (= |v_ULTIMATE.start_main_#t~ite79_26| |v_ULTIMATE.start_main_#t~ite80_32|) .cse4))) (or (and (or (and .cse6 .cse7) (and .cse1 .cse2)) (= v_~x$w_buff1_used~0_373 0)) (and .cse8 .cse0 (= v_~x$w_buff1_used~0_374 v_~x$w_buff1_used~0_373))) (= (store |v_#memory_int_282| |v_~#x~0.base_178| (store .cse9 |v_~#x~0.offset_178| |v_ULTIMATE.start_main_#t~ite80_32|)) |v_#memory_int_281|) (let ((.cse11 (= (mod v_~x$w_buff1_used~0_373 256) 0)) (.cse10 (= (mod v_~x$r_buff0_thd0~0_67 256) 0))) (or (and (or (and .cse2 (not .cse10)) (and .cse6 (not .cse11))) (= v_~x$r_buff1_thd0~0_63 0)) (and (or .cse11 .cse12) (or .cse13 .cse10) (= v_~x$r_buff1_thd0~0_64 v_~x$r_buff1_thd0~0_63))))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_68, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_23|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, #memory_int=|v_#memory_int_282|, ~#x~0.base=|v_~#x~0.base_178|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_374, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_22|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_64, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_455} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_67, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_21|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_373, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_20|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_63, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_454, ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_26|, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_32|, ULTIMATE.start_main_#t~ite82=|v_ULTIMATE.start_main_#t~ite82_28|, ULTIMATE.start_main_#t~ite81=|v_ULTIMATE.start_main_#t~ite81_36|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_28|, #memory_int=|v_#memory_int_281|, ~#x~0.base=|v_~#x~0.base_178|} AuxVars[|v_ULTIMATE.start_main_#t~ite79_26|, |v_ULTIMATE.start_main_#t~ite80_32|, |v_ULTIMATE.start_main_#t~mem78_27|] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem78, ULTIMATE.start_main_#t~ite84, ULTIMATE.start_main_#t~ite83, ULTIMATE.start_main_#t~ite82, ULTIMATE.start_main_#t~ite81, ULTIMATE.start_main_#t~ite80, #memory_int, ~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite79, ~x$r_buff1_thd0~0, ~x$w_buff0_used~0] under condition 198791#(and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)) [2021-01-26 22:48:56,514 WARN L146 IndependenceRelation]: Expensive independence query (2920 ms) for statements [1256] L857-1-->L858: Formula: (= |v_#memory_int_28| (store |v_#memory_int_29| |v_ULTIMATE.start_main_~#t1782~0.base_5| (store (select |v_#memory_int_29| |v_ULTIMATE.start_main_~#t1782~0.base_5|) |v_ULTIMATE.start_main_~#t1782~0.offset_5| 2))) InVars {#memory_int=|v_#memory_int_29|, ULTIMATE.start_main_~#t1782~0.base=|v_ULTIMATE.start_main_~#t1782~0.base_5|, ULTIMATE.start_main_~#t1782~0.offset=|v_ULTIMATE.start_main_~#t1782~0.offset_5|} OutVars{#memory_int=|v_#memory_int_28|, ULTIMATE.start_main_~#t1782~0.base=|v_ULTIMATE.start_main_~#t1782~0.base_5|, ULTIMATE.start_main_~#t1782~0.offset=|v_ULTIMATE.start_main_~#t1782~0.offset_5|} AuxVars[] AssignedVars[#memory_int] and [1357] L809-->L816: Formula: (let ((.cse4 (= (mod v_~x$w_buff0_used~0_502 256) 0)) (.cse5 (= (mod v_~x$r_buff1_thd2~0_258 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_422 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd2~0_292 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_503 256) 0))) (let ((.cse13 (not .cse16)) (.cse8 (or .cse14 .cse16)) (.cse9 (select |v_#memory_int_296| |v_~#x~0.base_186|)) (.cse12 (not .cse15)) (.cse7 (not .cse5)) (.cse1 (not .cse4)) (.cse2 (not .cse14)) (.cse10 (or .cse5 .cse15)) (.cse0 (or .cse14 .cse4))) (and (or (and (= v_~x$r_buff0_thd2~0_291 v_~x$r_buff0_thd2~0_292) .cse0) (and .cse1 (= v_~x$r_buff0_thd2~0_291 0) .cse2)) (let ((.cse6 (= (mod v_~x$w_buff1_used~0_421 256) 0)) (.cse3 (= (mod v_~x$r_buff0_thd2~0_291 256) 0))) (or (and (or .cse3 .cse4) (= v_~x$r_buff1_thd2~0_258 v_~x$r_buff1_thd2~0_257) (or .cse5 .cse6)) (and (= v_~x$r_buff1_thd2~0_257 0) (or (and (not .cse6) .cse7) (and .cse1 (not .cse3)))))) (let ((.cse11 (= |v_P1_#t~mem61_50| |v_P1Thread1of1ForFork1_#t~mem61_1|))) (or (and .cse8 (or (and (= |v_P1_#t~ite62_49| |v_P1_#t~mem61_50|) (= (select .cse9 |v_~#x~0.offset_186|) |v_P1_#t~mem61_50|) .cse10) (and (= |v_P1_#t~ite62_49| v_~x$w_buff1~0_126) .cse11 .cse12 .cse7)) (= |v_P1_#t~ite62_49| |v_P1_#t~ite63_43|)) (and .cse13 .cse11 (= |v_P1_#t~ite62_49| |v_P1Thread1of1ForFork1_#t~ite62_1|) .cse2 (= |v_P1_#t~ite63_43| v_~x$w_buff0~0_133)))) (or (and .cse13 (= v_~x$w_buff0_used~0_502 0) .cse2) (and (= v_~x$w_buff0_used~0_503 v_~x$w_buff0_used~0_502) .cse8)) (= (store |v_#memory_int_296| |v_~#x~0.base_186| (store .cse9 |v_~#x~0.offset_186| |v_P1_#t~ite63_43|)) |v_#memory_int_295|) (or (and (= v_~x$w_buff1_used~0_421 0) (or (and .cse12 .cse7) (and .cse1 .cse2))) (and .cse10 (= v_~x$w_buff1_used~0_422 v_~x$w_buff1_used~0_421) .cse0))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_133, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_1|, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, #memory_int=|v_#memory_int_296|, ~#x~0.base=|v_~#x~0.base_186|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_422, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_258, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_292, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_503} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_133, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_257, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_421, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_291, P1Thread1of1ForFork1_#t~ite65=|v_P1Thread1of1ForFork1_#t~ite65_1|, P1Thread1of1ForFork1_#t~ite66=|v_P1Thread1of1ForFork1_#t~ite66_1|, P1Thread1of1ForFork1_#t~ite67=|v_P1Thread1of1ForFork1_#t~ite67_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_502, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_2|, P1Thread1of1ForFork1_#t~ite63=|v_P1Thread1of1ForFork1_#t~ite63_1|, P1Thread1of1ForFork1_#t~ite64=|v_P1Thread1of1ForFork1_#t~ite64_1|, #memory_int=|v_#memory_int_295|, ~#x~0.base=|v_~#x~0.base_186|} AuxVars[|v_P1_#t~ite62_49|, |v_P1_#t~mem61_50|, |v_P1_#t~ite63_43|] AssignedVars[P1Thread1of1ForFork1_#t~ite62, P1Thread1of1ForFork1_#t~ite63, P1Thread1of1ForFork1_#t~ite64, #memory_int, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, P1Thread1of1ForFork1_#t~mem61, ~x$r_buff0_thd2~0, P1Thread1of1ForFork1_#t~ite65, P1Thread1of1ForFork1_#t~ite66, P1Thread1of1ForFork1_#t~ite67, ~x$w_buff0_used~0] under condition 198791#(and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)) [2021-01-26 22:49:00,434 WARN L146 IndependenceRelation]: Expensive independence query (3918 ms) for statements [1364] L829-->L836: Formula: (let ((.cse5 (= (mod v_~x$w_buff0_used~0_416 256) 0)) (.cse4 (= (mod v_~x$r_buff1_thd3~0_56 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_332 256) 0)) (.cse14 (= 0 (mod v_~x$r_buff0_thd3~0_62 256))) (.cse16 (= (mod v_~x$w_buff0_used~0_417 256) 0))) (let ((.cse11 (not .cse16)) (.cse6 (or .cse14 .cse16)) (.cse8 (not .cse15)) (.cse3 (not .cse4)) (.cse9 (or .cse15 .cse4)) (.cse13 (or .cse14 .cse5)) (.cse0 (not .cse5)) (.cse12 (not .cse14)) (.cse10 (select |v_#memory_int_258| |v_~#x~0.base_162|))) (and (let ((.cse2 (= (mod v_~x$w_buff1_used~0_331 256) 0)) (.cse1 (= (mod v_~x$r_buff0_thd3~0_61 256) 0))) (or (and (= v_~x$r_buff1_thd3~0_55 0) (or (and .cse0 (not .cse1)) (and (not .cse2) .cse3))) (and (= v_~x$r_buff1_thd3~0_56 v_~x$r_buff1_thd3~0_55) (or .cse2 .cse4) (or .cse5 .cse1)))) (let ((.cse7 (= |v_P2_#t~mem68_38| |v_P2Thread1of1ForFork2_#t~mem68_1|))) (or (and (= |v_P2_#t~ite69_39| |v_P2_#t~ite70_33|) .cse6 (or (and .cse7 (= |v_P2_#t~ite69_39| v_~x$w_buff1~0_86) .cse3 .cse8) (and .cse9 (= |v_P2_#t~ite69_39| |v_P2_#t~mem68_38|) (= |v_P2_#t~mem68_38| (select .cse10 |v_~#x~0.offset_162|))))) (and (= |v_P2_#t~ite69_39| |v_P2Thread1of1ForFork2_#t~ite69_1|) .cse7 .cse11 (= |v_P2_#t~ite70_33| v_~x$w_buff0~0_115) .cse12))) (or (and .cse11 (= v_~x$w_buff0_used~0_416 0) .cse12) (and .cse6 (= v_~x$w_buff0_used~0_417 v_~x$w_buff0_used~0_416))) (or (and (= v_~x$w_buff1_used~0_331 0) (or (and .cse0 .cse12) (and .cse8 .cse3))) (and .cse9 .cse13 (= v_~x$w_buff1_used~0_332 v_~x$w_buff1_used~0_331))) (or (and .cse13 (= v_~x$r_buff0_thd3~0_62 v_~x$r_buff0_thd3~0_61)) (and .cse0 (= v_~x$r_buff0_thd3~0_61 0) .cse12)) (= (store |v_#memory_int_258| |v_~#x~0.base_162| (store .cse10 |v_~#x~0.offset_162| |v_P2_#t~ite70_33|)) |v_#memory_int_257|)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_115, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_1|, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_1|, #memory_int=|v_#memory_int_258|, ~#x~0.base=|v_~#x~0.base_162|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_56, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_332, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_62, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_417} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_115, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_2|, P2Thread1of1ForFork2_#t~ite73=|v_P2Thread1of1ForFork2_#t~ite73_1|, P2Thread1of1ForFork2_#t~ite72=|v_P2Thread1of1ForFork2_#t~ite72_1|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_55, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_331, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_1|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_61, P2Thread1of1ForFork2_#t~ite71=|v_P2Thread1of1ForFork2_#t~ite71_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_416, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_2|, P2Thread1of1ForFork2_#t~ite74=|v_P2Thread1of1ForFork2_#t~ite74_1|, #memory_int=|v_#memory_int_257|, ~#x~0.base=|v_~#x~0.base_162|} AuxVars[|v_P2_#t~ite70_33|, |v_P2_#t~mem68_38|, |v_P2_#t~ite69_39|] AssignedVars[P2Thread1of1ForFork2_#t~ite69, P2Thread1of1ForFork2_#t~mem68, P2Thread1of1ForFork2_#t~ite74, P2Thread1of1ForFork2_#t~ite73, P2Thread1of1ForFork2_#t~ite72, #memory_int, ~x$r_buff1_thd3~0, ~x$w_buff1_used~0, P2Thread1of1ForFork2_#t~ite70, ~x$r_buff0_thd3~0, P2Thread1of1ForFork2_#t~ite71, ~x$w_buff0_used~0] and [1357] L809-->L816: Formula: (let ((.cse4 (= (mod v_~x$w_buff0_used~0_502 256) 0)) (.cse5 (= (mod v_~x$r_buff1_thd2~0_258 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_422 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd2~0_292 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_503 256) 0))) (let ((.cse13 (not .cse16)) (.cse8 (or .cse14 .cse16)) (.cse9 (select |v_#memory_int_296| |v_~#x~0.base_186|)) (.cse12 (not .cse15)) (.cse7 (not .cse5)) (.cse1 (not .cse4)) (.cse2 (not .cse14)) (.cse10 (or .cse5 .cse15)) (.cse0 (or .cse14 .cse4))) (and (or (and (= v_~x$r_buff0_thd2~0_291 v_~x$r_buff0_thd2~0_292) .cse0) (and .cse1 (= v_~x$r_buff0_thd2~0_291 0) .cse2)) (let ((.cse6 (= (mod v_~x$w_buff1_used~0_421 256) 0)) (.cse3 (= (mod v_~x$r_buff0_thd2~0_291 256) 0))) (or (and (or .cse3 .cse4) (= v_~x$r_buff1_thd2~0_258 v_~x$r_buff1_thd2~0_257) (or .cse5 .cse6)) (and (= v_~x$r_buff1_thd2~0_257 0) (or (and (not .cse6) .cse7) (and .cse1 (not .cse3)))))) (let ((.cse11 (= |v_P1_#t~mem61_50| |v_P1Thread1of1ForFork1_#t~mem61_1|))) (or (and .cse8 (or (and (= |v_P1_#t~ite62_49| |v_P1_#t~mem61_50|) (= (select .cse9 |v_~#x~0.offset_186|) |v_P1_#t~mem61_50|) .cse10) (and (= |v_P1_#t~ite62_49| v_~x$w_buff1~0_126) .cse11 .cse12 .cse7)) (= |v_P1_#t~ite62_49| |v_P1_#t~ite63_43|)) (and .cse13 .cse11 (= |v_P1_#t~ite62_49| |v_P1Thread1of1ForFork1_#t~ite62_1|) .cse2 (= |v_P1_#t~ite63_43| v_~x$w_buff0~0_133)))) (or (and .cse13 (= v_~x$w_buff0_used~0_502 0) .cse2) (and (= v_~x$w_buff0_used~0_503 v_~x$w_buff0_used~0_502) .cse8)) (= (store |v_#memory_int_296| |v_~#x~0.base_186| (store .cse9 |v_~#x~0.offset_186| |v_P1_#t~ite63_43|)) |v_#memory_int_295|) (or (and (= v_~x$w_buff1_used~0_421 0) (or (and .cse12 .cse7) (and .cse1 .cse2))) (and .cse10 (= v_~x$w_buff1_used~0_422 v_~x$w_buff1_used~0_421) .cse0))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_133, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_1|, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, #memory_int=|v_#memory_int_296|, ~#x~0.base=|v_~#x~0.base_186|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_422, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_258, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_292, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_503} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_133, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_257, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_421, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_291, P1Thread1of1ForFork1_#t~ite65=|v_P1Thread1of1ForFork1_#t~ite65_1|, P1Thread1of1ForFork1_#t~ite66=|v_P1Thread1of1ForFork1_#t~ite66_1|, P1Thread1of1ForFork1_#t~ite67=|v_P1Thread1of1ForFork1_#t~ite67_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_502, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_2|, P1Thread1of1ForFork1_#t~ite63=|v_P1Thread1of1ForFork1_#t~ite63_1|, P1Thread1of1ForFork1_#t~ite64=|v_P1Thread1of1ForFork1_#t~ite64_1|, #memory_int=|v_#memory_int_295|, ~#x~0.base=|v_~#x~0.base_186|} AuxVars[|v_P1_#t~ite62_49|, |v_P1_#t~mem61_50|, |v_P1_#t~ite63_43|] AssignedVars[P1Thread1of1ForFork1_#t~ite62, P1Thread1of1ForFork1_#t~ite63, P1Thread1of1ForFork1_#t~ite64, #memory_int, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, P1Thread1of1ForFork1_#t~mem61, ~x$r_buff0_thd2~0, P1Thread1of1ForFork1_#t~ite65, P1Thread1of1ForFork1_#t~ite66, P1Thread1of1ForFork1_#t~ite67, ~x$w_buff0_used~0] under condition 198791#(and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)) [2021-01-26 22:49:04,473 WARN L146 IndependenceRelation]: Expensive independence query (4037 ms) for statements [1340] L2-1-->L869: Formula: (let ((.cse13 (= (mod v_~x$w_buff0_used~0_454 256) 0)) (.cse12 (= (mod v_~x$r_buff1_thd0~0_64 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_374 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd0~0_68 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_455 256) 0))) (let ((.cse3 (not .cse16)) (.cse4 (or .cse16 .cse14)) (.cse7 (not .cse15)) (.cse1 (not .cse14)) (.cse8 (or .cse15 .cse12)) (.cse0 (or .cse13 .cse14)) (.cse9 (select |v_#memory_int_282| |v_~#x~0.base_178|)) (.cse2 (not .cse13)) (.cse6 (not .cse12))) (and (or (and .cse0 (= v_~x$r_buff0_thd0~0_68 v_~x$r_buff0_thd0~0_67)) (and .cse1 .cse2 (= v_~x$r_buff0_thd0~0_67 0))) (or (and (= v_~x$w_buff0_used~0_454 0) .cse1 .cse3) (and .cse4 (= v_~x$w_buff0_used~0_455 v_~x$w_buff0_used~0_454))) (let ((.cse5 (= |v_ULTIMATE.start_main_#t~mem78_23| |v_ULTIMATE.start_main_#t~mem78_27|))) (or (and .cse1 (= v_~x$w_buff0~0_125 |v_ULTIMATE.start_main_#t~ite80_32|) (= |v_ULTIMATE.start_main_#t~ite79_22| |v_ULTIMATE.start_main_#t~ite79_26|) .cse3 .cse5) (and (or (and .cse6 .cse7 .cse5 (= |v_ULTIMATE.start_main_#t~ite79_26| v_~x$w_buff1~0_98)) (and .cse8 (= |v_ULTIMATE.start_main_#t~mem78_27| (select .cse9 |v_~#x~0.offset_178|)) (= |v_ULTIMATE.start_main_#t~mem78_27| |v_ULTIMATE.start_main_#t~ite79_26|))) (= |v_ULTIMATE.start_main_#t~ite79_26| |v_ULTIMATE.start_main_#t~ite80_32|) .cse4))) (or (and (or (and .cse6 .cse7) (and .cse1 .cse2)) (= v_~x$w_buff1_used~0_373 0)) (and .cse8 .cse0 (= v_~x$w_buff1_used~0_374 v_~x$w_buff1_used~0_373))) (= (store |v_#memory_int_282| |v_~#x~0.base_178| (store .cse9 |v_~#x~0.offset_178| |v_ULTIMATE.start_main_#t~ite80_32|)) |v_#memory_int_281|) (let ((.cse11 (= (mod v_~x$w_buff1_used~0_373 256) 0)) (.cse10 (= (mod v_~x$r_buff0_thd0~0_67 256) 0))) (or (and (or (and .cse2 (not .cse10)) (and .cse6 (not .cse11))) (= v_~x$r_buff1_thd0~0_63 0)) (and (or .cse11 .cse12) (or .cse13 .cse10) (= v_~x$r_buff1_thd0~0_64 v_~x$r_buff1_thd0~0_63))))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_68, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_23|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, #memory_int=|v_#memory_int_282|, ~#x~0.base=|v_~#x~0.base_178|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_374, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_22|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_64, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_455} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_67, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_21|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_373, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_20|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_63, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_454, ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_26|, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_32|, ULTIMATE.start_main_#t~ite82=|v_ULTIMATE.start_main_#t~ite82_28|, ULTIMATE.start_main_#t~ite81=|v_ULTIMATE.start_main_#t~ite81_36|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_28|, #memory_int=|v_#memory_int_281|, ~#x~0.base=|v_~#x~0.base_178|} AuxVars[|v_ULTIMATE.start_main_#t~ite79_26|, |v_ULTIMATE.start_main_#t~ite80_32|, |v_ULTIMATE.start_main_#t~mem78_27|] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem78, ULTIMATE.start_main_#t~ite84, ULTIMATE.start_main_#t~ite83, ULTIMATE.start_main_#t~ite82, ULTIMATE.start_main_#t~ite81, ULTIMATE.start_main_#t~ite80, #memory_int, ~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite79, ~x$r_buff1_thd0~0, ~x$w_buff0_used~0] and [1357] L809-->L816: Formula: (let ((.cse4 (= (mod v_~x$w_buff0_used~0_502 256) 0)) (.cse5 (= (mod v_~x$r_buff1_thd2~0_258 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_422 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd2~0_292 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_503 256) 0))) (let ((.cse13 (not .cse16)) (.cse8 (or .cse14 .cse16)) (.cse9 (select |v_#memory_int_296| |v_~#x~0.base_186|)) (.cse12 (not .cse15)) (.cse7 (not .cse5)) (.cse1 (not .cse4)) (.cse2 (not .cse14)) (.cse10 (or .cse5 .cse15)) (.cse0 (or .cse14 .cse4))) (and (or (and (= v_~x$r_buff0_thd2~0_291 v_~x$r_buff0_thd2~0_292) .cse0) (and .cse1 (= v_~x$r_buff0_thd2~0_291 0) .cse2)) (let ((.cse6 (= (mod v_~x$w_buff1_used~0_421 256) 0)) (.cse3 (= (mod v_~x$r_buff0_thd2~0_291 256) 0))) (or (and (or .cse3 .cse4) (= v_~x$r_buff1_thd2~0_258 v_~x$r_buff1_thd2~0_257) (or .cse5 .cse6)) (and (= v_~x$r_buff1_thd2~0_257 0) (or (and (not .cse6) .cse7) (and .cse1 (not .cse3)))))) (let ((.cse11 (= |v_P1_#t~mem61_50| |v_P1Thread1of1ForFork1_#t~mem61_1|))) (or (and .cse8 (or (and (= |v_P1_#t~ite62_49| |v_P1_#t~mem61_50|) (= (select .cse9 |v_~#x~0.offset_186|) |v_P1_#t~mem61_50|) .cse10) (and (= |v_P1_#t~ite62_49| v_~x$w_buff1~0_126) .cse11 .cse12 .cse7)) (= |v_P1_#t~ite62_49| |v_P1_#t~ite63_43|)) (and .cse13 .cse11 (= |v_P1_#t~ite62_49| |v_P1Thread1of1ForFork1_#t~ite62_1|) .cse2 (= |v_P1_#t~ite63_43| v_~x$w_buff0~0_133)))) (or (and .cse13 (= v_~x$w_buff0_used~0_502 0) .cse2) (and (= v_~x$w_buff0_used~0_503 v_~x$w_buff0_used~0_502) .cse8)) (= (store |v_#memory_int_296| |v_~#x~0.base_186| (store .cse9 |v_~#x~0.offset_186| |v_P1_#t~ite63_43|)) |v_#memory_int_295|) (or (and (= v_~x$w_buff1_used~0_421 0) (or (and .cse12 .cse7) (and .cse1 .cse2))) (and .cse10 (= v_~x$w_buff1_used~0_422 v_~x$w_buff1_used~0_421) .cse0))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_133, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_1|, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, #memory_int=|v_#memory_int_296|, ~#x~0.base=|v_~#x~0.base_186|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_422, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_258, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_292, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_503} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_133, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_257, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_421, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_291, P1Thread1of1ForFork1_#t~ite65=|v_P1Thread1of1ForFork1_#t~ite65_1|, P1Thread1of1ForFork1_#t~ite66=|v_P1Thread1of1ForFork1_#t~ite66_1|, P1Thread1of1ForFork1_#t~ite67=|v_P1Thread1of1ForFork1_#t~ite67_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_502, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_2|, P1Thread1of1ForFork1_#t~ite63=|v_P1Thread1of1ForFork1_#t~ite63_1|, P1Thread1of1ForFork1_#t~ite64=|v_P1Thread1of1ForFork1_#t~ite64_1|, #memory_int=|v_#memory_int_295|, ~#x~0.base=|v_~#x~0.base_186|} AuxVars[|v_P1_#t~ite62_49|, |v_P1_#t~mem61_50|, |v_P1_#t~ite63_43|] AssignedVars[P1Thread1of1ForFork1_#t~ite62, P1Thread1of1ForFork1_#t~ite63, P1Thread1of1ForFork1_#t~ite64, #memory_int, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, P1Thread1of1ForFork1_#t~mem61, ~x$r_buff0_thd2~0, P1Thread1of1ForFork1_#t~ite65, P1Thread1of1ForFork1_#t~ite66, P1Thread1of1ForFork1_#t~ite67, ~x$w_buff0_used~0] under condition 198791#(and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)) [2021-01-26 22:49:04,670 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:06,812 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:09,790 WARN L146 IndependenceRelation]: Expensive independence query (2976 ms) for statements [1235] L855-1-->L856: Formula: (= |v_#memory_int_26| (store |v_#memory_int_27| |v_ULTIMATE.start_main_~#t1781~0.base_5| (store (select |v_#memory_int_27| |v_ULTIMATE.start_main_~#t1781~0.base_5|) |v_ULTIMATE.start_main_~#t1781~0.offset_5| 1))) InVars {#memory_int=|v_#memory_int_27|, ULTIMATE.start_main_~#t1781~0.base=|v_ULTIMATE.start_main_~#t1781~0.base_5|, ULTIMATE.start_main_~#t1781~0.offset=|v_ULTIMATE.start_main_~#t1781~0.offset_5|} OutVars{#memory_int=|v_#memory_int_26|, ULTIMATE.start_main_~#t1781~0.base=|v_ULTIMATE.start_main_~#t1781~0.base_5|, ULTIMATE.start_main_~#t1781~0.offset=|v_ULTIMATE.start_main_~#t1781~0.offset_5|} AuxVars[] AssignedVars[#memory_int] and [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] under condition 198796#(and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)) [2021-01-26 22:49:13,956 WARN L146 IndependenceRelation]: Expensive independence query (3990 ms) for statements [1357] L809-->L816: Formula: (let ((.cse4 (= (mod v_~x$w_buff0_used~0_502 256) 0)) (.cse5 (= (mod v_~x$r_buff1_thd2~0_258 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_422 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd2~0_292 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_503 256) 0))) (let ((.cse13 (not .cse16)) (.cse8 (or .cse14 .cse16)) (.cse9 (select |v_#memory_int_296| |v_~#x~0.base_186|)) (.cse12 (not .cse15)) (.cse7 (not .cse5)) (.cse1 (not .cse4)) (.cse2 (not .cse14)) (.cse10 (or .cse5 .cse15)) (.cse0 (or .cse14 .cse4))) (and (or (and (= v_~x$r_buff0_thd2~0_291 v_~x$r_buff0_thd2~0_292) .cse0) (and .cse1 (= v_~x$r_buff0_thd2~0_291 0) .cse2)) (let ((.cse6 (= (mod v_~x$w_buff1_used~0_421 256) 0)) (.cse3 (= (mod v_~x$r_buff0_thd2~0_291 256) 0))) (or (and (or .cse3 .cse4) (= v_~x$r_buff1_thd2~0_258 v_~x$r_buff1_thd2~0_257) (or .cse5 .cse6)) (and (= v_~x$r_buff1_thd2~0_257 0) (or (and (not .cse6) .cse7) (and .cse1 (not .cse3)))))) (let ((.cse11 (= |v_P1_#t~mem61_50| |v_P1Thread1of1ForFork1_#t~mem61_1|))) (or (and .cse8 (or (and (= |v_P1_#t~ite62_49| |v_P1_#t~mem61_50|) (= (select .cse9 |v_~#x~0.offset_186|) |v_P1_#t~mem61_50|) .cse10) (and (= |v_P1_#t~ite62_49| v_~x$w_buff1~0_126) .cse11 .cse12 .cse7)) (= |v_P1_#t~ite62_49| |v_P1_#t~ite63_43|)) (and .cse13 .cse11 (= |v_P1_#t~ite62_49| |v_P1Thread1of1ForFork1_#t~ite62_1|) .cse2 (= |v_P1_#t~ite63_43| v_~x$w_buff0~0_133)))) (or (and .cse13 (= v_~x$w_buff0_used~0_502 0) .cse2) (and (= v_~x$w_buff0_used~0_503 v_~x$w_buff0_used~0_502) .cse8)) (= (store |v_#memory_int_296| |v_~#x~0.base_186| (store .cse9 |v_~#x~0.offset_186| |v_P1_#t~ite63_43|)) |v_#memory_int_295|) (or (and (= v_~x$w_buff1_used~0_421 0) (or (and .cse12 .cse7) (and .cse1 .cse2))) (and .cse10 (= v_~x$w_buff1_used~0_422 v_~x$w_buff1_used~0_421) .cse0))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_133, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_1|, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, #memory_int=|v_#memory_int_296|, ~#x~0.base=|v_~#x~0.base_186|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_422, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_258, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_292, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_503} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_133, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_257, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_421, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_291, P1Thread1of1ForFork1_#t~ite65=|v_P1Thread1of1ForFork1_#t~ite65_1|, P1Thread1of1ForFork1_#t~ite66=|v_P1Thread1of1ForFork1_#t~ite66_1|, P1Thread1of1ForFork1_#t~ite67=|v_P1Thread1of1ForFork1_#t~ite67_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_502, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_2|, P1Thread1of1ForFork1_#t~ite63=|v_P1Thread1of1ForFork1_#t~ite63_1|, P1Thread1of1ForFork1_#t~ite64=|v_P1Thread1of1ForFork1_#t~ite64_1|, #memory_int=|v_#memory_int_295|, ~#x~0.base=|v_~#x~0.base_186|} AuxVars[|v_P1_#t~ite62_49|, |v_P1_#t~mem61_50|, |v_P1_#t~ite63_43|] AssignedVars[P1Thread1of1ForFork1_#t~ite62, P1Thread1of1ForFork1_#t~ite63, P1Thread1of1ForFork1_#t~ite64, #memory_int, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, P1Thread1of1ForFork1_#t~mem61, ~x$r_buff0_thd2~0, P1Thread1of1ForFork1_#t~ite65, P1Thread1of1ForFork1_#t~ite66, P1Thread1of1ForFork1_#t~ite67, ~x$w_buff0_used~0] and [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] under condition 198791#(and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)) [2021-01-26 22:49:16,701 WARN L146 IndependenceRelation]: Expensive independence query (2743 ms) for statements [1256] L857-1-->L858: Formula: (= |v_#memory_int_28| (store |v_#memory_int_29| |v_ULTIMATE.start_main_~#t1782~0.base_5| (store (select |v_#memory_int_29| |v_ULTIMATE.start_main_~#t1782~0.base_5|) |v_ULTIMATE.start_main_~#t1782~0.offset_5| 2))) InVars {#memory_int=|v_#memory_int_29|, ULTIMATE.start_main_~#t1782~0.base=|v_ULTIMATE.start_main_~#t1782~0.base_5|, ULTIMATE.start_main_~#t1782~0.offset=|v_ULTIMATE.start_main_~#t1782~0.offset_5|} OutVars{#memory_int=|v_#memory_int_28|, ULTIMATE.start_main_~#t1782~0.base=|v_ULTIMATE.start_main_~#t1782~0.base_5|, ULTIMATE.start_main_~#t1782~0.offset=|v_ULTIMATE.start_main_~#t1782~0.offset_5|} AuxVars[] AssignedVars[#memory_int] and [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] under condition 198791#(and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)) [2021-01-26 22:49:20,802 WARN L146 IndependenceRelation]: Expensive independence query (4098 ms) for statements [1364] L829-->L836: Formula: (let ((.cse5 (= (mod v_~x$w_buff0_used~0_416 256) 0)) (.cse4 (= (mod v_~x$r_buff1_thd3~0_56 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_332 256) 0)) (.cse14 (= 0 (mod v_~x$r_buff0_thd3~0_62 256))) (.cse16 (= (mod v_~x$w_buff0_used~0_417 256) 0))) (let ((.cse11 (not .cse16)) (.cse6 (or .cse14 .cse16)) (.cse8 (not .cse15)) (.cse3 (not .cse4)) (.cse9 (or .cse15 .cse4)) (.cse13 (or .cse14 .cse5)) (.cse0 (not .cse5)) (.cse12 (not .cse14)) (.cse10 (select |v_#memory_int_258| |v_~#x~0.base_162|))) (and (let ((.cse2 (= (mod v_~x$w_buff1_used~0_331 256) 0)) (.cse1 (= (mod v_~x$r_buff0_thd3~0_61 256) 0))) (or (and (= v_~x$r_buff1_thd3~0_55 0) (or (and .cse0 (not .cse1)) (and (not .cse2) .cse3))) (and (= v_~x$r_buff1_thd3~0_56 v_~x$r_buff1_thd3~0_55) (or .cse2 .cse4) (or .cse5 .cse1)))) (let ((.cse7 (= |v_P2_#t~mem68_38| |v_P2Thread1of1ForFork2_#t~mem68_1|))) (or (and (= |v_P2_#t~ite69_39| |v_P2_#t~ite70_33|) .cse6 (or (and .cse7 (= |v_P2_#t~ite69_39| v_~x$w_buff1~0_86) .cse3 .cse8) (and .cse9 (= |v_P2_#t~ite69_39| |v_P2_#t~mem68_38|) (= |v_P2_#t~mem68_38| (select .cse10 |v_~#x~0.offset_162|))))) (and (= |v_P2_#t~ite69_39| |v_P2Thread1of1ForFork2_#t~ite69_1|) .cse7 .cse11 (= |v_P2_#t~ite70_33| v_~x$w_buff0~0_115) .cse12))) (or (and .cse11 (= v_~x$w_buff0_used~0_416 0) .cse12) (and .cse6 (= v_~x$w_buff0_used~0_417 v_~x$w_buff0_used~0_416))) (or (and (= v_~x$w_buff1_used~0_331 0) (or (and .cse0 .cse12) (and .cse8 .cse3))) (and .cse9 .cse13 (= v_~x$w_buff1_used~0_332 v_~x$w_buff1_used~0_331))) (or (and .cse13 (= v_~x$r_buff0_thd3~0_62 v_~x$r_buff0_thd3~0_61)) (and .cse0 (= v_~x$r_buff0_thd3~0_61 0) .cse12)) (= (store |v_#memory_int_258| |v_~#x~0.base_162| (store .cse10 |v_~#x~0.offset_162| |v_P2_#t~ite70_33|)) |v_#memory_int_257|)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_115, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_1|, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_1|, #memory_int=|v_#memory_int_258|, ~#x~0.base=|v_~#x~0.base_162|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_56, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_332, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_62, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_417} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_115, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_2|, P2Thread1of1ForFork2_#t~ite73=|v_P2Thread1of1ForFork2_#t~ite73_1|, P2Thread1of1ForFork2_#t~ite72=|v_P2Thread1of1ForFork2_#t~ite72_1|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_55, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_331, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_1|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_61, P2Thread1of1ForFork2_#t~ite71=|v_P2Thread1of1ForFork2_#t~ite71_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_416, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_2|, P2Thread1of1ForFork2_#t~ite74=|v_P2Thread1of1ForFork2_#t~ite74_1|, #memory_int=|v_#memory_int_257|, ~#x~0.base=|v_~#x~0.base_162|} AuxVars[|v_P2_#t~ite70_33|, |v_P2_#t~mem68_38|, |v_P2_#t~ite69_39|] AssignedVars[P2Thread1of1ForFork2_#t~ite69, P2Thread1of1ForFork2_#t~mem68, P2Thread1of1ForFork2_#t~ite74, P2Thread1of1ForFork2_#t~ite73, P2Thread1of1ForFork2_#t~ite72, #memory_int, ~x$r_buff1_thd3~0, ~x$w_buff1_used~0, P2Thread1of1ForFork2_#t~ite70, ~x$r_buff0_thd3~0, P2Thread1of1ForFork2_#t~ite71, ~x$w_buff0_used~0] and [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] under condition 198791#(and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)) [2021-01-26 22:49:24,892 WARN L146 IndependenceRelation]: Expensive independence query (4088 ms) for statements [1340] L2-1-->L869: Formula: (let ((.cse13 (= (mod v_~x$w_buff0_used~0_454 256) 0)) (.cse12 (= (mod v_~x$r_buff1_thd0~0_64 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_374 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd0~0_68 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_455 256) 0))) (let ((.cse3 (not .cse16)) (.cse4 (or .cse16 .cse14)) (.cse7 (not .cse15)) (.cse1 (not .cse14)) (.cse8 (or .cse15 .cse12)) (.cse0 (or .cse13 .cse14)) (.cse9 (select |v_#memory_int_282| |v_~#x~0.base_178|)) (.cse2 (not .cse13)) (.cse6 (not .cse12))) (and (or (and .cse0 (= v_~x$r_buff0_thd0~0_68 v_~x$r_buff0_thd0~0_67)) (and .cse1 .cse2 (= v_~x$r_buff0_thd0~0_67 0))) (or (and (= v_~x$w_buff0_used~0_454 0) .cse1 .cse3) (and .cse4 (= v_~x$w_buff0_used~0_455 v_~x$w_buff0_used~0_454))) (let ((.cse5 (= |v_ULTIMATE.start_main_#t~mem78_23| |v_ULTIMATE.start_main_#t~mem78_27|))) (or (and .cse1 (= v_~x$w_buff0~0_125 |v_ULTIMATE.start_main_#t~ite80_32|) (= |v_ULTIMATE.start_main_#t~ite79_22| |v_ULTIMATE.start_main_#t~ite79_26|) .cse3 .cse5) (and (or (and .cse6 .cse7 .cse5 (= |v_ULTIMATE.start_main_#t~ite79_26| v_~x$w_buff1~0_98)) (and .cse8 (= |v_ULTIMATE.start_main_#t~mem78_27| (select .cse9 |v_~#x~0.offset_178|)) (= |v_ULTIMATE.start_main_#t~mem78_27| |v_ULTIMATE.start_main_#t~ite79_26|))) (= |v_ULTIMATE.start_main_#t~ite79_26| |v_ULTIMATE.start_main_#t~ite80_32|) .cse4))) (or (and (or (and .cse6 .cse7) (and .cse1 .cse2)) (= v_~x$w_buff1_used~0_373 0)) (and .cse8 .cse0 (= v_~x$w_buff1_used~0_374 v_~x$w_buff1_used~0_373))) (= (store |v_#memory_int_282| |v_~#x~0.base_178| (store .cse9 |v_~#x~0.offset_178| |v_ULTIMATE.start_main_#t~ite80_32|)) |v_#memory_int_281|) (let ((.cse11 (= (mod v_~x$w_buff1_used~0_373 256) 0)) (.cse10 (= (mod v_~x$r_buff0_thd0~0_67 256) 0))) (or (and (or (and .cse2 (not .cse10)) (and .cse6 (not .cse11))) (= v_~x$r_buff1_thd0~0_63 0)) (and (or .cse11 .cse12) (or .cse13 .cse10) (= v_~x$r_buff1_thd0~0_64 v_~x$r_buff1_thd0~0_63))))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_68, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_23|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, #memory_int=|v_#memory_int_282|, ~#x~0.base=|v_~#x~0.base_178|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_374, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_22|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_64, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_455} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_125, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_67, ULTIMATE.start_main_#t~mem78=|v_ULTIMATE.start_main_#t~mem78_21|, ~#x~0.offset=|v_~#x~0.offset_178|, ~x$w_buff1~0=v_~x$w_buff1~0_98, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_373, ULTIMATE.start_main_#t~ite79=|v_ULTIMATE.start_main_#t~ite79_20|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_63, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_454, ULTIMATE.start_main_#t~ite84=|v_ULTIMATE.start_main_#t~ite84_26|, ULTIMATE.start_main_#t~ite83=|v_ULTIMATE.start_main_#t~ite83_32|, ULTIMATE.start_main_#t~ite82=|v_ULTIMATE.start_main_#t~ite82_28|, ULTIMATE.start_main_#t~ite81=|v_ULTIMATE.start_main_#t~ite81_36|, ULTIMATE.start_main_#t~ite80=|v_ULTIMATE.start_main_#t~ite80_28|, #memory_int=|v_#memory_int_281|, ~#x~0.base=|v_~#x~0.base_178|} AuxVars[|v_ULTIMATE.start_main_#t~ite79_26|, |v_ULTIMATE.start_main_#t~ite80_32|, |v_ULTIMATE.start_main_#t~mem78_27|] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem78, ULTIMATE.start_main_#t~ite84, ULTIMATE.start_main_#t~ite83, ULTIMATE.start_main_#t~ite82, ULTIMATE.start_main_#t~ite81, ULTIMATE.start_main_#t~ite80, #memory_int, ~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite79, ~x$r_buff1_thd0~0, ~x$w_buff0_used~0] and [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] under condition 198791#(and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)) [2021-01-26 22:49:26,098 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:26,209 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:26,300 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:30,393 WARN L146 IndependenceRelation]: Expensive independence query (4092 ms) for statements [1364] L829-->L836: Formula: (let ((.cse5 (= (mod v_~x$w_buff0_used~0_416 256) 0)) (.cse4 (= (mod v_~x$r_buff1_thd3~0_56 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_332 256) 0)) (.cse14 (= 0 (mod v_~x$r_buff0_thd3~0_62 256))) (.cse16 (= (mod v_~x$w_buff0_used~0_417 256) 0))) (let ((.cse11 (not .cse16)) (.cse6 (or .cse14 .cse16)) (.cse8 (not .cse15)) (.cse3 (not .cse4)) (.cse9 (or .cse15 .cse4)) (.cse13 (or .cse14 .cse5)) (.cse0 (not .cse5)) (.cse12 (not .cse14)) (.cse10 (select |v_#memory_int_258| |v_~#x~0.base_162|))) (and (let ((.cse2 (= (mod v_~x$w_buff1_used~0_331 256) 0)) (.cse1 (= (mod v_~x$r_buff0_thd3~0_61 256) 0))) (or (and (= v_~x$r_buff1_thd3~0_55 0) (or (and .cse0 (not .cse1)) (and (not .cse2) .cse3))) (and (= v_~x$r_buff1_thd3~0_56 v_~x$r_buff1_thd3~0_55) (or .cse2 .cse4) (or .cse5 .cse1)))) (let ((.cse7 (= |v_P2_#t~mem68_38| |v_P2Thread1of1ForFork2_#t~mem68_1|))) (or (and (= |v_P2_#t~ite69_39| |v_P2_#t~ite70_33|) .cse6 (or (and .cse7 (= |v_P2_#t~ite69_39| v_~x$w_buff1~0_86) .cse3 .cse8) (and .cse9 (= |v_P2_#t~ite69_39| |v_P2_#t~mem68_38|) (= |v_P2_#t~mem68_38| (select .cse10 |v_~#x~0.offset_162|))))) (and (= |v_P2_#t~ite69_39| |v_P2Thread1of1ForFork2_#t~ite69_1|) .cse7 .cse11 (= |v_P2_#t~ite70_33| v_~x$w_buff0~0_115) .cse12))) (or (and .cse11 (= v_~x$w_buff0_used~0_416 0) .cse12) (and .cse6 (= v_~x$w_buff0_used~0_417 v_~x$w_buff0_used~0_416))) (or (and (= v_~x$w_buff1_used~0_331 0) (or (and .cse0 .cse12) (and .cse8 .cse3))) (and .cse9 .cse13 (= v_~x$w_buff1_used~0_332 v_~x$w_buff1_used~0_331))) (or (and .cse13 (= v_~x$r_buff0_thd3~0_62 v_~x$r_buff0_thd3~0_61)) (and .cse0 (= v_~x$r_buff0_thd3~0_61 0) .cse12)) (= (store |v_#memory_int_258| |v_~#x~0.base_162| (store .cse10 |v_~#x~0.offset_162| |v_P2_#t~ite70_33|)) |v_#memory_int_257|)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_115, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_1|, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_1|, #memory_int=|v_#memory_int_258|, ~#x~0.base=|v_~#x~0.base_162|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_56, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_332, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_62, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_417} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_115, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_2|, P2Thread1of1ForFork2_#t~ite73=|v_P2Thread1of1ForFork2_#t~ite73_1|, P2Thread1of1ForFork2_#t~ite72=|v_P2Thread1of1ForFork2_#t~ite72_1|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_55, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_331, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_1|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_61, P2Thread1of1ForFork2_#t~ite71=|v_P2Thread1of1ForFork2_#t~ite71_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_416, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_2|, P2Thread1of1ForFork2_#t~ite74=|v_P2Thread1of1ForFork2_#t~ite74_1|, #memory_int=|v_#memory_int_257|, ~#x~0.base=|v_~#x~0.base_162|} AuxVars[|v_P2_#t~ite70_33|, |v_P2_#t~mem68_38|, |v_P2_#t~ite69_39|] AssignedVars[P2Thread1of1ForFork2_#t~ite69, P2Thread1of1ForFork2_#t~mem68, P2Thread1of1ForFork2_#t~ite74, P2Thread1of1ForFork2_#t~ite73, P2Thread1of1ForFork2_#t~ite72, #memory_int, ~x$r_buff1_thd3~0, ~x$w_buff1_used~0, P2Thread1of1ForFork2_#t~ite70, ~x$r_buff0_thd3~0, P2Thread1of1ForFork2_#t~ite71, ~x$w_buff0_used~0] and [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] under condition 230721#(and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (= |~#x~0.offset| 0)) [2021-01-26 22:49:30,413 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:31,024 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:35,116 WARN L146 IndependenceRelation]: Expensive independence query (4091 ms) for statements [1364] L829-->L836: Formula: (let ((.cse5 (= (mod v_~x$w_buff0_used~0_416 256) 0)) (.cse4 (= (mod v_~x$r_buff1_thd3~0_56 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_332 256) 0)) (.cse14 (= 0 (mod v_~x$r_buff0_thd3~0_62 256))) (.cse16 (= (mod v_~x$w_buff0_used~0_417 256) 0))) (let ((.cse11 (not .cse16)) (.cse6 (or .cse14 .cse16)) (.cse8 (not .cse15)) (.cse3 (not .cse4)) (.cse9 (or .cse15 .cse4)) (.cse13 (or .cse14 .cse5)) (.cse0 (not .cse5)) (.cse12 (not .cse14)) (.cse10 (select |v_#memory_int_258| |v_~#x~0.base_162|))) (and (let ((.cse2 (= (mod v_~x$w_buff1_used~0_331 256) 0)) (.cse1 (= (mod v_~x$r_buff0_thd3~0_61 256) 0))) (or (and (= v_~x$r_buff1_thd3~0_55 0) (or (and .cse0 (not .cse1)) (and (not .cse2) .cse3))) (and (= v_~x$r_buff1_thd3~0_56 v_~x$r_buff1_thd3~0_55) (or .cse2 .cse4) (or .cse5 .cse1)))) (let ((.cse7 (= |v_P2_#t~mem68_38| |v_P2Thread1of1ForFork2_#t~mem68_1|))) (or (and (= |v_P2_#t~ite69_39| |v_P2_#t~ite70_33|) .cse6 (or (and .cse7 (= |v_P2_#t~ite69_39| v_~x$w_buff1~0_86) .cse3 .cse8) (and .cse9 (= |v_P2_#t~ite69_39| |v_P2_#t~mem68_38|) (= |v_P2_#t~mem68_38| (select .cse10 |v_~#x~0.offset_162|))))) (and (= |v_P2_#t~ite69_39| |v_P2Thread1of1ForFork2_#t~ite69_1|) .cse7 .cse11 (= |v_P2_#t~ite70_33| v_~x$w_buff0~0_115) .cse12))) (or (and .cse11 (= v_~x$w_buff0_used~0_416 0) .cse12) (and .cse6 (= v_~x$w_buff0_used~0_417 v_~x$w_buff0_used~0_416))) (or (and (= v_~x$w_buff1_used~0_331 0) (or (and .cse0 .cse12) (and .cse8 .cse3))) (and .cse9 .cse13 (= v_~x$w_buff1_used~0_332 v_~x$w_buff1_used~0_331))) (or (and .cse13 (= v_~x$r_buff0_thd3~0_62 v_~x$r_buff0_thd3~0_61)) (and .cse0 (= v_~x$r_buff0_thd3~0_61 0) .cse12)) (= (store |v_#memory_int_258| |v_~#x~0.base_162| (store .cse10 |v_~#x~0.offset_162| |v_P2_#t~ite70_33|)) |v_#memory_int_257|)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_115, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_1|, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_1|, #memory_int=|v_#memory_int_258|, ~#x~0.base=|v_~#x~0.base_162|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_56, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_332, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_62, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_417} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_115, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_2|, P2Thread1of1ForFork2_#t~ite73=|v_P2Thread1of1ForFork2_#t~ite73_1|, P2Thread1of1ForFork2_#t~ite72=|v_P2Thread1of1ForFork2_#t~ite72_1|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_55, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_331, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_1|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_61, P2Thread1of1ForFork2_#t~ite71=|v_P2Thread1of1ForFork2_#t~ite71_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_416, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_2|, P2Thread1of1ForFork2_#t~ite74=|v_P2Thread1of1ForFork2_#t~ite74_1|, #memory_int=|v_#memory_int_257|, ~#x~0.base=|v_~#x~0.base_162|} AuxVars[|v_P2_#t~ite70_33|, |v_P2_#t~mem68_38|, |v_P2_#t~ite69_39|] AssignedVars[P2Thread1of1ForFork2_#t~ite69, P2Thread1of1ForFork2_#t~mem68, P2Thread1of1ForFork2_#t~ite74, P2Thread1of1ForFork2_#t~ite73, P2Thread1of1ForFork2_#t~ite72, #memory_int, ~x$r_buff1_thd3~0, ~x$w_buff1_used~0, P2Thread1of1ForFork2_#t~ite70, ~x$r_buff0_thd3~0, P2Thread1of1ForFork2_#t~ite71, ~x$w_buff0_used~0] and [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] under condition 230785#(and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (<= 1 ~main$tmp_guard1~0) (= ~x$r_buff1_thd2~0 0) (<= (div ~main$tmp_guard1~0 256) 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)) [2021-01-26 22:49:35,876 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:36,176 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:36,269 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:40,349 WARN L146 IndependenceRelation]: Expensive independence query (4079 ms) for statements [1364] L829-->L836: Formula: (let ((.cse5 (= (mod v_~x$w_buff0_used~0_416 256) 0)) (.cse4 (= (mod v_~x$r_buff1_thd3~0_56 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_332 256) 0)) (.cse14 (= 0 (mod v_~x$r_buff0_thd3~0_62 256))) (.cse16 (= (mod v_~x$w_buff0_used~0_417 256) 0))) (let ((.cse11 (not .cse16)) (.cse6 (or .cse14 .cse16)) (.cse8 (not .cse15)) (.cse3 (not .cse4)) (.cse9 (or .cse15 .cse4)) (.cse13 (or .cse14 .cse5)) (.cse0 (not .cse5)) (.cse12 (not .cse14)) (.cse10 (select |v_#memory_int_258| |v_~#x~0.base_162|))) (and (let ((.cse2 (= (mod v_~x$w_buff1_used~0_331 256) 0)) (.cse1 (= (mod v_~x$r_buff0_thd3~0_61 256) 0))) (or (and (= v_~x$r_buff1_thd3~0_55 0) (or (and .cse0 (not .cse1)) (and (not .cse2) .cse3))) (and (= v_~x$r_buff1_thd3~0_56 v_~x$r_buff1_thd3~0_55) (or .cse2 .cse4) (or .cse5 .cse1)))) (let ((.cse7 (= |v_P2_#t~mem68_38| |v_P2Thread1of1ForFork2_#t~mem68_1|))) (or (and (= |v_P2_#t~ite69_39| |v_P2_#t~ite70_33|) .cse6 (or (and .cse7 (= |v_P2_#t~ite69_39| v_~x$w_buff1~0_86) .cse3 .cse8) (and .cse9 (= |v_P2_#t~ite69_39| |v_P2_#t~mem68_38|) (= |v_P2_#t~mem68_38| (select .cse10 |v_~#x~0.offset_162|))))) (and (= |v_P2_#t~ite69_39| |v_P2Thread1of1ForFork2_#t~ite69_1|) .cse7 .cse11 (= |v_P2_#t~ite70_33| v_~x$w_buff0~0_115) .cse12))) (or (and .cse11 (= v_~x$w_buff0_used~0_416 0) .cse12) (and .cse6 (= v_~x$w_buff0_used~0_417 v_~x$w_buff0_used~0_416))) (or (and (= v_~x$w_buff1_used~0_331 0) (or (and .cse0 .cse12) (and .cse8 .cse3))) (and .cse9 .cse13 (= v_~x$w_buff1_used~0_332 v_~x$w_buff1_used~0_331))) (or (and .cse13 (= v_~x$r_buff0_thd3~0_62 v_~x$r_buff0_thd3~0_61)) (and .cse0 (= v_~x$r_buff0_thd3~0_61 0) .cse12)) (= (store |v_#memory_int_258| |v_~#x~0.base_162| (store .cse10 |v_~#x~0.offset_162| |v_P2_#t~ite70_33|)) |v_#memory_int_257|)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_115, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_1|, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_1|, #memory_int=|v_#memory_int_258|, ~#x~0.base=|v_~#x~0.base_162|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_56, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_332, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_62, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_417} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_115, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_2|, P2Thread1of1ForFork2_#t~ite73=|v_P2Thread1of1ForFork2_#t~ite73_1|, P2Thread1of1ForFork2_#t~ite72=|v_P2Thread1of1ForFork2_#t~ite72_1|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_55, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_331, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_1|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_61, P2Thread1of1ForFork2_#t~ite71=|v_P2Thread1of1ForFork2_#t~ite71_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_416, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_2|, P2Thread1of1ForFork2_#t~ite74=|v_P2Thread1of1ForFork2_#t~ite74_1|, #memory_int=|v_#memory_int_257|, ~#x~0.base=|v_~#x~0.base_162|} AuxVars[|v_P2_#t~ite70_33|, |v_P2_#t~mem68_38|, |v_P2_#t~ite69_39|] AssignedVars[P2Thread1of1ForFork2_#t~ite69, P2Thread1of1ForFork2_#t~mem68, P2Thread1of1ForFork2_#t~ite74, P2Thread1of1ForFork2_#t~ite73, P2Thread1of1ForFork2_#t~ite72, #memory_int, ~x$r_buff1_thd3~0, ~x$w_buff1_used~0, P2Thread1of1ForFork2_#t~ite70, ~x$r_buff0_thd3~0, P2Thread1of1ForFork2_#t~ite71, ~x$w_buff0_used~0] and [1357] L809-->L816: Formula: (let ((.cse4 (= (mod v_~x$w_buff0_used~0_502 256) 0)) (.cse5 (= (mod v_~x$r_buff1_thd2~0_258 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_422 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd2~0_292 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_503 256) 0))) (let ((.cse13 (not .cse16)) (.cse8 (or .cse14 .cse16)) (.cse9 (select |v_#memory_int_296| |v_~#x~0.base_186|)) (.cse12 (not .cse15)) (.cse7 (not .cse5)) (.cse1 (not .cse4)) (.cse2 (not .cse14)) (.cse10 (or .cse5 .cse15)) (.cse0 (or .cse14 .cse4))) (and (or (and (= v_~x$r_buff0_thd2~0_291 v_~x$r_buff0_thd2~0_292) .cse0) (and .cse1 (= v_~x$r_buff0_thd2~0_291 0) .cse2)) (let ((.cse6 (= (mod v_~x$w_buff1_used~0_421 256) 0)) (.cse3 (= (mod v_~x$r_buff0_thd2~0_291 256) 0))) (or (and (or .cse3 .cse4) (= v_~x$r_buff1_thd2~0_258 v_~x$r_buff1_thd2~0_257) (or .cse5 .cse6)) (and (= v_~x$r_buff1_thd2~0_257 0) (or (and (not .cse6) .cse7) (and .cse1 (not .cse3)))))) (let ((.cse11 (= |v_P1_#t~mem61_50| |v_P1Thread1of1ForFork1_#t~mem61_1|))) (or (and .cse8 (or (and (= |v_P1_#t~ite62_49| |v_P1_#t~mem61_50|) (= (select .cse9 |v_~#x~0.offset_186|) |v_P1_#t~mem61_50|) .cse10) (and (= |v_P1_#t~ite62_49| v_~x$w_buff1~0_126) .cse11 .cse12 .cse7)) (= |v_P1_#t~ite62_49| |v_P1_#t~ite63_43|)) (and .cse13 .cse11 (= |v_P1_#t~ite62_49| |v_P1Thread1of1ForFork1_#t~ite62_1|) .cse2 (= |v_P1_#t~ite63_43| v_~x$w_buff0~0_133)))) (or (and .cse13 (= v_~x$w_buff0_used~0_502 0) .cse2) (and (= v_~x$w_buff0_used~0_503 v_~x$w_buff0_used~0_502) .cse8)) (= (store |v_#memory_int_296| |v_~#x~0.base_186| (store .cse9 |v_~#x~0.offset_186| |v_P1_#t~ite63_43|)) |v_#memory_int_295|) (or (and (= v_~x$w_buff1_used~0_421 0) (or (and .cse12 .cse7) (and .cse1 .cse2))) (and .cse10 (= v_~x$w_buff1_used~0_422 v_~x$w_buff1_used~0_421) .cse0))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_133, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_1|, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, #memory_int=|v_#memory_int_296|, ~#x~0.base=|v_~#x~0.base_186|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_422, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_258, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_292, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_503} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_133, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_257, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_421, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_291, P1Thread1of1ForFork1_#t~ite65=|v_P1Thread1of1ForFork1_#t~ite65_1|, P1Thread1of1ForFork1_#t~ite66=|v_P1Thread1of1ForFork1_#t~ite66_1|, P1Thread1of1ForFork1_#t~ite67=|v_P1Thread1of1ForFork1_#t~ite67_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_502, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_2|, P1Thread1of1ForFork1_#t~ite63=|v_P1Thread1of1ForFork1_#t~ite63_1|, P1Thread1of1ForFork1_#t~ite64=|v_P1Thread1of1ForFork1_#t~ite64_1|, #memory_int=|v_#memory_int_295|, ~#x~0.base=|v_~#x~0.base_186|} AuxVars[|v_P1_#t~ite62_49|, |v_P1_#t~mem61_50|, |v_P1_#t~ite63_43|] AssignedVars[P1Thread1of1ForFork1_#t~ite62, P1Thread1of1ForFork1_#t~ite63, P1Thread1of1ForFork1_#t~ite64, #memory_int, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, P1Thread1of1ForFork1_#t~mem61, ~x$r_buff0_thd2~0, P1Thread1of1ForFork1_#t~ite65, P1Thread1of1ForFork1_#t~ite66, P1Thread1of1ForFork1_#t~ite67, ~x$w_buff0_used~0] under condition 230795#(and (<= 1 ~main$tmp_guard1~0) (= (select |#valid| |~#x~0.base|) 1) (<= (div ~main$tmp_guard1~0 256) 0) (= |~#x~0.offset| 0)) [2021-01-26 22:49:40,427 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:44,592 WARN L146 IndependenceRelation]: Expensive independence query (4082 ms) for statements [1350] L773-->L780: Formula: (let ((.cse10 (= (mod v_~x$r_buff1_thd1~0_52 256) 0)) (.cse14 (= 0 (mod v_~x$w_buff1_used~0_366 256))) (.cse9 (= (mod v_~x$w_buff0_used~0_446 256) 0)) (.cse15 (= (mod v_~x$r_buff0_thd1~0_75 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_447 256) 0))) (let ((.cse4 (not .cse16)) (.cse5 (or .cse15 .cse16)) (.cse3 (select |v_#memory_int_270| |v_~#x~0.base_172|)) (.cse1 (not .cse15)) (.cse2 (not .cse9)) (.cse13 (not .cse14)) (.cse8 (not .cse10)) (.cse0 (or .cse15 .cse9)) (.cse12 (or .cse14 .cse10))) (and (or (and .cse0 (= v_~x$r_buff0_thd1~0_75 v_~x$r_buff0_thd1~0_74)) (and .cse1 .cse2 (= v_~x$r_buff0_thd1~0_74 0))) (= (store |v_#memory_int_270| |v_~#x~0.base_172| (store .cse3 |v_~#x~0.offset_172| |v_P0_#t~ite7_39|)) |v_#memory_int_269|) (or (and .cse1 .cse4 (= v_~x$w_buff0_used~0_446 0)) (and .cse5 (= v_~x$w_buff0_used~0_447 v_~x$w_buff0_used~0_446))) (let ((.cse6 (= (mod v_~x$r_buff0_thd1~0_74 256) 0)) (.cse7 (= (mod v_~x$w_buff1_used~0_365 256) 0))) (or (and (= v_~x$r_buff1_thd1~0_51 0) (or (and (not .cse6) .cse2) (and (not .cse7) .cse8))) (and (or .cse9 .cse6) (= v_~x$r_buff1_thd1~0_52 v_~x$r_buff1_thd1~0_51) (or .cse7 .cse10)))) (let ((.cse11 (= |v_P0Thread1of1ForFork0_#t~mem5_1| |v_P0_#t~mem5_38|))) (or (and .cse11 .cse1 .cse4 (= |v_P0Thread1of1ForFork0_#t~ite6_1| |v_P0_#t~ite6_33|) (= |v_P0_#t~ite7_39| v_~x$w_buff0~0_117)) (and .cse5 (= |v_P0_#t~ite7_39| |v_P0_#t~ite6_33|) (or (and .cse12 (= |v_P0_#t~ite6_33| |v_P0_#t~mem5_38|) (= |v_P0_#t~mem5_38| (select .cse3 |v_~#x~0.offset_172|))) (and .cse11 (= |v_P0_#t~ite6_33| v_~x$w_buff1~0_96) .cse13 .cse8))))) (or (and (or (and .cse1 .cse2) (and .cse13 .cse8)) (= v_~x$w_buff1_used~0_365 0)) (and .cse0 .cse12 (= v_~x$w_buff1_used~0_366 v_~x$w_buff1_used~0_365)))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_1|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_75, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, #memory_int=|v_#memory_int_270|, ~#x~0.base=|v_~#x~0.base_172|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_366, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_52, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_447} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_117, P0Thread1of1ForFork0_#t~ite11=|v_P0Thread1of1ForFork0_#t~ite11_1|, P0Thread1of1ForFork0_#t~ite10=|v_P0Thread1of1ForFork0_#t~ite10_1|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_74, ~#x~0.offset=|v_~#x~0.offset_172|, ~x$w_buff1~0=v_~x$w_buff1~0_96, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_365, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_51, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_446, P0Thread1of1ForFork0_#t~ite6=|v_P0Thread1of1ForFork0_#t~ite6_2|, P0Thread1of1ForFork0_#t~mem5=|v_P0Thread1of1ForFork0_#t~mem5_2|, P0Thread1of1ForFork0_#t~ite9=|v_P0Thread1of1ForFork0_#t~ite9_1|, P0Thread1of1ForFork0_#t~ite7=|v_P0Thread1of1ForFork0_#t~ite7_1|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_1|, #memory_int=|v_#memory_int_269|, ~#x~0.base=|v_~#x~0.base_172|} AuxVars[|v_P0_#t~ite7_39|, |v_P0_#t~mem5_38|, |v_P0_#t~ite6_33|] AssignedVars[P0Thread1of1ForFork0_#t~ite11, P0Thread1of1ForFork0_#t~ite10, P0Thread1of1ForFork0_#t~ite6, P0Thread1of1ForFork0_#t~mem5, ~x$r_buff0_thd1~0, P0Thread1of1ForFork0_#t~ite9, P0Thread1of1ForFork0_#t~ite7, P0Thread1of1ForFork0_#t~ite8, #memory_int, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$w_buff0_used~0] and [1357] L809-->L816: Formula: (let ((.cse4 (= (mod v_~x$w_buff0_used~0_502 256) 0)) (.cse5 (= (mod v_~x$r_buff1_thd2~0_258 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_422 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd2~0_292 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_503 256) 0))) (let ((.cse13 (not .cse16)) (.cse8 (or .cse14 .cse16)) (.cse9 (select |v_#memory_int_296| |v_~#x~0.base_186|)) (.cse12 (not .cse15)) (.cse7 (not .cse5)) (.cse1 (not .cse4)) (.cse2 (not .cse14)) (.cse10 (or .cse5 .cse15)) (.cse0 (or .cse14 .cse4))) (and (or (and (= v_~x$r_buff0_thd2~0_291 v_~x$r_buff0_thd2~0_292) .cse0) (and .cse1 (= v_~x$r_buff0_thd2~0_291 0) .cse2)) (let ((.cse6 (= (mod v_~x$w_buff1_used~0_421 256) 0)) (.cse3 (= (mod v_~x$r_buff0_thd2~0_291 256) 0))) (or (and (or .cse3 .cse4) (= v_~x$r_buff1_thd2~0_258 v_~x$r_buff1_thd2~0_257) (or .cse5 .cse6)) (and (= v_~x$r_buff1_thd2~0_257 0) (or (and (not .cse6) .cse7) (and .cse1 (not .cse3)))))) (let ((.cse11 (= |v_P1_#t~mem61_50| |v_P1Thread1of1ForFork1_#t~mem61_1|))) (or (and .cse8 (or (and (= |v_P1_#t~ite62_49| |v_P1_#t~mem61_50|) (= (select .cse9 |v_~#x~0.offset_186|) |v_P1_#t~mem61_50|) .cse10) (and (= |v_P1_#t~ite62_49| v_~x$w_buff1~0_126) .cse11 .cse12 .cse7)) (= |v_P1_#t~ite62_49| |v_P1_#t~ite63_43|)) (and .cse13 .cse11 (= |v_P1_#t~ite62_49| |v_P1Thread1of1ForFork1_#t~ite62_1|) .cse2 (= |v_P1_#t~ite63_43| v_~x$w_buff0~0_133)))) (or (and .cse13 (= v_~x$w_buff0_used~0_502 0) .cse2) (and (= v_~x$w_buff0_used~0_503 v_~x$w_buff0_used~0_502) .cse8)) (= (store |v_#memory_int_296| |v_~#x~0.base_186| (store .cse9 |v_~#x~0.offset_186| |v_P1_#t~ite63_43|)) |v_#memory_int_295|) (or (and (= v_~x$w_buff1_used~0_421 0) (or (and .cse12 .cse7) (and .cse1 .cse2))) (and .cse10 (= v_~x$w_buff1_used~0_422 v_~x$w_buff1_used~0_421) .cse0))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_133, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_1|, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, #memory_int=|v_#memory_int_296|, ~#x~0.base=|v_~#x~0.base_186|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_422, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_258, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_292, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_503} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_133, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_257, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_421, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_291, P1Thread1of1ForFork1_#t~ite65=|v_P1Thread1of1ForFork1_#t~ite65_1|, P1Thread1of1ForFork1_#t~ite66=|v_P1Thread1of1ForFork1_#t~ite66_1|, P1Thread1of1ForFork1_#t~ite67=|v_P1Thread1of1ForFork1_#t~ite67_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_502, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_2|, P1Thread1of1ForFork1_#t~ite63=|v_P1Thread1of1ForFork1_#t~ite63_1|, P1Thread1of1ForFork1_#t~ite64=|v_P1Thread1of1ForFork1_#t~ite64_1|, #memory_int=|v_#memory_int_295|, ~#x~0.base=|v_~#x~0.base_186|} AuxVars[|v_P1_#t~ite62_49|, |v_P1_#t~mem61_50|, |v_P1_#t~ite63_43|] AssignedVars[P1Thread1of1ForFork1_#t~ite62, P1Thread1of1ForFork1_#t~ite63, P1Thread1of1ForFork1_#t~ite64, #memory_int, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, P1Thread1of1ForFork1_#t~mem61, ~x$r_buff0_thd2~0, P1Thread1of1ForFork1_#t~ite65, P1Thread1of1ForFork1_#t~ite66, P1Thread1of1ForFork1_#t~ite67, ~x$w_buff0_used~0] under condition 230795#(and (<= 1 ~main$tmp_guard1~0) (= (select |#valid| |~#x~0.base|) 1) (<= (div ~main$tmp_guard1~0 256) 0) (= |~#x~0.offset| 0)) [2021-01-26 22:49:44,636 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:45,244 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:45,326 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:45,433 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:45,856 WARN L193 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 59 [2021-01-26 22:49:45,899 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:46,188 WARN L193 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 64 [2021-01-26 22:49:46,362 WARN L193 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 61 [2021-01-26 22:49:46,514 WARN L193 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 52 [2021-01-26 22:49:46,654 WARN L193 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 49 [2021-01-26 22:49:47,061 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:47,216 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:48,448 WARN L146 IndependenceRelation]: Expensive independence query (1231 ms) for statements [1349] L761-->L773: Formula: (and (= |v_P0Thread1of1ForFork0_reach_error_#t~nondet2.base_3| |v_P0Thread1of1ForFork0_reach_error_#t~nondet2.base_4|) (= v_~x$w_buff0_used~0_Out_3 1) (= (ite (not (and (not (= (mod v_~x$w_buff0_used~0_Out_3 256) 0)) (not (= (mod v_~x$w_buff1_used~0_Out_3 256) 0)))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_3|) (= v_~x$r_buff0_thd1~0_Out_1 1) (= v_~x$w_buff1~0_Out_3 v_~x$w_buff0~0_In_35) (= v_~x$r_buff1_thd2~0_Out_1 v_~x$r_buff0_thd2~0_In_79) (= |v_P0Thread1of1ForFork0_reach_error_#t~nondet2.offset_3| |v_P0Thread1of1ForFork0_reach_error_#t~nondet2.offset_4|) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_3 0)) (= v_~x$w_buff1_used~0_Out_3 v_~x$w_buff0_used~0_In_109) (= v_~x$r_buff1_thd1~0_Out_1 v_~x$r_buff0_thd1~0_In_11) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_3 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_3|) (= v_~x$r_buff0_thd3~0_In_11 v_~x$r_buff1_thd3~0_Out_1) (= v_~x$r_buff1_thd0~0_Out_1 v_~x$r_buff0_thd0~0_In_11) (= v_~x$w_buff0~0_Out_3 1)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_In_35, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_In_11, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_In_11, P0Thread1of1ForFork0_reach_error_#t~nondet2.offset=|v_P0Thread1of1ForFork0_reach_error_#t~nondet2.offset_3|, P0Thread1of1ForFork0_reach_error_#t~nondet2.base=|v_P0Thread1of1ForFork0_reach_error_#t~nondet2.base_3|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_In_11, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_In_79, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_In_109} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_Out_3, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_In_11, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_Out_1, ~x$w_buff1~0=v_~x$w_buff1~0_Out_3, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_Out_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_Out_1, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_Out_3, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_Out_1, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_In_11, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_In_79, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_Out_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_Out_3, P0Thread1of1ForFork0_reach_error_#t~nondet2.offset=|v_P0Thread1of1ForFork0_reach_error_#t~nondet2.offset_4|, P0Thread1of1ForFork0_reach_error_#t~nondet2.base=|v_P0Thread1of1ForFork0_reach_error_#t~nondet2.base_4|, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_3, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_3|} AuxVars[] AssignedVars[~x$w_buff0~0, ~x$r_buff0_thd1~0, ~x$w_buff1~0, ~x$r_buff1_thd3~0, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$r_buff1_thd0~0, ~x$w_buff0_used~0, P0Thread1of1ForFork0_reach_error_#t~nondet2.offset, P0Thread1of1ForFork0_reach_error_#t~nondet2.base, P0Thread1of1ForFork0___VERIFIER_assert_~expression, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression] and [1357] L809-->L816: Formula: (let ((.cse4 (= (mod v_~x$w_buff0_used~0_502 256) 0)) (.cse5 (= (mod v_~x$r_buff1_thd2~0_258 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_422 256) 0)) (.cse14 (= (mod v_~x$r_buff0_thd2~0_292 256) 0)) (.cse16 (= (mod v_~x$w_buff0_used~0_503 256) 0))) (let ((.cse13 (not .cse16)) (.cse8 (or .cse14 .cse16)) (.cse9 (select |v_#memory_int_296| |v_~#x~0.base_186|)) (.cse12 (not .cse15)) (.cse7 (not .cse5)) (.cse1 (not .cse4)) (.cse2 (not .cse14)) (.cse10 (or .cse5 .cse15)) (.cse0 (or .cse14 .cse4))) (and (or (and (= v_~x$r_buff0_thd2~0_291 v_~x$r_buff0_thd2~0_292) .cse0) (and .cse1 (= v_~x$r_buff0_thd2~0_291 0) .cse2)) (let ((.cse6 (= (mod v_~x$w_buff1_used~0_421 256) 0)) (.cse3 (= (mod v_~x$r_buff0_thd2~0_291 256) 0))) (or (and (or .cse3 .cse4) (= v_~x$r_buff1_thd2~0_258 v_~x$r_buff1_thd2~0_257) (or .cse5 .cse6)) (and (= v_~x$r_buff1_thd2~0_257 0) (or (and (not .cse6) .cse7) (and .cse1 (not .cse3)))))) (let ((.cse11 (= |v_P1_#t~mem61_50| |v_P1Thread1of1ForFork1_#t~mem61_1|))) (or (and .cse8 (or (and (= |v_P1_#t~ite62_49| |v_P1_#t~mem61_50|) (= (select .cse9 |v_~#x~0.offset_186|) |v_P1_#t~mem61_50|) .cse10) (and (= |v_P1_#t~ite62_49| v_~x$w_buff1~0_126) .cse11 .cse12 .cse7)) (= |v_P1_#t~ite62_49| |v_P1_#t~ite63_43|)) (and .cse13 .cse11 (= |v_P1_#t~ite62_49| |v_P1Thread1of1ForFork1_#t~ite62_1|) .cse2 (= |v_P1_#t~ite63_43| v_~x$w_buff0~0_133)))) (or (and .cse13 (= v_~x$w_buff0_used~0_502 0) .cse2) (and (= v_~x$w_buff0_used~0_503 v_~x$w_buff0_used~0_502) .cse8)) (= (store |v_#memory_int_296| |v_~#x~0.base_186| (store .cse9 |v_~#x~0.offset_186| |v_P1_#t~ite63_43|)) |v_#memory_int_295|) (or (and (= v_~x$w_buff1_used~0_421 0) (or (and .cse12 .cse7) (and .cse1 .cse2))) (and .cse10 (= v_~x$w_buff1_used~0_422 v_~x$w_buff1_used~0_421) .cse0))))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_133, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_1|, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, #memory_int=|v_#memory_int_296|, ~#x~0.base=|v_~#x~0.base_186|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_422, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_258, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_292, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_503} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_133, ~#x~0.offset=|v_~#x~0.offset_186|, ~x$w_buff1~0=v_~x$w_buff1~0_126, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_257, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_421, P1Thread1of1ForFork1_#t~mem61=|v_P1Thread1of1ForFork1_#t~mem61_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_291, P1Thread1of1ForFork1_#t~ite65=|v_P1Thread1of1ForFork1_#t~ite65_1|, P1Thread1of1ForFork1_#t~ite66=|v_P1Thread1of1ForFork1_#t~ite66_1|, P1Thread1of1ForFork1_#t~ite67=|v_P1Thread1of1ForFork1_#t~ite67_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_502, P1Thread1of1ForFork1_#t~ite62=|v_P1Thread1of1ForFork1_#t~ite62_2|, P1Thread1of1ForFork1_#t~ite63=|v_P1Thread1of1ForFork1_#t~ite63_1|, P1Thread1of1ForFork1_#t~ite64=|v_P1Thread1of1ForFork1_#t~ite64_1|, #memory_int=|v_#memory_int_295|, ~#x~0.base=|v_~#x~0.base_186|} AuxVars[|v_P1_#t~ite62_49|, |v_P1_#t~mem61_50|, |v_P1_#t~ite63_43|] AssignedVars[P1Thread1of1ForFork1_#t~ite62, P1Thread1of1ForFork1_#t~ite63, P1Thread1of1ForFork1_#t~ite64, #memory_int, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, P1Thread1of1ForFork1_#t~mem61, ~x$r_buff0_thd2~0, P1Thread1of1ForFork1_#t~ite65, P1Thread1of1ForFork1_#t~ite66, P1Thread1of1ForFork1_#t~ite67, ~x$w_buff0_used~0] under condition 230795#(and (<= 1 ~main$tmp_guard1~0) (= (select |#valid| |~#x~0.base|) 1) (<= (div ~main$tmp_guard1~0 256) 0) (= |~#x~0.offset| 0)) [2021-01-26 22:49:48,519 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:48,859 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:50,530 WARN L146 IndependenceRelation]: Expensive independence query (1271 ms) for statements [1364] L829-->L836: Formula: (let ((.cse5 (= (mod v_~x$w_buff0_used~0_416 256) 0)) (.cse4 (= (mod v_~x$r_buff1_thd3~0_56 256) 0)) (.cse15 (= (mod v_~x$w_buff1_used~0_332 256) 0)) (.cse14 (= 0 (mod v_~x$r_buff0_thd3~0_62 256))) (.cse16 (= (mod v_~x$w_buff0_used~0_417 256) 0))) (let ((.cse11 (not .cse16)) (.cse6 (or .cse14 .cse16)) (.cse8 (not .cse15)) (.cse3 (not .cse4)) (.cse9 (or .cse15 .cse4)) (.cse13 (or .cse14 .cse5)) (.cse0 (not .cse5)) (.cse12 (not .cse14)) (.cse10 (select |v_#memory_int_258| |v_~#x~0.base_162|))) (and (let ((.cse2 (= (mod v_~x$w_buff1_used~0_331 256) 0)) (.cse1 (= (mod v_~x$r_buff0_thd3~0_61 256) 0))) (or (and (= v_~x$r_buff1_thd3~0_55 0) (or (and .cse0 (not .cse1)) (and (not .cse2) .cse3))) (and (= v_~x$r_buff1_thd3~0_56 v_~x$r_buff1_thd3~0_55) (or .cse2 .cse4) (or .cse5 .cse1)))) (let ((.cse7 (= |v_P2_#t~mem68_38| |v_P2Thread1of1ForFork2_#t~mem68_1|))) (or (and (= |v_P2_#t~ite69_39| |v_P2_#t~ite70_33|) .cse6 (or (and .cse7 (= |v_P2_#t~ite69_39| v_~x$w_buff1~0_86) .cse3 .cse8) (and .cse9 (= |v_P2_#t~ite69_39| |v_P2_#t~mem68_38|) (= |v_P2_#t~mem68_38| (select .cse10 |v_~#x~0.offset_162|))))) (and (= |v_P2_#t~ite69_39| |v_P2Thread1of1ForFork2_#t~ite69_1|) .cse7 .cse11 (= |v_P2_#t~ite70_33| v_~x$w_buff0~0_115) .cse12))) (or (and .cse11 (= v_~x$w_buff0_used~0_416 0) .cse12) (and .cse6 (= v_~x$w_buff0_used~0_417 v_~x$w_buff0_used~0_416))) (or (and (= v_~x$w_buff1_used~0_331 0) (or (and .cse0 .cse12) (and .cse8 .cse3))) (and .cse9 .cse13 (= v_~x$w_buff1_used~0_332 v_~x$w_buff1_used~0_331))) (or (and .cse13 (= v_~x$r_buff0_thd3~0_62 v_~x$r_buff0_thd3~0_61)) (and .cse0 (= v_~x$r_buff0_thd3~0_61 0) .cse12)) (= (store |v_#memory_int_258| |v_~#x~0.base_162| (store .cse10 |v_~#x~0.offset_162| |v_P2_#t~ite70_33|)) |v_#memory_int_257|)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_115, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_1|, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_1|, #memory_int=|v_#memory_int_258|, ~#x~0.base=|v_~#x~0.base_162|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_56, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_332, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_62, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_417} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_115, ~#x~0.offset=|v_~#x~0.offset_162|, ~x$w_buff1~0=v_~x$w_buff1~0_86, P2Thread1of1ForFork2_#t~mem68=|v_P2Thread1of1ForFork2_#t~mem68_2|, P2Thread1of1ForFork2_#t~ite73=|v_P2Thread1of1ForFork2_#t~ite73_1|, P2Thread1of1ForFork2_#t~ite72=|v_P2Thread1of1ForFork2_#t~ite72_1|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_55, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_331, P2Thread1of1ForFork2_#t~ite70=|v_P2Thread1of1ForFork2_#t~ite70_1|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_61, P2Thread1of1ForFork2_#t~ite71=|v_P2Thread1of1ForFork2_#t~ite71_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_416, P2Thread1of1ForFork2_#t~ite69=|v_P2Thread1of1ForFork2_#t~ite69_2|, P2Thread1of1ForFork2_#t~ite74=|v_P2Thread1of1ForFork2_#t~ite74_1|, #memory_int=|v_#memory_int_257|, ~#x~0.base=|v_~#x~0.base_162|} AuxVars[|v_P2_#t~ite70_33|, |v_P2_#t~mem68_38|, |v_P2_#t~ite69_39|] AssignedVars[P2Thread1of1ForFork2_#t~ite69, P2Thread1of1ForFork2_#t~mem68, P2Thread1of1ForFork2_#t~ite74, P2Thread1of1ForFork2_#t~ite73, P2Thread1of1ForFork2_#t~ite72, #memory_int, ~x$r_buff1_thd3~0, ~x$w_buff1_used~0, P2Thread1of1ForFork2_#t~ite70, ~x$r_buff0_thd3~0, P2Thread1of1ForFork2_#t~ite71, ~x$w_buff0_used~0] and [1349] L761-->L773: Formula: (and (= |v_P0Thread1of1ForFork0_reach_error_#t~nondet2.base_3| |v_P0Thread1of1ForFork0_reach_error_#t~nondet2.base_4|) (= v_~x$w_buff0_used~0_Out_3 1) (= (ite (not (and (not (= (mod v_~x$w_buff0_used~0_Out_3 256) 0)) (not (= (mod v_~x$w_buff1_used~0_Out_3 256) 0)))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_3|) (= v_~x$r_buff0_thd1~0_Out_1 1) (= v_~x$w_buff1~0_Out_3 v_~x$w_buff0~0_In_35) (= v_~x$r_buff1_thd2~0_Out_1 v_~x$r_buff0_thd2~0_In_79) (= |v_P0Thread1of1ForFork0_reach_error_#t~nondet2.offset_3| |v_P0Thread1of1ForFork0_reach_error_#t~nondet2.offset_4|) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_3 0)) (= v_~x$w_buff1_used~0_Out_3 v_~x$w_buff0_used~0_In_109) (= v_~x$r_buff1_thd1~0_Out_1 v_~x$r_buff0_thd1~0_In_11) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_3 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_3|) (= v_~x$r_buff0_thd3~0_In_11 v_~x$r_buff1_thd3~0_Out_1) (= v_~x$r_buff1_thd0~0_Out_1 v_~x$r_buff0_thd0~0_In_11) (= v_~x$w_buff0~0_Out_3 1)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_In_35, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_In_11, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_In_11, P0Thread1of1ForFork0_reach_error_#t~nondet2.offset=|v_P0Thread1of1ForFork0_reach_error_#t~nondet2.offset_3|, P0Thread1of1ForFork0_reach_error_#t~nondet2.base=|v_P0Thread1of1ForFork0_reach_error_#t~nondet2.base_3|, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_In_11, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_In_79, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_In_109} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_Out_3, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_In_11, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_Out_1, ~x$w_buff1~0=v_~x$w_buff1~0_Out_3, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_Out_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_Out_1, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_Out_3, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_Out_1, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_In_11, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_In_79, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_Out_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_Out_3, P0Thread1of1ForFork0_reach_error_#t~nondet2.offset=|v_P0Thread1of1ForFork0_reach_error_#t~nondet2.offset_4|, P0Thread1of1ForFork0_reach_error_#t~nondet2.base=|v_P0Thread1of1ForFork0_reach_error_#t~nondet2.base_4|, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_3, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_3|} AuxVars[] AssignedVars[~x$w_buff0~0, ~x$r_buff0_thd1~0, ~x$w_buff1~0, ~x$r_buff1_thd3~0, ~x$r_buff1_thd2~0, ~x$w_buff1_used~0, ~x$r_buff1_thd1~0, ~x$r_buff1_thd0~0, ~x$w_buff0_used~0, P0Thread1of1ForFork0_reach_error_#t~nondet2.offset, P0Thread1of1ForFork0_reach_error_#t~nondet2.base, P0Thread1of1ForFork0___VERIFIER_assert_~expression, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression] under condition 198791#(and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)) Size of Word is: 100 and size of Sequence is : 101[2021-01-26 22:49:51,948 INFO L164 SleepSetCegar]: Size of mCounterexample is: 101 [2021-01-26 22:49:51,951 INFO L165 SleepSetCegar]: [198811#[ULTIMATE.startENTRY]true, 198813#[L-1]true, 198815#[L-1-1]true, 198817#[L17]true, 198819#[L17-1]true, 198821#[L17-2]true, 198823#[L17-3]true, 198825#[L17-4]true, 198827#[L711]true, 198829#[L713](= ~__unbuffered_p0_EAX~0 0), 198831#[L714](= ~__unbuffered_p0_EAX~0 0), 198833#[L715](= ~__unbuffered_p0_EAX~0 0), 198835#[L716](= ~__unbuffered_p0_EAX~0 0), 198837#[L717](= ~__unbuffered_p0_EAX~0 0), 198839#[L718](= ~__unbuffered_p0_EAX~0 0), 198841#[L719](= ~__unbuffered_p0_EAX~0 0), 198843#[L720](= ~__unbuffered_p0_EAX~0 0), 198845#[L721](= ~__unbuffered_p0_EAX~0 0), 198847#[L722](= ~__unbuffered_p0_EAX~0 0), 198849#[L723](= ~__unbuffered_p0_EAX~0 0), 198851#[L724](= ~__unbuffered_p0_EAX~0 0), 198853#[L725](= ~__unbuffered_p0_EAX~0 0), 198855#[L726](= ~__unbuffered_p0_EAX~0 0), 198857#[L727](= ~__unbuffered_p0_EAX~0 0), 198859#[L728](= ~__unbuffered_p0_EAX~0 0), 198861#[L729](= ~__unbuffered_p0_EAX~0 0), 198863#[L731](= ~__unbuffered_p0_EAX~0 0), 198865#[L732](= ~__unbuffered_p0_EAX~0 0), 198867#[L733](= ~__unbuffered_p0_EAX~0 0), 198869#[L735](= ~__unbuffered_p0_EAX~0 0), 198871#[L735-1](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p0_EAX~0 0) (= |~#x~0.offset| 0)), 198873#[L735-2](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p0_EAX~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198875#[L737](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p0_EAX~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198877#[L738](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p0_EAX~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198879#[L739](and (= (select |#valid| |~#x~0.base|) 1) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198881#[L740](and (= (select |#valid| |~#x~0.base|) 1) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198883#[L741](and (= (select |#valid| |~#x~0.base|) 1) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198885#[L742](and (= (select |#valid| |~#x~0.base|) 1) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198887#[L743](and (= (select |#valid| |~#x~0.base|) 1) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198889#[L744](and (= (select |#valid| |~#x~0.base|) 1) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198891#[L745](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198893#[L746](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198895#[L747](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198897#[L748](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0)), 198899#[L749](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198901#[L750](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198903#[L751](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198905#[L753](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198907#[L754](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198909#[L755](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198911#[L756](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198913#[L-1-2](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198915#[L-1-3](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198917#[L853](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198919#[L853-1](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198921#[L854](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198923#[P0ENTRY, L854-1](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198925#[L854-1, L759](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 198929#[L855, L759](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0)), 270457#[L855-1, L759](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0)), 270459#[L856, L759](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0)), 270461#[L856-1, P1ENTRY, L759](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0)), 270465#[P1ENTRY, L759, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0)), 270467#[L759, L857, L788](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0)), 270473#[L806, L759, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 270477#[L759, L809, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 270479#[L816, L759, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293537#[L819, L759, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293541#[L759, P1FINAL, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293545#[P1EXIT, L759, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293549#[L857-1, P1EXIT, L759](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293551#[P1EXIT, L759, L858](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293553#[P1EXIT, L858-1, L759, P2ENTRY](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293555#[P1EXIT, L759, L859, P2ENTRY](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293559#[P1EXIT, L861, L759, P2ENTRY](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293563#[P1EXIT, L862, L759, P2ENTRY](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293567#[P1EXIT, L2, L759, P2ENTRY](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293571#[P1EXIT, L759, P2ENTRY, L3](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293577#[P1EXIT, L2-1, L759, P2ENTRY](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293681#[P1EXIT, L759, L869, P2ENTRY](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 293687#[L824, P1EXIT, L759, L869](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 295039#[P1EXIT, L826, L759, L869](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 295041#[P1EXIT, L759, L869, L829](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 295045#[L761, P1EXIT, L869, L829](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|)), 295053#[L773, P1EXIT, L869, L829](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (= |~#x~0.offset| 0)), 295061#[P1EXIT, L869, L829, L780](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295071#[P1EXIT, L874, L829, L780](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295079#[L783, P1EXIT, L874, L829](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295087#[P1EXIT, L874, L829, P0FINAL](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295091#[P1EXIT, L874, L829, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295097#[L836, P1EXIT, L874, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295101#[P1EXIT, L839, L874, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295103#[P1EXIT, L874, P2FINAL, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295109#[P2EXIT, P1EXIT, L874, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295111#[P2EXIT, L875, P1EXIT, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295113#[P2EXIT, P1EXIT, L18, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295115#[P2EXIT, L18-1, P1EXIT, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295117#[P2EXIT, L18-2, P1EXIT, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295121#[P2EXIT, P1EXIT, L17-5, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295123#[P2EXIT, L17-7, P1EXIT, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 295127#[P2EXIT, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1EXIT, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0))] [2021-01-26 22:49:51,951 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2021-01-26 22:49:51,951 INFO L429 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 22:49:51,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 22:49:51,952 INFO L82 PathProgramCache]: Analyzing trace with hash -1616627993, now seen corresponding path program 5 times [2021-01-26 22:49:51,952 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 22:49:51,952 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064876935] [2021-01-26 22:49:51,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 22:49:52,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 22:49:52,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 22:49:52,180 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064876935] [2021-01-26 22:49:52,180 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 22:49:52,180 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2021-01-26 22:49:52,180 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1948545169] [2021-01-26 22:49:52,181 INFO L461 AbstractCegarLoop]: Interpolant automaton has 7 states [2021-01-26 22:49:52,181 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 22:49:52,181 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-01-26 22:49:52,181 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2021-01-26 22:49:52,182 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 22:49:52,182 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 22:49:52,333 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:52,442 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:52,864 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:52,996 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 22:49:53,084 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check Size of Word is: 100 and size of Sequence is : 101[2021-01-26 22:49:53,785 INFO L164 SleepSetCegar]: Size of mCounterexample is: 101 [2021-01-26 22:49:53,787 INFO L165 SleepSetCegar]: [295138#[ULTIMATE.startENTRY]true, 295140#[L-1]true, 295142#[L-1-1]true, 295144#[L17]true, 295146#[L17-1]true, 295148#[L17-2]true, 295150#[L17-3]true, 295152#[L17-4]true, 295154#[L711](= ~__unbuffered_cnt~0 0), 295156#[L713](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295158#[L714](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295160#[L715](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295162#[L716](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295164#[L717](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295166#[L718](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295168#[L719](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295170#[L720](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295172#[L721](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295174#[L722](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295176#[L723](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295178#[L724](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295180#[L725](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295182#[L726](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295184#[L727](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295186#[L728](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295188#[L729](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295190#[L731](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295192#[L732](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 295196#[L733](and (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295198#[L735](and (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295200#[L735-1](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295202#[L735-2](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295204#[L737](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295206#[L738](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295208#[L739](and (= (select |#valid| |~#x~0.base|) 1) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295210#[L740](and (= (select |#valid| |~#x~0.base|) 1) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295212#[L741](and (= (select |#valid| |~#x~0.base|) 1) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295214#[L742](and (= (select |#valid| |~#x~0.base|) 1) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295216#[L743](and (= (select |#valid| |~#x~0.base|) 1) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295218#[L744](and (= (select |#valid| |~#x~0.base|) 1) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295220#[L745](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295222#[L746](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295224#[L747](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295226#[L748](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295228#[L749](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~x$r_buff1_thd0~0 0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= |~#x~0.offset| 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295230#[L750](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295232#[L751](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295234#[L753](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295236#[L754](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295238#[L755](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295240#[L756](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295242#[L-1-2](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295244#[L-1-3](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295246#[L853](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295248#[L853-1](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295250#[L854](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295252#[P0ENTRY, L854-1](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295254#[L854-1, L759](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 295258#[L855, L759](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= 0 ~x$w_buff0~0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 313312#[L855-1, L759](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 313314#[L856, L759](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 313316#[L856-1, P1ENTRY, L759](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 313320#[P1ENTRY, L759, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 313322#[L759, L857, L788](and (= (select |#valid| |~#x~0.base|) 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 313328#[L806, L759, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= ~y~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 313332#[L759, L809, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 313334#[L816, L759, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 322072#[L819, L759, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (<= ~main$tmp_guard0~0 0)), 322076#[L759, P1FINAL, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (<= ~main$tmp_guard0~0 0)), 322080#[P1EXIT, L759, L857](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (<= ~main$tmp_guard0~0 0)), 322084#[L857-1, P1EXIT, L759](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (<= ~main$tmp_guard0~0 0)), 322086#[P1EXIT, L759, L858](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (<= ~main$tmp_guard0~0 0)), 322088#[P1EXIT, L858-1, L759, P2ENTRY](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (<= ~main$tmp_guard0~0 0)), 322090#[P1EXIT, L759, L859, P2ENTRY](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (<= ~main$tmp_guard0~0 0)), 322096#[L824, P1EXIT, L759, L859](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (<= ~main$tmp_guard0~0 0)), 323627#[P1EXIT, L826, L759, L859](and (= (select |#valid| |~#x~0.base|) 1) (= ~y~0 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (<= ~main$tmp_guard0~0 0)), 323640#[P1EXIT, L759, L829, L859](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (<= ~main$tmp_guard0~0 0)), 323657#[L761, P1EXIT, L829, L859](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1781~0.base|)) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (= ~x$w_buff0_used~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1780~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select (store |#memory_int| |ULTIMATE.start_main_~#t1781~0.base| (store (select |#memory_int| |ULTIMATE.start_main_~#t1781~0.base|) |ULTIMATE.start_main_~#t1781~0.offset| 1)) |~#x~0.base|) |~#x~0.offset|) 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) ~x$w_buff0~0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (<= ~main$tmp_guard0~0 0)), 323675#[L773, P1EXIT, L829, L859](and (= (select |#valid| |~#x~0.base|) 1) (= ~__unbuffered_p1_EAX$read_delayed~0 1) (= ~x$r_buff1_thd0~0 0) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (= ~x$r_buff1_thd2~0 0) (not (= |~#x~0.base| |ULTIMATE.start_main_~#t1782~0.base|)) (= 0 ~x$r_buff0_thd0~0) (= |~#x~0.base| ~__unbuffered_p1_EAX$read_delayed_var~0.base) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= 0 ~x$r_buff0_thd2~0) (= ~__unbuffered_p1_EAX~0 0) (= (select (select |#memory_int| |~#x~0.base|) |~#x~0.offset|) 0) (= ~__unbuffered_p1_EAX$read_delayed_var~0.offset |~#x~0.offset|) (<= ~main$tmp_guard0~0 0)), 323687#[P1EXIT, L829, L780, L859](and (= (select |#valid| |~#x~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (<= ~__unbuffered_cnt~0 1) (= |~#x~0.offset| 0) (<= ~main$tmp_guard0~0 0)), 323699#[L783, P1EXIT, L829, L859](and (= (select |#valid| |~#x~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= |~#x~0.offset| 0) (<= ~main$tmp_guard0~0 0)), 323715#[P1EXIT, L829, L859, P0FINAL](and (= (select |#valid| |~#x~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= |~#x~0.offset| 0) (<= ~main$tmp_guard0~0 0)), 323725#[P1EXIT, L829, P0EXIT, L859](and (= (select |#valid| |~#x~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= |~#x~0.offset| 0) (<= ~main$tmp_guard0~0 0)), 323737#[L836, P1EXIT, P0EXIT, L859](and (= (select |#valid| |~#x~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= |~#x~0.offset| 0) (<= ~main$tmp_guard0~0 0)), 323743#[P1EXIT, L839, P0EXIT, L859](and (= (select |#valid| |~#x~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= |~#x~0.offset| 0) (<= ~main$tmp_guard0~0 0)), 323753#[P1EXIT, L861, L839, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323757#[P1EXIT, L862, L839, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323761#[P1EXIT, L839, L2, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323765#[P1EXIT, L839, P0EXIT, L3](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323771#[P1EXIT, L839, L2-1, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323783#[P1EXIT, L839, L869, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323791#[P1EXIT, L839, L874, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323793#[P1EXIT, L874, P2FINAL, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323799#[P2EXIT, P1EXIT, L874, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323801#[P2EXIT, L875, P1EXIT, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323803#[P2EXIT, P1EXIT, L18, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323805#[P2EXIT, L18-1, P1EXIT, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323807#[P2EXIT, L18-2, P1EXIT, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323811#[P2EXIT, P1EXIT, L17-5, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323813#[P2EXIT, L17-7, P1EXIT, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0)), 323817#[P2EXIT, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1EXIT, P0EXIT](and (= (select |#valid| |~#x~0.base|) 1) (= |~#x~0.offset| 0))] [2021-01-26 22:49:53,787 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2021-01-26 22:49:53,788 INFO L429 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 22:49:53,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 22:49:53,788 INFO L82 PathProgramCache]: Analyzing trace with hash 1759272879, now seen corresponding path program 6 times [2021-01-26 22:49:53,788 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 22:49:53,788 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005462350] [2021-01-26 22:49:53,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 22:49:53,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-01-26 22:49:53,913 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-01-26 22:49:54,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-01-26 22:49:54,019 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-01-26 22:49:54,108 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-01-26 22:49:54,108 INFO L605 BasicCegarLoop]: Counterexample might be feasible [2021-01-26 22:49:54,108 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2021-01-26 22:49:54,397 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 26.01 10:49:54 BasicIcfg [2021-01-26 22:49:54,397 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2021-01-26 22:49:54,399 INFO L168 Benchmark]: Toolchain (without parser) took 122168.22 ms. Allocated memory was 302.0 MB in the beginning and 1.1 GB in the end (delta: 790.6 MB). Free memory was 274.9 MB in the beginning and 329.7 MB in the end (delta: -54.8 MB). Peak memory consumption was 736.9 MB. Max. memory is 16.0 GB. [2021-01-26 22:49:54,399 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 302.0 MB. Free memory was 271.6 MB in the beginning and 271.2 MB in the end (delta: 320.7 kB). There was no memory consumed. Max. memory is 16.0 GB. [2021-01-26 22:49:54,400 INFO L168 Benchmark]: CACSL2BoogieTranslator took 817.11 ms. Allocated memory is still 302.0 MB. Free memory was 273.9 MB in the beginning and 268.5 MB in the end (delta: 5.3 MB). Peak memory consumption was 30.6 MB. Max. memory is 16.0 GB. [2021-01-26 22:49:54,401 INFO L168 Benchmark]: Boogie Procedure Inliner took 60.69 ms. Allocated memory is still 302.0 MB. Free memory was 268.5 MB in the beginning and 266.4 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.0 GB. [2021-01-26 22:49:54,401 INFO L168 Benchmark]: Boogie Preprocessor took 56.27 ms. Allocated memory is still 302.0 MB. Free memory was 266.4 MB in the beginning and 263.3 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.0 GB. [2021-01-26 22:49:54,402 INFO L168 Benchmark]: RCFGBuilder took 3213.34 ms. Allocated memory was 302.0 MB in the beginning and 379.6 MB in the end (delta: 77.6 MB). Free memory was 263.3 MB in the beginning and 267.3 MB in the end (delta: -4.0 MB). Peak memory consumption was 164.1 MB. Max. memory is 16.0 GB. [2021-01-26 22:49:54,403 INFO L168 Benchmark]: TraceAbstraction took 118001.18 ms. Allocated memory was 379.6 MB in the beginning and 1.1 GB in the end (delta: 713.0 MB). Free memory was 266.2 MB in the beginning and 329.7 MB in the end (delta: -63.5 MB). Peak memory consumption was 650.6 MB. Max. memory is 16.0 GB. [2021-01-26 22:49:54,406 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 302.0 MB. Free memory was 271.6 MB in the beginning and 271.2 MB in the end (delta: 320.7 kB). There was no memory consumed. Max. memory is 16.0 GB. * CACSL2BoogieTranslator took 817.11 ms. Allocated memory is still 302.0 MB. Free memory was 273.9 MB in the beginning and 268.5 MB in the end (delta: 5.3 MB). Peak memory consumption was 30.6 MB. Max. memory is 16.0 GB. * Boogie Procedure Inliner took 60.69 ms. Allocated memory is still 302.0 MB. Free memory was 268.5 MB in the beginning and 266.4 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.0 GB. * Boogie Preprocessor took 56.27 ms. Allocated memory is still 302.0 MB. Free memory was 266.4 MB in the beginning and 263.3 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.0 GB. * RCFGBuilder took 3213.34 ms. Allocated memory was 302.0 MB in the beginning and 379.6 MB in the end (delta: 77.6 MB). Free memory was 263.3 MB in the beginning and 267.3 MB in the end (delta: -4.0 MB). Peak memory consumption was 164.1 MB. Max. memory is 16.0 GB. * TraceAbstraction took 118001.18 ms. Allocated memory was 379.6 MB in the beginning and 1.1 GB in the end (delta: 713.0 MB). Free memory was 266.2 MB in the beginning and 329.7 MB in the end (delta: -63.5 MB). Peak memory consumption was 650.6 MB. Max. memory is 16.0 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 17]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L709] 0 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L711] 0 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L713] 0 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0] [L714] 0 _Bool __unbuffered_p1_EAX$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0] [L715] 0 int __unbuffered_p1_EAX$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0] [L716] 0 _Bool __unbuffered_p1_EAX$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0] [L717] 0 _Bool __unbuffered_p1_EAX$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0] [L718] 0 _Bool __unbuffered_p1_EAX$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0] [L719] 0 _Bool __unbuffered_p1_EAX$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0] [L720] 0 _Bool __unbuffered_p1_EAX$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0] [L721] 0 _Bool __unbuffered_p1_EAX$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0] [L722] 0 _Bool __unbuffered_p1_EAX$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0] [L723] 0 _Bool __unbuffered_p1_EAX$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0] [L724] 0 _Bool __unbuffered_p1_EAX$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0] [L725] 0 int *__unbuffered_p1_EAX$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}] [L726] 0 int __unbuffered_p1_EAX$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0] [L727] 0 _Bool __unbuffered_p1_EAX$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0] [L728] 0 int __unbuffered_p1_EAX$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0] [L729] 0 _Bool __unbuffered_p1_EAX$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0] [L731] 0 int __unbuffered_p2_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0] [L732] 0 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0] [L733] 0 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L735] 0 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}] [L736] 0 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0] [L737] 0 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0] [L738] 0 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L739] 0 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L740] 0 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L741] 0 _Bool x$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0] [L742] 0 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0] [L743] 0 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L744] 0 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L745] 0 _Bool x$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0] [L746] 0 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0] [L747] 0 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L748] 0 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L749] 0 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L750] 0 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L751] 0 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L753] 0 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L754] 0 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L755] 0 _Bool weak$$choice1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L756] 0 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L853] 0 pthread_t t1780; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L854] FCALL, FORK 0 pthread_create(&t1780, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L855] 0 pthread_t t1781; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L856] FCALL, FORK 0 pthread_create(&t1781, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=0, __unbuffered_p1_EAX$read_delayed_var={0:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L789] 2 weak$$choice0 = __VERIFIER_nondet_bool() [L790] 2 weak$$choice2 = __VERIFIER_nondet_bool() [L791] 2 x$flush_delayed = weak$$choice2 [L792] EXPR 2 \read(x) [L792] 2 x$mem_tmp = x [L793] 2 weak$$choice1 = __VERIFIER_nondet_bool() [L794] EXPR 2 !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L794] EXPR 2 \read(x) [L794] EXPR 2 !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L794] 2 x = !x$w_buff0_used ? x : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x : (weak$$choice1 ? x$w_buff0 : x$w_buff1)) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$w_buff1 : x$w_buff0) : (weak$$choice0 ? x$w_buff0 : x)))) [L795] EXPR 2 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)))) [L795] 2 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff0 : x$w_buff0)))) [L796] EXPR 2 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)))) [L796] 2 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$w_buff1 : x$w_buff1)))) [L797] EXPR 2 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0)))) [L797] 2 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 || !weak$$choice1 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : weak$$choice0)))) [L798] EXPR 2 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L798] 2 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? weak$$choice0 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L799] EXPR 2 weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L799] 2 x$r_buff0_thd2 = weak$$choice2 ? x$r_buff0_thd2 : (!x$w_buff0_used ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? x$r_buff0_thd2 : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L800] EXPR 2 weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L800] 2 x$r_buff1_thd2 = weak$$choice2 ? x$r_buff1_thd2 : (!x$w_buff0_used ? x$r_buff1_thd2 : (x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : (x$w_buff0_used && !x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (weak$$choice0 ? x$r_buff1_thd2 : (_Bool)0) : (x$w_buff0_used && x$r_buff1_thd2 && x$w_buff1_used && !x$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)))) [L801] 2 __unbuffered_p1_EAX$read_delayed = (_Bool)1 [L802] 2 __unbuffered_p1_EAX$read_delayed_var = &x [L803] EXPR 2 \read(x) [L803] 2 __unbuffered_p1_EAX = x [L804] EXPR 2 x$flush_delayed ? x$mem_tmp : x [L804] 2 x = x$flush_delayed ? x$mem_tmp : x [L805] 2 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L808] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L811] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L811] EXPR 2 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x [L811] EXPR 2 \read(x) [L811] EXPR 2 x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x [L811] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L811] 2 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L812] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L812] 2 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L813] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L813] 2 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L814] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L814] 2 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L815] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L815] 2 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L818] 2 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L820] 2 return 0; VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L857] 0 pthread_t t1782; VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L858] FCALL, FORK 0 pthread_create(&t1782, ((void *)0), P2, ((void *)0)) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L825] 3 __unbuffered_p2_EAX = y VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L828] 3 y = 2 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L760] 1 __unbuffered_p0_EAX = y VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=2, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L763] 1 x$w_buff1 = x$w_buff0 [L764] 1 x$w_buff0 = 1 [L765] 1 x$w_buff1_used = x$w_buff0_used [L766] 1 x$w_buff0_used = (_Bool)1 [L18] COND FALSE 1 !(!expression) [L768] 1 x$r_buff1_thd0 = x$r_buff0_thd0 [L769] 1 x$r_buff1_thd1 = x$r_buff0_thd1 [L770] 1 x$r_buff1_thd2 = x$r_buff0_thd2 [L771] 1 x$r_buff1_thd3 = x$r_buff0_thd3 [L772] 1 x$r_buff0_thd1 = (_Bool)1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=2, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2] [L775] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L775] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L776] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L776] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L777] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L777] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L778] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L778] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L779] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L779] 1 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L782] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p0_EAX=2, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L784] 1 return 0; VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p0_EAX=2, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L831] EXPR 3 x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x) [L831] EXPR 3 x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x [L831] EXPR 3 \read(x) [L831] EXPR 3 x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x [L831] EXPR 3 x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x) [L831] 3 x = x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x) [L832] EXPR 3 x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used [L832] 3 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used [L833] EXPR 3 x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$w_buff1_used [L833] 3 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$w_buff1_used [L834] EXPR 3 x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$r_buff0_thd3 [L834] 3 x$r_buff0_thd3 = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$r_buff0_thd3 [L835] EXPR 3 x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$r_buff1_thd3 [L835] 3 x$r_buff1_thd3 = x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$r_buff1_thd3 [L838] 3 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [\result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L860] 0 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [\result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L3] COND FALSE 0 !(!cond) VAL [\result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p1_EAX=0, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L864] EXPR 0 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L864] EXPR 0 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x [L864] EXPR 0 \read(x) [L864] EXPR 0 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x [L864] EXPR 0 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L864] 0 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L865] EXPR 0 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L865] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L866] EXPR 0 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L866] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L867] EXPR 0 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L867] 0 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L868] EXPR 0 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L868] 0 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L871] 0 weak$$choice1 = __VERIFIER_nondet_bool() [L872] EXPR 0 __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX [L872] EXPR 0 weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX [L872] EXPR 0 \read(*__unbuffered_p1_EAX$read_delayed_var) [L872] EXPR 0 weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX [L872] EXPR 0 __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX [L872] 0 __unbuffered_p1_EAX = __unbuffered_p1_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p1_EAX$read_delayed_var : __unbuffered_p1_EAX) : __unbuffered_p1_EAX [L873] 0 main$tmp_guard1 = !(y == 2 && __unbuffered_p0_EAX == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L840] 3 return 0; VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L18] COND TRUE 0 !expression VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L17] COND FALSE 0 !(0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] [L17] 0 __assert_fail ("0", "safe000_power.opt.c", 8, __extension__ __PRETTY_FUNCTION__) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EAX$flush_delayed=0, __unbuffered_p1_EAX$mem_tmp=0, __unbuffered_p1_EAX$r_buff0_thd0=0, __unbuffered_p1_EAX$r_buff0_thd1=0, __unbuffered_p1_EAX$r_buff0_thd2=0, __unbuffered_p1_EAX$r_buff0_thd3=0, __unbuffered_p1_EAX$r_buff1_thd0=0, __unbuffered_p1_EAX$r_buff1_thd1=0, __unbuffered_p1_EAX$r_buff1_thd2=0, __unbuffered_p1_EAX$r_buff1_thd3=0, __unbuffered_p1_EAX$read_delayed=1, __unbuffered_p1_EAX$read_delayed_var={7:0}, __unbuffered_p1_EAX$w_buff0=0, __unbuffered_p1_EAX$w_buff0_used=0, __unbuffered_p1_EAX$w_buff1=0, __unbuffered_p1_EAX$w_buff1_used=0, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x={7:0}, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=1, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=1, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 118 locations, 2 error locations. Started 1 CEGAR loops. VerificationResult: UNSAFE, OverallTime: 117.5s, OverallIterations: 7, TraceHistogramMax: 0, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: No data available, PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=0occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 1.0s SatisfiabilityAnalysisTime, 1.9s InterpolantComputationTime, 659 NumberOfCodeBlocks, 659 NumberOfCodeBlocksAsserted, 7 NumberOfCheckSat, 553 ConstructedInterpolants, 0 QuantifiedInterpolants, 263378 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 6 InterpolantComputations, 6 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...