/usr/bin/java -Xmx16000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml -s ../../../trunk/examples/settings/automizer/concurrent/svcomp-Reach-32bit-Automizer_Default-noMmResRef-Sleep-NoLbe-Delay.epf -i ../../../trunk/examples/svcomp/pthread-wmm/thin001_power.opt.i -------------------------------------------------------------------------------- This is Ultimate 0.2.0-6f57305 [2021-01-26 23:10:29,972 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-01-26 23:10:29,975 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-01-26 23:10:30,010 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-01-26 23:10:30,011 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-01-26 23:10:30,012 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-01-26 23:10:30,014 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-01-26 23:10:30,016 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-01-26 23:10:30,019 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-01-26 23:10:30,020 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-01-26 23:10:30,021 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-01-26 23:10:30,023 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-01-26 23:10:30,023 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-01-26 23:10:30,025 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-01-26 23:10:30,026 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-01-26 23:10:30,028 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-01-26 23:10:30,029 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-01-26 23:10:30,030 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-01-26 23:10:30,032 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-01-26 23:10:30,035 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-01-26 23:10:30,037 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-01-26 23:10:30,039 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-01-26 23:10:30,040 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-01-26 23:10:30,042 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-01-26 23:10:30,045 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-01-26 23:10:30,046 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-01-26 23:10:30,046 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-01-26 23:10:30,048 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-01-26 23:10:30,048 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-01-26 23:10:30,050 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-01-26 23:10:30,050 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-01-26 23:10:30,051 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-01-26 23:10:30,053 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-01-26 23:10:30,054 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-01-26 23:10:30,055 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-01-26 23:10:30,056 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-01-26 23:10:30,057 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-01-26 23:10:30,057 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-01-26 23:10:30,058 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-01-26 23:10:30,059 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-01-26 23:10:30,060 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-01-26 23:10:30,061 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/concurrent/svcomp-Reach-32bit-Automizer_Default-noMmResRef-Sleep-NoLbe-Delay.epf [2021-01-26 23:10:30,093 INFO L113 SettingsManager]: Loading preferences was successful [2021-01-26 23:10:30,093 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-01-26 23:10:30,095 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-01-26 23:10:30,095 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-01-26 23:10:30,095 INFO L138 SettingsManager]: * Use SBE=true [2021-01-26 23:10:30,096 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-01-26 23:10:30,096 INFO L138 SettingsManager]: * sizeof long=4 [2021-01-26 23:10:30,096 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-01-26 23:10:30,096 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-01-26 23:10:30,097 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-01-26 23:10:30,097 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-01-26 23:10:30,097 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-01-26 23:10:30,098 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-01-26 23:10:30,098 INFO L138 SettingsManager]: * sizeof long double=12 [2021-01-26 23:10:30,098 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-01-26 23:10:30,098 INFO L138 SettingsManager]: * Use constant arrays=true [2021-01-26 23:10:30,099 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-01-26 23:10:30,099 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-01-26 23:10:30,099 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-01-26 23:10:30,100 INFO L138 SettingsManager]: * To the following directory=./dump/ [2021-01-26 23:10:30,100 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-01-26 23:10:30,100 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-01-26 23:10:30,101 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-01-26 23:10:30,101 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-01-26 23:10:30,101 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-01-26 23:10:30,101 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-01-26 23:10:30,102 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-01-26 23:10:30,102 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2021-01-26 23:10:30,102 INFO L138 SettingsManager]: * Lazy Petri-NFA conversion=true [2021-01-26 23:10:30,102 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=SLEEP_SET_FA [2021-01-26 23:10:30,103 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-01-26 23:10:30,103 INFO L138 SettingsManager]: * Minimization of abstraction=NONE [2021-01-26 23:10:30,103 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2021-01-26 23:10:30,104 INFO L138 SettingsManager]: * Sleep set reduction in concurrent analysis=DELAY_SET WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2021-01-26 23:10:30,529 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-01-26 23:10:30,557 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-01-26 23:10:30,560 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-01-26 23:10:30,562 INFO L271 PluginConnector]: Initializing CDTParser... [2021-01-26 23:10:30,563 INFO L275 PluginConnector]: CDTParser initialized [2021-01-26 23:10:30,564 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/pthread-wmm/thin001_power.opt.i [2021-01-26 23:10:30,662 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/eda4b2e74/7a57498adc10459bb5aaddbf81e61219/FLAG06eb01bd3 [2021-01-26 23:10:31,553 INFO L306 CDTParser]: Found 1 translation units. [2021-01-26 23:10:31,553 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/pthread-wmm/thin001_power.opt.i [2021-01-26 23:10:31,570 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/eda4b2e74/7a57498adc10459bb5aaddbf81e61219/FLAG06eb01bd3 [2021-01-26 23:10:31,749 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/eda4b2e74/7a57498adc10459bb5aaddbf81e61219 [2021-01-26 23:10:31,752 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-01-26 23:10:31,765 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2021-01-26 23:10:31,767 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-01-26 23:10:31,767 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-01-26 23:10:31,771 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-01-26 23:10:31,772 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.01 11:10:31" (1/1) ... [2021-01-26 23:10:31,775 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@261676b5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:31, skipping insertion in model container [2021-01-26 23:10:31,776 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.01 11:10:31" (1/1) ... [2021-01-26 23:10:31,784 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-01-26 23:10:31,831 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-01-26 23:10:32,308 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-01-26 23:10:32,320 INFO L203 MainTranslator]: Completed pre-run [2021-01-26 23:10:32,419 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-01-26 23:10:32,584 INFO L208 MainTranslator]: Completed translation [2021-01-26 23:10:32,585 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:32 WrapperNode [2021-01-26 23:10:32,589 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-01-26 23:10:32,591 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-01-26 23:10:32,592 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-01-26 23:10:32,592 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-01-26 23:10:32,601 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:32" (1/1) ... [2021-01-26 23:10:32,648 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:32" (1/1) ... [2021-01-26 23:10:32,686 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-01-26 23:10:32,687 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-01-26 23:10:32,687 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-01-26 23:10:32,687 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-01-26 23:10:32,697 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:32" (1/1) ... [2021-01-26 23:10:32,698 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:32" (1/1) ... [2021-01-26 23:10:32,705 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:32" (1/1) ... [2021-01-26 23:10:32,705 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:32" (1/1) ... [2021-01-26 23:10:32,719 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:32" (1/1) ... [2021-01-26 23:10:32,724 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:32" (1/1) ... [2021-01-26 23:10:32,732 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:32" (1/1) ... [2021-01-26 23:10:32,746 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-01-26 23:10:32,749 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-01-26 23:10:32,749 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-01-26 23:10:32,749 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-01-26 23:10:32,756 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:32" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-01-26 23:10:32,860 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-01-26 23:10:32,860 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-01-26 23:10:32,861 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2021-01-26 23:10:32,861 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-01-26 23:10:32,862 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-01-26 23:10:32,863 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2021-01-26 23:10:32,863 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2021-01-26 23:10:32,863 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2021-01-26 23:10:32,863 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2021-01-26 23:10:32,863 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2021-01-26 23:10:32,863 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2021-01-26 23:10:32,864 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-01-26 23:10:32,864 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2021-01-26 23:10:32,864 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-01-26 23:10:32,864 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-01-26 23:10:32,866 WARN L208 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2021-01-26 23:10:36,404 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-01-26 23:10:36,405 INFO L298 CfgBuilder]: Removed 14 assume(true) statements. [2021-01-26 23:10:36,407 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.01 11:10:36 BoogieIcfgContainer [2021-01-26 23:10:36,407 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-01-26 23:10:36,409 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-01-26 23:10:36,409 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-01-26 23:10:36,413 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-01-26 23:10:36,413 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 26.01 11:10:31" (1/3) ... [2021-01-26 23:10:36,414 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@914e407 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.01 11:10:36, skipping insertion in model container [2021-01-26 23:10:36,414 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.01 11:10:32" (2/3) ... [2021-01-26 23:10:36,414 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@914e407 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.01 11:10:36, skipping insertion in model container [2021-01-26 23:10:36,415 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.01 11:10:36" (3/3) ... [2021-01-26 23:10:36,416 INFO L111 eAbstractionObserver]: Analyzing ICFG thin001_power.opt.i [2021-01-26 23:10:36,433 WARN L168 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2021-01-26 23:10:36,433 INFO L179 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-01-26 23:10:36,437 INFO L191 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2021-01-26 23:10:36,438 INFO L351 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2021-01-26 23:10:36,492 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,493 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,493 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,493 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,493 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,493 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,494 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,494 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,494 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,494 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,495 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,495 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,495 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,495 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,496 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,496 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,496 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,496 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,496 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,496 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,497 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,497 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,497 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,497 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,497 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,498 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,499 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,499 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,499 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,499 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,499 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,500 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,500 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,501 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,502 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,502 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,502 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,503 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,504 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,504 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,504 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,504 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,505 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,505 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,505 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,505 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,506 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,506 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,506 WARN L313 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,506 WARN L313 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,506 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,507 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,507 WARN L313 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,507 WARN L313 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,507 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,507 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,508 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,508 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,508 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,508 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,508 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,508 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,509 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,509 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,509 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,509 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,509 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,548 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,548 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,548 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,548 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,549 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,549 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,552 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,552 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,552 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,553 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,553 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,553 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,553 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,553 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,553 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,554 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,554 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,557 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,557 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,558 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,558 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,558 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,558 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,558 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,558 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,559 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,559 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,559 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,559 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,559 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,559 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,560 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,560 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,560 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,560 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,560 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,560 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,560 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,561 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,561 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,561 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,561 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,561 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,561 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,562 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,562 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,562 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,562 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,562 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,563 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,563 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,563 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,563 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,563 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,563 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,564 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,564 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,564 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,564 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,564 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,564 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,564 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,565 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,565 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,565 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,565 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,565 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,565 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,565 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,566 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,566 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,566 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,566 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,566 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,566 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,572 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,572 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,572 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,572 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,572 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,573 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,573 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,573 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,573 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,573 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,573 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,573 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,574 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,574 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,574 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,574 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,574 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,574 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,574 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,574 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,575 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,575 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,575 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,575 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,575 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,575 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,575 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,576 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,576 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,576 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,576 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,576 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,577 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,577 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,577 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,577 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,577 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,577 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,578 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,578 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,578 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,579 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,579 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,579 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,579 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,579 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,579 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,580 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,580 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,580 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,580 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,580 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,580 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,581 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,581 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,581 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,581 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,581 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,581 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,582 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,582 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,582 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,582 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,582 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,582 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,583 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,583 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,583 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,583 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,583 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,583 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,584 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,584 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,584 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,584 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,584 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,584 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,585 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,585 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,585 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,585 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,585 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,585 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,586 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,586 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,586 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,586 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,586 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,591 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,591 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,591 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,592 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,592 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,592 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,592 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,592 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,592 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,593 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,593 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,593 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,594 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,594 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,594 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,594 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,594 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,594 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,595 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,595 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,596 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,596 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,598 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,599 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite64| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,599 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,599 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,599 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite62| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,599 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite60| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,600 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,600 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite47| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,600 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite49| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,600 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,600 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,601 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,601 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite45| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,601 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,601 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite66| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,601 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem58| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,601 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,602 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,602 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite53| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,602 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,602 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,602 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite51| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,603 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem61| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,603 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,603 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,603 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,603 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite57| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,604 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,604 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite55| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,604 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,604 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,604 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,605 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem59| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,605 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite63| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,605 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,605 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,605 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,605 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite48| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,606 WARN L313 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,606 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,606 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite67| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,606 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite44| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,606 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite46| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,607 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite65| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,607 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,607 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,607 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,607 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,607 WARN L313 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,608 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite52| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,608 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,608 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite50| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,608 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,608 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,609 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,609 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,609 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite56| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,609 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,609 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite54| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,610 WARN L313 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,612 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,612 WARN L313 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,612 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,613 WARN L313 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,614 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,614 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,615 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,615 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,615 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,615 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,615 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,616 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,616 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_reach_error_#t~nondet2.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,616 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,616 WARN L313 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,616 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,616 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,617 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,617 WARN L313 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-01-26 23:10:36,618 INFO L149 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2021-01-26 23:10:36,633 INFO L253 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2021-01-26 23:10:36,659 INFO L377 AbstractCegarLoop]: Interprodecural is true [2021-01-26 23:10:36,660 INFO L378 AbstractCegarLoop]: Hoare is true [2021-01-26 23:10:36,660 INFO L379 AbstractCegarLoop]: Compute interpolants for FPandBP [2021-01-26 23:10:36,660 INFO L380 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2021-01-26 23:10:36,660 INFO L381 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-01-26 23:10:36,660 INFO L382 AbstractCegarLoop]: Difference is false [2021-01-26 23:10:36,660 INFO L383 AbstractCegarLoop]: Minimize is NONE [2021-01-26 23:10:36,661 INFO L387 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== Size of Word is: 73 and size of Sequence is : 74[2021-01-26 23:10:36,705 INFO L164 SleepSetCegar]: Size of mCounterexample is: 74 [2021-01-26 23:10:36,706 INFO L165 SleepSetCegar]: [132#[ULTIMATE.startENTRY]don't care, 134#[L-1]don't care, 136#[L-1-1]don't care, 138#[L17]don't care, 140#[L17-1]don't care, 142#[L17-2]don't care, 144#[L17-3]don't care, 146#[L17-4]don't care, 148#[L711]don't care, 150#[L713]don't care, 152#[L715]don't care, 154#[L716]don't care, 156#[L717]don't care, 158#[L718]don't care, 160#[L719]don't care, 162#[L720]don't care, 164#[L721]don't care, 166#[L722]don't care, 168#[L723]don't care, 170#[L724]don't care, 172#[L725]don't care, 174#[L726]don't care, 176#[L727]don't care, 178#[L728]don't care, 180#[L729]don't care, 182#[L730]don't care, 184#[L731]don't care, 186#[L732]don't care, 188#[L733]don't care, 190#[L735]don't care, 192#[L737]don't care, 194#[L737-1]don't care, 196#[L737-2]don't care, 198#[L739]don't care, 200#[L740]don't care, 202#[L741]don't care, 204#[L742]don't care, 206#[L743]don't care, 208#[L744]don't care, 210#[L745]don't care, 212#[L746]don't care, 214#[L747]don't care, 216#[L748]don't care, 218#[L749]don't care, 220#[L750]don't care, 222#[L751]don't care, 224#[L752]don't care, 226#[L753]don't care, 228#[L755]don't care, 230#[L756]don't care, 232#[L757]don't care, 234#[L758]don't care, 236#[L-1-2]don't care, 238#[L-1-3]don't care, 240#[L850]don't care, 242#[L850-1]don't care, 244#[L851]don't care, 246#[P0ENTRY, L851-1]don't care, 250#[P0ENTRY, L852]don't care, 254#[P0ENTRY, L852-1]don't care, 256#[L853, P0ENTRY]don't care, 262#[L853, L761]don't care, 266#[L853, L763]don't care, 270#[L853, L766]don't care, 274#[L853, L771]don't care, 278#[L853, P0FINAL]don't care, 282#[L853, P0EXIT]don't care, 284#[P1ENTRY, L853-1, P0EXIT]don't care, 286#[L854, P1ENTRY, P0EXIT]don't care, 290#[P1ENTRY, L854-1, P0EXIT]don't care, 294#[P1ENTRY, L855, P0EXIT]don't care, 300#[L776, L855, P0EXIT]don't care, 304#[L778, L855, P0EXIT]don't care, 308#[P1Err0ASSERT_VIOLATIONERROR_FUNCTION, L855, P0EXIT]don't care] [2021-01-26 23:10:36,707 INFO L429 AbstractCegarLoop]: === Iteration 1 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 23:10:36,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 23:10:36,724 INFO L82 PathProgramCache]: Analyzing trace with hash 1210439952, now seen corresponding path program 1 times [2021-01-26 23:10:36,738 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 23:10:36,738 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499120138] [2021-01-26 23:10:36,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 23:10:36,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 23:10:37,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 23:10:37,158 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [499120138] [2021-01-26 23:10:37,158 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 23:10:37,159 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-26 23:10:37,159 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36006156] [2021-01-26 23:10:37,170 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-26 23:10:37,170 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 23:10:37,185 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-26 23:10:37,187 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-26 23:10:37,189 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 23:10:37,191 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 3 states, 2 states have (on average 36.5) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 23:10:37,217 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check Size of Word is: 93 and size of Sequence is : 94[2021-01-26 23:10:37,302 INFO L164 SleepSetCegar]: Size of mCounterexample is: 94 [2021-01-26 23:10:37,302 INFO L165 SleepSetCegar]: [314#[ULTIMATE.startENTRY]true, 315#[L-1]true, 316#[L-1-1]true, 317#[L17]true, 318#[L17-1]true, 319#[L17-2]true, 320#[L17-3]true, 321#[L17-4]true, 322#[L711]true, 323#[L713]true, 324#[L715]true, 325#[L716]true, 326#[L717]true, 327#[L718]true, 328#[L719]true, 329#[L720]true, 330#[L721]true, 331#[L722]true, 332#[L723]true, 333#[L724]true, 334#[L725]true, 335#[L726]true, 336#[L727]true, 337#[L728]true, 338#[L729]true, 339#[L730]true, 340#[L731]true, 341#[L732]true, 342#[L733]true, 343#[L735]true, 344#[L737]true, 345#[L737-1]true, 346#[L737-2]true, 347#[L739]true, 348#[L740]true, 349#[L741]true, 350#[L742]true, 351#[L743]true, 352#[L744]true, 353#[L745]true, 354#[L746]true, 355#[L747]true, 356#[L748]true, 357#[L749]true, 358#[L750]true, 359#[L751]true, 360#[L752](= ~y$w_buff0_used~0 0), 361#[L753](= ~y$w_buff0_used~0 0), 362#[L755](= ~y$w_buff0_used~0 0), 363#[L756](= ~y$w_buff0_used~0 0), 364#[L757](= ~y$w_buff0_used~0 0), 365#[L758](= ~y$w_buff0_used~0 0), 366#[L-1-2](= ~y$w_buff0_used~0 0), 367#[L-1-3](= ~y$w_buff0_used~0 0), 368#[L850](= ~y$w_buff0_used~0 0), 369#[L850-1](= ~y$w_buff0_used~0 0), 370#[L851](= ~y$w_buff0_used~0 0), 371#[P0ENTRY, L851-1](= ~y$w_buff0_used~0 0), 373#[P0ENTRY, L852](= ~y$w_buff0_used~0 0), 375#[P0ENTRY, L852-1](= ~y$w_buff0_used~0 0), 376#[L853, P0ENTRY](= ~y$w_buff0_used~0 0), 379#[L853, L761](= ~y$w_buff0_used~0 0), 381#[L853, L763](= ~y$w_buff0_used~0 0), 383#[L853, L766](= ~y$w_buff0_used~0 0), 385#[L853, L771](= ~y$w_buff0_used~0 0), 387#[L853, P0FINAL](= ~y$w_buff0_used~0 0), 389#[L853, P0EXIT](= ~y$w_buff0_used~0 0), 390#[P1ENTRY, L853-1, P0EXIT](= ~y$w_buff0_used~0 0), 391#[L854, P1ENTRY, P0EXIT](= ~y$w_buff0_used~0 0), 393#[P1ENTRY, L854-1, P0EXIT](= ~y$w_buff0_used~0 0), 395#[P1ENTRY, L855, P0EXIT](= ~y$w_buff0_used~0 0), 398#[L776, L855, P0EXIT](= ~y$w_buff0_used~0 0), 400#[L778, L855, P0EXIT](= ~y$w_buff0_used~0 0), 403#[L790, L855, P0EXIT]true, 409#[L855, P0EXIT, L797]true, 414#[L800, L855, P0EXIT]true, 420#[L855, P0EXIT, P1FINAL]true, 427#[L855, P0EXIT, P1EXIT]true, 430#[P0EXIT, P1EXIT, L855-1, P2ENTRY]true, 435#[L856, P0EXIT, P1EXIT, P2ENTRY]true, 442#[P0EXIT, P1EXIT, P2ENTRY, L858]true, 448#[P0EXIT, P1EXIT, P2ENTRY, L859]true, 453#[P0EXIT, L2, P1EXIT, P2ENTRY]true, 460#[P0EXIT, P1EXIT, P2ENTRY, L3]true, 469#[L2-1, P0EXIT, P1EXIT, P2ENTRY]true, 516#[L866, P0EXIT, P1EXIT, P2ENTRY]true, 522#[P0EXIT, P1EXIT, P2ENTRY, L871]true, 527#[L872, P0EXIT, P1EXIT, P2ENTRY]true, 533#[P0EXIT, L18, P1EXIT, P2ENTRY]true, 540#[L18-1, P0EXIT, P1EXIT, P2ENTRY]true, 547#[L18-2, P0EXIT, P1EXIT, P2ENTRY]true, 555#[P0EXIT, P1EXIT, P2ENTRY, L17-5]true, 562#[L17-7, P0EXIT, P1EXIT, P2ENTRY]true, 571#[ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0EXIT, P1EXIT, P2ENTRY]true] [2021-01-26 23:10:37,303 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-01-26 23:10:37,303 INFO L429 AbstractCegarLoop]: === Iteration 2 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 23:10:37,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 23:10:37,304 INFO L82 PathProgramCache]: Analyzing trace with hash 1744364800, now seen corresponding path program 1 times [2021-01-26 23:10:37,304 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 23:10:37,304 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177833274] [2021-01-26 23:10:37,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 23:10:37,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 23:10:37,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 23:10:37,674 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177833274] [2021-01-26 23:10:37,674 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 23:10:37,674 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2021-01-26 23:10:37,675 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1309088080] [2021-01-26 23:10:37,677 INFO L461 AbstractCegarLoop]: Interpolant automaton has 7 states [2021-01-26 23:10:37,677 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 23:10:37,678 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-01-26 23:10:37,678 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2021-01-26 23:10:37,678 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 23:10:37,679 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 7 states, 7 states have (on average 13.285714285714286) internal successors, (93), 7 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 23:10:37,881 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check Size of Word is: 95 and size of Sequence is : 96[2021-01-26 23:10:38,290 INFO L164 SleepSetCegar]: Size of mCounterexample is: 96 [2021-01-26 23:10:38,291 INFO L165 SleepSetCegar]: [582#[ULTIMATE.startENTRY]true, 584#[L-1]true, 586#[L-1-1]true, 588#[L17]true, 590#[L17-1]true, 592#[L17-2]true, 594#[L17-3]true, 596#[L17-4]true, 598#[L711]true, 600#[L713]true, 602#[L715]true, 604#[L716](= ~__unbuffered_p2_EAX~0 0), 606#[L717](= ~__unbuffered_p2_EAX~0 0), 608#[L718](= ~__unbuffered_p2_EAX~0 0), 610#[L719](= ~__unbuffered_p2_EAX~0 0), 612#[L720](= ~__unbuffered_p2_EAX~0 0), 614#[L721](= ~__unbuffered_p2_EAX~0 0), 616#[L722](= ~__unbuffered_p2_EAX~0 0), 618#[L723](= ~__unbuffered_p2_EAX~0 0), 620#[L724](= ~__unbuffered_p2_EAX~0 0), 622#[L725](= ~__unbuffered_p2_EAX~0 0), 624#[L726](= ~__unbuffered_p2_EAX~0 0), 626#[L727](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 628#[L728](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 630#[L729](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 632#[L730](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 634#[L731](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 636#[L732](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 638#[L733](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 640#[L735](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 642#[L737](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 644#[L737-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 646#[L737-2](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 648#[L739](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 650#[L740](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 652#[L741](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 654#[L742](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 656#[L743](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 658#[L744](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 660#[L745](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 662#[L746](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 664#[L747](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 666#[L748](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 668#[L749](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 670#[L750](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 672#[L751](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 674#[L752](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 676#[L753](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 678#[L755](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 680#[L756](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 682#[L757](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 684#[L758](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 686#[L-1-2](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 688#[L-1-3](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 690#[L850](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 692#[L850-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 694#[L851](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 696#[P0ENTRY, L851-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 700#[P0ENTRY, L852](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 704#[P0ENTRY, L852-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 706#[L853, P0ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 712#[L853, L761](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 716#[L853, L763](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 720#[L853, L766](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 724#[L853, L771](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 728#[L853, P0FINAL](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 732#[L853, P0EXIT](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 734#[P1ENTRY, L853-1, P0EXIT](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 736#[L854, P1ENTRY, P0EXIT](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 740#[P1ENTRY, L854-1, P0EXIT](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 744#[P1ENTRY, L855, P0EXIT](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 750#[L776, L855, P0EXIT](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 754#[L778, L855, P0EXIT](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0)), 760#[L790, L855, P0EXIT](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 764#[L855, P0EXIT, L797](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 766#[L800, L855, P0EXIT](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 770#[L855, P0EXIT, P1FINAL](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 776#[L855, P0EXIT, P1EXIT](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 778#[P0EXIT, P1EXIT, L855-1, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 780#[L856, P0EXIT, P1EXIT, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 786#[P0EXIT, P1EXIT, P2ENTRY, L858](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 790#[P0EXIT, P1EXIT, P2ENTRY, L859](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 792#[P0EXIT, L2, P1EXIT, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 798#[P0EXIT, P1EXIT, P2ENTRY, L3](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 804#[L2-1, P0EXIT, P1EXIT, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 838#[L866, P0EXIT, P1EXIT, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 840#[L866, P0EXIT, P1EXIT, L805](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0)), 1422#[L823, L866, P0EXIT, P1EXIT]true, 1429#[L823, P0EXIT, P1EXIT, L871]true, 1431#[L872, L823, P0EXIT, P1EXIT]true, 1437#[L823, P0EXIT, L18, P1EXIT]true, 1441#[L823, L18-1, P0EXIT, P1EXIT]true, 1443#[L823, L18-2, P0EXIT, P1EXIT]true, 1454#[L823, P0EXIT, P1EXIT, L17-5]true, 1467#[L823, L17-7, P0EXIT, P1EXIT]true, 1480#[L823, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0EXIT, P1EXIT]true] [2021-01-26 23:10:38,291 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-01-26 23:10:38,291 INFO L429 AbstractCegarLoop]: === Iteration 3 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 23:10:38,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 23:10:38,292 INFO L82 PathProgramCache]: Analyzing trace with hash -164218879, now seen corresponding path program 1 times [2021-01-26 23:10:38,292 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 23:10:38,293 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281073582] [2021-01-26 23:10:38,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 23:10:38,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 23:10:38,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 23:10:38,841 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281073582] [2021-01-26 23:10:38,841 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 23:10:38,842 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2021-01-26 23:10:38,842 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583510342] [2021-01-26 23:10:38,842 INFO L461 AbstractCegarLoop]: Interpolant automaton has 9 states [2021-01-26 23:10:38,843 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 23:10:38,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2021-01-26 23:10:38,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2021-01-26 23:10:38,844 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 23:10:38,844 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 9 states, 9 states have (on average 10.555555555555555) internal successors, (95), 9 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 23:10:39,112 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:10:39,357 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:10:41,970 WARN L146 IndependenceRelation]: Expensive independence query (2434 ms) for statements [1265] L805-->L823: Formula: (let ((.cse15 (= (mod v_~y$r_buff1_thd3~0_294 256) 0)) (.cse48 (mod v_~y$w_buff0_used~0_481 256)) (.cse16 (= (mod v_~y$r_buff0_thd3~0_336 256) 0))) (let ((.cse26 (= (mod v_~weak$$choice2~0_94 256) 0)) (.cse31 (= (mod v_~y$w_buff1_used~0_393 256) 0)) (.cse12 (= (mod v_~weak$$choice0~0_145 256) 0)) (.cse2 (not .cse16)) (.cse46 (= (mod v_~y$w_buff1_used~0_394 256) 0)) (.cse21 (= .cse48 0)) (.cse19 (not .cse15)) (.cse27 (= (mod v_~y$w_buff0_used~0_480 256) 0)) (.cse41 (select |v_#memory_int_288| |v_~#y~0.base_184|))) (let ((.cse0 (select .cse41 |v_~#y~0.offset_184|)) (.cse32 (or .cse16 .cse27)) (.cse13 (= (mod v_~weak$$choice1~0_73 256) 0)) (.cse17 (or .cse2 .cse46 .cse21 .cse19)) (.cse18 (or .cse2 .cse46 .cse21 .cse15)) (.cse11 (not .cse46)) (.cse20 (or .cse21 .cse16)) (.cse9 (not .cse21)) (.cse14 (not .cse12)) (.cse29 (not .cse31)) (.cse28 (not .cse27)) (.cse23 (not .cse26))) (and (= v_~y$mem_tmp~0_32 .cse0) (let ((.cse1 (= |v_P2_#t~ite22_83| |v_P2Thread1of1ForFork0_#t~ite22_1|)) (.cse3 (= |v_P2_#t~ite18_85| |v_P2Thread1of1ForFork0_#t~ite18_1|)) (.cse4 (= |v_P2_#t~ite23_71| |v_P2Thread1of1ForFork0_#t~ite23_1|)) (.cse5 (= |v_P2_#t~ite24_59| |v_P2Thread1of1ForFork0_#t~ite24_1|)) (.cse6 (= |v_P2_#t~ite19_87| |v_P2Thread1of1ForFork0_#t~ite19_1|)) (.cse7 (= |v_P2_#t~ite20_77| |v_P2Thread1of1ForFork0_#t~ite20_1|)) (.cse8 (= |v_P2_#t~mem17_88| |v_P2Thread1of1ForFork0_#t~mem17_1|)) (.cse10 (= |v_P2_#t~mem21_92| |v_P2Thread1of1ForFork0_#t~mem21_1|))) (or (and (or (and .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 (= |v_P2_#t~ite25_63| v_~y$w_buff0~0_135) .cse7 .cse8 .cse9 .cse10) (and (or (and .cse1 .cse11 .cse4 (or (and .cse12 (= |v_P2_#t~ite19_87| |v_P2_#t~ite18_85|) (or (and .cse13 (= v_~y$w_buff1~0_134 |v_P2_#t~ite18_85|)) (and (= |v_P2_#t~ite18_85| v_~y$w_buff0~0_135) (not .cse13))) .cse8) (and .cse3 .cse14 (= |v_P2_#t~ite19_87| |v_P2_#t~mem17_88|) (= |v_P2_#t~mem17_88| .cse0))) .cse15 (= |v_P2_#t~ite19_87| |v_P2_#t~ite24_59|) .cse16 .cse7 .cse9 .cse10) (and .cse17 (= |v_P2_#t~ite24_59| |v_P2_#t~ite23_71|) .cse3 .cse6 (or (and .cse18 (= |v_P2_#t~ite22_83| |v_P2_#t~ite23_71|) (or (and (= |v_P2_#t~ite22_83| |v_P2_#t~mem21_92|) .cse12 (= |v_P2_#t~mem21_92| .cse0)) (and (= |v_P2_#t~ite22_83| v_~y$w_buff0~0_135) .cse14 .cse10)) .cse7) (and .cse1 .cse11 (or (and .cse12 (= |v_P2_#t~ite20_77| v_~y$w_buff0~0_135)) (and (= v_~y$w_buff1~0_134 |v_P2_#t~ite20_77|) .cse14)) (= |v_P2_#t~ite20_77| |v_P2_#t~ite23_71|) .cse16 .cse19 .cse9 .cse10)) .cse8)) .cse20 (= |v_P2_#t~ite24_59| |v_P2_#t~ite25_63|))) (= |v_P2_#t~ite25_63| v_~__unbuffered_p2_EAX~0_43) (= |v_P2Thread1of1ForFork0_#t~mem16_1| |v_P2_#t~mem16_52|) .cse9) (and .cse1 .cse3 .cse21 (= |v_P2_#t~ite25_63| |v_P2Thread1of1ForFork0_#t~ite25_1|) .cse4 (= |v_P2_#t~mem16_52| .cse0) .cse5 .cse6 (= |v_P2_#t~mem16_52| v_~__unbuffered_p2_EAX~0_43) .cse7 .cse8 .cse10))) (let ((.cse24 (= |v_P2_#t~ite49_61| |v_P2Thread1of1ForFork0_#t~ite49_1|)) (.cse22 (= |v_P2_#t~ite48_67| |v_P2Thread1of1ForFork0_#t~ite48_1|)) (.cse25 (= |v_P2_#t~ite47_69| |v_P2Thread1of1ForFork0_#t~ite47_1|))) (or (and .cse22 .cse23 (= v_~y$r_buff0_thd3~0_336 v_~y$r_buff0_thd3~0_335) .cse24 (= |v_P2_#t~ite50_47| |v_P2Thread1of1ForFork0_#t~ite50_1|) .cse25) (and .cse26 (= |v_P2_#t~ite50_47| v_~y$r_buff0_thd3~0_335) (or (and .cse22 (= |v_P2_#t~ite50_47| v_~y$r_buff0_thd3~0_336) .cse24 .cse25 .cse27) (and .cse28 (= |v_P2_#t~ite49_61| |v_P2_#t~ite50_47|) (or (and .cse2 .cse28 .cse22 (= |v_P2_#t~ite49_61| 0) .cse25) (and (or (and (let ((.cse30 (= |v_P2_#t~ite47_69| 0))) (or (and .cse29 .cse28 .cse16 .cse30 .cse19) (and .cse30 (or .cse2 .cse15 .cse31 .cse27)))) (or .cse2 .cse31 .cse27 .cse19) (= |v_P2_#t~ite48_67| |v_P2_#t~ite47_69|)) (and .cse29 .cse28 .cse15 (= |v_P2_#t~ite48_67| v_~y$r_buff0_thd3~0_336) .cse16 .cse25)) (= |v_P2_#t~ite48_67| |v_P2_#t~ite49_61|) .cse32))))))) (= |v_~#y~0.base_184| v_~__unbuffered_p2_EAX$read_delayed_var~0.base_32) (let ((.cse35 (= |v_P2_#t~ite34_57| |v_P2Thread1of1ForFork0_#t~ite34_1|)) (.cse33 (= |v_P2_#t~ite33_63| |v_P2Thread1of1ForFork0_#t~ite33_1|)) (.cse34 (= |v_P2_#t~ite32_75| |v_P2Thread1of1ForFork0_#t~ite32_1|))) (or (and .cse23 .cse33 .cse34 (= |v_P2_#t~ite35_53| |v_P2Thread1of1ForFork0_#t~ite35_1|) .cse35 (= v_~y$w_buff1~0_134 v_~y$w_buff1~0_133)) (and (or (and (= v_~y$w_buff1~0_134 |v_P2_#t~ite35_53|) .cse21 .cse33 .cse34 .cse35) (and (= |v_P2_#t~ite34_57| |v_P2_#t~ite35_53|) (or (and (= v_~y$w_buff1~0_134 |v_P2_#t~ite34_57|) .cse2 .cse33 .cse34 .cse9) (and (or (and .cse17 (= |v_P2_#t~ite32_75| |v_P2_#t~ite33_63|) (let ((.cse36 (= v_~y$w_buff1~0_134 |v_P2_#t~ite32_75|))) (or (and .cse18 .cse36) (and .cse11 .cse16 .cse36 .cse19 .cse9)))) (and .cse11 .cse15 .cse34 .cse16 (= v_~y$w_buff1~0_134 |v_P2_#t~ite33_63|) .cse9)) .cse20 (= |v_P2_#t~ite34_57| |v_P2_#t~ite33_63|))) .cse9)) (= v_~y$w_buff1~0_133 |v_P2_#t~ite35_53|) .cse26))) (let ((.cse37 (= |v_P2_#t~ite28_61| |v_P2Thread1of1ForFork0_#t~ite28_1|)) (.cse38 (= |v_P2_#t~ite27_73| |v_P2Thread1of1ForFork0_#t~ite27_1|)) (.cse39 (= |v_P2_#t~ite29_59| |v_P2Thread1of1ForFork0_#t~ite29_1|))) (or (and .cse37 (= v_~y$w_buff0~0_135 v_~y$w_buff0~0_134) .cse23 .cse38 (= |v_P2_#t~ite30_47| |v_P2Thread1of1ForFork0_#t~ite30_1|) .cse39) (and (or (and (or (and .cse37 .cse2 .cse38 (= |v_P2_#t~ite29_59| v_~y$w_buff0~0_135) .cse9) (and (= |v_P2_#t~ite29_59| |v_P2_#t~ite28_61|) .cse20 (or (and .cse17 (= |v_P2_#t~ite27_73| |v_P2_#t~ite28_61|) (let ((.cse40 (= |v_P2_#t~ite27_73| v_~y$w_buff0~0_135))) (or (and .cse11 .cse40 .cse16 .cse19 .cse9) (and .cse18 .cse40)))) (and .cse11 .cse38 .cse15 (= |v_P2_#t~ite28_61| v_~y$w_buff0~0_135) .cse16 .cse9)))) (= |v_P2_#t~ite29_59| |v_P2_#t~ite30_47|) .cse9) (and .cse37 (= |v_P2_#t~ite30_47| v_~y$w_buff0~0_135) .cse21 .cse38 .cse39)) .cse26 (= |v_P2_#t~ite30_47| v_~y$w_buff0~0_134)))) (= |v_~#y~0.offset_184| v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_32) (= (ite (= |v_P2_#t~ite41_55| 0) 0 1) v_~y$w_buff0_used~0_480) (= v_~__unbuffered_p2_EAX$read_delayed~0_31 1) (= 0 v_~y$flush_delayed~0_48) (= (store |v_#memory_int_288| |v_~#y~0.base_184| (store .cse41 |v_~#y~0.offset_184| |v_P2_#t~ite60_37|)) |v_#memory_int_286|) (= |v_P2Thread1of1ForFork0_#t~nondet13_1| v_~weak$$choice2~0_94) (let ((.cse42 (= |v_P2_#t~ite43_77| |v_P2Thread1of1ForFork0_#t~ite43_1|)) (.cse43 (= |v_P2_#t~ite44_73| |v_P2Thread1of1ForFork0_#t~ite44_1|)) (.cse44 (= |v_P2_#t~ite42_87| |v_P2Thread1of1ForFork0_#t~ite42_1|))) (or (and (or (and .cse42 (= |v_P2_#t~ite45_65| v_~y$w_buff1_used~0_394) .cse43 .cse27 .cse44) (and .cse28 (= |v_P2_#t~ite44_73| |v_P2_#t~ite45_65|) (or (and (or (and (= |v_P2_#t~ite42_87| |v_P2_#t~ite43_77|) (let ((.cse45 (= |v_P2_#t~ite42_87| 0))) (or (and .cse28 .cse11 .cse45 .cse16 .cse19) (and (or .cse2 .cse46 .cse15 .cse27) .cse45))) (or .cse2 .cse46 .cse27 .cse19)) (and (= |v_P2_#t~ite43_77| v_~weak$$choice0~0_145) .cse28 .cse11 .cse15 .cse16 .cse44)) .cse32 (= |v_P2_#t~ite44_73| |v_P2_#t~ite43_77|)) (and .cse42 .cse2 .cse28 (= |v_P2_#t~ite44_73| 0) .cse44)))) (= |v_P2_#t~ite45_65| v_~y$w_buff1_used~0_393) .cse26) (and .cse42 (= |v_P2_#t~ite45_65| |v_P2Thread1of1ForFork0_#t~ite45_1|) .cse23 .cse43 (= v_~y$w_buff1_used~0_394 v_~y$w_buff1_used~0_393) .cse44))) (= |v_P2Thread1of1ForFork0_#t~nondet15_1| v_~weak$$choice1~0_73) (let ((.cse47 (= |v_P2Thread1of1ForFork0_#t~ite39_1| |v_P2_#t~ite39_53|)) (.cse49 (= |v_P2Thread1of1ForFork0_#t~ite37_1| |v_P2_#t~ite37_67|)) (.cse50 (= |v_P2Thread1of1ForFork0_#t~ite38_1| |v_P2_#t~ite38_63|))) (or (and .cse47 .cse23 (= |v_P2_#t~ite41_55| .cse48) (= |v_P2Thread1of1ForFork0_#t~ite40_1| |v_P2_#t~ite40_39|) .cse49 .cse50) (and .cse26 (= |v_P2_#t~ite40_39| |v_P2_#t~ite41_55|) (or (and (= |v_P2_#t~ite39_53| |v_P2_#t~ite40_39|) (or (and .cse2 (= |v_P2_#t~ite39_53| 0) .cse49 .cse50 .cse9) (and (= |v_P2_#t~ite39_53| |v_P2_#t~ite38_63|) (or (and (= |v_P2_#t~ite38_63| (ite (or .cse13 .cse14) 1 0)) .cse11 .cse15 .cse16 .cse49 .cse9) (and .cse17 (let ((.cse51 (= |v_P2_#t~ite37_67| v_~weak$$choice0~0_145))) (or (and .cse18 .cse51) (and .cse11 .cse51 .cse16 .cse19 .cse9))) (= |v_P2_#t~ite38_63| (mod |v_P2_#t~ite37_67| 256)))) .cse20)) .cse9) (and .cse47 .cse21 .cse49 (= |v_P2_#t~ite40_39| .cse48) .cse50))))) (or (and .cse23 (= |v_P2Thread1of1ForFork0_#t~mem59_1| |v_P2_#t~mem59_36|) (= |v_P2_#t~ite60_37| v_~y$mem_tmp~0_32)) (and (= |v_P2_#t~ite60_37| |v_P2_#t~mem59_36|) (= |v_P2_#t~mem59_36| v_~__unbuffered_p2_EAX~0_43) .cse26)) (let ((.cse57 (= |v_P2_#t~ite54_55| |v_P2Thread1of1ForFork0_#t~ite54_1|)) (.cse52 (= |v_P2_#t~ite53_73| |v_P2Thread1of1ForFork0_#t~ite53_1|)) (.cse56 (= |v_P2_#t~ite52_67| |v_P2Thread1of1ForFork0_#t~ite52_1|)) (.cse58 (= |v_P2_#t~ite55_53| |v_P2Thread1of1ForFork0_#t~ite55_1|))) (or (and .cse26 (or (and .cse28 (= |v_P2_#t~ite55_53| |v_P2_#t~ite56_47|) (let ((.cse53 (= (mod v_~y$r_buff0_thd3~0_335 256) 0))) (let ((.cse55 (not .cse53))) (or (and (or (and (= |v_P2_#t~ite54_55| |v_P2_#t~ite52_67|) .cse29 .cse28 .cse52 .cse15 .cse53 (or (and .cse14 (= |v_P2_#t~ite52_67| v_~y$r_buff1_thd3~0_294)) (and .cse12 (= |v_P2_#t~ite52_67| 0)))) (and (let ((.cse54 (= |v_P2_#t~ite53_73| 0))) (or (and .cse29 .cse28 .cse54 .cse53 .cse19) (and (or .cse55 .cse15 .cse31 .cse27) .cse54))) .cse56 (= |v_P2_#t~ite54_55| |v_P2_#t~ite53_73|) (or .cse55 .cse31 .cse27 .cse19))) (or .cse53 .cse27) (= |v_P2_#t~ite54_55| |v_P2_#t~ite55_53|)) (and .cse28 .cse57 .cse55 .cse52 .cse56 (= |v_P2_#t~ite55_53| 0)))))) (and .cse57 (= |v_P2_#t~ite56_47| v_~y$r_buff1_thd3~0_294) .cse52 .cse56 .cse58 .cse27)) (= |v_P2_#t~ite56_47| v_~y$r_buff1_thd3~0_293)) (and (= v_~y$r_buff1_thd3~0_294 v_~y$r_buff1_thd3~0_293) .cse57 .cse23 .cse52 .cse56 (= |v_P2_#t~ite56_47| |v_P2Thread1of1ForFork0_#t~ite56_1|) .cse58))) (= |v_P2Thread1of1ForFork0_#t~nondet12_1| v_~weak$$choice0~0_145))))) InVars {P2Thread1of1ForFork0_#t~mem16=|v_P2Thread1of1ForFork0_#t~mem16_1|, P2Thread1of1ForFork0_#t~ite20=|v_P2Thread1of1ForFork0_#t~ite20_1|, P2Thread1of1ForFork0_#t~ite47=|v_P2Thread1of1ForFork0_#t~ite47_1|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_294, P2Thread1of1ForFork0_#t~ite49=|v_P2Thread1of1ForFork0_#t~ite49_1|, P2Thread1of1ForFork0_#t~ite28=|v_P2Thread1of1ForFork0_#t~ite28_1|, P2Thread1of1ForFork0_#t~ite22=|v_P2Thread1of1ForFork0_#t~ite22_1|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_1|, P2Thread1of1ForFork0_#t~ite45=|v_P2Thread1of1ForFork0_#t~ite45_1|, P2Thread1of1ForFork0_#t~ite24=|v_P2Thread1of1ForFork0_#t~ite24_1|, P2Thread1of1ForFork0_#t~nondet15=|v_P2Thread1of1ForFork0_#t~nondet15_1|, P2Thread1of1ForFork0_#t~ite53=|v_P2Thread1of1ForFork0_#t~ite53_1|, P2Thread1of1ForFork0_#t~nondet13=|v_P2Thread1of1ForFork0_#t~nondet13_1|, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_1|, P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_1|, ~y$w_buff1~0=v_~y$w_buff1~0_134, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_1|, P2Thread1of1ForFork0_#t~ite55=|v_P2Thread1of1ForFork0_#t~ite55_1|, P2Thread1of1ForFork0_#t~ite34=|v_P2Thread1of1ForFork0_#t~ite34_1|, P2Thread1of1ForFork0_#t~ite19=|v_P2Thread1of1ForFork0_#t~ite19_1|, P2Thread1of1ForFork0_#t~mem21=|v_P2Thread1of1ForFork0_#t~mem21_1|, ~#y~0.offset=|v_~#y~0.offset_184|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_481, P2Thread1of1ForFork0_#t~mem59=|v_P2Thread1of1ForFork0_#t~mem59_1|, P2Thread1of1ForFork0_#t~mem17=|v_P2Thread1of1ForFork0_#t~mem17_1|, P2Thread1of1ForFork0_#t~ite40=|v_P2Thread1of1ForFork0_#t~ite40_1|, P2Thread1of1ForFork0_#t~ite42=|v_P2Thread1of1ForFork0_#t~ite42_1|, ~#y~0.base=|v_~#y~0.base_184|, P2Thread1of1ForFork0_#t~ite25=|v_P2Thread1of1ForFork0_#t~ite25_1|, P2Thread1of1ForFork0_#t~ite48=|v_P2Thread1of1ForFork0_#t~ite48_1|, P2Thread1of1ForFork0_#t~ite27=|v_P2Thread1of1ForFork0_#t~ite27_1|, P2Thread1of1ForFork0_#t~ite44=|v_P2Thread1of1ForFork0_#t~ite44_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_336, ~y$w_buff0~0=v_~y$w_buff0~0_135, P2Thread1of1ForFork0_#t~ite23=|v_P2Thread1of1ForFork0_#t~ite23_1|, P2Thread1of1ForFork0_#t~ite29=|v_P2Thread1of1ForFork0_#t~ite29_1|, P2Thread1of1ForFork0_#t~ite52=|v_P2Thread1of1ForFork0_#t~ite52_1|, P2Thread1of1ForFork0_#t~ite50=|v_P2Thread1of1ForFork0_#t~ite50_1|, P2Thread1of1ForFork0_#t~nondet12=|v_P2Thread1of1ForFork0_#t~nondet12_1|, P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_1|, P2Thread1of1ForFork0_#t~ite39=|v_P2Thread1of1ForFork0_#t~ite39_1|, P2Thread1of1ForFork0_#t~ite56=|v_P2Thread1of1ForFork0_#t~ite56_1|, P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_1|, P2Thread1of1ForFork0_#t~ite54=|v_P2Thread1of1ForFork0_#t~ite54_1|, P2Thread1of1ForFork0_#t~ite35=|v_P2Thread1of1ForFork0_#t~ite35_1|, #memory_int=|v_#memory_int_288|, P2Thread1of1ForFork0_#t~ite18=|v_P2Thread1of1ForFork0_#t~ite18_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_394} OutVars{P2Thread1of1ForFork0_#t~mem16=|v_P2Thread1of1ForFork0_#t~mem16_2|, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_32, ~__unbuffered_p2_EAX$read_delayed_var~0.base=v_~__unbuffered_p2_EAX$read_delayed_var~0.base_32, P2Thread1of1ForFork0_#t~ite41=|v_P2Thread1of1ForFork0_#t~ite41_1|, P2Thread1of1ForFork0_#t~ite20=|v_P2Thread1of1ForFork0_#t~ite20_2|, P2Thread1of1ForFork0_#t~ite60=|v_P2Thread1of1ForFork0_#t~ite60_1|, P2Thread1of1ForFork0_#t~ite26=|v_P2Thread1of1ForFork0_#t~ite26_1|, P2Thread1of1ForFork0_#t~ite47=|v_P2Thread1of1ForFork0_#t~ite47_2|, ~y$mem_tmp~0=v_~y$mem_tmp~0_32, ~weak$$choice1~0=v_~weak$$choice1~0_73, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_293, P2Thread1of1ForFork0_#t~ite49=|v_P2Thread1of1ForFork0_#t~ite49_2|, P2Thread1of1ForFork0_#t~ite28=|v_P2Thread1of1ForFork0_#t~ite28_2|, P2Thread1of1ForFork0_#t~ite22=|v_P2Thread1of1ForFork0_#t~ite22_2|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_2|, P2Thread1of1ForFork0_#t~ite45=|v_P2Thread1of1ForFork0_#t~ite45_2|, P2Thread1of1ForFork0_#t~ite24=|v_P2Thread1of1ForFork0_#t~ite24_2|, ~y$flush_delayed~0=v_~y$flush_delayed~0_48, P2Thread1of1ForFork0_#t~mem58=|v_P2Thread1of1ForFork0_#t~mem58_1|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_43, P2Thread1of1ForFork0_#t~mem14=|v_P2Thread1of1ForFork0_#t~mem14_1|, P2Thread1of1ForFork0_#t~nondet15=|v_P2Thread1of1ForFork0_#t~nondet15_2|, P2Thread1of1ForFork0_#t~ite53=|v_P2Thread1of1ForFork0_#t~ite53_2|, P2Thread1of1ForFork0_#t~nondet13=|v_P2Thread1of1ForFork0_#t~nondet13_2|, P2Thread1of1ForFork0_#t~ite51=|v_P2Thread1of1ForFork0_#t~ite51_1|, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_2|, ~weak$$choice0~0=v_~weak$$choice0~0_145, P2Thread1of1ForFork0_#t~ite36=|v_P2Thread1of1ForFork0_#t~ite36_1|, P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_2|, ~y$w_buff1~0=v_~y$w_buff1~0_133, P2Thread1of1ForFork0_#t~ite57=|v_P2Thread1of1ForFork0_#t~ite57_1|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_2|, P2Thread1of1ForFork0_#t~ite55=|v_P2Thread1of1ForFork0_#t~ite55_2|, P2Thread1of1ForFork0_#t~ite34=|v_P2Thread1of1ForFork0_#t~ite34_2|, P2Thread1of1ForFork0_#t~ite19=|v_P2Thread1of1ForFork0_#t~ite19_2|, P2Thread1of1ForFork0_#t~mem21=|v_P2Thread1of1ForFork0_#t~mem21_2|, ~#y~0.offset=|v_~#y~0.offset_184|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_480, P2Thread1of1ForFork0_#t~mem59=|v_P2Thread1of1ForFork0_#t~mem59_2|, P2Thread1of1ForFork0_#t~mem17=|v_P2Thread1of1ForFork0_#t~mem17_2|, P2Thread1of1ForFork0_#t~ite40=|v_P2Thread1of1ForFork0_#t~ite40_2|, P2Thread1of1ForFork0_#t~ite42=|v_P2Thread1of1ForFork0_#t~ite42_2|, ~#y~0.base=|v_~#y~0.base_184|, P2Thread1of1ForFork0_#t~ite25=|v_P2Thread1of1ForFork0_#t~ite25_2|, P2Thread1of1ForFork0_#t~ite48=|v_P2Thread1of1ForFork0_#t~ite48_2|, P2Thread1of1ForFork0_#t~ite27=|v_P2Thread1of1ForFork0_#t~ite27_2|, P2Thread1of1ForFork0_#t~ite44=|v_P2Thread1of1ForFork0_#t~ite44_2|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_335, ~y$w_buff0~0=v_~y$w_buff0~0_134, P2Thread1of1ForFork0_#t~ite46=|v_P2Thread1of1ForFork0_#t~ite46_1|, P2Thread1of1ForFork0_#t~ite23=|v_P2Thread1of1ForFork0_#t~ite23_2|, P2Thread1of1ForFork0_#t~ite29=|v_P2Thread1of1ForFork0_#t~ite29_2|, P2Thread1of1ForFork0_#t~ite52=|v_P2Thread1of1ForFork0_#t~ite52_2|, P2Thread1of1ForFork0_#t~ite50=|v_P2Thread1of1ForFork0_#t~ite50_2|, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_1|, P2Thread1of1ForFork0_#t~nondet12=|v_P2Thread1of1ForFork0_#t~nondet12_2|, ~__unbuffered_p2_EAX$read_delayed~0=v_~__unbuffered_p2_EAX$read_delayed~0_31, P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_2|, P2Thread1of1ForFork0_#t~ite39=|v_P2Thread1of1ForFork0_#t~ite39_2|, P2Thread1of1ForFork0_#t~ite56=|v_P2Thread1of1ForFork0_#t~ite56_2|, P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_2|, P2Thread1of1ForFork0_#t~ite54=|v_P2Thread1of1ForFork0_#t~ite54_2|, P2Thread1of1ForFork0_#t~ite35=|v_P2Thread1of1ForFork0_#t~ite35_2|, #memory_int=|v_#memory_int_286|, P2Thread1of1ForFork0_#t~ite18=|v_P2Thread1of1ForFork0_#t~ite18_2|, ~weak$$choice2~0=v_~weak$$choice2~0_94, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_393} AuxVars[|v_P2_#t~ite48_67|, |v_P2_#t~ite25_63|, |v_P2_#t~mem16_52|, |v_P2_#t~ite43_77|, |v_P2_#t~ite42_87|, |v_P2_#t~mem17_88|, |v_P2_#t~ite52_67|, |v_P2_#t~ite56_47|, |v_P2_#t~ite54_55|, |v_P2_#t~ite19_87|, |v_P2_#t~mem21_92|, |v_P2_#t~ite35_53|, |v_P2_#t~ite40_39|, |v_P2_#t~mem59_36|, |v_P2_#t~ite38_63|, |v_P2_#t~ite39_53|, |v_P2_#t~ite45_65|, |v_P2_#t~ite22_83|, |v_P2_#t~ite27_73|, |v_P2_#t~ite47_69|, |v_P2_#t~ite28_61|, |v_P2_#t~ite44_73|, |v_P2_#t~ite30_47|, |v_P2_#t~ite60_37|, |v_P2_#t~ite29_59|, |v_P2_#t~ite49_61|, |v_P2_#t~ite23_71|, |v_P2_#t~ite18_85|, |v_P2_#t~ite33_63|, |v_P2_#t~ite53_73|, |v_P2_#t~ite37_67|, |v_P2_#t~ite55_53|, |v_P2_#t~ite34_57|, |v_P2_#t~ite32_75|, |v_P2_#t~ite50_47|, |v_P2_#t~ite24_59|, |v_P2_#t~ite20_77|, |v_P2_#t~ite41_55|] AssignedVars[P2Thread1of1ForFork0_#t~mem16, ~__unbuffered_p2_EAX$read_delayed_var~0.offset, ~__unbuffered_p2_EAX$read_delayed_var~0.base, P2Thread1of1ForFork0_#t~ite41, P2Thread1of1ForFork0_#t~ite20, P2Thread1of1ForFork0_#t~ite60, P2Thread1of1ForFork0_#t~ite26, P2Thread1of1ForFork0_#t~ite47, ~y$mem_tmp~0, ~weak$$choice1~0, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#t~ite49, P2Thread1of1ForFork0_#t~ite28, P2Thread1of1ForFork0_#t~ite22, P2Thread1of1ForFork0_#t~ite43, P2Thread1of1ForFork0_#t~ite45, P2Thread1of1ForFork0_#t~ite24, ~y$flush_delayed~0, P2Thread1of1ForFork0_#t~mem58, ~__unbuffered_p2_EAX~0, P2Thread1of1ForFork0_#t~mem14, P2Thread1of1ForFork0_#t~nondet15, P2Thread1of1ForFork0_#t~ite53, P2Thread1of1ForFork0_#t~nondet13, P2Thread1of1ForFork0_#t~ite51, P2Thread1of1ForFork0_#t~ite30, ~weak$$choice0~0, P2Thread1of1ForFork0_#t~ite36, P2Thread1of1ForFork0_#t~ite38, ~y$w_buff1~0, P2Thread1of1ForFork0_#t~ite57, P2Thread1of1ForFork0_#t~ite32, P2Thread1of1ForFork0_#t~ite55, P2Thread1of1ForFork0_#t~ite34, P2Thread1of1ForFork0_#t~ite19, P2Thread1of1ForFork0_#t~mem21, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~mem59, P2Thread1of1ForFork0_#t~mem17, P2Thread1of1ForFork0_#t~ite40, P2Thread1of1ForFork0_#t~ite42, P2Thread1of1ForFork0_#t~ite25, P2Thread1of1ForFork0_#t~ite48, P2Thread1of1ForFork0_#t~ite27, P2Thread1of1ForFork0_#t~ite44, ~y$r_buff0_thd3~0, ~y$w_buff0~0, P2Thread1of1ForFork0_#t~ite46, P2Thread1of1ForFork0_#t~ite23, P2Thread1of1ForFork0_#t~ite29, P2Thread1of1ForFork0_#t~ite52, P2Thread1of1ForFork0_#t~ite50, P2Thread1of1ForFork0_#t~ite31, P2Thread1of1ForFork0_#t~nondet12, ~__unbuffered_p2_EAX$read_delayed~0, P2Thread1of1ForFork0_#t~ite37, P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite56, P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite54, P2Thread1of1ForFork0_#t~ite35, #memory_int, P2Thread1of1ForFork0_#t~ite18, ~weak$$choice2~0, ~y$w_buff1_used~0] and [1246] L2-1-->L866: Formula: (let ((.cse15 (= (mod v_~y$w_buff0_used~0_417 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd0~0_72 256) 0)) (.cse12 (= (mod v_~y$w_buff0_used~0_416 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd0~0_58 256) 0)) (.cse16 (= (mod v_~y$w_buff1_used~0_322 256) 0))) (let ((.cse4 (not .cse16)) (.cse0 (or .cse13 .cse16)) (.cse5 (not .cse13)) (.cse2 (not .cse12)) (.cse1 (or .cse14 .cse12)) (.cse8 (select |v_#memory_int_247| |v_~#y~0.base_164|)) (.cse9 (not .cse15)) (.cse3 (not .cse14)) (.cse6 (or .cse14 .cse15))) (and (or (and (= v_~y$w_buff1_used~0_322 v_~y$w_buff1_used~0_321) .cse0 .cse1) (and (or (and .cse2 .cse3) (and .cse4 .cse5)) (= v_~y$w_buff1_used~0_321 0))) (let ((.cse7 (= |v_ULTIMATE.start_main_#t~mem71_25| |v_ULTIMATE.start_main_#t~mem71_29|))) (or (and .cse6 (or (and .cse4 .cse7 .cse5 (= v_~y$w_buff1~0_111 |v_ULTIMATE.start_main_#t~ite72_28|)) (and .cse0 (= |v_ULTIMATE.start_main_#t~mem71_29| (select .cse8 |v_~#y~0.offset_164|)) (= |v_ULTIMATE.start_main_#t~mem71_29| |v_ULTIMATE.start_main_#t~ite72_28|))) (= |v_ULTIMATE.start_main_#t~ite73_36| |v_ULTIMATE.start_main_#t~ite72_28|)) (and (= |v_ULTIMATE.start_main_#t~ite72_24| |v_ULTIMATE.start_main_#t~ite72_28|) (= |v_ULTIMATE.start_main_#t~ite73_36| v_~y$w_buff0~0_108) .cse7 .cse9 .cse3))) (let ((.cse10 (= (mod v_~y$r_buff0_thd0~0_71 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_321 256) 0))) (or (and (= v_~y$r_buff1_thd0~0_57 0) (or (and .cse2 (not .cse10)) (and (not .cse11) .cse5))) (and (or .cse10 .cse12) (or .cse13 .cse11) (= v_~y$r_buff1_thd0~0_58 v_~y$r_buff1_thd0~0_57)))) (or (and .cse2 (= v_~y$r_buff0_thd0~0_71 0) .cse3) (and .cse1 (= v_~y$r_buff0_thd0~0_72 v_~y$r_buff0_thd0~0_71))) (= (store |v_#memory_int_247| |v_~#y~0.base_164| (store .cse8 |v_~#y~0.offset_164| |v_ULTIMATE.start_main_#t~ite73_36|)) |v_#memory_int_246|) (or (and .cse9 (= v_~y$w_buff0_used~0_416 0) .cse3) (and (= v_~y$w_buff0_used~0_417 v_~y$w_buff0_used~0_416) .cse6))))) InVars {~#y~0.offset=|v_~#y~0.offset_164|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_24|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_417, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_72, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_247|, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_25|, ~#y~0.base=|v_~#y~0.base_164|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_58, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_322} OutVars{~#y~0.offset=|v_~#y~0.offset_164|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_416, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_23|, ~#y~0.base=|v_~#y~0.base_164|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_26|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_30|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_28|, ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_32|, ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_24|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_22|, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_71, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_246|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_57, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_321} AuxVars[|v_ULTIMATE.start_main_#t~ite73_36|, |v_ULTIMATE.start_main_#t~ite72_28|, |v_ULTIMATE.start_main_#t~mem71_29|] AssignedVars[ULTIMATE.start_main_#t~ite73, ULTIMATE.start_main_#t~ite74, ULTIMATE.start_main_#t~ite72, ~y$w_buff0_used~0, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem71, #memory_int, ULTIMATE.start_main_#t~ite77, ~y$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76, ~y$w_buff1_used~0] under condition null [2021-01-26 23:10:46,107 WARN L146 IndependenceRelation]: Expensive independence query (4134 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1246] L2-1-->L866: Formula: (let ((.cse15 (= (mod v_~y$w_buff0_used~0_417 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd0~0_72 256) 0)) (.cse12 (= (mod v_~y$w_buff0_used~0_416 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd0~0_58 256) 0)) (.cse16 (= (mod v_~y$w_buff1_used~0_322 256) 0))) (let ((.cse4 (not .cse16)) (.cse0 (or .cse13 .cse16)) (.cse5 (not .cse13)) (.cse2 (not .cse12)) (.cse1 (or .cse14 .cse12)) (.cse8 (select |v_#memory_int_247| |v_~#y~0.base_164|)) (.cse9 (not .cse15)) (.cse3 (not .cse14)) (.cse6 (or .cse14 .cse15))) (and (or (and (= v_~y$w_buff1_used~0_322 v_~y$w_buff1_used~0_321) .cse0 .cse1) (and (or (and .cse2 .cse3) (and .cse4 .cse5)) (= v_~y$w_buff1_used~0_321 0))) (let ((.cse7 (= |v_ULTIMATE.start_main_#t~mem71_25| |v_ULTIMATE.start_main_#t~mem71_29|))) (or (and .cse6 (or (and .cse4 .cse7 .cse5 (= v_~y$w_buff1~0_111 |v_ULTIMATE.start_main_#t~ite72_28|)) (and .cse0 (= |v_ULTIMATE.start_main_#t~mem71_29| (select .cse8 |v_~#y~0.offset_164|)) (= |v_ULTIMATE.start_main_#t~mem71_29| |v_ULTIMATE.start_main_#t~ite72_28|))) (= |v_ULTIMATE.start_main_#t~ite73_36| |v_ULTIMATE.start_main_#t~ite72_28|)) (and (= |v_ULTIMATE.start_main_#t~ite72_24| |v_ULTIMATE.start_main_#t~ite72_28|) (= |v_ULTIMATE.start_main_#t~ite73_36| v_~y$w_buff0~0_108) .cse7 .cse9 .cse3))) (let ((.cse10 (= (mod v_~y$r_buff0_thd0~0_71 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_321 256) 0))) (or (and (= v_~y$r_buff1_thd0~0_57 0) (or (and .cse2 (not .cse10)) (and (not .cse11) .cse5))) (and (or .cse10 .cse12) (or .cse13 .cse11) (= v_~y$r_buff1_thd0~0_58 v_~y$r_buff1_thd0~0_57)))) (or (and .cse2 (= v_~y$r_buff0_thd0~0_71 0) .cse3) (and .cse1 (= v_~y$r_buff0_thd0~0_72 v_~y$r_buff0_thd0~0_71))) (= (store |v_#memory_int_247| |v_~#y~0.base_164| (store .cse8 |v_~#y~0.offset_164| |v_ULTIMATE.start_main_#t~ite73_36|)) |v_#memory_int_246|) (or (and .cse9 (= v_~y$w_buff0_used~0_416 0) .cse3) (and (= v_~y$w_buff0_used~0_417 v_~y$w_buff0_used~0_416) .cse6))))) InVars {~#y~0.offset=|v_~#y~0.offset_164|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_24|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_417, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_72, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_247|, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_25|, ~#y~0.base=|v_~#y~0.base_164|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_58, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_322} OutVars{~#y~0.offset=|v_~#y~0.offset_164|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_416, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_23|, ~#y~0.base=|v_~#y~0.base_164|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_26|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_30|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_28|, ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_32|, ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_24|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_22|, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_71, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_246|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_57, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_321} AuxVars[|v_ULTIMATE.start_main_#t~ite73_36|, |v_ULTIMATE.start_main_#t~ite72_28|, |v_ULTIMATE.start_main_#t~mem71_29|] AssignedVars[ULTIMATE.start_main_#t~ite73, ULTIMATE.start_main_#t~ite74, ULTIMATE.start_main_#t~ite72, ~y$w_buff0_used~0, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem71, #memory_int, ULTIMATE.start_main_#t~ite77, ~y$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76, ~y$w_buff1_used~0] under condition null [2021-01-26 23:10:46,404 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:10:51,237 WARN L146 IndependenceRelation]: Expensive independence query (4096 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition null [2021-01-26 23:10:51,248 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:10:55,333 WARN L146 IndependenceRelation]: Expensive independence query (4084 ms) for statements [1246] L2-1-->L866: Formula: (let ((.cse15 (= (mod v_~y$w_buff0_used~0_417 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd0~0_72 256) 0)) (.cse12 (= (mod v_~y$w_buff0_used~0_416 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd0~0_58 256) 0)) (.cse16 (= (mod v_~y$w_buff1_used~0_322 256) 0))) (let ((.cse4 (not .cse16)) (.cse0 (or .cse13 .cse16)) (.cse5 (not .cse13)) (.cse2 (not .cse12)) (.cse1 (or .cse14 .cse12)) (.cse8 (select |v_#memory_int_247| |v_~#y~0.base_164|)) (.cse9 (not .cse15)) (.cse3 (not .cse14)) (.cse6 (or .cse14 .cse15))) (and (or (and (= v_~y$w_buff1_used~0_322 v_~y$w_buff1_used~0_321) .cse0 .cse1) (and (or (and .cse2 .cse3) (and .cse4 .cse5)) (= v_~y$w_buff1_used~0_321 0))) (let ((.cse7 (= |v_ULTIMATE.start_main_#t~mem71_25| |v_ULTIMATE.start_main_#t~mem71_29|))) (or (and .cse6 (or (and .cse4 .cse7 .cse5 (= v_~y$w_buff1~0_111 |v_ULTIMATE.start_main_#t~ite72_28|)) (and .cse0 (= |v_ULTIMATE.start_main_#t~mem71_29| (select .cse8 |v_~#y~0.offset_164|)) (= |v_ULTIMATE.start_main_#t~mem71_29| |v_ULTIMATE.start_main_#t~ite72_28|))) (= |v_ULTIMATE.start_main_#t~ite73_36| |v_ULTIMATE.start_main_#t~ite72_28|)) (and (= |v_ULTIMATE.start_main_#t~ite72_24| |v_ULTIMATE.start_main_#t~ite72_28|) (= |v_ULTIMATE.start_main_#t~ite73_36| v_~y$w_buff0~0_108) .cse7 .cse9 .cse3))) (let ((.cse10 (= (mod v_~y$r_buff0_thd0~0_71 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_321 256) 0))) (or (and (= v_~y$r_buff1_thd0~0_57 0) (or (and .cse2 (not .cse10)) (and (not .cse11) .cse5))) (and (or .cse10 .cse12) (or .cse13 .cse11) (= v_~y$r_buff1_thd0~0_58 v_~y$r_buff1_thd0~0_57)))) (or (and .cse2 (= v_~y$r_buff0_thd0~0_71 0) .cse3) (and .cse1 (= v_~y$r_buff0_thd0~0_72 v_~y$r_buff0_thd0~0_71))) (= (store |v_#memory_int_247| |v_~#y~0.base_164| (store .cse8 |v_~#y~0.offset_164| |v_ULTIMATE.start_main_#t~ite73_36|)) |v_#memory_int_246|) (or (and .cse9 (= v_~y$w_buff0_used~0_416 0) .cse3) (and (= v_~y$w_buff0_used~0_417 v_~y$w_buff0_used~0_416) .cse6))))) InVars {~#y~0.offset=|v_~#y~0.offset_164|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_24|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_417, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_72, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_247|, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_25|, ~#y~0.base=|v_~#y~0.base_164|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_58, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_322} OutVars{~#y~0.offset=|v_~#y~0.offset_164|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_416, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_23|, ~#y~0.base=|v_~#y~0.base_164|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_26|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_30|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_28|, ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_32|, ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_24|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_22|, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_71, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_246|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_57, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_321} AuxVars[|v_ULTIMATE.start_main_#t~ite73_36|, |v_ULTIMATE.start_main_#t~ite72_28|, |v_ULTIMATE.start_main_#t~mem71_29|] AssignedVars[ULTIMATE.start_main_#t~ite73, ULTIMATE.start_main_#t~ite74, ULTIMATE.start_main_#t~ite72, ~y$w_buff0_used~0, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem71, #memory_int, ULTIMATE.start_main_#t~ite77, ~y$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition null [2021-01-26 23:10:59,357 WARN L146 IndependenceRelation]: Expensive independence query (4023 ms) for statements [1246] L2-1-->L866: Formula: (let ((.cse15 (= (mod v_~y$w_buff0_used~0_417 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd0~0_72 256) 0)) (.cse12 (= (mod v_~y$w_buff0_used~0_416 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd0~0_58 256) 0)) (.cse16 (= (mod v_~y$w_buff1_used~0_322 256) 0))) (let ((.cse4 (not .cse16)) (.cse0 (or .cse13 .cse16)) (.cse5 (not .cse13)) (.cse2 (not .cse12)) (.cse1 (or .cse14 .cse12)) (.cse8 (select |v_#memory_int_247| |v_~#y~0.base_164|)) (.cse9 (not .cse15)) (.cse3 (not .cse14)) (.cse6 (or .cse14 .cse15))) (and (or (and (= v_~y$w_buff1_used~0_322 v_~y$w_buff1_used~0_321) .cse0 .cse1) (and (or (and .cse2 .cse3) (and .cse4 .cse5)) (= v_~y$w_buff1_used~0_321 0))) (let ((.cse7 (= |v_ULTIMATE.start_main_#t~mem71_25| |v_ULTIMATE.start_main_#t~mem71_29|))) (or (and .cse6 (or (and .cse4 .cse7 .cse5 (= v_~y$w_buff1~0_111 |v_ULTIMATE.start_main_#t~ite72_28|)) (and .cse0 (= |v_ULTIMATE.start_main_#t~mem71_29| (select .cse8 |v_~#y~0.offset_164|)) (= |v_ULTIMATE.start_main_#t~mem71_29| |v_ULTIMATE.start_main_#t~ite72_28|))) (= |v_ULTIMATE.start_main_#t~ite73_36| |v_ULTIMATE.start_main_#t~ite72_28|)) (and (= |v_ULTIMATE.start_main_#t~ite72_24| |v_ULTIMATE.start_main_#t~ite72_28|) (= |v_ULTIMATE.start_main_#t~ite73_36| v_~y$w_buff0~0_108) .cse7 .cse9 .cse3))) (let ((.cse10 (= (mod v_~y$r_buff0_thd0~0_71 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_321 256) 0))) (or (and (= v_~y$r_buff1_thd0~0_57 0) (or (and .cse2 (not .cse10)) (and (not .cse11) .cse5))) (and (or .cse10 .cse12) (or .cse13 .cse11) (= v_~y$r_buff1_thd0~0_58 v_~y$r_buff1_thd0~0_57)))) (or (and .cse2 (= v_~y$r_buff0_thd0~0_71 0) .cse3) (and .cse1 (= v_~y$r_buff0_thd0~0_72 v_~y$r_buff0_thd0~0_71))) (= (store |v_#memory_int_247| |v_~#y~0.base_164| (store .cse8 |v_~#y~0.offset_164| |v_ULTIMATE.start_main_#t~ite73_36|)) |v_#memory_int_246|) (or (and .cse9 (= v_~y$w_buff0_used~0_416 0) .cse3) (and (= v_~y$w_buff0_used~0_417 v_~y$w_buff0_used~0_416) .cse6))))) InVars {~#y~0.offset=|v_~#y~0.offset_164|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_24|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_417, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_72, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_247|, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_25|, ~#y~0.base=|v_~#y~0.base_164|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_58, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_322} OutVars{~#y~0.offset=|v_~#y~0.offset_164|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_416, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_23|, ~#y~0.base=|v_~#y~0.base_164|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_26|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_30|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_28|, ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_32|, ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_24|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_22|, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_71, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_246|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_57, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_321} AuxVars[|v_ULTIMATE.start_main_#t~ite73_36|, |v_ULTIMATE.start_main_#t~ite72_28|, |v_ULTIMATE.start_main_#t~mem71_29|] AssignedVars[ULTIMATE.start_main_#t~ite73, ULTIMATE.start_main_#t~ite74, ULTIMATE.start_main_#t~ite72, ~y$w_buff0_used~0, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem71, #memory_int, ULTIMATE.start_main_#t~ite77, ~y$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition 1675#(and (= ~z~0 0) (<= (div ~y$w_buff0_used~0 256) 0) (= ~__unbuffered_p0_EAX~0 0) (<= 1 ~y$w_buff0_used~0) (= ~y$r_buff0_thd2~0 1)) [2021-01-26 23:10:59,562 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:00,153 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:00,980 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:04,929 WARN L146 IndependenceRelation]: Expensive independence query (3948 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition 1489#(and (<= (div ~y$w_buff0_used~0 256) 0) (= ~__unbuffered_p0_EAX~0 0) (<= 1 ~y$w_buff0_used~0) (= ~y$r_buff0_thd2~0 1)) [2021-01-26 23:11:04,934 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:05,176 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:05,564 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:05,882 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:09,634 WARN L146 IndependenceRelation]: Expensive independence query (3751 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition 10317#(and (<= 1 ~main$tmp_guard1~0) (<= (div ~main$tmp_guard1~0 256) 0) (or (<= (+ |ULTIMATE.start___VERIFIER_assert_#in~expression| 255) 0) (<= 1 |ULTIMATE.start___VERIFIER_assert_#in~expression|)) (<= (div ~y$w_buff0_used~0 256) 0) (= ~__unbuffered_p0_EAX~0 0) (<= 1 ~y$w_buff0_used~0) (or (<= 1 ULTIMATE.start___VERIFIER_assert_~expression) (<= (+ ULTIMATE.start___VERIFIER_assert_~expression 255) 0)) (= ~y$r_buff0_thd2~0 1)) [2021-01-26 23:11:09,707 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:09,993 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:14,025 WARN L146 IndependenceRelation]: Expensive independence query (4031 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition 11523#(and (<= 1 ~main$tmp_guard1~0) (<= (div ~main$tmp_guard1~0 256) 0) (or (<= (+ |ULTIMATE.start___VERIFIER_assert_#in~expression| 255) 0) (<= 1 |ULTIMATE.start___VERIFIER_assert_#in~expression|)) (<= (div ~y$w_buff0_used~0 256) 0) (= ~__unbuffered_p0_EAX~0 0) (<= 1 ~y$w_buff0_used~0) (= ~y$r_buff0_thd2~0 1)) [2021-01-26 23:11:14,054 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:14,352 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:18,469 WARN L146 IndependenceRelation]: Expensive independence query (4115 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition 11735#(and (<= 1 ~main$tmp_guard1~0) (<= (div ~main$tmp_guard1~0 256) 0) (<= (div ~y$w_buff0_used~0 256) 0) (= ~__unbuffered_p0_EAX~0 0) (<= 1 ~y$w_buff0_used~0) (= ~y$r_buff0_thd2~0 1)) [2021-01-26 23:11:18,479 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:19,057 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:19,514 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:23,620 WARN L146 IndependenceRelation]: Expensive independence query (4105 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1246] L2-1-->L866: Formula: (let ((.cse15 (= (mod v_~y$w_buff0_used~0_417 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd0~0_72 256) 0)) (.cse12 (= (mod v_~y$w_buff0_used~0_416 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd0~0_58 256) 0)) (.cse16 (= (mod v_~y$w_buff1_used~0_322 256) 0))) (let ((.cse4 (not .cse16)) (.cse0 (or .cse13 .cse16)) (.cse5 (not .cse13)) (.cse2 (not .cse12)) (.cse1 (or .cse14 .cse12)) (.cse8 (select |v_#memory_int_247| |v_~#y~0.base_164|)) (.cse9 (not .cse15)) (.cse3 (not .cse14)) (.cse6 (or .cse14 .cse15))) (and (or (and (= v_~y$w_buff1_used~0_322 v_~y$w_buff1_used~0_321) .cse0 .cse1) (and (or (and .cse2 .cse3) (and .cse4 .cse5)) (= v_~y$w_buff1_used~0_321 0))) (let ((.cse7 (= |v_ULTIMATE.start_main_#t~mem71_25| |v_ULTIMATE.start_main_#t~mem71_29|))) (or (and .cse6 (or (and .cse4 .cse7 .cse5 (= v_~y$w_buff1~0_111 |v_ULTIMATE.start_main_#t~ite72_28|)) (and .cse0 (= |v_ULTIMATE.start_main_#t~mem71_29| (select .cse8 |v_~#y~0.offset_164|)) (= |v_ULTIMATE.start_main_#t~mem71_29| |v_ULTIMATE.start_main_#t~ite72_28|))) (= |v_ULTIMATE.start_main_#t~ite73_36| |v_ULTIMATE.start_main_#t~ite72_28|)) (and (= |v_ULTIMATE.start_main_#t~ite72_24| |v_ULTIMATE.start_main_#t~ite72_28|) (= |v_ULTIMATE.start_main_#t~ite73_36| v_~y$w_buff0~0_108) .cse7 .cse9 .cse3))) (let ((.cse10 (= (mod v_~y$r_buff0_thd0~0_71 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_321 256) 0))) (or (and (= v_~y$r_buff1_thd0~0_57 0) (or (and .cse2 (not .cse10)) (and (not .cse11) .cse5))) (and (or .cse10 .cse12) (or .cse13 .cse11) (= v_~y$r_buff1_thd0~0_58 v_~y$r_buff1_thd0~0_57)))) (or (and .cse2 (= v_~y$r_buff0_thd0~0_71 0) .cse3) (and .cse1 (= v_~y$r_buff0_thd0~0_72 v_~y$r_buff0_thd0~0_71))) (= (store |v_#memory_int_247| |v_~#y~0.base_164| (store .cse8 |v_~#y~0.offset_164| |v_ULTIMATE.start_main_#t~ite73_36|)) |v_#memory_int_246|) (or (and .cse9 (= v_~y$w_buff0_used~0_416 0) .cse3) (and (= v_~y$w_buff0_used~0_417 v_~y$w_buff0_used~0_416) .cse6))))) InVars {~#y~0.offset=|v_~#y~0.offset_164|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_24|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_417, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_72, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_247|, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_25|, ~#y~0.base=|v_~#y~0.base_164|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_58, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_322} OutVars{~#y~0.offset=|v_~#y~0.offset_164|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_416, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_23|, ~#y~0.base=|v_~#y~0.base_164|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_26|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_30|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_28|, ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_32|, ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_24|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_22|, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_71, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_246|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_57, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_321} AuxVars[|v_ULTIMATE.start_main_#t~ite73_36|, |v_ULTIMATE.start_main_#t~ite72_28|, |v_ULTIMATE.start_main_#t~mem71_29|] AssignedVars[ULTIMATE.start_main_#t~ite73, ULTIMATE.start_main_#t~ite74, ULTIMATE.start_main_#t~ite72, ~y$w_buff0_used~0, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem71, #memory_int, ULTIMATE.start_main_#t~ite77, ~y$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76, ~y$w_buff1_used~0] under condition 1489#(and (<= (div ~y$w_buff0_used~0 256) 0) (= ~__unbuffered_p0_EAX~0 0) (<= 1 ~y$w_buff0_used~0) (= ~y$r_buff0_thd2~0 1)) [2021-01-26 23:11:27,808 WARN L146 IndependenceRelation]: Expensive independence query (4085 ms) for statements [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] and [1246] L2-1-->L866: Formula: (let ((.cse15 (= (mod v_~y$w_buff0_used~0_417 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd0~0_72 256) 0)) (.cse12 (= (mod v_~y$w_buff0_used~0_416 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd0~0_58 256) 0)) (.cse16 (= (mod v_~y$w_buff1_used~0_322 256) 0))) (let ((.cse4 (not .cse16)) (.cse0 (or .cse13 .cse16)) (.cse5 (not .cse13)) (.cse2 (not .cse12)) (.cse1 (or .cse14 .cse12)) (.cse8 (select |v_#memory_int_247| |v_~#y~0.base_164|)) (.cse9 (not .cse15)) (.cse3 (not .cse14)) (.cse6 (or .cse14 .cse15))) (and (or (and (= v_~y$w_buff1_used~0_322 v_~y$w_buff1_used~0_321) .cse0 .cse1) (and (or (and .cse2 .cse3) (and .cse4 .cse5)) (= v_~y$w_buff1_used~0_321 0))) (let ((.cse7 (= |v_ULTIMATE.start_main_#t~mem71_25| |v_ULTIMATE.start_main_#t~mem71_29|))) (or (and .cse6 (or (and .cse4 .cse7 .cse5 (= v_~y$w_buff1~0_111 |v_ULTIMATE.start_main_#t~ite72_28|)) (and .cse0 (= |v_ULTIMATE.start_main_#t~mem71_29| (select .cse8 |v_~#y~0.offset_164|)) (= |v_ULTIMATE.start_main_#t~mem71_29| |v_ULTIMATE.start_main_#t~ite72_28|))) (= |v_ULTIMATE.start_main_#t~ite73_36| |v_ULTIMATE.start_main_#t~ite72_28|)) (and (= |v_ULTIMATE.start_main_#t~ite72_24| |v_ULTIMATE.start_main_#t~ite72_28|) (= |v_ULTIMATE.start_main_#t~ite73_36| v_~y$w_buff0~0_108) .cse7 .cse9 .cse3))) (let ((.cse10 (= (mod v_~y$r_buff0_thd0~0_71 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_321 256) 0))) (or (and (= v_~y$r_buff1_thd0~0_57 0) (or (and .cse2 (not .cse10)) (and (not .cse11) .cse5))) (and (or .cse10 .cse12) (or .cse13 .cse11) (= v_~y$r_buff1_thd0~0_58 v_~y$r_buff1_thd0~0_57)))) (or (and .cse2 (= v_~y$r_buff0_thd0~0_71 0) .cse3) (and .cse1 (= v_~y$r_buff0_thd0~0_72 v_~y$r_buff0_thd0~0_71))) (= (store |v_#memory_int_247| |v_~#y~0.base_164| (store .cse8 |v_~#y~0.offset_164| |v_ULTIMATE.start_main_#t~ite73_36|)) |v_#memory_int_246|) (or (and .cse9 (= v_~y$w_buff0_used~0_416 0) .cse3) (and (= v_~y$w_buff0_used~0_417 v_~y$w_buff0_used~0_416) .cse6))))) InVars {~#y~0.offset=|v_~#y~0.offset_164|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_24|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_417, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_72, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_247|, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_25|, ~#y~0.base=|v_~#y~0.base_164|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_58, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_322} OutVars{~#y~0.offset=|v_~#y~0.offset_164|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_416, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_23|, ~#y~0.base=|v_~#y~0.base_164|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_26|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_30|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_28|, ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_32|, ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_24|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_22|, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_71, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_246|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_57, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_321} AuxVars[|v_ULTIMATE.start_main_#t~ite73_36|, |v_ULTIMATE.start_main_#t~ite72_28|, |v_ULTIMATE.start_main_#t~mem71_29|] AssignedVars[ULTIMATE.start_main_#t~ite73, ULTIMATE.start_main_#t~ite74, ULTIMATE.start_main_#t~ite72, ~y$w_buff0_used~0, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem71, #memory_int, ULTIMATE.start_main_#t~ite77, ~y$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76, ~y$w_buff1_used~0] under condition 1489#(and (<= (div ~y$w_buff0_used~0 256) 0) (= ~__unbuffered_p0_EAX~0 0) (<= 1 ~y$w_buff0_used~0) (= ~y$r_buff0_thd2~0 1)) [2021-01-26 23:11:31,512 WARN L146 IndependenceRelation]: Expensive independence query (3474 ms) for statements [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] and [1182] L854-1-->L855: Formula: (= |v_#memory_int_24| (store |v_#memory_int_25| |v_ULTIMATE.start_main_~#t2686~0.base_3| (store (select |v_#memory_int_25| |v_ULTIMATE.start_main_~#t2686~0.base_3|) |v_ULTIMATE.start_main_~#t2686~0.offset_3| 2))) InVars {#memory_int=|v_#memory_int_25|, ULTIMATE.start_main_~#t2686~0.offset=|v_ULTIMATE.start_main_~#t2686~0.offset_3|, ULTIMATE.start_main_~#t2686~0.base=|v_ULTIMATE.start_main_~#t2686~0.base_3|} OutVars{#memory_int=|v_#memory_int_24|, ULTIMATE.start_main_~#t2686~0.offset=|v_ULTIMATE.start_main_~#t2686~0.offset_3|, ULTIMATE.start_main_~#t2686~0.base=|v_ULTIMATE.start_main_~#t2686~0.base_3|} AuxVars[] AssignedVars[#memory_int] under condition null [2021-01-26 23:11:34,048 WARN L146 IndependenceRelation]: Expensive independence query (2535 ms) for statements [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] and [1182] L854-1-->L855: Formula: (= |v_#memory_int_24| (store |v_#memory_int_25| |v_ULTIMATE.start_main_~#t2686~0.base_3| (store (select |v_#memory_int_25| |v_ULTIMATE.start_main_~#t2686~0.base_3|) |v_ULTIMATE.start_main_~#t2686~0.offset_3| 2))) InVars {#memory_int=|v_#memory_int_25|, ULTIMATE.start_main_~#t2686~0.offset=|v_ULTIMATE.start_main_~#t2686~0.offset_3|, ULTIMATE.start_main_~#t2686~0.base=|v_ULTIMATE.start_main_~#t2686~0.base_3|} OutVars{#memory_int=|v_#memory_int_24|, ULTIMATE.start_main_~#t2686~0.offset=|v_ULTIMATE.start_main_~#t2686~0.offset_3|, ULTIMATE.start_main_~#t2686~0.base=|v_ULTIMATE.start_main_~#t2686~0.base_3|} AuxVars[] AssignedVars[#memory_int] under condition 1675#(and (= ~z~0 0) (<= (div ~y$w_buff0_used~0 256) 0) (= ~__unbuffered_p0_EAX~0 0) (<= 1 ~y$w_buff0_used~0) (= ~y$r_buff0_thd2~0 1)) [2021-01-26 23:11:36,234 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:36,262 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:36,353 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:36,460 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:36,505 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:36,523 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check Size of Word is: 92 and size of Sequence is : 93[2021-01-26 23:11:36,670 INFO L164 SleepSetCegar]: Size of mCounterexample is: 93 [2021-01-26 23:11:36,671 INFO L165 SleepSetCegar]: [1495#[ULTIMATE.startENTRY]true, 1497#[L-1]true, 1499#[L-1-1]true, 1501#[L17]true, 1503#[L17-1]true, 1505#[L17-2]true, 1507#[L17-3]true, 1509#[L17-4]true, 1511#[L711]true, 1513#[L713](= ~__unbuffered_p0_EAX~0 0), 1515#[L715](= ~__unbuffered_p0_EAX~0 0), 1517#[L716](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1519#[L717](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1521#[L718](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1523#[L719](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1525#[L720](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1527#[L721](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1529#[L722](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1531#[L723](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1533#[L724](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1535#[L725](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1537#[L726](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1539#[L727](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1541#[L728](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1543#[L729](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1545#[L730](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1547#[L731](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1549#[L732](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1551#[L733](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1553#[L735](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1555#[L737](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1557#[L737-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1559#[L737-2](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1561#[L739](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1563#[L740](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1565#[L741](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1567#[L742](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1569#[L743](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1571#[L744](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1573#[L745](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1575#[L746](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1577#[L747](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1579#[L748](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1581#[L749](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1583#[L750](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1585#[L751](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1587#[L752](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1589#[L753](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1591#[L755](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1595#[L756](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1597#[L757](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1599#[L758](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1601#[L-1-2](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1603#[L-1-3](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1605#[L850](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1607#[L850-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1609#[L851](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1611#[P0ENTRY, L851-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1615#[P0ENTRY, L852](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1619#[P0ENTRY, L852-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1621#[L853, P0ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1627#[L853, L761](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 1629#[L761, P1ENTRY, L853-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82419#[L854, L761, P1ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82433#[L761, P1ENTRY, L854-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82447#[L761, P1ENTRY, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82463#[L776, L761, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82477#[L778, L761, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82498#[L761, L790, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (<= (div ~y$w_buff0_used~0 256) 0) (= ~__unbuffered_p0_EAX~0 0) (<= 1 ~y$w_buff0_used~0) (= ~y$r_buff0_thd2~0 1)), 82512#[L761, L855, L797](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82524#[L761, L800, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82538#[L761, L855, P1FINAL](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82554#[L761, L855, P1EXIT](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82561#[L761, P1EXIT, L855-1, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82573#[L856, L761, P1EXIT, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82589#[L761, P1EXIT, P2ENTRY, L858](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82603#[L761, P1EXIT, P2ENTRY, L859](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82615#[L761, L2, P1EXIT, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82631#[L761, P1EXIT, P2ENTRY, L3](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82652#[L761, L2-1, P1EXIT, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82817#[L761, L866, P1EXIT, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 82829#[L761, L866, P1EXIT, L805](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 84375#[L823, L761, L866, P1EXIT](and (= ~z~0 0) (= ~__unbuffered_p0_EAX~0 0)), 84384#[L761, L866, P1EXIT, L826](= ~__unbuffered_p0_EAX~0 0), 85449#[L866, P1EXIT, L763, L826]true, 85453#[P1EXIT, L763, L871, L826]true, 85459#[L872, P1EXIT, L763, L826]true, 85465#[L18, P1EXIT, L763, L826]true, 85473#[L18-1, P1EXIT, L763, L826]true, 85477#[L18-2, P1EXIT, L763, L826]true, 85492#[P1EXIT, L763, L17-5, L826]true, 85516#[L17-7, P1EXIT, L763, L826]true, 85544#[ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1EXIT, L763, L826]true] [2021-01-26 23:11:36,672 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2021-01-26 23:11:36,672 INFO L429 AbstractCegarLoop]: === Iteration 4 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 23:11:36,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 23:11:36,675 INFO L82 PathProgramCache]: Analyzing trace with hash 411953815, now seen corresponding path program 1 times [2021-01-26 23:11:36,676 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 23:11:36,676 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222535105] [2021-01-26 23:11:36,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 23:11:36,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 23:11:37,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 23:11:37,004 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1222535105] [2021-01-26 23:11:37,004 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 23:11:37,004 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2021-01-26 23:11:37,004 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1262129017] [2021-01-26 23:11:37,005 INFO L461 AbstractCegarLoop]: Interpolant automaton has 7 states [2021-01-26 23:11:37,005 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 23:11:37,005 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-01-26 23:11:37,006 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2021-01-26 23:11:37,006 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 23:11:37,006 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 7 states, 7 states have (on average 13.142857142857142) internal successors, (92), 7 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 23:11:37,671 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:39,121 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:40,276 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:41,051 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:41,989 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:42,089 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:42,118 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:42,641 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:42,690 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:42,944 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check Size of Word is: 91 and size of Sequence is : 92[2021-01-26 23:11:42,978 INFO L164 SleepSetCegar]: Size of mCounterexample is: 92 [2021-01-26 23:11:42,979 INFO L165 SleepSetCegar]: [85559#[ULTIMATE.startENTRY]true, 85561#[L-1]true, 85563#[L-1-1]true, 85565#[L17]true, 85567#[L17-1]true, 85569#[L17-2]true, 85571#[L17-3]true, 85573#[L17-4]true, 85575#[L711]true, 85577#[L713](= ~__unbuffered_p0_EAX~0 0), 85579#[L715](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85581#[L716](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85583#[L717](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85585#[L718](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85587#[L719](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85589#[L720](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85591#[L721](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85593#[L722](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85595#[L723](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85597#[L724](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85599#[L725](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85601#[L726](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85603#[L727](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85605#[L728](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85607#[L729](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85609#[L730](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85611#[L731](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85613#[L732](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85615#[L733](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85617#[L735](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85621#[L737](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85623#[L737-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85625#[L737-2](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85627#[L739](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85629#[L740](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85631#[L741](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85633#[L742](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85635#[L743](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85637#[L744](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85639#[L745](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85641#[L746](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85643#[L747](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85645#[L748](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85647#[L749](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85649#[L750](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85651#[L751](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85653#[L752](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85655#[L753](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85657#[L755](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85659#[L756](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85661#[L757](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85663#[L758](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85665#[L-1-2](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85667#[L-1-3](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85669#[L850](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85671#[L850-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85673#[L851](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85675#[P0ENTRY, L851-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85679#[P0ENTRY, L852](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85683#[P0ENTRY, L852-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85685#[L853, P0ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85691#[L853, L761](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 85693#[L761, P1ENTRY, L853-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 133969#[L854, L761, P1ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 133973#[L761, P1ENTRY, L854-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 133977#[L761, P1ENTRY, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 133983#[L776, L761, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 133985#[L776, L761, L855-1, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 183697#[L776, L856, L761, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 183717#[L776, L761, P2ENTRY, L858](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 183735#[L776, L761, P2ENTRY, L859](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 183751#[L776, L761, L2, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 183771#[L776, L761, P2ENTRY, L3](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 183798#[L776, L761, L2-1, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 184327#[L776, L761, L866, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 184343#[L776, L761, L866, L805](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 190745#[L776, L823, L761, L866](and (= ~x~0 0) (= ~z~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 190758#[L776, L761, L866, L826](and (= ~x~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196625#[L776, L866, L763, L826](and (= ~x~0 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196639#[L776, L866, L766, L826](and (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196649#[L776, L866, L771, L826](and (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196667#[L776, L866, P0FINAL, L826](and (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196681#[L776, L866, P0EXIT, L826](and (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196687#[L778, L866, P0EXIT, L826](= ~y$w_buff0_used~0 0), 196695#[L778, P0EXIT, L871, L826](= ~y$w_buff0_used~0 0), 196701#[L872, L778, P0EXIT, L826](= ~y$w_buff0_used~0 0), 196709#[L778, P0EXIT, L18, L826](= ~y$w_buff0_used~0 0), 196721#[L778, L18-1, P0EXIT, L826](= ~y$w_buff0_used~0 0), 196725#[L778, L18-2, P0EXIT, L826](= ~y$w_buff0_used~0 0), 196753#[L778, P0EXIT, L17-5, L826](= ~y$w_buff0_used~0 0), 196792#[L778, L17-7, P0EXIT, L826](= ~y$w_buff0_used~0 0), 196837#[L778, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0EXIT, L826](= ~y$w_buff0_used~0 0)] [2021-01-26 23:11:42,979 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2021-01-26 23:11:42,980 INFO L429 AbstractCegarLoop]: === Iteration 5 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 23:11:42,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 23:11:42,980 INFO L82 PathProgramCache]: Analyzing trace with hash 1678067908, now seen corresponding path program 1 times [2021-01-26 23:11:42,980 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 23:11:42,980 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [898265789] [2021-01-26 23:11:42,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 23:11:43,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 23:11:43,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 23:11:43,735 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [898265789] [2021-01-26 23:11:43,735 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 23:11:43,735 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2021-01-26 23:11:43,735 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627695384] [2021-01-26 23:11:43,736 INFO L461 AbstractCegarLoop]: Interpolant automaton has 18 states [2021-01-26 23:11:43,736 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 23:11:43,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-01-26 23:11:43,737 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=229, Unknown=0, NotChecked=0, Total=306 [2021-01-26 23:11:43,738 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 23:11:43,738 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 18 states, 18 states have (on average 5.055555555555555) internal successors, (91), 18 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 23:11:44,024 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:44,201 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:48,945 WARN L146 IndependenceRelation]: Expensive independence query (4092 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1246] L2-1-->L866: Formula: (let ((.cse15 (= (mod v_~y$w_buff0_used~0_417 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd0~0_72 256) 0)) (.cse12 (= (mod v_~y$w_buff0_used~0_416 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd0~0_58 256) 0)) (.cse16 (= (mod v_~y$w_buff1_used~0_322 256) 0))) (let ((.cse4 (not .cse16)) (.cse0 (or .cse13 .cse16)) (.cse5 (not .cse13)) (.cse2 (not .cse12)) (.cse1 (or .cse14 .cse12)) (.cse8 (select |v_#memory_int_247| |v_~#y~0.base_164|)) (.cse9 (not .cse15)) (.cse3 (not .cse14)) (.cse6 (or .cse14 .cse15))) (and (or (and (= v_~y$w_buff1_used~0_322 v_~y$w_buff1_used~0_321) .cse0 .cse1) (and (or (and .cse2 .cse3) (and .cse4 .cse5)) (= v_~y$w_buff1_used~0_321 0))) (let ((.cse7 (= |v_ULTIMATE.start_main_#t~mem71_25| |v_ULTIMATE.start_main_#t~mem71_29|))) (or (and .cse6 (or (and .cse4 .cse7 .cse5 (= v_~y$w_buff1~0_111 |v_ULTIMATE.start_main_#t~ite72_28|)) (and .cse0 (= |v_ULTIMATE.start_main_#t~mem71_29| (select .cse8 |v_~#y~0.offset_164|)) (= |v_ULTIMATE.start_main_#t~mem71_29| |v_ULTIMATE.start_main_#t~ite72_28|))) (= |v_ULTIMATE.start_main_#t~ite73_36| |v_ULTIMATE.start_main_#t~ite72_28|)) (and (= |v_ULTIMATE.start_main_#t~ite72_24| |v_ULTIMATE.start_main_#t~ite72_28|) (= |v_ULTIMATE.start_main_#t~ite73_36| v_~y$w_buff0~0_108) .cse7 .cse9 .cse3))) (let ((.cse10 (= (mod v_~y$r_buff0_thd0~0_71 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_321 256) 0))) (or (and (= v_~y$r_buff1_thd0~0_57 0) (or (and .cse2 (not .cse10)) (and (not .cse11) .cse5))) (and (or .cse10 .cse12) (or .cse13 .cse11) (= v_~y$r_buff1_thd0~0_58 v_~y$r_buff1_thd0~0_57)))) (or (and .cse2 (= v_~y$r_buff0_thd0~0_71 0) .cse3) (and .cse1 (= v_~y$r_buff0_thd0~0_72 v_~y$r_buff0_thd0~0_71))) (= (store |v_#memory_int_247| |v_~#y~0.base_164| (store .cse8 |v_~#y~0.offset_164| |v_ULTIMATE.start_main_#t~ite73_36|)) |v_#memory_int_246|) (or (and .cse9 (= v_~y$w_buff0_used~0_416 0) .cse3) (and (= v_~y$w_buff0_used~0_417 v_~y$w_buff0_used~0_416) .cse6))))) InVars {~#y~0.offset=|v_~#y~0.offset_164|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_24|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_417, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_72, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_247|, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_25|, ~#y~0.base=|v_~#y~0.base_164|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_58, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_322} OutVars{~#y~0.offset=|v_~#y~0.offset_164|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_416, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_23|, ~#y~0.base=|v_~#y~0.base_164|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_26|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_30|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_28|, ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_32|, ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_24|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_22|, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_71, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_246|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_57, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_321} AuxVars[|v_ULTIMATE.start_main_#t~ite73_36|, |v_ULTIMATE.start_main_#t~ite72_28|, |v_ULTIMATE.start_main_#t~mem71_29|] AssignedVars[ULTIMATE.start_main_#t~ite73, ULTIMATE.start_main_#t~ite74, ULTIMATE.start_main_#t~ite72, ~y$w_buff0_used~0, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem71, #memory_int, ULTIMATE.start_main_#t~ite77, ~y$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76, ~y$w_buff1_used~0] under condition 196848#(= (select |#valid| |~#y~0.base|) 1) [2021-01-26 23:11:49,093 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:53,810 WARN L146 IndependenceRelation]: Expensive independence query (4083 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition 196848#(= (select |#valid| |~#y~0.base|) 1) [2021-01-26 23:11:53,824 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:53,982 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:11:56,902 WARN L146 IndependenceRelation]: Expensive independence query (2616 ms) for statements [1265] L805-->L823: Formula: (let ((.cse15 (= (mod v_~y$r_buff1_thd3~0_294 256) 0)) (.cse48 (mod v_~y$w_buff0_used~0_481 256)) (.cse16 (= (mod v_~y$r_buff0_thd3~0_336 256) 0))) (let ((.cse26 (= (mod v_~weak$$choice2~0_94 256) 0)) (.cse31 (= (mod v_~y$w_buff1_used~0_393 256) 0)) (.cse12 (= (mod v_~weak$$choice0~0_145 256) 0)) (.cse2 (not .cse16)) (.cse46 (= (mod v_~y$w_buff1_used~0_394 256) 0)) (.cse21 (= .cse48 0)) (.cse19 (not .cse15)) (.cse27 (= (mod v_~y$w_buff0_used~0_480 256) 0)) (.cse41 (select |v_#memory_int_288| |v_~#y~0.base_184|))) (let ((.cse0 (select .cse41 |v_~#y~0.offset_184|)) (.cse32 (or .cse16 .cse27)) (.cse13 (= (mod v_~weak$$choice1~0_73 256) 0)) (.cse17 (or .cse2 .cse46 .cse21 .cse19)) (.cse18 (or .cse2 .cse46 .cse21 .cse15)) (.cse11 (not .cse46)) (.cse20 (or .cse21 .cse16)) (.cse9 (not .cse21)) (.cse14 (not .cse12)) (.cse29 (not .cse31)) (.cse28 (not .cse27)) (.cse23 (not .cse26))) (and (= v_~y$mem_tmp~0_32 .cse0) (let ((.cse1 (= |v_P2_#t~ite22_83| |v_P2Thread1of1ForFork0_#t~ite22_1|)) (.cse3 (= |v_P2_#t~ite18_85| |v_P2Thread1of1ForFork0_#t~ite18_1|)) (.cse4 (= |v_P2_#t~ite23_71| |v_P2Thread1of1ForFork0_#t~ite23_1|)) (.cse5 (= |v_P2_#t~ite24_59| |v_P2Thread1of1ForFork0_#t~ite24_1|)) (.cse6 (= |v_P2_#t~ite19_87| |v_P2Thread1of1ForFork0_#t~ite19_1|)) (.cse7 (= |v_P2_#t~ite20_77| |v_P2Thread1of1ForFork0_#t~ite20_1|)) (.cse8 (= |v_P2_#t~mem17_88| |v_P2Thread1of1ForFork0_#t~mem17_1|)) (.cse10 (= |v_P2_#t~mem21_92| |v_P2Thread1of1ForFork0_#t~mem21_1|))) (or (and (or (and .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 (= |v_P2_#t~ite25_63| v_~y$w_buff0~0_135) .cse7 .cse8 .cse9 .cse10) (and (or (and .cse1 .cse11 .cse4 (or (and .cse12 (= |v_P2_#t~ite19_87| |v_P2_#t~ite18_85|) (or (and .cse13 (= v_~y$w_buff1~0_134 |v_P2_#t~ite18_85|)) (and (= |v_P2_#t~ite18_85| v_~y$w_buff0~0_135) (not .cse13))) .cse8) (and .cse3 .cse14 (= |v_P2_#t~ite19_87| |v_P2_#t~mem17_88|) (= |v_P2_#t~mem17_88| .cse0))) .cse15 (= |v_P2_#t~ite19_87| |v_P2_#t~ite24_59|) .cse16 .cse7 .cse9 .cse10) (and .cse17 (= |v_P2_#t~ite24_59| |v_P2_#t~ite23_71|) .cse3 .cse6 (or (and .cse18 (= |v_P2_#t~ite22_83| |v_P2_#t~ite23_71|) (or (and (= |v_P2_#t~ite22_83| |v_P2_#t~mem21_92|) .cse12 (= |v_P2_#t~mem21_92| .cse0)) (and (= |v_P2_#t~ite22_83| v_~y$w_buff0~0_135) .cse14 .cse10)) .cse7) (and .cse1 .cse11 (or (and .cse12 (= |v_P2_#t~ite20_77| v_~y$w_buff0~0_135)) (and (= v_~y$w_buff1~0_134 |v_P2_#t~ite20_77|) .cse14)) (= |v_P2_#t~ite20_77| |v_P2_#t~ite23_71|) .cse16 .cse19 .cse9 .cse10)) .cse8)) .cse20 (= |v_P2_#t~ite24_59| |v_P2_#t~ite25_63|))) (= |v_P2_#t~ite25_63| v_~__unbuffered_p2_EAX~0_43) (= |v_P2Thread1of1ForFork0_#t~mem16_1| |v_P2_#t~mem16_52|) .cse9) (and .cse1 .cse3 .cse21 (= |v_P2_#t~ite25_63| |v_P2Thread1of1ForFork0_#t~ite25_1|) .cse4 (= |v_P2_#t~mem16_52| .cse0) .cse5 .cse6 (= |v_P2_#t~mem16_52| v_~__unbuffered_p2_EAX~0_43) .cse7 .cse8 .cse10))) (let ((.cse24 (= |v_P2_#t~ite49_61| |v_P2Thread1of1ForFork0_#t~ite49_1|)) (.cse22 (= |v_P2_#t~ite48_67| |v_P2Thread1of1ForFork0_#t~ite48_1|)) (.cse25 (= |v_P2_#t~ite47_69| |v_P2Thread1of1ForFork0_#t~ite47_1|))) (or (and .cse22 .cse23 (= v_~y$r_buff0_thd3~0_336 v_~y$r_buff0_thd3~0_335) .cse24 (= |v_P2_#t~ite50_47| |v_P2Thread1of1ForFork0_#t~ite50_1|) .cse25) (and .cse26 (= |v_P2_#t~ite50_47| v_~y$r_buff0_thd3~0_335) (or (and .cse22 (= |v_P2_#t~ite50_47| v_~y$r_buff0_thd3~0_336) .cse24 .cse25 .cse27) (and .cse28 (= |v_P2_#t~ite49_61| |v_P2_#t~ite50_47|) (or (and .cse2 .cse28 .cse22 (= |v_P2_#t~ite49_61| 0) .cse25) (and (or (and (let ((.cse30 (= |v_P2_#t~ite47_69| 0))) (or (and .cse29 .cse28 .cse16 .cse30 .cse19) (and .cse30 (or .cse2 .cse15 .cse31 .cse27)))) (or .cse2 .cse31 .cse27 .cse19) (= |v_P2_#t~ite48_67| |v_P2_#t~ite47_69|)) (and .cse29 .cse28 .cse15 (= |v_P2_#t~ite48_67| v_~y$r_buff0_thd3~0_336) .cse16 .cse25)) (= |v_P2_#t~ite48_67| |v_P2_#t~ite49_61|) .cse32))))))) (= |v_~#y~0.base_184| v_~__unbuffered_p2_EAX$read_delayed_var~0.base_32) (let ((.cse35 (= |v_P2_#t~ite34_57| |v_P2Thread1of1ForFork0_#t~ite34_1|)) (.cse33 (= |v_P2_#t~ite33_63| |v_P2Thread1of1ForFork0_#t~ite33_1|)) (.cse34 (= |v_P2_#t~ite32_75| |v_P2Thread1of1ForFork0_#t~ite32_1|))) (or (and .cse23 .cse33 .cse34 (= |v_P2_#t~ite35_53| |v_P2Thread1of1ForFork0_#t~ite35_1|) .cse35 (= v_~y$w_buff1~0_134 v_~y$w_buff1~0_133)) (and (or (and (= v_~y$w_buff1~0_134 |v_P2_#t~ite35_53|) .cse21 .cse33 .cse34 .cse35) (and (= |v_P2_#t~ite34_57| |v_P2_#t~ite35_53|) (or (and (= v_~y$w_buff1~0_134 |v_P2_#t~ite34_57|) .cse2 .cse33 .cse34 .cse9) (and (or (and .cse17 (= |v_P2_#t~ite32_75| |v_P2_#t~ite33_63|) (let ((.cse36 (= v_~y$w_buff1~0_134 |v_P2_#t~ite32_75|))) (or (and .cse18 .cse36) (and .cse11 .cse16 .cse36 .cse19 .cse9)))) (and .cse11 .cse15 .cse34 .cse16 (= v_~y$w_buff1~0_134 |v_P2_#t~ite33_63|) .cse9)) .cse20 (= |v_P2_#t~ite34_57| |v_P2_#t~ite33_63|))) .cse9)) (= v_~y$w_buff1~0_133 |v_P2_#t~ite35_53|) .cse26))) (let ((.cse37 (= |v_P2_#t~ite28_61| |v_P2Thread1of1ForFork0_#t~ite28_1|)) (.cse38 (= |v_P2_#t~ite27_73| |v_P2Thread1of1ForFork0_#t~ite27_1|)) (.cse39 (= |v_P2_#t~ite29_59| |v_P2Thread1of1ForFork0_#t~ite29_1|))) (or (and .cse37 (= v_~y$w_buff0~0_135 v_~y$w_buff0~0_134) .cse23 .cse38 (= |v_P2_#t~ite30_47| |v_P2Thread1of1ForFork0_#t~ite30_1|) .cse39) (and (or (and (or (and .cse37 .cse2 .cse38 (= |v_P2_#t~ite29_59| v_~y$w_buff0~0_135) .cse9) (and (= |v_P2_#t~ite29_59| |v_P2_#t~ite28_61|) .cse20 (or (and .cse17 (= |v_P2_#t~ite27_73| |v_P2_#t~ite28_61|) (let ((.cse40 (= |v_P2_#t~ite27_73| v_~y$w_buff0~0_135))) (or (and .cse11 .cse40 .cse16 .cse19 .cse9) (and .cse18 .cse40)))) (and .cse11 .cse38 .cse15 (= |v_P2_#t~ite28_61| v_~y$w_buff0~0_135) .cse16 .cse9)))) (= |v_P2_#t~ite29_59| |v_P2_#t~ite30_47|) .cse9) (and .cse37 (= |v_P2_#t~ite30_47| v_~y$w_buff0~0_135) .cse21 .cse38 .cse39)) .cse26 (= |v_P2_#t~ite30_47| v_~y$w_buff0~0_134)))) (= |v_~#y~0.offset_184| v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_32) (= (ite (= |v_P2_#t~ite41_55| 0) 0 1) v_~y$w_buff0_used~0_480) (= v_~__unbuffered_p2_EAX$read_delayed~0_31 1) (= 0 v_~y$flush_delayed~0_48) (= (store |v_#memory_int_288| |v_~#y~0.base_184| (store .cse41 |v_~#y~0.offset_184| |v_P2_#t~ite60_37|)) |v_#memory_int_286|) (= |v_P2Thread1of1ForFork0_#t~nondet13_1| v_~weak$$choice2~0_94) (let ((.cse42 (= |v_P2_#t~ite43_77| |v_P2Thread1of1ForFork0_#t~ite43_1|)) (.cse43 (= |v_P2_#t~ite44_73| |v_P2Thread1of1ForFork0_#t~ite44_1|)) (.cse44 (= |v_P2_#t~ite42_87| |v_P2Thread1of1ForFork0_#t~ite42_1|))) (or (and (or (and .cse42 (= |v_P2_#t~ite45_65| v_~y$w_buff1_used~0_394) .cse43 .cse27 .cse44) (and .cse28 (= |v_P2_#t~ite44_73| |v_P2_#t~ite45_65|) (or (and (or (and (= |v_P2_#t~ite42_87| |v_P2_#t~ite43_77|) (let ((.cse45 (= |v_P2_#t~ite42_87| 0))) (or (and .cse28 .cse11 .cse45 .cse16 .cse19) (and (or .cse2 .cse46 .cse15 .cse27) .cse45))) (or .cse2 .cse46 .cse27 .cse19)) (and (= |v_P2_#t~ite43_77| v_~weak$$choice0~0_145) .cse28 .cse11 .cse15 .cse16 .cse44)) .cse32 (= |v_P2_#t~ite44_73| |v_P2_#t~ite43_77|)) (and .cse42 .cse2 .cse28 (= |v_P2_#t~ite44_73| 0) .cse44)))) (= |v_P2_#t~ite45_65| v_~y$w_buff1_used~0_393) .cse26) (and .cse42 (= |v_P2_#t~ite45_65| |v_P2Thread1of1ForFork0_#t~ite45_1|) .cse23 .cse43 (= v_~y$w_buff1_used~0_394 v_~y$w_buff1_used~0_393) .cse44))) (= |v_P2Thread1of1ForFork0_#t~nondet15_1| v_~weak$$choice1~0_73) (let ((.cse47 (= |v_P2Thread1of1ForFork0_#t~ite39_1| |v_P2_#t~ite39_53|)) (.cse49 (= |v_P2Thread1of1ForFork0_#t~ite37_1| |v_P2_#t~ite37_67|)) (.cse50 (= |v_P2Thread1of1ForFork0_#t~ite38_1| |v_P2_#t~ite38_63|))) (or (and .cse47 .cse23 (= |v_P2_#t~ite41_55| .cse48) (= |v_P2Thread1of1ForFork0_#t~ite40_1| |v_P2_#t~ite40_39|) .cse49 .cse50) (and .cse26 (= |v_P2_#t~ite40_39| |v_P2_#t~ite41_55|) (or (and (= |v_P2_#t~ite39_53| |v_P2_#t~ite40_39|) (or (and .cse2 (= |v_P2_#t~ite39_53| 0) .cse49 .cse50 .cse9) (and (= |v_P2_#t~ite39_53| |v_P2_#t~ite38_63|) (or (and (= |v_P2_#t~ite38_63| (ite (or .cse13 .cse14) 1 0)) .cse11 .cse15 .cse16 .cse49 .cse9) (and .cse17 (let ((.cse51 (= |v_P2_#t~ite37_67| v_~weak$$choice0~0_145))) (or (and .cse18 .cse51) (and .cse11 .cse51 .cse16 .cse19 .cse9))) (= |v_P2_#t~ite38_63| (mod |v_P2_#t~ite37_67| 256)))) .cse20)) .cse9) (and .cse47 .cse21 .cse49 (= |v_P2_#t~ite40_39| .cse48) .cse50))))) (or (and .cse23 (= |v_P2Thread1of1ForFork0_#t~mem59_1| |v_P2_#t~mem59_36|) (= |v_P2_#t~ite60_37| v_~y$mem_tmp~0_32)) (and (= |v_P2_#t~ite60_37| |v_P2_#t~mem59_36|) (= |v_P2_#t~mem59_36| v_~__unbuffered_p2_EAX~0_43) .cse26)) (let ((.cse57 (= |v_P2_#t~ite54_55| |v_P2Thread1of1ForFork0_#t~ite54_1|)) (.cse52 (= |v_P2_#t~ite53_73| |v_P2Thread1of1ForFork0_#t~ite53_1|)) (.cse56 (= |v_P2_#t~ite52_67| |v_P2Thread1of1ForFork0_#t~ite52_1|)) (.cse58 (= |v_P2_#t~ite55_53| |v_P2Thread1of1ForFork0_#t~ite55_1|))) (or (and .cse26 (or (and .cse28 (= |v_P2_#t~ite55_53| |v_P2_#t~ite56_47|) (let ((.cse53 (= (mod v_~y$r_buff0_thd3~0_335 256) 0))) (let ((.cse55 (not .cse53))) (or (and (or (and (= |v_P2_#t~ite54_55| |v_P2_#t~ite52_67|) .cse29 .cse28 .cse52 .cse15 .cse53 (or (and .cse14 (= |v_P2_#t~ite52_67| v_~y$r_buff1_thd3~0_294)) (and .cse12 (= |v_P2_#t~ite52_67| 0)))) (and (let ((.cse54 (= |v_P2_#t~ite53_73| 0))) (or (and .cse29 .cse28 .cse54 .cse53 .cse19) (and (or .cse55 .cse15 .cse31 .cse27) .cse54))) .cse56 (= |v_P2_#t~ite54_55| |v_P2_#t~ite53_73|) (or .cse55 .cse31 .cse27 .cse19))) (or .cse53 .cse27) (= |v_P2_#t~ite54_55| |v_P2_#t~ite55_53|)) (and .cse28 .cse57 .cse55 .cse52 .cse56 (= |v_P2_#t~ite55_53| 0)))))) (and .cse57 (= |v_P2_#t~ite56_47| v_~y$r_buff1_thd3~0_294) .cse52 .cse56 .cse58 .cse27)) (= |v_P2_#t~ite56_47| v_~y$r_buff1_thd3~0_293)) (and (= v_~y$r_buff1_thd3~0_294 v_~y$r_buff1_thd3~0_293) .cse57 .cse23 .cse52 .cse56 (= |v_P2_#t~ite56_47| |v_P2Thread1of1ForFork0_#t~ite56_1|) .cse58))) (= |v_P2Thread1of1ForFork0_#t~nondet12_1| v_~weak$$choice0~0_145))))) InVars {P2Thread1of1ForFork0_#t~mem16=|v_P2Thread1of1ForFork0_#t~mem16_1|, P2Thread1of1ForFork0_#t~ite20=|v_P2Thread1of1ForFork0_#t~ite20_1|, P2Thread1of1ForFork0_#t~ite47=|v_P2Thread1of1ForFork0_#t~ite47_1|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_294, P2Thread1of1ForFork0_#t~ite49=|v_P2Thread1of1ForFork0_#t~ite49_1|, P2Thread1of1ForFork0_#t~ite28=|v_P2Thread1of1ForFork0_#t~ite28_1|, P2Thread1of1ForFork0_#t~ite22=|v_P2Thread1of1ForFork0_#t~ite22_1|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_1|, P2Thread1of1ForFork0_#t~ite45=|v_P2Thread1of1ForFork0_#t~ite45_1|, P2Thread1of1ForFork0_#t~ite24=|v_P2Thread1of1ForFork0_#t~ite24_1|, P2Thread1of1ForFork0_#t~nondet15=|v_P2Thread1of1ForFork0_#t~nondet15_1|, P2Thread1of1ForFork0_#t~ite53=|v_P2Thread1of1ForFork0_#t~ite53_1|, P2Thread1of1ForFork0_#t~nondet13=|v_P2Thread1of1ForFork0_#t~nondet13_1|, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_1|, P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_1|, ~y$w_buff1~0=v_~y$w_buff1~0_134, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_1|, P2Thread1of1ForFork0_#t~ite55=|v_P2Thread1of1ForFork0_#t~ite55_1|, P2Thread1of1ForFork0_#t~ite34=|v_P2Thread1of1ForFork0_#t~ite34_1|, P2Thread1of1ForFork0_#t~ite19=|v_P2Thread1of1ForFork0_#t~ite19_1|, P2Thread1of1ForFork0_#t~mem21=|v_P2Thread1of1ForFork0_#t~mem21_1|, ~#y~0.offset=|v_~#y~0.offset_184|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_481, P2Thread1of1ForFork0_#t~mem59=|v_P2Thread1of1ForFork0_#t~mem59_1|, P2Thread1of1ForFork0_#t~mem17=|v_P2Thread1of1ForFork0_#t~mem17_1|, P2Thread1of1ForFork0_#t~ite40=|v_P2Thread1of1ForFork0_#t~ite40_1|, P2Thread1of1ForFork0_#t~ite42=|v_P2Thread1of1ForFork0_#t~ite42_1|, ~#y~0.base=|v_~#y~0.base_184|, P2Thread1of1ForFork0_#t~ite25=|v_P2Thread1of1ForFork0_#t~ite25_1|, P2Thread1of1ForFork0_#t~ite48=|v_P2Thread1of1ForFork0_#t~ite48_1|, P2Thread1of1ForFork0_#t~ite27=|v_P2Thread1of1ForFork0_#t~ite27_1|, P2Thread1of1ForFork0_#t~ite44=|v_P2Thread1of1ForFork0_#t~ite44_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_336, ~y$w_buff0~0=v_~y$w_buff0~0_135, P2Thread1of1ForFork0_#t~ite23=|v_P2Thread1of1ForFork0_#t~ite23_1|, P2Thread1of1ForFork0_#t~ite29=|v_P2Thread1of1ForFork0_#t~ite29_1|, P2Thread1of1ForFork0_#t~ite52=|v_P2Thread1of1ForFork0_#t~ite52_1|, P2Thread1of1ForFork0_#t~ite50=|v_P2Thread1of1ForFork0_#t~ite50_1|, P2Thread1of1ForFork0_#t~nondet12=|v_P2Thread1of1ForFork0_#t~nondet12_1|, P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_1|, P2Thread1of1ForFork0_#t~ite39=|v_P2Thread1of1ForFork0_#t~ite39_1|, P2Thread1of1ForFork0_#t~ite56=|v_P2Thread1of1ForFork0_#t~ite56_1|, P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_1|, P2Thread1of1ForFork0_#t~ite54=|v_P2Thread1of1ForFork0_#t~ite54_1|, P2Thread1of1ForFork0_#t~ite35=|v_P2Thread1of1ForFork0_#t~ite35_1|, #memory_int=|v_#memory_int_288|, P2Thread1of1ForFork0_#t~ite18=|v_P2Thread1of1ForFork0_#t~ite18_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_394} OutVars{P2Thread1of1ForFork0_#t~mem16=|v_P2Thread1of1ForFork0_#t~mem16_2|, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_32, ~__unbuffered_p2_EAX$read_delayed_var~0.base=v_~__unbuffered_p2_EAX$read_delayed_var~0.base_32, P2Thread1of1ForFork0_#t~ite41=|v_P2Thread1of1ForFork0_#t~ite41_1|, P2Thread1of1ForFork0_#t~ite20=|v_P2Thread1of1ForFork0_#t~ite20_2|, P2Thread1of1ForFork0_#t~ite60=|v_P2Thread1of1ForFork0_#t~ite60_1|, P2Thread1of1ForFork0_#t~ite26=|v_P2Thread1of1ForFork0_#t~ite26_1|, P2Thread1of1ForFork0_#t~ite47=|v_P2Thread1of1ForFork0_#t~ite47_2|, ~y$mem_tmp~0=v_~y$mem_tmp~0_32, ~weak$$choice1~0=v_~weak$$choice1~0_73, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_293, P2Thread1of1ForFork0_#t~ite49=|v_P2Thread1of1ForFork0_#t~ite49_2|, P2Thread1of1ForFork0_#t~ite28=|v_P2Thread1of1ForFork0_#t~ite28_2|, P2Thread1of1ForFork0_#t~ite22=|v_P2Thread1of1ForFork0_#t~ite22_2|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_2|, P2Thread1of1ForFork0_#t~ite45=|v_P2Thread1of1ForFork0_#t~ite45_2|, P2Thread1of1ForFork0_#t~ite24=|v_P2Thread1of1ForFork0_#t~ite24_2|, ~y$flush_delayed~0=v_~y$flush_delayed~0_48, P2Thread1of1ForFork0_#t~mem58=|v_P2Thread1of1ForFork0_#t~mem58_1|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_43, P2Thread1of1ForFork0_#t~mem14=|v_P2Thread1of1ForFork0_#t~mem14_1|, P2Thread1of1ForFork0_#t~nondet15=|v_P2Thread1of1ForFork0_#t~nondet15_2|, P2Thread1of1ForFork0_#t~ite53=|v_P2Thread1of1ForFork0_#t~ite53_2|, P2Thread1of1ForFork0_#t~nondet13=|v_P2Thread1of1ForFork0_#t~nondet13_2|, P2Thread1of1ForFork0_#t~ite51=|v_P2Thread1of1ForFork0_#t~ite51_1|, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_2|, ~weak$$choice0~0=v_~weak$$choice0~0_145, P2Thread1of1ForFork0_#t~ite36=|v_P2Thread1of1ForFork0_#t~ite36_1|, P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_2|, ~y$w_buff1~0=v_~y$w_buff1~0_133, P2Thread1of1ForFork0_#t~ite57=|v_P2Thread1of1ForFork0_#t~ite57_1|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_2|, P2Thread1of1ForFork0_#t~ite55=|v_P2Thread1of1ForFork0_#t~ite55_2|, P2Thread1of1ForFork0_#t~ite34=|v_P2Thread1of1ForFork0_#t~ite34_2|, P2Thread1of1ForFork0_#t~ite19=|v_P2Thread1of1ForFork0_#t~ite19_2|, P2Thread1of1ForFork0_#t~mem21=|v_P2Thread1of1ForFork0_#t~mem21_2|, ~#y~0.offset=|v_~#y~0.offset_184|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_480, P2Thread1of1ForFork0_#t~mem59=|v_P2Thread1of1ForFork0_#t~mem59_2|, P2Thread1of1ForFork0_#t~mem17=|v_P2Thread1of1ForFork0_#t~mem17_2|, P2Thread1of1ForFork0_#t~ite40=|v_P2Thread1of1ForFork0_#t~ite40_2|, P2Thread1of1ForFork0_#t~ite42=|v_P2Thread1of1ForFork0_#t~ite42_2|, ~#y~0.base=|v_~#y~0.base_184|, P2Thread1of1ForFork0_#t~ite25=|v_P2Thread1of1ForFork0_#t~ite25_2|, P2Thread1of1ForFork0_#t~ite48=|v_P2Thread1of1ForFork0_#t~ite48_2|, P2Thread1of1ForFork0_#t~ite27=|v_P2Thread1of1ForFork0_#t~ite27_2|, P2Thread1of1ForFork0_#t~ite44=|v_P2Thread1of1ForFork0_#t~ite44_2|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_335, ~y$w_buff0~0=v_~y$w_buff0~0_134, P2Thread1of1ForFork0_#t~ite46=|v_P2Thread1of1ForFork0_#t~ite46_1|, P2Thread1of1ForFork0_#t~ite23=|v_P2Thread1of1ForFork0_#t~ite23_2|, P2Thread1of1ForFork0_#t~ite29=|v_P2Thread1of1ForFork0_#t~ite29_2|, P2Thread1of1ForFork0_#t~ite52=|v_P2Thread1of1ForFork0_#t~ite52_2|, P2Thread1of1ForFork0_#t~ite50=|v_P2Thread1of1ForFork0_#t~ite50_2|, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_1|, P2Thread1of1ForFork0_#t~nondet12=|v_P2Thread1of1ForFork0_#t~nondet12_2|, ~__unbuffered_p2_EAX$read_delayed~0=v_~__unbuffered_p2_EAX$read_delayed~0_31, P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_2|, P2Thread1of1ForFork0_#t~ite39=|v_P2Thread1of1ForFork0_#t~ite39_2|, P2Thread1of1ForFork0_#t~ite56=|v_P2Thread1of1ForFork0_#t~ite56_2|, P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_2|, P2Thread1of1ForFork0_#t~ite54=|v_P2Thread1of1ForFork0_#t~ite54_2|, P2Thread1of1ForFork0_#t~ite35=|v_P2Thread1of1ForFork0_#t~ite35_2|, #memory_int=|v_#memory_int_286|, P2Thread1of1ForFork0_#t~ite18=|v_P2Thread1of1ForFork0_#t~ite18_2|, ~weak$$choice2~0=v_~weak$$choice2~0_94, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_393} AuxVars[|v_P2_#t~ite48_67|, |v_P2_#t~ite25_63|, |v_P2_#t~mem16_52|, |v_P2_#t~ite43_77|, |v_P2_#t~ite42_87|, |v_P2_#t~mem17_88|, |v_P2_#t~ite52_67|, |v_P2_#t~ite56_47|, |v_P2_#t~ite54_55|, |v_P2_#t~ite19_87|, |v_P2_#t~mem21_92|, |v_P2_#t~ite35_53|, |v_P2_#t~ite40_39|, |v_P2_#t~mem59_36|, |v_P2_#t~ite38_63|, |v_P2_#t~ite39_53|, |v_P2_#t~ite45_65|, |v_P2_#t~ite22_83|, |v_P2_#t~ite27_73|, |v_P2_#t~ite47_69|, |v_P2_#t~ite28_61|, |v_P2_#t~ite44_73|, |v_P2_#t~ite30_47|, |v_P2_#t~ite60_37|, |v_P2_#t~ite29_59|, |v_P2_#t~ite49_61|, |v_P2_#t~ite23_71|, |v_P2_#t~ite18_85|, |v_P2_#t~ite33_63|, |v_P2_#t~ite53_73|, |v_P2_#t~ite37_67|, |v_P2_#t~ite55_53|, |v_P2_#t~ite34_57|, |v_P2_#t~ite32_75|, |v_P2_#t~ite50_47|, |v_P2_#t~ite24_59|, |v_P2_#t~ite20_77|, |v_P2_#t~ite41_55|] AssignedVars[P2Thread1of1ForFork0_#t~mem16, ~__unbuffered_p2_EAX$read_delayed_var~0.offset, ~__unbuffered_p2_EAX$read_delayed_var~0.base, P2Thread1of1ForFork0_#t~ite41, P2Thread1of1ForFork0_#t~ite20, P2Thread1of1ForFork0_#t~ite60, P2Thread1of1ForFork0_#t~ite26, P2Thread1of1ForFork0_#t~ite47, ~y$mem_tmp~0, ~weak$$choice1~0, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#t~ite49, P2Thread1of1ForFork0_#t~ite28, P2Thread1of1ForFork0_#t~ite22, P2Thread1of1ForFork0_#t~ite43, P2Thread1of1ForFork0_#t~ite45, P2Thread1of1ForFork0_#t~ite24, ~y$flush_delayed~0, P2Thread1of1ForFork0_#t~mem58, ~__unbuffered_p2_EAX~0, P2Thread1of1ForFork0_#t~mem14, P2Thread1of1ForFork0_#t~nondet15, P2Thread1of1ForFork0_#t~ite53, P2Thread1of1ForFork0_#t~nondet13, P2Thread1of1ForFork0_#t~ite51, P2Thread1of1ForFork0_#t~ite30, ~weak$$choice0~0, P2Thread1of1ForFork0_#t~ite36, P2Thread1of1ForFork0_#t~ite38, ~y$w_buff1~0, P2Thread1of1ForFork0_#t~ite57, P2Thread1of1ForFork0_#t~ite32, P2Thread1of1ForFork0_#t~ite55, P2Thread1of1ForFork0_#t~ite34, P2Thread1of1ForFork0_#t~ite19, P2Thread1of1ForFork0_#t~mem21, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~mem59, P2Thread1of1ForFork0_#t~mem17, P2Thread1of1ForFork0_#t~ite40, P2Thread1of1ForFork0_#t~ite42, P2Thread1of1ForFork0_#t~ite25, P2Thread1of1ForFork0_#t~ite48, P2Thread1of1ForFork0_#t~ite27, P2Thread1of1ForFork0_#t~ite44, ~y$r_buff0_thd3~0, ~y$w_buff0~0, P2Thread1of1ForFork0_#t~ite46, P2Thread1of1ForFork0_#t~ite23, P2Thread1of1ForFork0_#t~ite29, P2Thread1of1ForFork0_#t~ite52, P2Thread1of1ForFork0_#t~ite50, P2Thread1of1ForFork0_#t~ite31, P2Thread1of1ForFork0_#t~nondet12, ~__unbuffered_p2_EAX$read_delayed~0, P2Thread1of1ForFork0_#t~ite37, P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite56, P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite54, P2Thread1of1ForFork0_#t~ite35, #memory_int, P2Thread1of1ForFork0_#t~ite18, ~weak$$choice2~0, ~y$w_buff1_used~0] and [1246] L2-1-->L866: Formula: (let ((.cse15 (= (mod v_~y$w_buff0_used~0_417 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd0~0_72 256) 0)) (.cse12 (= (mod v_~y$w_buff0_used~0_416 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd0~0_58 256) 0)) (.cse16 (= (mod v_~y$w_buff1_used~0_322 256) 0))) (let ((.cse4 (not .cse16)) (.cse0 (or .cse13 .cse16)) (.cse5 (not .cse13)) (.cse2 (not .cse12)) (.cse1 (or .cse14 .cse12)) (.cse8 (select |v_#memory_int_247| |v_~#y~0.base_164|)) (.cse9 (not .cse15)) (.cse3 (not .cse14)) (.cse6 (or .cse14 .cse15))) (and (or (and (= v_~y$w_buff1_used~0_322 v_~y$w_buff1_used~0_321) .cse0 .cse1) (and (or (and .cse2 .cse3) (and .cse4 .cse5)) (= v_~y$w_buff1_used~0_321 0))) (let ((.cse7 (= |v_ULTIMATE.start_main_#t~mem71_25| |v_ULTIMATE.start_main_#t~mem71_29|))) (or (and .cse6 (or (and .cse4 .cse7 .cse5 (= v_~y$w_buff1~0_111 |v_ULTIMATE.start_main_#t~ite72_28|)) (and .cse0 (= |v_ULTIMATE.start_main_#t~mem71_29| (select .cse8 |v_~#y~0.offset_164|)) (= |v_ULTIMATE.start_main_#t~mem71_29| |v_ULTIMATE.start_main_#t~ite72_28|))) (= |v_ULTIMATE.start_main_#t~ite73_36| |v_ULTIMATE.start_main_#t~ite72_28|)) (and (= |v_ULTIMATE.start_main_#t~ite72_24| |v_ULTIMATE.start_main_#t~ite72_28|) (= |v_ULTIMATE.start_main_#t~ite73_36| v_~y$w_buff0~0_108) .cse7 .cse9 .cse3))) (let ((.cse10 (= (mod v_~y$r_buff0_thd0~0_71 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_321 256) 0))) (or (and (= v_~y$r_buff1_thd0~0_57 0) (or (and .cse2 (not .cse10)) (and (not .cse11) .cse5))) (and (or .cse10 .cse12) (or .cse13 .cse11) (= v_~y$r_buff1_thd0~0_58 v_~y$r_buff1_thd0~0_57)))) (or (and .cse2 (= v_~y$r_buff0_thd0~0_71 0) .cse3) (and .cse1 (= v_~y$r_buff0_thd0~0_72 v_~y$r_buff0_thd0~0_71))) (= (store |v_#memory_int_247| |v_~#y~0.base_164| (store .cse8 |v_~#y~0.offset_164| |v_ULTIMATE.start_main_#t~ite73_36|)) |v_#memory_int_246|) (or (and .cse9 (= v_~y$w_buff0_used~0_416 0) .cse3) (and (= v_~y$w_buff0_used~0_417 v_~y$w_buff0_used~0_416) .cse6))))) InVars {~#y~0.offset=|v_~#y~0.offset_164|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_24|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_417, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_72, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_247|, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_25|, ~#y~0.base=|v_~#y~0.base_164|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_58, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_322} OutVars{~#y~0.offset=|v_~#y~0.offset_164|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_416, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_23|, ~#y~0.base=|v_~#y~0.base_164|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_26|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_30|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_28|, ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_32|, ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_24|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_22|, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_71, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_246|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_57, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_321} AuxVars[|v_ULTIMATE.start_main_#t~ite73_36|, |v_ULTIMATE.start_main_#t~ite72_28|, |v_ULTIMATE.start_main_#t~mem71_29|] AssignedVars[ULTIMATE.start_main_#t~ite73, ULTIMATE.start_main_#t~ite74, ULTIMATE.start_main_#t~ite72, ~y$w_buff0_used~0, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem71, #memory_int, ULTIMATE.start_main_#t~ite77, ~y$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76, ~y$w_buff1_used~0] under condition 196851#(and (= ~y$r_buff1_thd0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$r_buff0_thd0~0 0)) [2021-01-26 23:12:00,983 WARN L146 IndependenceRelation]: Expensive independence query (4080 ms) for statements [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] and [1246] L2-1-->L866: Formula: (let ((.cse15 (= (mod v_~y$w_buff0_used~0_417 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd0~0_72 256) 0)) (.cse12 (= (mod v_~y$w_buff0_used~0_416 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd0~0_58 256) 0)) (.cse16 (= (mod v_~y$w_buff1_used~0_322 256) 0))) (let ((.cse4 (not .cse16)) (.cse0 (or .cse13 .cse16)) (.cse5 (not .cse13)) (.cse2 (not .cse12)) (.cse1 (or .cse14 .cse12)) (.cse8 (select |v_#memory_int_247| |v_~#y~0.base_164|)) (.cse9 (not .cse15)) (.cse3 (not .cse14)) (.cse6 (or .cse14 .cse15))) (and (or (and (= v_~y$w_buff1_used~0_322 v_~y$w_buff1_used~0_321) .cse0 .cse1) (and (or (and .cse2 .cse3) (and .cse4 .cse5)) (= v_~y$w_buff1_used~0_321 0))) (let ((.cse7 (= |v_ULTIMATE.start_main_#t~mem71_25| |v_ULTIMATE.start_main_#t~mem71_29|))) (or (and .cse6 (or (and .cse4 .cse7 .cse5 (= v_~y$w_buff1~0_111 |v_ULTIMATE.start_main_#t~ite72_28|)) (and .cse0 (= |v_ULTIMATE.start_main_#t~mem71_29| (select .cse8 |v_~#y~0.offset_164|)) (= |v_ULTIMATE.start_main_#t~mem71_29| |v_ULTIMATE.start_main_#t~ite72_28|))) (= |v_ULTIMATE.start_main_#t~ite73_36| |v_ULTIMATE.start_main_#t~ite72_28|)) (and (= |v_ULTIMATE.start_main_#t~ite72_24| |v_ULTIMATE.start_main_#t~ite72_28|) (= |v_ULTIMATE.start_main_#t~ite73_36| v_~y$w_buff0~0_108) .cse7 .cse9 .cse3))) (let ((.cse10 (= (mod v_~y$r_buff0_thd0~0_71 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_321 256) 0))) (or (and (= v_~y$r_buff1_thd0~0_57 0) (or (and .cse2 (not .cse10)) (and (not .cse11) .cse5))) (and (or .cse10 .cse12) (or .cse13 .cse11) (= v_~y$r_buff1_thd0~0_58 v_~y$r_buff1_thd0~0_57)))) (or (and .cse2 (= v_~y$r_buff0_thd0~0_71 0) .cse3) (and .cse1 (= v_~y$r_buff0_thd0~0_72 v_~y$r_buff0_thd0~0_71))) (= (store |v_#memory_int_247| |v_~#y~0.base_164| (store .cse8 |v_~#y~0.offset_164| |v_ULTIMATE.start_main_#t~ite73_36|)) |v_#memory_int_246|) (or (and .cse9 (= v_~y$w_buff0_used~0_416 0) .cse3) (and (= v_~y$w_buff0_used~0_417 v_~y$w_buff0_used~0_416) .cse6))))) InVars {~#y~0.offset=|v_~#y~0.offset_164|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_24|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_417, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_72, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_247|, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_25|, ~#y~0.base=|v_~#y~0.base_164|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_58, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_322} OutVars{~#y~0.offset=|v_~#y~0.offset_164|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_416, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_23|, ~#y~0.base=|v_~#y~0.base_164|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_26|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_30|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_28|, ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_32|, ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_24|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_22|, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_71, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_246|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_57, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_321} AuxVars[|v_ULTIMATE.start_main_#t~ite73_36|, |v_ULTIMATE.start_main_#t~ite72_28|, |v_ULTIMATE.start_main_#t~mem71_29|] AssignedVars[ULTIMATE.start_main_#t~ite73, ULTIMATE.start_main_#t~ite74, ULTIMATE.start_main_#t~ite72, ~y$w_buff0_used~0, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem71, #memory_int, ULTIMATE.start_main_#t~ite77, ~y$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76, ~y$w_buff1_used~0] under condition 196848#(= (select |#valid| |~#y~0.base|) 1) [2021-01-26 23:12:01,562 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:05,644 WARN L146 IndependenceRelation]: Expensive independence query (4081 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition 200017#(and (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff0_thd0~0 0)) [2021-01-26 23:12:05,661 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:05,749 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:06,270 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:06,308 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:06,660 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:06,702 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:07,084 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:07,119 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:07,253 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:07,693 WARN L193 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 51 [2021-01-26 23:12:08,207 WARN L193 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 56 [2021-01-26 23:12:08,515 WARN L193 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 53 [2021-01-26 23:12:08,536 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:08,686 WARN L193 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 50 [2021-01-26 23:12:08,704 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:08,821 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:08,931 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:13,013 WARN L146 IndependenceRelation]: Expensive independence query (4082 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition 201327#(and (<= 1 ~main$tmp_guard1~0) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (<= (div ~main$tmp_guard1~0 256) 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (or (<= (+ |ULTIMATE.start___VERIFIER_assert_#in~expression| 255) 0) (<= 1 |ULTIMATE.start___VERIFIER_assert_#in~expression|)) (or (<= 1 ULTIMATE.start___VERIFIER_assert_~expression) (<= (+ ULTIMATE.start___VERIFIER_assert_~expression 255) 0)) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff0_thd0~0 0)) [2021-01-26 23:12:13,024 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:13,116 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:13,294 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:13,390 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:13,557 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:17,637 WARN L146 IndependenceRelation]: Expensive independence query (4079 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition 201303#(and (<= 1 ~main$tmp_guard1~0) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (<= (div ~main$tmp_guard1~0 256) 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (or (<= (+ |ULTIMATE.start___VERIFIER_assert_#in~expression| 255) 0) (<= 1 |ULTIMATE.start___VERIFIER_assert_#in~expression|)) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff0_thd0~0 0)) [2021-01-26 23:12:17,643 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:17,777 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:21,866 WARN L146 IndependenceRelation]: Expensive independence query (4089 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition 201291#(and (<= 1 ~main$tmp_guard1~0) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (<= (div ~main$tmp_guard1~0 256) 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff0_thd0~0 0)) [2021-01-26 23:12:21,872 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:21,945 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:24,624 WARN L146 IndependenceRelation]: Expensive independence query (2413 ms) for statements [1265] L805-->L823: Formula: (let ((.cse15 (= (mod v_~y$r_buff1_thd3~0_294 256) 0)) (.cse48 (mod v_~y$w_buff0_used~0_481 256)) (.cse16 (= (mod v_~y$r_buff0_thd3~0_336 256) 0))) (let ((.cse26 (= (mod v_~weak$$choice2~0_94 256) 0)) (.cse31 (= (mod v_~y$w_buff1_used~0_393 256) 0)) (.cse12 (= (mod v_~weak$$choice0~0_145 256) 0)) (.cse2 (not .cse16)) (.cse46 (= (mod v_~y$w_buff1_used~0_394 256) 0)) (.cse21 (= .cse48 0)) (.cse19 (not .cse15)) (.cse27 (= (mod v_~y$w_buff0_used~0_480 256) 0)) (.cse41 (select |v_#memory_int_288| |v_~#y~0.base_184|))) (let ((.cse0 (select .cse41 |v_~#y~0.offset_184|)) (.cse32 (or .cse16 .cse27)) (.cse13 (= (mod v_~weak$$choice1~0_73 256) 0)) (.cse17 (or .cse2 .cse46 .cse21 .cse19)) (.cse18 (or .cse2 .cse46 .cse21 .cse15)) (.cse11 (not .cse46)) (.cse20 (or .cse21 .cse16)) (.cse9 (not .cse21)) (.cse14 (not .cse12)) (.cse29 (not .cse31)) (.cse28 (not .cse27)) (.cse23 (not .cse26))) (and (= v_~y$mem_tmp~0_32 .cse0) (let ((.cse1 (= |v_P2_#t~ite22_83| |v_P2Thread1of1ForFork0_#t~ite22_1|)) (.cse3 (= |v_P2_#t~ite18_85| |v_P2Thread1of1ForFork0_#t~ite18_1|)) (.cse4 (= |v_P2_#t~ite23_71| |v_P2Thread1of1ForFork0_#t~ite23_1|)) (.cse5 (= |v_P2_#t~ite24_59| |v_P2Thread1of1ForFork0_#t~ite24_1|)) (.cse6 (= |v_P2_#t~ite19_87| |v_P2Thread1of1ForFork0_#t~ite19_1|)) (.cse7 (= |v_P2_#t~ite20_77| |v_P2Thread1of1ForFork0_#t~ite20_1|)) (.cse8 (= |v_P2_#t~mem17_88| |v_P2Thread1of1ForFork0_#t~mem17_1|)) (.cse10 (= |v_P2_#t~mem21_92| |v_P2Thread1of1ForFork0_#t~mem21_1|))) (or (and (or (and .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 (= |v_P2_#t~ite25_63| v_~y$w_buff0~0_135) .cse7 .cse8 .cse9 .cse10) (and (or (and .cse1 .cse11 .cse4 (or (and .cse12 (= |v_P2_#t~ite19_87| |v_P2_#t~ite18_85|) (or (and .cse13 (= v_~y$w_buff1~0_134 |v_P2_#t~ite18_85|)) (and (= |v_P2_#t~ite18_85| v_~y$w_buff0~0_135) (not .cse13))) .cse8) (and .cse3 .cse14 (= |v_P2_#t~ite19_87| |v_P2_#t~mem17_88|) (= |v_P2_#t~mem17_88| .cse0))) .cse15 (= |v_P2_#t~ite19_87| |v_P2_#t~ite24_59|) .cse16 .cse7 .cse9 .cse10) (and .cse17 (= |v_P2_#t~ite24_59| |v_P2_#t~ite23_71|) .cse3 .cse6 (or (and .cse18 (= |v_P2_#t~ite22_83| |v_P2_#t~ite23_71|) (or (and (= |v_P2_#t~ite22_83| |v_P2_#t~mem21_92|) .cse12 (= |v_P2_#t~mem21_92| .cse0)) (and (= |v_P2_#t~ite22_83| v_~y$w_buff0~0_135) .cse14 .cse10)) .cse7) (and .cse1 .cse11 (or (and .cse12 (= |v_P2_#t~ite20_77| v_~y$w_buff0~0_135)) (and (= v_~y$w_buff1~0_134 |v_P2_#t~ite20_77|) .cse14)) (= |v_P2_#t~ite20_77| |v_P2_#t~ite23_71|) .cse16 .cse19 .cse9 .cse10)) .cse8)) .cse20 (= |v_P2_#t~ite24_59| |v_P2_#t~ite25_63|))) (= |v_P2_#t~ite25_63| v_~__unbuffered_p2_EAX~0_43) (= |v_P2Thread1of1ForFork0_#t~mem16_1| |v_P2_#t~mem16_52|) .cse9) (and .cse1 .cse3 .cse21 (= |v_P2_#t~ite25_63| |v_P2Thread1of1ForFork0_#t~ite25_1|) .cse4 (= |v_P2_#t~mem16_52| .cse0) .cse5 .cse6 (= |v_P2_#t~mem16_52| v_~__unbuffered_p2_EAX~0_43) .cse7 .cse8 .cse10))) (let ((.cse24 (= |v_P2_#t~ite49_61| |v_P2Thread1of1ForFork0_#t~ite49_1|)) (.cse22 (= |v_P2_#t~ite48_67| |v_P2Thread1of1ForFork0_#t~ite48_1|)) (.cse25 (= |v_P2_#t~ite47_69| |v_P2Thread1of1ForFork0_#t~ite47_1|))) (or (and .cse22 .cse23 (= v_~y$r_buff0_thd3~0_336 v_~y$r_buff0_thd3~0_335) .cse24 (= |v_P2_#t~ite50_47| |v_P2Thread1of1ForFork0_#t~ite50_1|) .cse25) (and .cse26 (= |v_P2_#t~ite50_47| v_~y$r_buff0_thd3~0_335) (or (and .cse22 (= |v_P2_#t~ite50_47| v_~y$r_buff0_thd3~0_336) .cse24 .cse25 .cse27) (and .cse28 (= |v_P2_#t~ite49_61| |v_P2_#t~ite50_47|) (or (and .cse2 .cse28 .cse22 (= |v_P2_#t~ite49_61| 0) .cse25) (and (or (and (let ((.cse30 (= |v_P2_#t~ite47_69| 0))) (or (and .cse29 .cse28 .cse16 .cse30 .cse19) (and .cse30 (or .cse2 .cse15 .cse31 .cse27)))) (or .cse2 .cse31 .cse27 .cse19) (= |v_P2_#t~ite48_67| |v_P2_#t~ite47_69|)) (and .cse29 .cse28 .cse15 (= |v_P2_#t~ite48_67| v_~y$r_buff0_thd3~0_336) .cse16 .cse25)) (= |v_P2_#t~ite48_67| |v_P2_#t~ite49_61|) .cse32))))))) (= |v_~#y~0.base_184| v_~__unbuffered_p2_EAX$read_delayed_var~0.base_32) (let ((.cse35 (= |v_P2_#t~ite34_57| |v_P2Thread1of1ForFork0_#t~ite34_1|)) (.cse33 (= |v_P2_#t~ite33_63| |v_P2Thread1of1ForFork0_#t~ite33_1|)) (.cse34 (= |v_P2_#t~ite32_75| |v_P2Thread1of1ForFork0_#t~ite32_1|))) (or (and .cse23 .cse33 .cse34 (= |v_P2_#t~ite35_53| |v_P2Thread1of1ForFork0_#t~ite35_1|) .cse35 (= v_~y$w_buff1~0_134 v_~y$w_buff1~0_133)) (and (or (and (= v_~y$w_buff1~0_134 |v_P2_#t~ite35_53|) .cse21 .cse33 .cse34 .cse35) (and (= |v_P2_#t~ite34_57| |v_P2_#t~ite35_53|) (or (and (= v_~y$w_buff1~0_134 |v_P2_#t~ite34_57|) .cse2 .cse33 .cse34 .cse9) (and (or (and .cse17 (= |v_P2_#t~ite32_75| |v_P2_#t~ite33_63|) (let ((.cse36 (= v_~y$w_buff1~0_134 |v_P2_#t~ite32_75|))) (or (and .cse18 .cse36) (and .cse11 .cse16 .cse36 .cse19 .cse9)))) (and .cse11 .cse15 .cse34 .cse16 (= v_~y$w_buff1~0_134 |v_P2_#t~ite33_63|) .cse9)) .cse20 (= |v_P2_#t~ite34_57| |v_P2_#t~ite33_63|))) .cse9)) (= v_~y$w_buff1~0_133 |v_P2_#t~ite35_53|) .cse26))) (let ((.cse37 (= |v_P2_#t~ite28_61| |v_P2Thread1of1ForFork0_#t~ite28_1|)) (.cse38 (= |v_P2_#t~ite27_73| |v_P2Thread1of1ForFork0_#t~ite27_1|)) (.cse39 (= |v_P2_#t~ite29_59| |v_P2Thread1of1ForFork0_#t~ite29_1|))) (or (and .cse37 (= v_~y$w_buff0~0_135 v_~y$w_buff0~0_134) .cse23 .cse38 (= |v_P2_#t~ite30_47| |v_P2Thread1of1ForFork0_#t~ite30_1|) .cse39) (and (or (and (or (and .cse37 .cse2 .cse38 (= |v_P2_#t~ite29_59| v_~y$w_buff0~0_135) .cse9) (and (= |v_P2_#t~ite29_59| |v_P2_#t~ite28_61|) .cse20 (or (and .cse17 (= |v_P2_#t~ite27_73| |v_P2_#t~ite28_61|) (let ((.cse40 (= |v_P2_#t~ite27_73| v_~y$w_buff0~0_135))) (or (and .cse11 .cse40 .cse16 .cse19 .cse9) (and .cse18 .cse40)))) (and .cse11 .cse38 .cse15 (= |v_P2_#t~ite28_61| v_~y$w_buff0~0_135) .cse16 .cse9)))) (= |v_P2_#t~ite29_59| |v_P2_#t~ite30_47|) .cse9) (and .cse37 (= |v_P2_#t~ite30_47| v_~y$w_buff0~0_135) .cse21 .cse38 .cse39)) .cse26 (= |v_P2_#t~ite30_47| v_~y$w_buff0~0_134)))) (= |v_~#y~0.offset_184| v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_32) (= (ite (= |v_P2_#t~ite41_55| 0) 0 1) v_~y$w_buff0_used~0_480) (= v_~__unbuffered_p2_EAX$read_delayed~0_31 1) (= 0 v_~y$flush_delayed~0_48) (= (store |v_#memory_int_288| |v_~#y~0.base_184| (store .cse41 |v_~#y~0.offset_184| |v_P2_#t~ite60_37|)) |v_#memory_int_286|) (= |v_P2Thread1of1ForFork0_#t~nondet13_1| v_~weak$$choice2~0_94) (let ((.cse42 (= |v_P2_#t~ite43_77| |v_P2Thread1of1ForFork0_#t~ite43_1|)) (.cse43 (= |v_P2_#t~ite44_73| |v_P2Thread1of1ForFork0_#t~ite44_1|)) (.cse44 (= |v_P2_#t~ite42_87| |v_P2Thread1of1ForFork0_#t~ite42_1|))) (or (and (or (and .cse42 (= |v_P2_#t~ite45_65| v_~y$w_buff1_used~0_394) .cse43 .cse27 .cse44) (and .cse28 (= |v_P2_#t~ite44_73| |v_P2_#t~ite45_65|) (or (and (or (and (= |v_P2_#t~ite42_87| |v_P2_#t~ite43_77|) (let ((.cse45 (= |v_P2_#t~ite42_87| 0))) (or (and .cse28 .cse11 .cse45 .cse16 .cse19) (and (or .cse2 .cse46 .cse15 .cse27) .cse45))) (or .cse2 .cse46 .cse27 .cse19)) (and (= |v_P2_#t~ite43_77| v_~weak$$choice0~0_145) .cse28 .cse11 .cse15 .cse16 .cse44)) .cse32 (= |v_P2_#t~ite44_73| |v_P2_#t~ite43_77|)) (and .cse42 .cse2 .cse28 (= |v_P2_#t~ite44_73| 0) .cse44)))) (= |v_P2_#t~ite45_65| v_~y$w_buff1_used~0_393) .cse26) (and .cse42 (= |v_P2_#t~ite45_65| |v_P2Thread1of1ForFork0_#t~ite45_1|) .cse23 .cse43 (= v_~y$w_buff1_used~0_394 v_~y$w_buff1_used~0_393) .cse44))) (= |v_P2Thread1of1ForFork0_#t~nondet15_1| v_~weak$$choice1~0_73) (let ((.cse47 (= |v_P2Thread1of1ForFork0_#t~ite39_1| |v_P2_#t~ite39_53|)) (.cse49 (= |v_P2Thread1of1ForFork0_#t~ite37_1| |v_P2_#t~ite37_67|)) (.cse50 (= |v_P2Thread1of1ForFork0_#t~ite38_1| |v_P2_#t~ite38_63|))) (or (and .cse47 .cse23 (= |v_P2_#t~ite41_55| .cse48) (= |v_P2Thread1of1ForFork0_#t~ite40_1| |v_P2_#t~ite40_39|) .cse49 .cse50) (and .cse26 (= |v_P2_#t~ite40_39| |v_P2_#t~ite41_55|) (or (and (= |v_P2_#t~ite39_53| |v_P2_#t~ite40_39|) (or (and .cse2 (= |v_P2_#t~ite39_53| 0) .cse49 .cse50 .cse9) (and (= |v_P2_#t~ite39_53| |v_P2_#t~ite38_63|) (or (and (= |v_P2_#t~ite38_63| (ite (or .cse13 .cse14) 1 0)) .cse11 .cse15 .cse16 .cse49 .cse9) (and .cse17 (let ((.cse51 (= |v_P2_#t~ite37_67| v_~weak$$choice0~0_145))) (or (and .cse18 .cse51) (and .cse11 .cse51 .cse16 .cse19 .cse9))) (= |v_P2_#t~ite38_63| (mod |v_P2_#t~ite37_67| 256)))) .cse20)) .cse9) (and .cse47 .cse21 .cse49 (= |v_P2_#t~ite40_39| .cse48) .cse50))))) (or (and .cse23 (= |v_P2Thread1of1ForFork0_#t~mem59_1| |v_P2_#t~mem59_36|) (= |v_P2_#t~ite60_37| v_~y$mem_tmp~0_32)) (and (= |v_P2_#t~ite60_37| |v_P2_#t~mem59_36|) (= |v_P2_#t~mem59_36| v_~__unbuffered_p2_EAX~0_43) .cse26)) (let ((.cse57 (= |v_P2_#t~ite54_55| |v_P2Thread1of1ForFork0_#t~ite54_1|)) (.cse52 (= |v_P2_#t~ite53_73| |v_P2Thread1of1ForFork0_#t~ite53_1|)) (.cse56 (= |v_P2_#t~ite52_67| |v_P2Thread1of1ForFork0_#t~ite52_1|)) (.cse58 (= |v_P2_#t~ite55_53| |v_P2Thread1of1ForFork0_#t~ite55_1|))) (or (and .cse26 (or (and .cse28 (= |v_P2_#t~ite55_53| |v_P2_#t~ite56_47|) (let ((.cse53 (= (mod v_~y$r_buff0_thd3~0_335 256) 0))) (let ((.cse55 (not .cse53))) (or (and (or (and (= |v_P2_#t~ite54_55| |v_P2_#t~ite52_67|) .cse29 .cse28 .cse52 .cse15 .cse53 (or (and .cse14 (= |v_P2_#t~ite52_67| v_~y$r_buff1_thd3~0_294)) (and .cse12 (= |v_P2_#t~ite52_67| 0)))) (and (let ((.cse54 (= |v_P2_#t~ite53_73| 0))) (or (and .cse29 .cse28 .cse54 .cse53 .cse19) (and (or .cse55 .cse15 .cse31 .cse27) .cse54))) .cse56 (= |v_P2_#t~ite54_55| |v_P2_#t~ite53_73|) (or .cse55 .cse31 .cse27 .cse19))) (or .cse53 .cse27) (= |v_P2_#t~ite54_55| |v_P2_#t~ite55_53|)) (and .cse28 .cse57 .cse55 .cse52 .cse56 (= |v_P2_#t~ite55_53| 0)))))) (and .cse57 (= |v_P2_#t~ite56_47| v_~y$r_buff1_thd3~0_294) .cse52 .cse56 .cse58 .cse27)) (= |v_P2_#t~ite56_47| v_~y$r_buff1_thd3~0_293)) (and (= v_~y$r_buff1_thd3~0_294 v_~y$r_buff1_thd3~0_293) .cse57 .cse23 .cse52 .cse56 (= |v_P2_#t~ite56_47| |v_P2Thread1of1ForFork0_#t~ite56_1|) .cse58))) (= |v_P2Thread1of1ForFork0_#t~nondet12_1| v_~weak$$choice0~0_145))))) InVars {P2Thread1of1ForFork0_#t~mem16=|v_P2Thread1of1ForFork0_#t~mem16_1|, P2Thread1of1ForFork0_#t~ite20=|v_P2Thread1of1ForFork0_#t~ite20_1|, P2Thread1of1ForFork0_#t~ite47=|v_P2Thread1of1ForFork0_#t~ite47_1|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_294, P2Thread1of1ForFork0_#t~ite49=|v_P2Thread1of1ForFork0_#t~ite49_1|, P2Thread1of1ForFork0_#t~ite28=|v_P2Thread1of1ForFork0_#t~ite28_1|, P2Thread1of1ForFork0_#t~ite22=|v_P2Thread1of1ForFork0_#t~ite22_1|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_1|, P2Thread1of1ForFork0_#t~ite45=|v_P2Thread1of1ForFork0_#t~ite45_1|, P2Thread1of1ForFork0_#t~ite24=|v_P2Thread1of1ForFork0_#t~ite24_1|, P2Thread1of1ForFork0_#t~nondet15=|v_P2Thread1of1ForFork0_#t~nondet15_1|, P2Thread1of1ForFork0_#t~ite53=|v_P2Thread1of1ForFork0_#t~ite53_1|, P2Thread1of1ForFork0_#t~nondet13=|v_P2Thread1of1ForFork0_#t~nondet13_1|, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_1|, P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_1|, ~y$w_buff1~0=v_~y$w_buff1~0_134, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_1|, P2Thread1of1ForFork0_#t~ite55=|v_P2Thread1of1ForFork0_#t~ite55_1|, P2Thread1of1ForFork0_#t~ite34=|v_P2Thread1of1ForFork0_#t~ite34_1|, P2Thread1of1ForFork0_#t~ite19=|v_P2Thread1of1ForFork0_#t~ite19_1|, P2Thread1of1ForFork0_#t~mem21=|v_P2Thread1of1ForFork0_#t~mem21_1|, ~#y~0.offset=|v_~#y~0.offset_184|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_481, P2Thread1of1ForFork0_#t~mem59=|v_P2Thread1of1ForFork0_#t~mem59_1|, P2Thread1of1ForFork0_#t~mem17=|v_P2Thread1of1ForFork0_#t~mem17_1|, P2Thread1of1ForFork0_#t~ite40=|v_P2Thread1of1ForFork0_#t~ite40_1|, P2Thread1of1ForFork0_#t~ite42=|v_P2Thread1of1ForFork0_#t~ite42_1|, ~#y~0.base=|v_~#y~0.base_184|, P2Thread1of1ForFork0_#t~ite25=|v_P2Thread1of1ForFork0_#t~ite25_1|, P2Thread1of1ForFork0_#t~ite48=|v_P2Thread1of1ForFork0_#t~ite48_1|, P2Thread1of1ForFork0_#t~ite27=|v_P2Thread1of1ForFork0_#t~ite27_1|, P2Thread1of1ForFork0_#t~ite44=|v_P2Thread1of1ForFork0_#t~ite44_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_336, ~y$w_buff0~0=v_~y$w_buff0~0_135, P2Thread1of1ForFork0_#t~ite23=|v_P2Thread1of1ForFork0_#t~ite23_1|, P2Thread1of1ForFork0_#t~ite29=|v_P2Thread1of1ForFork0_#t~ite29_1|, P2Thread1of1ForFork0_#t~ite52=|v_P2Thread1of1ForFork0_#t~ite52_1|, P2Thread1of1ForFork0_#t~ite50=|v_P2Thread1of1ForFork0_#t~ite50_1|, P2Thread1of1ForFork0_#t~nondet12=|v_P2Thread1of1ForFork0_#t~nondet12_1|, P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_1|, P2Thread1of1ForFork0_#t~ite39=|v_P2Thread1of1ForFork0_#t~ite39_1|, P2Thread1of1ForFork0_#t~ite56=|v_P2Thread1of1ForFork0_#t~ite56_1|, P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_1|, P2Thread1of1ForFork0_#t~ite54=|v_P2Thread1of1ForFork0_#t~ite54_1|, P2Thread1of1ForFork0_#t~ite35=|v_P2Thread1of1ForFork0_#t~ite35_1|, #memory_int=|v_#memory_int_288|, P2Thread1of1ForFork0_#t~ite18=|v_P2Thread1of1ForFork0_#t~ite18_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_394} OutVars{P2Thread1of1ForFork0_#t~mem16=|v_P2Thread1of1ForFork0_#t~mem16_2|, ~__unbuffered_p2_EAX$read_delayed_var~0.offset=v_~__unbuffered_p2_EAX$read_delayed_var~0.offset_32, ~__unbuffered_p2_EAX$read_delayed_var~0.base=v_~__unbuffered_p2_EAX$read_delayed_var~0.base_32, P2Thread1of1ForFork0_#t~ite41=|v_P2Thread1of1ForFork0_#t~ite41_1|, P2Thread1of1ForFork0_#t~ite20=|v_P2Thread1of1ForFork0_#t~ite20_2|, P2Thread1of1ForFork0_#t~ite60=|v_P2Thread1of1ForFork0_#t~ite60_1|, P2Thread1of1ForFork0_#t~ite26=|v_P2Thread1of1ForFork0_#t~ite26_1|, P2Thread1of1ForFork0_#t~ite47=|v_P2Thread1of1ForFork0_#t~ite47_2|, ~y$mem_tmp~0=v_~y$mem_tmp~0_32, ~weak$$choice1~0=v_~weak$$choice1~0_73, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_293, P2Thread1of1ForFork0_#t~ite49=|v_P2Thread1of1ForFork0_#t~ite49_2|, P2Thread1of1ForFork0_#t~ite28=|v_P2Thread1of1ForFork0_#t~ite28_2|, P2Thread1of1ForFork0_#t~ite22=|v_P2Thread1of1ForFork0_#t~ite22_2|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_2|, P2Thread1of1ForFork0_#t~ite45=|v_P2Thread1of1ForFork0_#t~ite45_2|, P2Thread1of1ForFork0_#t~ite24=|v_P2Thread1of1ForFork0_#t~ite24_2|, ~y$flush_delayed~0=v_~y$flush_delayed~0_48, P2Thread1of1ForFork0_#t~mem58=|v_P2Thread1of1ForFork0_#t~mem58_1|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_43, P2Thread1of1ForFork0_#t~mem14=|v_P2Thread1of1ForFork0_#t~mem14_1|, P2Thread1of1ForFork0_#t~nondet15=|v_P2Thread1of1ForFork0_#t~nondet15_2|, P2Thread1of1ForFork0_#t~ite53=|v_P2Thread1of1ForFork0_#t~ite53_2|, P2Thread1of1ForFork0_#t~nondet13=|v_P2Thread1of1ForFork0_#t~nondet13_2|, P2Thread1of1ForFork0_#t~ite51=|v_P2Thread1of1ForFork0_#t~ite51_1|, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_2|, ~weak$$choice0~0=v_~weak$$choice0~0_145, P2Thread1of1ForFork0_#t~ite36=|v_P2Thread1of1ForFork0_#t~ite36_1|, P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_2|, ~y$w_buff1~0=v_~y$w_buff1~0_133, P2Thread1of1ForFork0_#t~ite57=|v_P2Thread1of1ForFork0_#t~ite57_1|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_2|, P2Thread1of1ForFork0_#t~ite55=|v_P2Thread1of1ForFork0_#t~ite55_2|, P2Thread1of1ForFork0_#t~ite34=|v_P2Thread1of1ForFork0_#t~ite34_2|, P2Thread1of1ForFork0_#t~ite19=|v_P2Thread1of1ForFork0_#t~ite19_2|, P2Thread1of1ForFork0_#t~mem21=|v_P2Thread1of1ForFork0_#t~mem21_2|, ~#y~0.offset=|v_~#y~0.offset_184|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_480, P2Thread1of1ForFork0_#t~mem59=|v_P2Thread1of1ForFork0_#t~mem59_2|, P2Thread1of1ForFork0_#t~mem17=|v_P2Thread1of1ForFork0_#t~mem17_2|, P2Thread1of1ForFork0_#t~ite40=|v_P2Thread1of1ForFork0_#t~ite40_2|, P2Thread1of1ForFork0_#t~ite42=|v_P2Thread1of1ForFork0_#t~ite42_2|, ~#y~0.base=|v_~#y~0.base_184|, P2Thread1of1ForFork0_#t~ite25=|v_P2Thread1of1ForFork0_#t~ite25_2|, P2Thread1of1ForFork0_#t~ite48=|v_P2Thread1of1ForFork0_#t~ite48_2|, P2Thread1of1ForFork0_#t~ite27=|v_P2Thread1of1ForFork0_#t~ite27_2|, P2Thread1of1ForFork0_#t~ite44=|v_P2Thread1of1ForFork0_#t~ite44_2|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_335, ~y$w_buff0~0=v_~y$w_buff0~0_134, P2Thread1of1ForFork0_#t~ite46=|v_P2Thread1of1ForFork0_#t~ite46_1|, P2Thread1of1ForFork0_#t~ite23=|v_P2Thread1of1ForFork0_#t~ite23_2|, P2Thread1of1ForFork0_#t~ite29=|v_P2Thread1of1ForFork0_#t~ite29_2|, P2Thread1of1ForFork0_#t~ite52=|v_P2Thread1of1ForFork0_#t~ite52_2|, P2Thread1of1ForFork0_#t~ite50=|v_P2Thread1of1ForFork0_#t~ite50_2|, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_1|, P2Thread1of1ForFork0_#t~nondet12=|v_P2Thread1of1ForFork0_#t~nondet12_2|, ~__unbuffered_p2_EAX$read_delayed~0=v_~__unbuffered_p2_EAX$read_delayed~0_31, P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_2|, P2Thread1of1ForFork0_#t~ite39=|v_P2Thread1of1ForFork0_#t~ite39_2|, P2Thread1of1ForFork0_#t~ite56=|v_P2Thread1of1ForFork0_#t~ite56_2|, P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_2|, P2Thread1of1ForFork0_#t~ite54=|v_P2Thread1of1ForFork0_#t~ite54_2|, P2Thread1of1ForFork0_#t~ite35=|v_P2Thread1of1ForFork0_#t~ite35_2|, #memory_int=|v_#memory_int_286|, P2Thread1of1ForFork0_#t~ite18=|v_P2Thread1of1ForFork0_#t~ite18_2|, ~weak$$choice2~0=v_~weak$$choice2~0_94, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_393} AuxVars[|v_P2_#t~ite48_67|, |v_P2_#t~ite25_63|, |v_P2_#t~mem16_52|, |v_P2_#t~ite43_77|, |v_P2_#t~ite42_87|, |v_P2_#t~mem17_88|, |v_P2_#t~ite52_67|, |v_P2_#t~ite56_47|, |v_P2_#t~ite54_55|, |v_P2_#t~ite19_87|, |v_P2_#t~mem21_92|, |v_P2_#t~ite35_53|, |v_P2_#t~ite40_39|, |v_P2_#t~mem59_36|, |v_P2_#t~ite38_63|, |v_P2_#t~ite39_53|, |v_P2_#t~ite45_65|, |v_P2_#t~ite22_83|, |v_P2_#t~ite27_73|, |v_P2_#t~ite47_69|, |v_P2_#t~ite28_61|, |v_P2_#t~ite44_73|, |v_P2_#t~ite30_47|, |v_P2_#t~ite60_37|, |v_P2_#t~ite29_59|, |v_P2_#t~ite49_61|, |v_P2_#t~ite23_71|, |v_P2_#t~ite18_85|, |v_P2_#t~ite33_63|, |v_P2_#t~ite53_73|, |v_P2_#t~ite37_67|, |v_P2_#t~ite55_53|, |v_P2_#t~ite34_57|, |v_P2_#t~ite32_75|, |v_P2_#t~ite50_47|, |v_P2_#t~ite24_59|, |v_P2_#t~ite20_77|, |v_P2_#t~ite41_55|] AssignedVars[P2Thread1of1ForFork0_#t~mem16, ~__unbuffered_p2_EAX$read_delayed_var~0.offset, ~__unbuffered_p2_EAX$read_delayed_var~0.base, P2Thread1of1ForFork0_#t~ite41, P2Thread1of1ForFork0_#t~ite20, P2Thread1of1ForFork0_#t~ite60, P2Thread1of1ForFork0_#t~ite26, P2Thread1of1ForFork0_#t~ite47, ~y$mem_tmp~0, ~weak$$choice1~0, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#t~ite49, P2Thread1of1ForFork0_#t~ite28, P2Thread1of1ForFork0_#t~ite22, P2Thread1of1ForFork0_#t~ite43, P2Thread1of1ForFork0_#t~ite45, P2Thread1of1ForFork0_#t~ite24, ~y$flush_delayed~0, P2Thread1of1ForFork0_#t~mem58, ~__unbuffered_p2_EAX~0, P2Thread1of1ForFork0_#t~mem14, P2Thread1of1ForFork0_#t~nondet15, P2Thread1of1ForFork0_#t~ite53, P2Thread1of1ForFork0_#t~nondet13, P2Thread1of1ForFork0_#t~ite51, P2Thread1of1ForFork0_#t~ite30, ~weak$$choice0~0, P2Thread1of1ForFork0_#t~ite36, P2Thread1of1ForFork0_#t~ite38, ~y$w_buff1~0, P2Thread1of1ForFork0_#t~ite57, P2Thread1of1ForFork0_#t~ite32, P2Thread1of1ForFork0_#t~ite55, P2Thread1of1ForFork0_#t~ite34, P2Thread1of1ForFork0_#t~ite19, P2Thread1of1ForFork0_#t~mem21, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~mem59, P2Thread1of1ForFork0_#t~mem17, P2Thread1of1ForFork0_#t~ite40, P2Thread1of1ForFork0_#t~ite42, P2Thread1of1ForFork0_#t~ite25, P2Thread1of1ForFork0_#t~ite48, P2Thread1of1ForFork0_#t~ite27, P2Thread1of1ForFork0_#t~ite44, ~y$r_buff0_thd3~0, ~y$w_buff0~0, P2Thread1of1ForFork0_#t~ite46, P2Thread1of1ForFork0_#t~ite23, P2Thread1of1ForFork0_#t~ite29, P2Thread1of1ForFork0_#t~ite52, P2Thread1of1ForFork0_#t~ite50, P2Thread1of1ForFork0_#t~ite31, P2Thread1of1ForFork0_#t~nondet12, ~__unbuffered_p2_EAX$read_delayed~0, P2Thread1of1ForFork0_#t~ite37, P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite56, P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite54, P2Thread1of1ForFork0_#t~ite35, #memory_int, P2Thread1of1ForFork0_#t~ite18, ~weak$$choice2~0, ~y$w_buff1_used~0] and [1246] L2-1-->L866: Formula: (let ((.cse15 (= (mod v_~y$w_buff0_used~0_417 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd0~0_72 256) 0)) (.cse12 (= (mod v_~y$w_buff0_used~0_416 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd0~0_58 256) 0)) (.cse16 (= (mod v_~y$w_buff1_used~0_322 256) 0))) (let ((.cse4 (not .cse16)) (.cse0 (or .cse13 .cse16)) (.cse5 (not .cse13)) (.cse2 (not .cse12)) (.cse1 (or .cse14 .cse12)) (.cse8 (select |v_#memory_int_247| |v_~#y~0.base_164|)) (.cse9 (not .cse15)) (.cse3 (not .cse14)) (.cse6 (or .cse14 .cse15))) (and (or (and (= v_~y$w_buff1_used~0_322 v_~y$w_buff1_used~0_321) .cse0 .cse1) (and (or (and .cse2 .cse3) (and .cse4 .cse5)) (= v_~y$w_buff1_used~0_321 0))) (let ((.cse7 (= |v_ULTIMATE.start_main_#t~mem71_25| |v_ULTIMATE.start_main_#t~mem71_29|))) (or (and .cse6 (or (and .cse4 .cse7 .cse5 (= v_~y$w_buff1~0_111 |v_ULTIMATE.start_main_#t~ite72_28|)) (and .cse0 (= |v_ULTIMATE.start_main_#t~mem71_29| (select .cse8 |v_~#y~0.offset_164|)) (= |v_ULTIMATE.start_main_#t~mem71_29| |v_ULTIMATE.start_main_#t~ite72_28|))) (= |v_ULTIMATE.start_main_#t~ite73_36| |v_ULTIMATE.start_main_#t~ite72_28|)) (and (= |v_ULTIMATE.start_main_#t~ite72_24| |v_ULTIMATE.start_main_#t~ite72_28|) (= |v_ULTIMATE.start_main_#t~ite73_36| v_~y$w_buff0~0_108) .cse7 .cse9 .cse3))) (let ((.cse10 (= (mod v_~y$r_buff0_thd0~0_71 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_321 256) 0))) (or (and (= v_~y$r_buff1_thd0~0_57 0) (or (and .cse2 (not .cse10)) (and (not .cse11) .cse5))) (and (or .cse10 .cse12) (or .cse13 .cse11) (= v_~y$r_buff1_thd0~0_58 v_~y$r_buff1_thd0~0_57)))) (or (and .cse2 (= v_~y$r_buff0_thd0~0_71 0) .cse3) (and .cse1 (= v_~y$r_buff0_thd0~0_72 v_~y$r_buff0_thd0~0_71))) (= (store |v_#memory_int_247| |v_~#y~0.base_164| (store .cse8 |v_~#y~0.offset_164| |v_ULTIMATE.start_main_#t~ite73_36|)) |v_#memory_int_246|) (or (and .cse9 (= v_~y$w_buff0_used~0_416 0) .cse3) (and (= v_~y$w_buff0_used~0_417 v_~y$w_buff0_used~0_416) .cse6))))) InVars {~#y~0.offset=|v_~#y~0.offset_164|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_24|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_417, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_72, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_247|, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_25|, ~#y~0.base=|v_~#y~0.base_164|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_58, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_322} OutVars{~#y~0.offset=|v_~#y~0.offset_164|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_416, ULTIMATE.start_main_#t~mem71=|v_ULTIMATE.start_main_#t~mem71_23|, ~#y~0.base=|v_~#y~0.base_164|, ULTIMATE.start_main_#t~ite77=|v_ULTIMATE.start_main_#t~ite77_26|, ULTIMATE.start_main_#t~ite75=|v_ULTIMATE.start_main_#t~ite75_30|, ULTIMATE.start_main_#t~ite76=|v_ULTIMATE.start_main_#t~ite76_28|, ULTIMATE.start_main_#t~ite73=|v_ULTIMATE.start_main_#t~ite73_32|, ULTIMATE.start_main_#t~ite74=|v_ULTIMATE.start_main_#t~ite74_24|, ULTIMATE.start_main_#t~ite72=|v_ULTIMATE.start_main_#t~ite72_22|, ~y$w_buff1~0=v_~y$w_buff1~0_111, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_71, ~y$w_buff0~0=v_~y$w_buff0~0_108, #memory_int=|v_#memory_int_246|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_57, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_321} AuxVars[|v_ULTIMATE.start_main_#t~ite73_36|, |v_ULTIMATE.start_main_#t~ite72_28|, |v_ULTIMATE.start_main_#t~mem71_29|] AssignedVars[ULTIMATE.start_main_#t~ite73, ULTIMATE.start_main_#t~ite74, ULTIMATE.start_main_#t~ite72, ~y$w_buff0_used~0, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~mem71, #memory_int, ULTIMATE.start_main_#t~ite77, ~y$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite75, ULTIMATE.start_main_#t~ite76, ~y$w_buff1_used~0] under condition 197025#(and (= ~y$r_buff1_thd0~0 0) (= ~y$w_buff0~0 0) (= ~y$r_buff1_thd3~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~y$r_buff0_thd0~0 0)) [2021-01-26 23:12:24,637 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:24,728 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:25,387 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:28,661 WARN L146 IndependenceRelation]: Expensive independence query (3273 ms) for statements [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] and [1182] L854-1-->L855: Formula: (= |v_#memory_int_24| (store |v_#memory_int_25| |v_ULTIMATE.start_main_~#t2686~0.base_3| (store (select |v_#memory_int_25| |v_ULTIMATE.start_main_~#t2686~0.base_3|) |v_ULTIMATE.start_main_~#t2686~0.offset_3| 2))) InVars {#memory_int=|v_#memory_int_25|, ULTIMATE.start_main_~#t2686~0.offset=|v_ULTIMATE.start_main_~#t2686~0.offset_3|, ULTIMATE.start_main_~#t2686~0.base=|v_ULTIMATE.start_main_~#t2686~0.base_3|} OutVars{#memory_int=|v_#memory_int_24|, ULTIMATE.start_main_~#t2686~0.offset=|v_ULTIMATE.start_main_~#t2686~0.offset_3|, ULTIMATE.start_main_~#t2686~0.base=|v_ULTIMATE.start_main_~#t2686~0.base_3|} AuxVars[] AssignedVars[#memory_int] under condition 196851#(and (= ~y$r_buff1_thd0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$r_buff0_thd0~0 0)) [2021-01-26 23:12:33,892 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:37,977 WARN L146 IndependenceRelation]: Expensive independence query (4084 ms) for statements [1267] L826-->L833: Formula: (let ((.cse7 (= (mod v_~y$w_buff0_used~0_462 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_376 256) 0)) (.cse5 (= (mod v_~y$r_buff1_thd3~0_276 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_463 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd3~0_318 256) 0))) (let ((.cse3 (select |v_#memory_int_279| |v_~#y~0.base_180|)) (.cse0 (or .cse16 .cse14)) (.cse2 (not .cse16)) (.cse10 (or .cse15 .cse5)) (.cse13 (or .cse7 .cse14)) (.cse11 (not .cse15)) (.cse8 (not .cse5)) (.cse1 (not .cse14)) (.cse9 (not .cse7))) (and (or (and (= v_~y$w_buff0_used~0_463 v_~y$w_buff0_used~0_462) .cse0) (and (= v_~y$w_buff0_used~0_462 0) .cse1 .cse2)) (= (store |v_#memory_int_279| |v_~#y~0.base_180| (store .cse3 |v_~#y~0.offset_180| |v_P2_#t~ite63_39|)) |v_#memory_int_278|) (let ((.cse4 (= (mod v_~y$w_buff1_used~0_375 256) 0)) (.cse6 (= (mod v_~y$r_buff0_thd3~0_317 256) 0))) (or (and (or .cse4 .cse5) (= v_~y$r_buff1_thd3~0_276 v_~y$r_buff1_thd3~0_275) (or .cse6 .cse7)) (and (or (and .cse8 (not .cse4)) (and .cse9 (not .cse6))) (= v_~y$r_buff1_thd3~0_275 0)))) (let ((.cse12 (= |v_P2Thread1of1ForFork0_#t~mem61_1| |v_P2_#t~mem61_38|))) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~ite63_39|) (or (and (= |v_P2_#t~ite62_33| |v_P2_#t~mem61_38|) (= (select .cse3 |v_~#y~0.offset_180|) |v_P2_#t~mem61_38|) .cse10) (and .cse11 .cse12 (= v_~y$w_buff1~0_127 |v_P2_#t~ite62_33|) .cse8)) .cse0) (and (= |v_P2Thread1of1ForFork0_#t~ite62_1| |v_P2_#t~ite62_33|) .cse1 .cse12 (= |v_P2_#t~ite63_39| v_~y$w_buff0~0_128) .cse2))) (or (and (= v_~y$r_buff0_thd3~0_318 v_~y$r_buff0_thd3~0_317) .cse13) (and .cse1 .cse9 (= v_~y$r_buff0_thd3~0_317 0))) (or (and .cse10 (= v_~y$w_buff1_used~0_376 v_~y$w_buff1_used~0_375) .cse13) (and (or (and .cse11 .cse8) (and .cse1 .cse9)) (= v_~y$w_buff1_used~0_375 0)))))) InVars {P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_1|, ~#y~0.offset=|v_~#y~0.offset_180|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_276, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_463, ~y$w_buff1~0=v_~y$w_buff1~0_127, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_318, ~y$w_buff0~0=v_~y$w_buff0~0_128, #memory_int=|v_#memory_int_279|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_1|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_376} OutVars{~#y~0.offset=|v_~#y~0.offset_180|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_462, P2Thread1of1ForFork0_#t~ite63=|v_P2Thread1of1ForFork0_#t~ite63_1|, P2Thread1of1ForFork0_#t~ite64=|v_P2Thread1of1ForFork0_#t~ite64_1|, ~#y~0.base=|v_~#y~0.base_180|, P2Thread1of1ForFork0_#t~ite62=|v_P2Thread1of1ForFork0_#t~ite62_2|, P2Thread1of1ForFork0_#t~mem61=|v_P2Thread1of1ForFork0_#t~mem61_2|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_275, P2Thread1of1ForFork0_#t~ite67=|v_P2Thread1of1ForFork0_#t~ite67_1|, ~y$w_buff1~0=v_~y$w_buff1~0_127, P2Thread1of1ForFork0_#t~ite65=|v_P2Thread1of1ForFork0_#t~ite65_1|, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_317, ~y$w_buff0~0=v_~y$w_buff0~0_128, P2Thread1of1ForFork0_#t~ite66=|v_P2Thread1of1ForFork0_#t~ite66_1|, #memory_int=|v_#memory_int_278|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_375} AuxVars[|v_P2_#t~ite62_33|, |v_P2_#t~ite63_39|, |v_P2_#t~mem61_38|] AssignedVars[P2Thread1of1ForFork0_#t~mem61, ~y$r_buff1_thd3~0, ~y$w_buff0_used~0, P2Thread1of1ForFork0_#t~ite67, P2Thread1of1ForFork0_#t~ite65, ~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite66, P2Thread1of1ForFork0_#t~ite63, #memory_int, P2Thread1of1ForFork0_#t~ite64, P2Thread1of1ForFork0_#t~ite62, ~y$w_buff1_used~0] and [1260] L790-->L797: Formula: (let ((.cse12 (= (mod v_~y$w_buff0_used~0_454 256) 0)) (.cse13 (= (mod v_~y$r_buff1_thd2~0_56 256) 0)) (.cse15 (= (mod v_~y$w_buff1_used~0_368 256) 0)) (.cse16 (= (mod v_~y$w_buff0_used~0_455 256) 0)) (.cse14 (= (mod v_~y$r_buff0_thd2~0_67 256) 0))) (let ((.cse3 (select |v_#memory_int_267| |v_~#y~0.base_174|)) (.cse0 (or .cse16 .cse14)) (.cse1 (not .cse16)) (.cse6 (not .cse15)) (.cse7 (or .cse15 .cse13)) (.cse4 (not .cse13)) (.cse9 (or .cse12 .cse14)) (.cse8 (not .cse12)) (.cse2 (not .cse14))) (and (or (and (= v_~y$w_buff0_used~0_455 v_~y$w_buff0_used~0_454) .cse0) (and .cse1 (= v_~y$w_buff0_used~0_454 0) .cse2)) (= (store |v_#memory_int_267| |v_~#y~0.base_174| (store .cse3 |v_~#y~0.offset_174| |v_P1_#t~ite7_31|)) |v_#memory_int_266|) (let ((.cse5 (= |v_P1_#t~mem5_42| |v_P1Thread1of1ForFork2_#t~mem5_1|))) (or (and (= |v_P1_#t~ite6_37| |v_P1_#t~ite7_31|) (or (and .cse4 (= v_~y$w_buff1~0_121 |v_P1_#t~ite6_37|) .cse5 .cse6) (and (= |v_P1_#t~ite6_37| |v_P1_#t~mem5_42|) (= (select .cse3 |v_~#y~0.offset_174|) |v_P1_#t~mem5_42|) .cse7)) .cse0) (and (= |v_P1_#t~ite7_31| v_~y$w_buff0~0_126) .cse1 .cse5 (= |v_P1_#t~ite6_37| |v_P1Thread1of1ForFork2_#t~ite6_1|) .cse2))) (or (and (= v_~y$w_buff1_used~0_367 0) (or (and .cse4 .cse6) (and .cse8 .cse2))) (and .cse9 .cse7 (= v_~y$w_buff1_used~0_368 v_~y$w_buff1_used~0_367))) (let ((.cse10 (= (mod v_~y$r_buff0_thd2~0_66 256) 0)) (.cse11 (= (mod v_~y$w_buff1_used~0_367 256) 0))) (or (and (= 0 v_~y$r_buff1_thd2~0_55) (or (and (not .cse10) .cse8) (and .cse4 (not .cse11)))) (and (or .cse12 .cse10) (or .cse13 .cse11) (= v_~y$r_buff1_thd2~0_56 v_~y$r_buff1_thd2~0_55)))) (or (and .cse9 (= v_~y$r_buff0_thd2~0_67 v_~y$r_buff0_thd2~0_66)) (and (= v_~y$r_buff0_thd2~0_66 0) .cse8 .cse2))))) InVars {~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, ~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_455, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_67, #memory_int=|v_#memory_int_267|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_1|, ~#y~0.base=|v_~#y~0.base_174|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_368} OutVars{~#y~0.offset=|v_~#y~0.offset_174|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_454, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_1|, P1Thread1of1ForFork2_#t~ite7=|v_P1Thread1of1ForFork2_#t~ite7_1|, P1Thread1of1ForFork2_#t~ite6=|v_P1Thread1of1ForFork2_#t~ite6_2|, ~#y~0.base=|v_~#y~0.base_174|, P1Thread1of1ForFork2_#t~ite11=|v_P1Thread1of1ForFork2_#t~ite11_1|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_55, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_1|, ~y$w_buff1~0=v_~y$w_buff1~0_121, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_1|, ~y$w_buff0~0=v_~y$w_buff0~0_126, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_66, #memory_int=|v_#memory_int_266|, P1Thread1of1ForFork2_#t~mem5=|v_P1Thread1of1ForFork2_#t~mem5_2|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_367} AuxVars[|v_P1_#t~mem5_42|, |v_P1_#t~ite7_31|, |v_P1_#t~ite6_37|] AssignedVars[~y$r_buff1_thd2~0, ~y$w_buff0_used~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite8, ~y$r_buff0_thd2~0, P1Thread1of1ForFork2_#t~ite10, #memory_int, P1Thread1of1ForFork2_#t~ite7, P1Thread1of1ForFork2_#t~mem5, P1Thread1of1ForFork2_#t~ite6, P1Thread1of1ForFork2_#t~ite11, ~y$w_buff1_used~0] under condition 201757#(and (<= 1 ~main$tmp_guard1~0) (not (= ~__unbuffered_p2_EAX~0 1)) (<= (div ~main$tmp_guard1~0 256) 0) (or (<= (+ |ULTIMATE.start___VERIFIER_assert_#in~expression| 255) 0) (<= 1 |ULTIMATE.start___VERIFIER_assert_#in~expression|)) (or (<= 1 ULTIMATE.start___VERIFIER_assert_~expression) (<= (+ ULTIMATE.start___VERIFIER_assert_~expression 255) 0)) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1))) Size of Word is: 93 and size of Sequence is : 94[2021-01-26 23:12:39,049 INFO L164 SleepSetCegar]: Size of mCounterexample is: 94 [2021-01-26 23:12:39,050 INFO L165 SleepSetCegar]: [196865#[ULTIMATE.startENTRY]true, 196867#[L-1]true, 196869#[L-1-1]true, 196871#[L17]true, 196873#[L17-1]true, 196875#[L17-2]true, 196877#[L17-3]true, 196879#[L17-4]true, 196881#[L711]true, 196883#[L713](= ~__unbuffered_p0_EAX~0 0), 196885#[L715](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196887#[L716](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196889#[L717](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196891#[L718](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196893#[L719](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196895#[L720](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196897#[L721](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196899#[L722](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196901#[L723](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196903#[L724](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196905#[L725](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196907#[L726](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196909#[L727](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196911#[L728](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196913#[L729](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196915#[L730](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196917#[L731](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196919#[L732](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196921#[L733](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196923#[L735](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196925#[L737](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196927#[L737-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196929#[L737-2](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196931#[L739](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196933#[L740](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0)), 196935#[L741](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196937#[L742](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196939#[L743](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196941#[L744](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196943#[L745](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196945#[L746](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196947#[L747](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196949#[L748](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196951#[L749](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196953#[L750](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196955#[L751](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$w_buff0~0 0) (= ~y$r_buff1_thd3~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196957#[L752](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$w_buff0~0 0) (= ~y$r_buff1_thd3~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196959#[L753](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$w_buff0~0 0) (= ~y$r_buff1_thd3~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196961#[L755](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196963#[L756](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196965#[L757](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196967#[L758](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196969#[L-1-2](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196971#[L-1-3](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196973#[L850](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196975#[L850-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196977#[L851](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196979#[P0ENTRY, L851-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196983#[P0ENTRY, L852](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196989#[P0ENTRY, L852-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196991#[L853, P0ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196997#[L853, L761](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 196999#[L761, P1ENTRY, L853-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 261169#[L854, L761, P1ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 261173#[L761, P1ENTRY, L854-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 261177#[L761, P1ENTRY, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 261183#[L776, L761, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 261185#[L776, L761, L855-1, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 297995#[L776, L856, L761, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 298001#[L776, L761, P2ENTRY, L858](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 298005#[L776, L761, P2ENTRY, L859](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 298007#[L776, L761, L2, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 298013#[L776, L761, P2ENTRY, L3](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 298019#[L776, L761, L2-1, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 298415#[L776, L761, L866, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 298417#[L776, L761, L866, L805](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 304423#[L776, L823, L761, L866](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 304425#[L776, L761, L866, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 310371#[L776, L866, L763, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 310379#[L776, L866, L766, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 310383#[L776, L866, L771, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 310395#[L776, L866, P0FINAL, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 310403#[L776, L866, P0EXIT, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0)), 310405#[L778, L866, P0EXIT, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~y$r_buff0_thd0~0 0)), 310417#[L790, L866, P0EXIT, L826](and (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff0_thd0~0 0)), 310423#[L866, P0EXIT, L797, L826](= (select |#valid| |~#y~0.base|) 1), 310437#[P0EXIT, L797, L871, L826](= (select |#valid| |~#y~0.base|) 1), 310447#[L872, P0EXIT, L797, L826](= (select |#valid| |~#y~0.base|) 1), 310461#[P0EXIT, L18, L797, L826](= (select |#valid| |~#y~0.base|) 1), 310475#[L18-1, P0EXIT, L797, L826](= (select |#valid| |~#y~0.base|) 1), 310487#[L18-2, P0EXIT, L797, L826](= (select |#valid| |~#y~0.base|) 1), 310510#[P0EXIT, L797, L17-5, L826](= (select |#valid| |~#y~0.base|) 1), 310550#[L17-7, P0EXIT, L797, L826](= (select |#valid| |~#y~0.base|) 1), 310594#[ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0EXIT, L797, L826](= (select |#valid| |~#y~0.base|) 1)] [2021-01-26 23:12:39,051 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2021-01-26 23:12:39,051 INFO L429 AbstractCegarLoop]: === Iteration 6 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 23:12:39,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 23:12:39,051 INFO L82 PathProgramCache]: Analyzing trace with hash 1978882597, now seen corresponding path program 1 times [2021-01-26 23:12:39,051 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 23:12:39,052 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1829760306] [2021-01-26 23:12:39,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 23:12:39,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 23:12:39,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 23:12:39,303 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1829760306] [2021-01-26 23:12:39,304 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 23:12:39,304 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2021-01-26 23:12:39,304 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054781877] [2021-01-26 23:12:39,305 INFO L461 AbstractCegarLoop]: Interpolant automaton has 6 states [2021-01-26 23:12:39,305 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 23:12:39,306 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-01-26 23:12:39,310 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2021-01-26 23:12:39,311 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 23:12:39,311 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 6 states, 6 states have (on average 15.5) internal successors, (93), 6 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 23:12:40,811 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:40,972 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check Size of Word is: 94 and size of Sequence is : 95[2021-01-26 23:12:43,526 INFO L164 SleepSetCegar]: Size of mCounterexample is: 95 [2021-01-26 23:12:43,528 INFO L165 SleepSetCegar]: [310606#[ULTIMATE.startENTRY]true, 310608#[L-1]true, 310610#[L-1-1]true, 310612#[L17]true, 310614#[L17-1]true, 310616#[L17-2]true, 310618#[L17-3]true, 310620#[L17-4]true, 310622#[L711](= ~__unbuffered_cnt~0 0), 310624#[L713](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310626#[L715](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310628#[L716](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310630#[L717](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310632#[L718](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310634#[L719](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310636#[L720](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310638#[L721](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310640#[L722](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310642#[L723](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310644#[L724](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310646#[L725](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310648#[L726](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310650#[L727](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310652#[L728](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310654#[L729](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310656#[L730](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310658#[L731](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310660#[L732](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 310664#[L733](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310666#[L735](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310668#[L737](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310670#[L737-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310672#[L737-2](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310674#[L739](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310676#[L740](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310678#[L741](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310680#[L742](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310682#[L743](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310684#[L744](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310686#[L745](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310688#[L746](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310690#[L747](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310692#[L748](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310694#[L749](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310696#[L750](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310698#[L751](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310700#[L752](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310702#[L753](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310704#[L755](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310706#[L756](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310708#[L757](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310710#[L758](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310712#[L-1-2](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310714#[L-1-3](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310716#[L850](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310718#[L850-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310720#[L851](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310722#[P0ENTRY, L851-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310726#[P0ENTRY, L852](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310730#[P0ENTRY, L852-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310732#[L853, P0ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310738#[L853, L761](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 310740#[L761, P1ENTRY, L853-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 362954#[L854, L761, P1ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 362958#[L761, P1ENTRY, L854-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 362962#[L761, P1ENTRY, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 362968#[L776, L761, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 362970#[L776, L761, L855-1, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 379390#[L776, L856, L761, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 379394#[L776, L856, L761, L805](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 385599#[L776, L856, L823, L761](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 385612#[L776, L856, L761, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 385631#[L776, L856, L763, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 385649#[L776, L856, L766, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 385669#[L776, L856, L771, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (<= ~main$tmp_guard0~0 0)), 385695#[L776, L856, P0FINAL, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (<= ~main$tmp_guard0~0 0)), 385719#[L776, L856, P0EXIT, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (<= ~main$tmp_guard0~0 0)), 385731#[L856, L778, P0EXIT, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~y$r_buff0_thd0~0 0) (<= ~main$tmp_guard0~0 0)), 385755#[L856, L790, P0EXIT, L826](and (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff0_thd0~0 0) (<= ~main$tmp_guard0~0 0)), 385765#[L856, P0EXIT, L797, L826](and (= (select |#valid| |~#y~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (<= ~main$tmp_guard0~0 0)), 385779#[L856, L800, P0EXIT, L826](and (= (select |#valid| |~#y~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (<= ~main$tmp_guard0~0 0)), 385797#[L800, P0EXIT, L858, L826](= (select |#valid| |~#y~0.base|) 1), 385803#[L800, P0EXIT, L859, L826](= (select |#valid| |~#y~0.base|) 1), 385807#[L800, P0EXIT, L2, L826](= (select |#valid| |~#y~0.base|) 1), 385815#[L800, P0EXIT, L3, L826](= (select |#valid| |~#y~0.base|) 1), 385823#[L800, L2-1, P0EXIT, L826](= (select |#valid| |~#y~0.base|) 1), 385857#[L800, L866, P0EXIT, L826](= (select |#valid| |~#y~0.base|) 1), 385869#[L800, P0EXIT, L871, L826](= (select |#valid| |~#y~0.base|) 1), 385881#[L872, L800, P0EXIT, L826](= (select |#valid| |~#y~0.base|) 1), 385897#[L800, P0EXIT, L18, L826](= (select |#valid| |~#y~0.base|) 1), 385913#[L800, L18-1, P0EXIT, L826](= (select |#valid| |~#y~0.base|) 1), 385929#[L18-2, L800, P0EXIT, L826](= (select |#valid| |~#y~0.base|) 1), 385947#[L800, P0EXIT, L17-5, L826](= (select |#valid| |~#y~0.base|) 1), 385984#[L800, L17-7, P0EXIT, L826](= (select |#valid| |~#y~0.base|) 1), 386036#[ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, L800, P0EXIT, L826](= (select |#valid| |~#y~0.base|) 1)] [2021-01-26 23:12:43,528 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2021-01-26 23:12:43,528 INFO L429 AbstractCegarLoop]: === Iteration 7 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 23:12:43,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 23:12:43,529 INFO L82 PathProgramCache]: Analyzing trace with hash 2107586648, now seen corresponding path program 1 times [2021-01-26 23:12:43,529 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 23:12:43,529 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347007188] [2021-01-26 23:12:43,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 23:12:43,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-26 23:12:43,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-26 23:12:43,817 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347007188] [2021-01-26 23:12:43,817 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-26 23:12:43,817 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2021-01-26 23:12:43,817 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594731267] [2021-01-26 23:12:43,818 INFO L461 AbstractCegarLoop]: Interpolant automaton has 8 states [2021-01-26 23:12:43,818 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-26 23:12:43,818 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2021-01-26 23:12:43,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2021-01-26 23:12:43,820 INFO L481 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2021-01-26 23:12:43,820 INFO L482 AbstractCegarLoop]: Interpolant automaton has has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-01-26 23:12:44,020 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:44,092 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:44,199 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check [2021-01-26 23:12:44,446 WARN L160 IndependenceRelation]: Requesting ManagedScript unlock before implication check Size of Word is: 98 and size of Sequence is : 99[2021-01-26 23:12:45,556 INFO L164 SleepSetCegar]: Size of mCounterexample is: 99 [2021-01-26 23:12:45,559 INFO L165 SleepSetCegar]: [386050#[ULTIMATE.startENTRY]true, 386052#[L-1]true, 386054#[L-1-1]true, 386056#[L17]true, 386058#[L17-1]true, 386060#[L17-2]true, 386062#[L17-3]true, 386064#[L17-4]true, 386066#[L711](= ~__unbuffered_cnt~0 0), 386068#[L713](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386070#[L715](and (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386072#[L716](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386074#[L717](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386076#[L718](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386078#[L719](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386080#[L720](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386082#[L721](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386084#[L722](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386086#[L723](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386088#[L724](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386090#[L725](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386092#[L726](and (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386094#[L727](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386096#[L728](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386098#[L729](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386100#[L730](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386102#[L731](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386104#[L732](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0)), 386108#[L733](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386110#[L735](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386112#[L737](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386114#[L737-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386116#[L737-2](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386118#[L739](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386120#[L740](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386122#[L741](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386124#[L742](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386126#[L743](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386128#[L744](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386130#[L745](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386132#[L746](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386134#[L747](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386136#[L748](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386138#[L749](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386140#[L750](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386142#[L751](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386144#[L752](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386146#[L753](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386148#[L755](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386150#[L756](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386152#[L757](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386154#[L758](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386156#[L-1-2](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386158#[L-1-3](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386160#[L850](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386162#[L850-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386164#[L851](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386166#[P0ENTRY, L851-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386170#[P0ENTRY, L852](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386174#[P0ENTRY, L852-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386176#[L853, P0ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386182#[L853, L761](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 386184#[L761, P1ENTRY, L853-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 401822#[L854, L761, P1ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 401826#[L761, P1ENTRY, L854-1](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 401830#[L761, P1ENTRY, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 401836#[L776, L761, L855](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 401838#[L776, L761, L855-1, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 408592#[L776, L856, L761, P2ENTRY](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 408596#[L776, L856, L761, L805](and (= ~__unbuffered_p2_EAX$read_delayed~0 0) (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (= ~__unbuffered_p2_EAX~0 0) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 410842#[L776, L856, L823, L761](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (= ~z~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 410844#[L776, L856, L761, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (= ~__unbuffered_p0_EAX~0 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 410846#[L776, L856, L763, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (= ~x~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 410852#[L776, L856, L766, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (= ~__unbuffered_cnt~0 0) (<= ~main$tmp_guard0~0 0)), 410856#[L776, L856, L771, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (<= ~__unbuffered_cnt~0 1) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (<= ~main$tmp_guard0~0 0)), 410866#[L776, L856, P0FINAL, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (<= ~__unbuffered_cnt~0 1) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (<= ~main$tmp_guard0~0 0)), 410874#[L776, L856, P0EXIT, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (<= ~__unbuffered_cnt~0 1) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~__unbuffered_p1_EAX~0 0) (= ~y$r_buff0_thd0~0 0) (<= ~main$tmp_guard0~0 0)), 410876#[L856, L778, P0EXIT, L826](and (= ~y$w_buff0~0 0) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (not (= |ULTIMATE.start_main_~#t2685~0.base| |~#y~0.base|)) (= ~y$w_buff0_used~0 0) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (<= ~__unbuffered_cnt~0 1) (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= ~y$r_buff1_thd3~0 0) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2686~0.base|)) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= |~#y~0.base| |ULTIMATE.start_main_~#t2684~0.base|)) (= ~y$w_buff1_used~0 0) (= ~y$r_buff0_thd0~0 0) (<= ~main$tmp_guard0~0 0)), 410888#[L856, L790, P0EXIT, L826](and (= ~y$r_buff1_thd0~0 0) (not (= ~__unbuffered_p2_EAX~0 1)) (= (select |#valid| |~#y~0.base|) 1) (= (select (select |#memory_int| |~#y~0.base|) |~#y~0.offset|) 0) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (not (= (select (select |#memory_int| ~__unbuffered_p2_EAX$read_delayed_var~0.base) ~__unbuffered_p2_EAX$read_delayed_var~0.offset) 1)) (<= ~__unbuffered_cnt~0 1) (= ~y$r_buff0_thd0~0 0) (<= ~main$tmp_guard0~0 0)), 410890#[L856, P0EXIT, L797, L826](and (= (select |#valid| |~#y~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (<= ~__unbuffered_cnt~0 1) (<= ~main$tmp_guard0~0 0)), 410896#[L856, L800, P0EXIT, L826](and (= (select |#valid| |~#y~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (<= ~__unbuffered_cnt~0 2) (<= ~main$tmp_guard0~0 0)), 410902#[L856, P0EXIT, P1FINAL, L826](and (= (select |#valid| |~#y~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (<= ~__unbuffered_cnt~0 2) (<= ~main$tmp_guard0~0 0)), 410920#[L856, P0EXIT, P1EXIT, L826](and (= (select |#valid| |~#y~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (<= ~__unbuffered_cnt~0 2) (<= ~main$tmp_guard0~0 0)), 410934#[L856, L833, P0EXIT, P1EXIT](and (= (select |#valid| |~#y~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (<= ~__unbuffered_cnt~0 2) (<= ~main$tmp_guard0~0 0)), 410946#[L856, L836, P0EXIT, P1EXIT](and (= (select |#valid| |~#y~0.base|) 1) (< 0 (+ (div ~main$tmp_guard0~0 256) 1)) (<= ~main$tmp_guard0~0 0)), 410960#[L836, P0EXIT, P1EXIT, L858](= (select |#valid| |~#y~0.base|) 1), 410968#[L836, P0EXIT, P1EXIT, L859](= (select |#valid| |~#y~0.base|) 1), 410974#[L836, P0EXIT, L2, P1EXIT](= (select |#valid| |~#y~0.base|) 1), 410984#[L836, P0EXIT, P1EXIT, L3](= (select |#valid| |~#y~0.base|) 1), 410994#[L836, L2-1, P0EXIT, P1EXIT](= (select |#valid| |~#y~0.base|) 1), 411010#[L866, L836, P0EXIT, P1EXIT](= (select |#valid| |~#y~0.base|) 1), 411026#[L836, P0EXIT, P1EXIT, L871](= (select |#valid| |~#y~0.base|) 1), 411040#[L872, L836, P0EXIT, P1EXIT](= (select |#valid| |~#y~0.base|) 1), 411058#[L836, P0EXIT, L18, P1EXIT](= (select |#valid| |~#y~0.base|) 1), 411074#[L18-1, L836, P0EXIT, P1EXIT](= (select |#valid| |~#y~0.base|) 1), 411094#[L18-2, L836, P0EXIT, P1EXIT](= (select |#valid| |~#y~0.base|) 1), 411121#[L836, P0EXIT, P1EXIT, L17-5](= (select |#valid| |~#y~0.base|) 1), 411164#[L836, L17-7, P0EXIT, P1EXIT](= (select |#valid| |~#y~0.base|) 1), 411207#[ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, L836, P0EXIT, P1EXIT](= (select |#valid| |~#y~0.base|) 1)] [2021-01-26 23:12:45,559 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2021-01-26 23:12:45,559 INFO L429 AbstractCegarLoop]: === Iteration 8 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-26 23:12:45,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-26 23:12:45,560 INFO L82 PathProgramCache]: Analyzing trace with hash -2067459654, now seen corresponding path program 1 times [2021-01-26 23:12:45,560 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-26 23:12:45,560 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935597139] [2021-01-26 23:12:45,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-26 23:12:45,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-01-26 23:12:45,675 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-01-26 23:12:45,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-01-26 23:12:45,781 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-01-26 23:12:45,855 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-01-26 23:12:45,855 INFO L605 BasicCegarLoop]: Counterexample might be feasible [2021-01-26 23:12:45,856 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2021-01-26 23:12:46,143 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 26.01 11:12:46 BasicIcfg [2021-01-26 23:12:46,143 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2021-01-26 23:12:46,145 INFO L168 Benchmark]: Toolchain (without parser) took 134390.48 ms. Allocated memory was 302.0 MB in the beginning and 1.5 GB in the end (delta: 1.2 GB). Free memory was 276.7 MB in the beginning and 682.6 MB in the end (delta: -405.9 MB). Peak memory consumption was 823.0 MB. Max. memory is 16.0 GB. [2021-01-26 23:12:46,146 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 302.0 MB. Free memory is still 272.1 MB. There was no memory consumed. Max. memory is 16.0 GB. [2021-01-26 23:12:46,146 INFO L168 Benchmark]: CACSL2BoogieTranslator took 822.75 ms. Allocated memory is still 302.0 MB. Free memory was 275.6 MB in the beginning and 280.5 MB in the end (delta: -4.9 MB). Peak memory consumption was 38.0 MB. Max. memory is 16.0 GB. [2021-01-26 23:12:46,147 INFO L168 Benchmark]: Boogie Procedure Inliner took 94.61 ms. Allocated memory is still 302.0 MB. Free memory was 280.5 MB in the beginning and 277.4 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.0 GB. [2021-01-26 23:12:46,148 INFO L168 Benchmark]: Boogie Preprocessor took 59.13 ms. Allocated memory is still 302.0 MB. Free memory was 277.4 MB in the beginning and 275.3 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.0 GB. [2021-01-26 23:12:46,149 INFO L168 Benchmark]: RCFGBuilder took 3658.79 ms. Allocated memory was 302.0 MB in the beginning and 379.6 MB in the end (delta: 77.6 MB). Free memory was 275.3 MB in the beginning and 155.3 MB in the end (delta: 120.0 MB). Peak memory consumption was 198.6 MB. Max. memory is 16.0 GB. [2021-01-26 23:12:46,149 INFO L168 Benchmark]: TraceAbstraction took 129734.36 ms. Allocated memory was 379.6 MB in the beginning and 1.5 GB in the end (delta: 1.2 GB). Free memory was 155.3 MB in the beginning and 682.6 MB in the end (delta: -527.3 MB). Peak memory consumption was 621.9 MB. Max. memory is 16.0 GB. [2021-01-26 23:12:46,153 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 302.0 MB. Free memory is still 272.1 MB. There was no memory consumed. Max. memory is 16.0 GB. * CACSL2BoogieTranslator took 822.75 ms. Allocated memory is still 302.0 MB. Free memory was 275.6 MB in the beginning and 280.5 MB in the end (delta: -4.9 MB). Peak memory consumption was 38.0 MB. Max. memory is 16.0 GB. * Boogie Procedure Inliner took 94.61 ms. Allocated memory is still 302.0 MB. Free memory was 280.5 MB in the beginning and 277.4 MB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.0 GB. * Boogie Preprocessor took 59.13 ms. Allocated memory is still 302.0 MB. Free memory was 277.4 MB in the beginning and 275.3 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.0 GB. * RCFGBuilder took 3658.79 ms. Allocated memory was 302.0 MB in the beginning and 379.6 MB in the end (delta: 77.6 MB). Free memory was 275.3 MB in the beginning and 155.3 MB in the end (delta: 120.0 MB). Peak memory consumption was 198.6 MB. Max. memory is 16.0 GB. * TraceAbstraction took 129734.36 ms. Allocated memory was 379.6 MB in the beginning and 1.5 GB in the end (delta: 1.2 GB). Free memory was 155.3 MB in the beginning and 682.6 MB in the end (delta: -527.3 MB). Peak memory consumption was 621.9 MB. Max. memory is 16.0 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 17]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L709] 0 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L711] 0 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L713] 0 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0] [L715] 0 int __unbuffered_p2_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0] [L716] 0 _Bool __unbuffered_p2_EAX$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0] [L717] 0 int __unbuffered_p2_EAX$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0] [L718] 0 _Bool __unbuffered_p2_EAX$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0] [L719] 0 _Bool __unbuffered_p2_EAX$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0] [L720] 0 _Bool __unbuffered_p2_EAX$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0] [L721] 0 _Bool __unbuffered_p2_EAX$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0] [L722] 0 _Bool __unbuffered_p2_EAX$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0] [L723] 0 _Bool __unbuffered_p2_EAX$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0] [L724] 0 _Bool __unbuffered_p2_EAX$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0] [L725] 0 _Bool __unbuffered_p2_EAX$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0] [L726] 0 _Bool __unbuffered_p2_EAX$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0] [L727] 0 int *__unbuffered_p2_EAX$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}] [L728] 0 int __unbuffered_p2_EAX$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0] [L729] 0 _Bool __unbuffered_p2_EAX$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0] [L730] 0 int __unbuffered_p2_EAX$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0] [L731] 0 _Bool __unbuffered_p2_EAX$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0] [L732] 0 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0] [L733] 0 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0] [L735] 0 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L737] 0 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}] [L738] 0 _Bool y$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0] [L739] 0 int y$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0] [L740] 0 _Bool y$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0] [L741] 0 _Bool y$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0] [L742] 0 _Bool y$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0] [L743] 0 _Bool y$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0] [L744] 0 _Bool y$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0] [L745] 0 _Bool y$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0] [L746] 0 _Bool y$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0] [L747] 0 _Bool y$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0] [L748] 0 _Bool y$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0] [L749] 0 int *y$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}] [L750] 0 int y$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0] [L751] 0 _Bool y$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0] [L752] 0 int y$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0] [L753] 0 _Bool y$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L755] 0 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L756] 0 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L757] 0 _Bool weak$$choice1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L758] 0 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L850] 0 pthread_t t2684; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L851] FCALL, FORK 0 pthread_create(&t2684, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L852] 0 pthread_t t2685; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L853] FCALL, FORK 0 pthread_create(&t2685, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L854] 0 pthread_t t2686; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L855] FCALL, FORK 0 pthread_create(&t2686, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=0, __unbuffered_p2_EAX$read_delayed_var={0:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L806] 3 weak$$choice0 = __VERIFIER_nondet_bool() [L807] 3 weak$$choice2 = __VERIFIER_nondet_bool() [L808] 3 y$flush_delayed = weak$$choice2 [L809] EXPR 3 \read(y) [L809] 3 y$mem_tmp = y [L810] 3 weak$$choice1 = __VERIFIER_nondet_bool() [L811] EXPR 3 !y$w_buff0_used ? y : (y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (weak$$choice0 ? y : (weak$$choice1 ? y$w_buff0 : y$w_buff1)) : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (weak$$choice0 ? y$w_buff1 : y$w_buff0) : (weak$$choice0 ? y$w_buff0 : y)))) [L811] EXPR 3 \read(y) [L811] EXPR 3 !y$w_buff0_used ? y : (y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (weak$$choice0 ? y : (weak$$choice1 ? y$w_buff0 : y$w_buff1)) : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (weak$$choice0 ? y$w_buff1 : y$w_buff0) : (weak$$choice0 ? y$w_buff0 : y)))) [L811] 3 y = !y$w_buff0_used ? y : (y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (weak$$choice0 ? y : (weak$$choice1 ? y$w_buff0 : y$w_buff1)) : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (weak$$choice0 ? y$w_buff1 : y$w_buff0) : (weak$$choice0 ? y$w_buff0 : y)))) [L812] EXPR 3 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? y$w_buff0 : y$w_buff0)))) [L812] 3 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? y$w_buff0 : y$w_buff0)))) [L813] EXPR 3 weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff1 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? y$w_buff1 : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? y$w_buff1 : y$w_buff1)))) [L813] 3 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff1 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? y$w_buff1 : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? y$w_buff1 : y$w_buff1)))) [L814] EXPR 3 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? weak$$choice0 || !weak$$choice1 : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? weak$$choice0 : weak$$choice0)))) [L814] 3 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? weak$$choice0 || !weak$$choice1 : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? weak$$choice0 : weak$$choice0)))) [L815] EXPR 3 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? weak$$choice0 : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)))) [L815] 3 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? weak$$choice0 : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)))) [L816] EXPR 3 weak$$choice2 ? y$r_buff0_thd3 : (!y$w_buff0_used ? y$r_buff0_thd3 : (y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? y$r_buff0_thd3 : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)))) [L816] 3 y$r_buff0_thd3 = weak$$choice2 ? y$r_buff0_thd3 : (!y$w_buff0_used ? y$r_buff0_thd3 : (y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? y$r_buff0_thd3 : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)))) [L817] EXPR 3 weak$$choice2 ? y$r_buff1_thd3 : (!y$w_buff0_used ? y$r_buff1_thd3 : (y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (weak$$choice0 ? y$r_buff1_thd3 : (_Bool)0) : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)))) [L817] 3 y$r_buff1_thd3 = weak$$choice2 ? y$r_buff1_thd3 : (!y$w_buff0_used ? y$r_buff1_thd3 : (y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : (y$w_buff0_used && !y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (weak$$choice0 ? y$r_buff1_thd3 : (_Bool)0) : (y$w_buff0_used && y$r_buff1_thd3 && y$w_buff1_used && !y$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)))) [L818] 3 __unbuffered_p2_EAX$read_delayed = (_Bool)1 [L819] 3 __unbuffered_p2_EAX$read_delayed_var = &y [L820] EXPR 3 \read(y) [L820] 3 __unbuffered_p2_EAX = y [L821] EXPR 3 y$flush_delayed ? y$mem_tmp : y [L821] 3 y = y$flush_delayed ? y$mem_tmp : y [L822] 3 y$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L825] 3 z = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L762] 1 __unbuffered_p0_EAX = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=0, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L765] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L770] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L772] 1 return 0; VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L777] 2 __unbuffered_p1_EAX = x VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L780] 2 y$w_buff1 = y$w_buff0 [L781] 2 y$w_buff0 = 1 [L782] 2 y$w_buff1_used = y$w_buff0_used [L783] 2 y$w_buff0_used = (_Bool)1 [L18] COND FALSE 2 !(!expression) [L785] 2 y$r_buff1_thd0 = y$r_buff0_thd0 [L786] 2 y$r_buff1_thd1 = y$r_buff0_thd1 [L787] 2 y$r_buff1_thd2 = y$r_buff0_thd2 [L788] 2 y$r_buff1_thd3 = y$r_buff0_thd3 [L789] 2 y$r_buff0_thd2 = (_Bool)1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=1, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L792] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L792] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L793] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L793] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L794] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L794] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L795] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L795] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L796] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$r_buff1_thd2 [L796] 2 y$r_buff1_thd2 = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$r_buff1_thd2 [L799] 2 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=1, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L801] 2 return 0; VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=1, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L828] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L828] EXPR 3 y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y [L828] EXPR 3 \read(y) [L828] EXPR 3 y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y [L828] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L828] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L829] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L829] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L830] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L830] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L831] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$r_buff0_thd3 [L831] 3 y$r_buff0_thd3 = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$r_buff0_thd3 [L832] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$r_buff1_thd3 [L832] 3 y$r_buff1_thd3 = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$r_buff1_thd3 [L835] 3 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [\result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=1, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L857] 0 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [\result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=1, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L3] COND FALSE 0 !(!cond) VAL [\result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=255, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=1, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L861] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L861] EXPR 0 y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y [L861] EXPR 0 \read(y) [L861] EXPR 0 y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y [L861] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L861] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L862] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L862] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L863] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L863] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L864] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L864] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L865] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L865] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L868] 0 weak$$choice1 = __VERIFIER_nondet_bool() [L869] EXPR 0 __unbuffered_p2_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p2_EAX$read_delayed_var : __unbuffered_p2_EAX) : __unbuffered_p2_EAX [L869] EXPR 0 weak$$choice1 ? *__unbuffered_p2_EAX$read_delayed_var : __unbuffered_p2_EAX [L869] EXPR 0 \read(*__unbuffered_p2_EAX$read_delayed_var) [L869] EXPR 0 weak$$choice1 ? *__unbuffered_p2_EAX$read_delayed_var : __unbuffered_p2_EAX [L869] EXPR 0 __unbuffered_p2_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p2_EAX$read_delayed_var : __unbuffered_p2_EAX) : __unbuffered_p2_EAX [L869] 0 __unbuffered_p2_EAX = __unbuffered_p2_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p2_EAX$read_delayed_var : __unbuffered_p2_EAX) : __unbuffered_p2_EAX [L870] 0 main$tmp_guard1 = !(__unbuffered_p0_EAX == 1 && __unbuffered_p1_EAX == 1 && __unbuffered_p2_EAX == 1) VAL [\result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=1, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L18] COND TRUE 0 !expression VAL [\result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=1, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L17] COND FALSE 0 !(0) VAL [\result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=1, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L17] 0 __assert_fail ("0", "thin001_power.opt.c", 8, __extension__ __PRETTY_FUNCTION__) VAL [\result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, __unbuffered_p2_EAX$flush_delayed=0, __unbuffered_p2_EAX$mem_tmp=0, __unbuffered_p2_EAX$r_buff0_thd0=0, __unbuffered_p2_EAX$r_buff0_thd1=0, __unbuffered_p2_EAX$r_buff0_thd2=0, __unbuffered_p2_EAX$r_buff0_thd3=0, __unbuffered_p2_EAX$r_buff1_thd0=0, __unbuffered_p2_EAX$r_buff1_thd1=0, __unbuffered_p2_EAX$r_buff1_thd2=0, __unbuffered_p2_EAX$r_buff1_thd3=0, __unbuffered_p2_EAX$read_delayed=1, __unbuffered_p2_EAX$read_delayed_var={7:0}, __unbuffered_p2_EAX$w_buff0=0, __unbuffered_p2_EAX$w_buff0_used=0, __unbuffered_p2_EAX$w_buff1=0, __unbuffered_p2_EAX$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=1, weak$$choice2=255, x=1, y={7:0}, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=1, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=1, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 118 locations, 2 error locations. Started 1 CEGAR loops. VerificationResult: UNSAFE, OverallTime: 129.2s, OverallIterations: 8, TraceHistogramMax: 0, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: No data available, PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=0occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.9s SatisfiabilityAnalysisTime, 1.6s InterpolantComputationTime, 729 NumberOfCodeBlocks, 729 NumberOfCodeBlocksAsserted, 8 NumberOfCheckSat, 624 ConstructedInterpolants, 0 QuantifiedInterpolants, 260160 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 7 InterpolantComputations, 7 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [MP z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forcibly destroying the process Received shutdown request...