./Ultimate.py --spec ../../sv-benchmarks/c/MemSafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c -s /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9af739900018493f70ca6be86d814e194413d937 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-10-27 04:45:31,394 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-27 04:45:31,395 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-27 04:45:31,406 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-27 04:45:31,406 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-27 04:45:31,407 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-27 04:45:31,408 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-27 04:45:31,409 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-27 04:45:31,410 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-27 04:45:31,411 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-27 04:45:31,411 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-27 04:45:31,411 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-27 04:45:31,415 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-27 04:45:31,416 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-27 04:45:31,417 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-27 04:45:31,417 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-27 04:45:31,418 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-27 04:45:31,419 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-27 04:45:31,422 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-27 04:45:31,423 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-27 04:45:31,424 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-27 04:45:31,425 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-27 04:45:31,426 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-27 04:45:31,426 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-27 04:45:31,427 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-27 04:45:31,427 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-27 04:45:31,435 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-27 04:45:31,436 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-27 04:45:31,436 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-27 04:45:31,437 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-27 04:45:31,437 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-27 04:45:31,437 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-27 04:45:31,438 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-27 04:45:31,438 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-27 04:45:31,438 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-27 04:45:31,439 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-27 04:45:31,439 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2018-10-27 04:45:31,455 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-27 04:45:31,456 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-27 04:45:31,457 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-10-27 04:45:31,457 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-10-27 04:45:31,457 INFO L133 SettingsManager]: * Use SBE=true [2018-10-27 04:45:31,457 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-27 04:45:31,457 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-27 04:45:31,457 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-10-27 04:45:31,457 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-27 04:45:31,458 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-27 04:45:31,458 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-27 04:45:31,458 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-10-27 04:45:31,458 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-10-27 04:45:31,460 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-10-27 04:45:31,460 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-27 04:45:31,460 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-27 04:45:31,461 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-27 04:45:31,461 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-10-27 04:45:31,461 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-27 04:45:31,461 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-10-27 04:45:31,461 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-27 04:45:31,461 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-27 04:45:31,461 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-27 04:45:31,462 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-10-27 04:45:31,462 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-27 04:45:31,462 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9af739900018493f70ca6be86d814e194413d937 [2018-10-27 04:45:31,495 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-27 04:45:31,503 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-27 04:45:31,506 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-27 04:45:31,507 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-27 04:45:31,507 INFO L276 PluginConnector]: CDTParser initialized [2018-10-27 04:45:31,508 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-10-27 04:45:31,548 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/data/71eb71d18/c5b54236e9f3495c8b56d2a383894906/FLAGca1817773 [2018-10-27 04:45:31,914 INFO L298 CDTParser]: Found 1 translation units. [2018-10-27 04:45:31,915 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-10-27 04:45:31,920 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/data/71eb71d18/c5b54236e9f3495c8b56d2a383894906/FLAGca1817773 [2018-10-27 04:45:31,931 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/data/71eb71d18/c5b54236e9f3495c8b56d2a383894906 [2018-10-27 04:45:31,934 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-27 04:45:31,934 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-10-27 04:45:31,935 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-27 04:45:31,935 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-27 04:45:31,938 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-27 04:45:31,939 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.10 04:45:31" (1/1) ... [2018-10-27 04:45:31,944 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@75f8560f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:45:31, skipping insertion in model container [2018-10-27 04:45:31,944 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.10 04:45:31" (1/1) ... [2018-10-27 04:45:31,951 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-27 04:45:31,965 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-27 04:45:32,077 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-27 04:45:32,083 INFO L189 MainTranslator]: Completed pre-run [2018-10-27 04:45:32,097 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-27 04:45:32,109 INFO L193 MainTranslator]: Completed translation [2018-10-27 04:45:32,110 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:45:32 WrapperNode [2018-10-27 04:45:32,110 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-27 04:45:32,110 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-27 04:45:32,111 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-27 04:45:32,111 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-27 04:45:32,122 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:45:32" (1/1) ... [2018-10-27 04:45:32,122 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:45:32" (1/1) ... [2018-10-27 04:45:32,129 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:45:32" (1/1) ... [2018-10-27 04:45:32,129 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:45:32" (1/1) ... [2018-10-27 04:45:32,134 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:45:32" (1/1) ... [2018-10-27 04:45:32,138 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:45:32" (1/1) ... [2018-10-27 04:45:32,139 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:45:32" (1/1) ... [2018-10-27 04:45:32,141 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-27 04:45:32,141 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-27 04:45:32,141 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-27 04:45:32,142 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-27 04:45:32,142 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:45:32" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-10-27 04:45:32,243 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-10-27 04:45:32,243 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-27 04:45:32,243 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2018-10-27 04:45:32,243 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-10-27 04:45:32,243 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2018-10-27 04:45:32,243 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-10-27 04:45:32,244 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-10-27 04:45:32,244 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-10-27 04:45:32,244 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-10-27 04:45:32,244 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-10-27 04:45:32,244 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-10-27 04:45:32,244 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-27 04:45:32,244 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-10-27 04:45:32,643 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-27 04:45:32,644 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 04:45:32 BoogieIcfgContainer [2018-10-27 04:45:32,644 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-27 04:45:32,645 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-10-27 04:45:32,645 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-10-27 04:45:32,647 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-10-27 04:45:32,648 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.10 04:45:31" (1/3) ... [2018-10-27 04:45:32,648 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2117bb35 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.10 04:45:32, skipping insertion in model container [2018-10-27 04:45:32,649 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 04:45:32" (2/3) ... [2018-10-27 04:45:32,649 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2117bb35 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.10 04:45:32, skipping insertion in model container [2018-10-27 04:45:32,649 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 04:45:32" (3/3) ... [2018-10-27 04:45:32,650 INFO L112 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-10-27 04:45:32,659 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-10-27 04:45:32,665 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2018-10-27 04:45:32,679 INFO L257 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2018-10-27 04:45:32,701 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-10-27 04:45:32,701 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-10-27 04:45:32,701 INFO L383 AbstractCegarLoop]: Hoare is false [2018-10-27 04:45:32,701 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-10-27 04:45:32,702 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-10-27 04:45:32,702 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-10-27 04:45:32,702 INFO L387 AbstractCegarLoop]: Difference is false [2018-10-27 04:45:32,702 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-10-27 04:45:32,702 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-10-27 04:45:32,718 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states. [2018-10-27 04:45:32,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-10-27 04:45:32,731 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:32,731 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:32,736 INFO L424 AbstractCegarLoop]: === Iteration 1 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:32,743 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:32,743 INFO L82 PathProgramCache]: Analyzing trace with hash -1496656545, now seen corresponding path program 1 times [2018-10-27 04:45:32,745 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:32,745 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:32,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:32,793 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:32,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:32,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:32,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:45:32,883 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:45:32,884 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 04:45:32,887 INFO L460 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-10-27 04:45:32,900 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-10-27 04:45:32,900 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-10-27 04:45:32,902 INFO L87 Difference]: Start difference. First operand 54 states. Second operand 2 states. [2018-10-27 04:45:32,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:32,918 INFO L93 Difference]: Finished difference Result 54 states and 57 transitions. [2018-10-27 04:45:32,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-10-27 04:45:32,919 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 14 [2018-10-27 04:45:32,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:32,928 INFO L225 Difference]: With dead ends: 54 [2018-10-27 04:45:32,928 INFO L226 Difference]: Without dead ends: 51 [2018-10-27 04:45:32,930 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-10-27 04:45:32,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-10-27 04:45:32,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2018-10-27 04:45:32,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-10-27 04:45:32,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 54 transitions. [2018-10-27 04:45:32,959 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 54 transitions. Word has length 14 [2018-10-27 04:45:32,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:32,960 INFO L481 AbstractCegarLoop]: Abstraction has 51 states and 54 transitions. [2018-10-27 04:45:32,960 INFO L482 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-10-27 04:45:32,960 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 54 transitions. [2018-10-27 04:45:32,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-10-27 04:45:32,961 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:32,961 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:32,961 INFO L424 AbstractCegarLoop]: === Iteration 2 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:32,961 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:32,961 INFO L82 PathProgramCache]: Analyzing trace with hash 405796804, now seen corresponding path program 1 times [2018-10-27 04:45:32,961 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:32,962 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:32,962 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:32,963 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:32,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:32,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:33,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:45:33,018 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:45:33,018 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 04:45:33,020 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:45:33,020 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:45:33,020 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:45:33,020 INFO L87 Difference]: Start difference. First operand 51 states and 54 transitions. Second operand 3 states. [2018-10-27 04:45:33,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:33,129 INFO L93 Difference]: Finished difference Result 74 states and 78 transitions. [2018-10-27 04:45:33,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:45:33,129 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-10-27 04:45:33,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:33,131 INFO L225 Difference]: With dead ends: 74 [2018-10-27 04:45:33,132 INFO L226 Difference]: Without dead ends: 74 [2018-10-27 04:45:33,132 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:45:33,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-10-27 04:45:33,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 55. [2018-10-27 04:45:33,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-10-27 04:45:33,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 58 transitions. [2018-10-27 04:45:33,141 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 58 transitions. Word has length 15 [2018-10-27 04:45:33,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:33,142 INFO L481 AbstractCegarLoop]: Abstraction has 55 states and 58 transitions. [2018-10-27 04:45:33,142 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:45:33,142 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 58 transitions. [2018-10-27 04:45:33,142 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-10-27 04:45:33,142 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:33,142 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:33,143 INFO L424 AbstractCegarLoop]: === Iteration 3 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:33,143 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:33,143 INFO L82 PathProgramCache]: Analyzing trace with hash -213588543, now seen corresponding path program 1 times [2018-10-27 04:45:33,143 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:33,143 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:33,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:33,144 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:33,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:33,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:33,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:45:33,380 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:45:33,380 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 04:45:33,381 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-10-27 04:45:33,381 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-10-27 04:45:33,381 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-10-27 04:45:33,381 INFO L87 Difference]: Start difference. First operand 55 states and 58 transitions. Second operand 6 states. [2018-10-27 04:45:33,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:33,745 INFO L93 Difference]: Finished difference Result 106 states and 111 transitions. [2018-10-27 04:45:33,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-27 04:45:33,746 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 16 [2018-10-27 04:45:33,746 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:33,748 INFO L225 Difference]: With dead ends: 106 [2018-10-27 04:45:33,748 INFO L226 Difference]: Without dead ends: 106 [2018-10-27 04:45:33,749 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-10-27 04:45:33,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-10-27 04:45:33,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 72. [2018-10-27 04:45:33,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-10-27 04:45:33,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 80 transitions. [2018-10-27 04:45:33,757 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 80 transitions. Word has length 16 [2018-10-27 04:45:33,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:33,757 INFO L481 AbstractCegarLoop]: Abstraction has 72 states and 80 transitions. [2018-10-27 04:45:33,757 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-10-27 04:45:33,757 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 80 transitions. [2018-10-27 04:45:33,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-10-27 04:45:33,758 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:33,758 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:33,759 INFO L424 AbstractCegarLoop]: === Iteration 4 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:33,760 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:33,760 INFO L82 PathProgramCache]: Analyzing trace with hash 1968689806, now seen corresponding path program 1 times [2018-10-27 04:45:33,760 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:33,760 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:33,761 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:33,761 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:33,761 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:33,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:33,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:45:33,981 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:45:33,981 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-10-27 04:45:33,981 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-10-27 04:45:33,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-10-27 04:45:33,982 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:45:33,982 INFO L87 Difference]: Start difference. First operand 72 states and 80 transitions. Second operand 8 states. [2018-10-27 04:45:34,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:34,491 INFO L93 Difference]: Finished difference Result 90 states and 96 transitions. [2018-10-27 04:45:34,491 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:45:34,491 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 17 [2018-10-27 04:45:34,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:34,492 INFO L225 Difference]: With dead ends: 90 [2018-10-27 04:45:34,492 INFO L226 Difference]: Without dead ends: 90 [2018-10-27 04:45:34,493 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2018-10-27 04:45:34,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-10-27 04:45:34,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 72. [2018-10-27 04:45:34,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-10-27 04:45:34,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 79 transitions. [2018-10-27 04:45:34,497 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 79 transitions. Word has length 17 [2018-10-27 04:45:34,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:34,497 INFO L481 AbstractCegarLoop]: Abstraction has 72 states and 79 transitions. [2018-10-27 04:45:34,497 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-10-27 04:45:34,497 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 79 transitions. [2018-10-27 04:45:34,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-10-27 04:45:34,497 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:34,498 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:34,498 INFO L424 AbstractCegarLoop]: === Iteration 5 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:34,498 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:34,498 INFO L82 PathProgramCache]: Analyzing trace with hash 1968689805, now seen corresponding path program 1 times [2018-10-27 04:45:34,498 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:34,498 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:34,499 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:34,499 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:34,499 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:34,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:34,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:45:34,557 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:45:34,557 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-10-27 04:45:34,557 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-27 04:45:34,557 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 04:45:34,558 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:45:34,558 INFO L87 Difference]: Start difference. First operand 72 states and 79 transitions. Second operand 5 states. [2018-10-27 04:45:34,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:34,632 INFO L93 Difference]: Finished difference Result 71 states and 77 transitions. [2018-10-27 04:45:34,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-10-27 04:45:34,633 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-10-27 04:45:34,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:34,633 INFO L225 Difference]: With dead ends: 71 [2018-10-27 04:45:34,633 INFO L226 Difference]: Without dead ends: 71 [2018-10-27 04:45:34,634 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-10-27 04:45:34,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-10-27 04:45:34,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2018-10-27 04:45:34,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-10-27 04:45:34,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 77 transitions. [2018-10-27 04:45:34,639 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 77 transitions. Word has length 17 [2018-10-27 04:45:34,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:34,639 INFO L481 AbstractCegarLoop]: Abstraction has 71 states and 77 transitions. [2018-10-27 04:45:34,639 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-27 04:45:34,639 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 77 transitions. [2018-10-27 04:45:34,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-10-27 04:45:34,639 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:34,640 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:34,640 INFO L424 AbstractCegarLoop]: === Iteration 6 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:34,640 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:34,640 INFO L82 PathProgramCache]: Analyzing trace with hash -1835389063, now seen corresponding path program 1 times [2018-10-27 04:45:34,640 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:34,640 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:34,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:34,641 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:34,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:34,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:34,763 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:45:34,763 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:34,763 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:34,775 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:34,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:34,798 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:34,840 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:45:34,863 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:34,863 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 3] total 9 [2018-10-27 04:45:34,864 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-10-27 04:45:34,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-10-27 04:45:34,864 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-10-27 04:45:34,864 INFO L87 Difference]: Start difference. First operand 71 states and 77 transitions. Second operand 10 states. [2018-10-27 04:45:35,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:35,227 INFO L93 Difference]: Finished difference Result 111 states and 120 transitions. [2018-10-27 04:45:35,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:45:35,227 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 22 [2018-10-27 04:45:35,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:35,228 INFO L225 Difference]: With dead ends: 111 [2018-10-27 04:45:35,228 INFO L226 Difference]: Without dead ends: 111 [2018-10-27 04:45:35,229 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 20 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2018-10-27 04:45:35,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-10-27 04:45:35,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 82. [2018-10-27 04:45:35,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-10-27 04:45:35,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 89 transitions. [2018-10-27 04:45:35,241 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 89 transitions. Word has length 22 [2018-10-27 04:45:35,241 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:35,241 INFO L481 AbstractCegarLoop]: Abstraction has 82 states and 89 transitions. [2018-10-27 04:45:35,242 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-10-27 04:45:35,242 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 89 transitions. [2018-10-27 04:45:35,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-10-27 04:45:35,242 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:35,242 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:35,243 INFO L424 AbstractCegarLoop]: === Iteration 7 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:35,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:35,243 INFO L82 PathProgramCache]: Analyzing trace with hash 1339122636, now seen corresponding path program 1 times [2018-10-27 04:45:35,243 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:35,243 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:35,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:35,244 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:35,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:35,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:35,326 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:45:35,326 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:35,326 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:35,332 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:35,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:35,346 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:35,389 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 04:45:35,406 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:35,406 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2018-10-27 04:45:35,406 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-10-27 04:45:35,406 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-10-27 04:45:35,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-10-27 04:45:35,407 INFO L87 Difference]: Start difference. First operand 82 states and 89 transitions. Second operand 10 states. [2018-10-27 04:45:35,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:35,684 INFO L93 Difference]: Finished difference Result 119 states and 124 transitions. [2018-10-27 04:45:35,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-10-27 04:45:35,685 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 26 [2018-10-27 04:45:35,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:35,686 INFO L225 Difference]: With dead ends: 119 [2018-10-27 04:45:35,686 INFO L226 Difference]: Without dead ends: 110 [2018-10-27 04:45:35,687 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=50, Invalid=132, Unknown=0, NotChecked=0, Total=182 [2018-10-27 04:45:35,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-10-27 04:45:35,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 88. [2018-10-27 04:45:35,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-10-27 04:45:35,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 93 transitions. [2018-10-27 04:45:35,692 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 93 transitions. Word has length 26 [2018-10-27 04:45:35,692 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:35,692 INFO L481 AbstractCegarLoop]: Abstraction has 88 states and 93 transitions. [2018-10-27 04:45:35,692 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-10-27 04:45:35,693 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 93 transitions. [2018-10-27 04:45:35,693 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-10-27 04:45:35,693 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:35,693 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:35,694 INFO L424 AbstractCegarLoop]: === Iteration 8 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:35,694 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:35,694 INFO L82 PathProgramCache]: Analyzing trace with hash -1002444924, now seen corresponding path program 2 times [2018-10-27 04:45:35,694 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:35,694 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:35,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:35,695 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:35,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:35,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:35,765 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-27 04:45:35,766 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:45:35,766 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 04:45:35,766 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-10-27 04:45:35,766 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 04:45:35,766 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:45:35,767 INFO L87 Difference]: Start difference. First operand 88 states and 93 transitions. Second operand 3 states. [2018-10-27 04:45:35,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:35,806 INFO L93 Difference]: Finished difference Result 86 states and 91 transitions. [2018-10-27 04:45:35,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 04:45:35,807 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2018-10-27 04:45:35,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:35,808 INFO L225 Difference]: With dead ends: 86 [2018-10-27 04:45:35,808 INFO L226 Difference]: Without dead ends: 86 [2018-10-27 04:45:35,808 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 04:45:35,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states. [2018-10-27 04:45:35,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 86. [2018-10-27 04:45:35,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-10-27 04:45:35,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 91 transitions. [2018-10-27 04:45:35,815 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 91 transitions. Word has length 32 [2018-10-27 04:45:35,815 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:35,815 INFO L481 AbstractCegarLoop]: Abstraction has 86 states and 91 transitions. [2018-10-27 04:45:35,815 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-10-27 04:45:35,815 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 91 transitions. [2018-10-27 04:45:35,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-10-27 04:45:35,816 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:35,816 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:35,816 INFO L424 AbstractCegarLoop]: === Iteration 9 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:35,816 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:35,816 INFO L82 PathProgramCache]: Analyzing trace with hash -1002444923, now seen corresponding path program 1 times [2018-10-27 04:45:35,816 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:35,816 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:35,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:35,817 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:35,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:35,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:36,034 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-27 04:45:36,034 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 04:45:36,034 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 04:45:36,035 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-10-27 04:45:36,035 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-10-27 04:45:36,035 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-10-27 04:45:36,035 INFO L87 Difference]: Start difference. First operand 86 states and 91 transitions. Second operand 6 states. [2018-10-27 04:45:36,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:36,112 INFO L93 Difference]: Finished difference Result 96 states and 102 transitions. [2018-10-27 04:45:36,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-27 04:45:36,112 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 32 [2018-10-27 04:45:36,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:36,113 INFO L225 Difference]: With dead ends: 96 [2018-10-27 04:45:36,113 INFO L226 Difference]: Without dead ends: 96 [2018-10-27 04:45:36,114 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-10-27 04:45:36,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-10-27 04:45:36,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 89. [2018-10-27 04:45:36,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-10-27 04:45:36,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 94 transitions. [2018-10-27 04:45:36,119 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 94 transitions. Word has length 32 [2018-10-27 04:45:36,119 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:36,119 INFO L481 AbstractCegarLoop]: Abstraction has 89 states and 94 transitions. [2018-10-27 04:45:36,119 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-10-27 04:45:36,120 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 94 transitions. [2018-10-27 04:45:36,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-27 04:45:36,122 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:36,122 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:36,122 INFO L424 AbstractCegarLoop]: === Iteration 10 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:36,123 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:36,123 INFO L82 PathProgramCache]: Analyzing trace with hash -627429204, now seen corresponding path program 1 times [2018-10-27 04:45:36,123 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:36,123 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:36,124 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:36,124 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:36,124 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:36,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:36,167 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-27 04:45:36,167 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:36,167 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-10-27 04:45:36,187 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:36,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:36,229 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:36,241 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-27 04:45:36,260 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:36,260 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-10-27 04:45:36,260 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-10-27 04:45:36,260 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 04:45:36,261 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:45:36,261 INFO L87 Difference]: Start difference. First operand 89 states and 94 transitions. Second operand 5 states. [2018-10-27 04:45:36,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:36,311 INFO L93 Difference]: Finished difference Result 121 states and 127 transitions. [2018-10-27 04:45:36,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-10-27 04:45:36,312 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 45 [2018-10-27 04:45:36,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:36,313 INFO L225 Difference]: With dead ends: 121 [2018-10-27 04:45:36,313 INFO L226 Difference]: Without dead ends: 121 [2018-10-27 04:45:36,313 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-10-27 04:45:36,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-10-27 04:45:36,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 97. [2018-10-27 04:45:36,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-10-27 04:45:36,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 103 transitions. [2018-10-27 04:45:36,318 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 103 transitions. Word has length 45 [2018-10-27 04:45:36,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:36,318 INFO L481 AbstractCegarLoop]: Abstraction has 97 states and 103 transitions. [2018-10-27 04:45:36,318 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-10-27 04:45:36,318 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 103 transitions. [2018-10-27 04:45:36,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-27 04:45:36,319 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:36,319 INFO L375 BasicCegarLoop]: trace histogram [6, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:36,320 INFO L424 AbstractCegarLoop]: === Iteration 11 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:36,320 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:36,320 INFO L82 PathProgramCache]: Analyzing trace with hash -760332838, now seen corresponding path program 1 times [2018-10-27 04:45:36,323 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:36,323 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:36,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:36,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:36,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:36,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:36,441 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 39 proven. 13 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-27 04:45:36,441 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:36,441 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:36,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:36,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:36,498 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:36,616 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 42 proven. 10 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-27 04:45:36,632 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:36,632 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 12 [2018-10-27 04:45:36,633 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-10-27 04:45:36,633 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-10-27 04:45:36,633 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2018-10-27 04:45:36,633 INFO L87 Difference]: Start difference. First operand 97 states and 103 transitions. Second operand 12 states. [2018-10-27 04:45:36,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:36,869 INFO L93 Difference]: Finished difference Result 122 states and 127 transitions. [2018-10-27 04:45:36,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-10-27 04:45:36,870 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 57 [2018-10-27 04:45:36,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:36,871 INFO L225 Difference]: With dead ends: 122 [2018-10-27 04:45:36,871 INFO L226 Difference]: Without dead ends: 119 [2018-10-27 04:45:36,872 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=87, Invalid=219, Unknown=0, NotChecked=0, Total=306 [2018-10-27 04:45:36,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-10-27 04:45:36,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 97. [2018-10-27 04:45:36,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-10-27 04:45:36,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 102 transitions. [2018-10-27 04:45:36,874 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 102 transitions. Word has length 57 [2018-10-27 04:45:36,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:36,874 INFO L481 AbstractCegarLoop]: Abstraction has 97 states and 102 transitions. [2018-10-27 04:45:36,874 INFO L482 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-10-27 04:45:36,874 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 102 transitions. [2018-10-27 04:45:36,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-10-27 04:45:36,875 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:36,875 INFO L375 BasicCegarLoop]: trace histogram [7, 6, 6, 5, 5, 5, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:36,876 INFO L424 AbstractCegarLoop]: === Iteration 12 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:36,876 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:36,876 INFO L82 PathProgramCache]: Analyzing trace with hash -1440913935, now seen corresponding path program 1 times [2018-10-27 04:45:36,876 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:36,880 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:36,881 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:36,881 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:36,881 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:36,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:37,329 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 53 proven. 30 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-27 04:45:37,329 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:37,329 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:37,335 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:37,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:37,354 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:37,427 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 83 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-27 04:45:37,444 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:37,444 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 9] total 16 [2018-10-27 04:45:37,444 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-10-27 04:45:37,445 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-10-27 04:45:37,445 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=196, Unknown=0, NotChecked=0, Total=240 [2018-10-27 04:45:37,445 INFO L87 Difference]: Start difference. First operand 97 states and 102 transitions. Second operand 16 states. [2018-10-27 04:45:38,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:38,004 INFO L93 Difference]: Finished difference Result 165 states and 170 transitions. [2018-10-27 04:45:38,005 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-10-27 04:45:38,005 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 60 [2018-10-27 04:45:38,005 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:38,006 INFO L225 Difference]: With dead ends: 165 [2018-10-27 04:45:38,006 INFO L226 Difference]: Without dead ends: 165 [2018-10-27 04:45:38,006 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 53 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 132 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=155, Invalid=601, Unknown=0, NotChecked=0, Total=756 [2018-10-27 04:45:38,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-10-27 04:45:38,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 134. [2018-10-27 04:45:38,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-10-27 04:45:38,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 140 transitions. [2018-10-27 04:45:38,010 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 140 transitions. Word has length 60 [2018-10-27 04:45:38,010 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:38,010 INFO L481 AbstractCegarLoop]: Abstraction has 134 states and 140 transitions. [2018-10-27 04:45:38,010 INFO L482 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-10-27 04:45:38,010 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 140 transitions. [2018-10-27 04:45:38,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-10-27 04:45:38,011 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:38,011 INFO L375 BasicCegarLoop]: trace histogram [7, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:38,012 INFO L424 AbstractCegarLoop]: === Iteration 13 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:38,012 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:38,015 INFO L82 PathProgramCache]: Analyzing trace with hash 1883390930, now seen corresponding path program 2 times [2018-10-27 04:45:38,015 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:38,015 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:38,015 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:38,016 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:38,016 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:38,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:38,152 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2018-10-27 04:45:38,152 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:38,152 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:38,159 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:45:38,192 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:45:38,193 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:45:38,195 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:38,226 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:45:38,227 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:38,233 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:45:38,233 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:38,240 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:45:38,241 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:14 [2018-10-27 04:45:38,254 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:45:38,254 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:45:38,255 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-10-27 04:45:38,255 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:38,262 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:45:38,263 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-10-27 04:45:38,264 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:38,270 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:45:38,270 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:25, output treesize:14 [2018-10-27 04:45:38,482 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-10-27 04:45:38,500 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:38,500 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-10-27 04:45:38,501 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-10-27 04:45:38,501 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-10-27 04:45:38,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2018-10-27 04:45:38,502 INFO L87 Difference]: Start difference. First operand 134 states and 140 transitions. Second operand 13 states. [2018-10-27 04:45:38,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:38,664 INFO L93 Difference]: Finished difference Result 147 states and 154 transitions. [2018-10-27 04:45:38,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-10-27 04:45:38,664 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 63 [2018-10-27 04:45:38,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:38,665 INFO L225 Difference]: With dead ends: 147 [2018-10-27 04:45:38,665 INFO L226 Difference]: Without dead ends: 147 [2018-10-27 04:45:38,666 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 59 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=69, Invalid=203, Unknown=0, NotChecked=0, Total=272 [2018-10-27 04:45:38,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-10-27 04:45:38,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 137. [2018-10-27 04:45:38,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-10-27 04:45:38,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 143 transitions. [2018-10-27 04:45:38,669 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 143 transitions. Word has length 63 [2018-10-27 04:45:38,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:38,669 INFO L481 AbstractCegarLoop]: Abstraction has 137 states and 143 transitions. [2018-10-27 04:45:38,669 INFO L482 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-10-27 04:45:38,669 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 143 transitions. [2018-10-27 04:45:38,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-10-27 04:45:38,671 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:38,671 INFO L375 BasicCegarLoop]: trace histogram [7, 5, 5, 5, 5, 5, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:38,671 INFO L424 AbstractCegarLoop]: === Iteration 14 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:38,671 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:38,671 INFO L82 PathProgramCache]: Analyzing trace with hash -206109032, now seen corresponding path program 1 times [2018-10-27 04:45:38,672 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:38,672 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:38,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:38,677 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:38,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:38,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:38,867 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 51 proven. 26 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-10-27 04:45:38,868 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:38,868 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:38,878 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:38,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:38,909 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:38,994 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-10-27 04:45:39,011 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:39,011 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 5] total 13 [2018-10-27 04:45:39,011 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-10-27 04:45:39,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-10-27 04:45:39,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=121, Unknown=0, NotChecked=0, Total=156 [2018-10-27 04:45:39,012 INFO L87 Difference]: Start difference. First operand 137 states and 143 transitions. Second operand 13 states. [2018-10-27 04:45:39,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:39,237 INFO L93 Difference]: Finished difference Result 153 states and 160 transitions. [2018-10-27 04:45:39,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-10-27 04:45:39,238 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 78 [2018-10-27 04:45:39,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:39,239 INFO L225 Difference]: With dead ends: 153 [2018-10-27 04:45:39,239 INFO L226 Difference]: Without dead ends: 153 [2018-10-27 04:45:39,239 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 78 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=104, Invalid=358, Unknown=0, NotChecked=0, Total=462 [2018-10-27 04:45:39,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-10-27 04:45:39,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 110. [2018-10-27 04:45:39,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-10-27 04:45:39,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 113 transitions. [2018-10-27 04:45:39,243 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 113 transitions. Word has length 78 [2018-10-27 04:45:39,244 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:39,244 INFO L481 AbstractCegarLoop]: Abstraction has 110 states and 113 transitions. [2018-10-27 04:45:39,244 INFO L482 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-10-27 04:45:39,244 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 113 transitions. [2018-10-27 04:45:39,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-10-27 04:45:39,245 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:39,245 INFO L375 BasicCegarLoop]: trace histogram [11, 8, 8, 8, 8, 8, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:39,245 INFO L424 AbstractCegarLoop]: === Iteration 15 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:39,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:39,245 INFO L82 PathProgramCache]: Analyzing trace with hash 293051877, now seen corresponding path program 3 times [2018-10-27 04:45:39,246 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:39,246 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:39,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:39,246 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:39,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:39,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:39,373 INFO L134 CoverageAnalysis]: Checked inductivity of 251 backedges. 121 proven. 114 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-27 04:45:39,373 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:39,373 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:39,381 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:45:39,394 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-10-27 04:45:39,395 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:45:39,397 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:39,407 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:45:39,407 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:39,412 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:45:39,412 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:39,429 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:45:39,429 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:14 [2018-10-27 04:45:39,443 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:45:39,444 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:45:39,444 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-10-27 04:45:39,445 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:39,453 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:45:39,454 INFO L700 Elim1Store]: detected not equals via solver [2018-10-27 04:45:39,455 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-10-27 04:45:39,455 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:39,459 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:45:39,459 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:25, output treesize:14 [2018-10-27 04:45:39,917 INFO L134 CoverageAnalysis]: Checked inductivity of 251 backedges. 8 proven. 4 refuted. 0 times theorem prover too weak. 239 trivial. 0 not checked. [2018-10-27 04:45:39,935 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:39,935 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 8] total 21 [2018-10-27 04:45:39,935 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-10-27 04:45:39,936 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-10-27 04:45:39,936 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=356, Unknown=0, NotChecked=0, Total=420 [2018-10-27 04:45:39,936 INFO L87 Difference]: Start difference. First operand 110 states and 113 transitions. Second operand 21 states. [2018-10-27 04:45:40,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:40,559 INFO L93 Difference]: Finished difference Result 126 states and 128 transitions. [2018-10-27 04:45:40,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-10-27 04:45:40,559 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 94 [2018-10-27 04:45:40,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:40,560 INFO L225 Difference]: With dead ends: 126 [2018-10-27 04:45:40,560 INFO L226 Difference]: Without dead ends: 107 [2018-10-27 04:45:40,561 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 127 GetRequests, 85 SyntacticMatches, 4 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 340 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=265, Invalid=1295, Unknown=0, NotChecked=0, Total=1560 [2018-10-27 04:45:40,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-10-27 04:45:40,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 101. [2018-10-27 04:45:40,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-10-27 04:45:40,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 102 transitions. [2018-10-27 04:45:40,564 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 102 transitions. Word has length 94 [2018-10-27 04:45:40,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:40,564 INFO L481 AbstractCegarLoop]: Abstraction has 101 states and 102 transitions. [2018-10-27 04:45:40,566 INFO L482 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-10-27 04:45:40,566 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 102 transitions. [2018-10-27 04:45:40,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-10-27 04:45:40,567 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:40,567 INFO L375 BasicCegarLoop]: trace histogram [12, 10, 10, 9, 9, 9, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:40,568 INFO L424 AbstractCegarLoop]: === Iteration 16 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:40,568 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:40,568 INFO L82 PathProgramCache]: Analyzing trace with hash 912066054, now seen corresponding path program 2 times [2018-10-27 04:45:40,568 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:40,568 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:40,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:40,569 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:40,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:40,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:41,309 INFO L134 CoverageAnalysis]: Checked inductivity of 313 backedges. 203 proven. 24 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-10-27 04:45:41,310 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:41,310 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:41,316 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:45:41,337 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:45:41,337 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:45:41,339 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:41,430 INFO L134 CoverageAnalysis]: Checked inductivity of 313 backedges. 214 proven. 13 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-10-27 04:45:41,447 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:41,447 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11] total 18 [2018-10-27 04:45:41,448 INFO L460 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-10-27 04:45:41,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-10-27 04:45:41,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=227, Unknown=0, NotChecked=0, Total=306 [2018-10-27 04:45:41,448 INFO L87 Difference]: Start difference. First operand 101 states and 102 transitions. Second operand 18 states. [2018-10-27 04:45:41,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:41,821 INFO L93 Difference]: Finished difference Result 142 states and 143 transitions. [2018-10-27 04:45:41,821 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-10-27 04:45:41,822 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 97 [2018-10-27 04:45:41,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:41,822 INFO L225 Difference]: With dead ends: 142 [2018-10-27 04:45:41,822 INFO L226 Difference]: Without dead ends: 142 [2018-10-27 04:45:41,823 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 92 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=174, Invalid=426, Unknown=0, NotChecked=0, Total=600 [2018-10-27 04:45:41,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-10-27 04:45:41,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 138. [2018-10-27 04:45:41,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-10-27 04:45:41,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 139 transitions. [2018-10-27 04:45:41,827 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 139 transitions. Word has length 97 [2018-10-27 04:45:41,827 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:41,827 INFO L481 AbstractCegarLoop]: Abstraction has 138 states and 139 transitions. [2018-10-27 04:45:41,827 INFO L482 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-10-27 04:45:41,828 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 139 transitions. [2018-10-27 04:45:41,828 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-10-27 04:45:41,829 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:41,829 INFO L375 BasicCegarLoop]: trace histogram [17, 14, 14, 13, 13, 13, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:41,829 INFO L424 AbstractCegarLoop]: === Iteration 17 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:41,829 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:41,829 INFO L82 PathProgramCache]: Analyzing trace with hash 1395146513, now seen corresponding path program 3 times [2018-10-27 04:45:41,829 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:41,829 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:41,830 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:41,830 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:41,830 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:41,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:42,079 INFO L134 CoverageAnalysis]: Checked inductivity of 655 backedges. 285 proven. 58 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-10-27 04:45:42,079 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:42,079 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:42,097 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:45:42,140 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-10-27 04:45:42,140 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:45:42,142 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:42,146 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:45:42,146 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:42,149 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:45:42,150 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:45:42,338 INFO L134 CoverageAnalysis]: Checked inductivity of 655 backedges. 285 proven. 38 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-10-27 04:45:42,354 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:42,355 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 14 [2018-10-27 04:45:42,355 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-10-27 04:45:42,355 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-10-27 04:45:42,355 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=151, Unknown=0, NotChecked=0, Total=210 [2018-10-27 04:45:42,355 INFO L87 Difference]: Start difference. First operand 138 states and 139 transitions. Second operand 15 states. [2018-10-27 04:45:42,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:42,498 INFO L93 Difference]: Finished difference Result 181 states and 183 transitions. [2018-10-27 04:45:42,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-10-27 04:45:42,499 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 134 [2018-10-27 04:45:42,500 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:42,500 INFO L225 Difference]: With dead ends: 181 [2018-10-27 04:45:42,500 INFO L226 Difference]: Without dead ends: 181 [2018-10-27 04:45:42,500 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 123 SyntacticMatches, 9 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 155 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=76, Invalid=196, Unknown=0, NotChecked=0, Total=272 [2018-10-27 04:45:42,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-10-27 04:45:42,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 175. [2018-10-27 04:45:42,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2018-10-27 04:45:42,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 177 transitions. [2018-10-27 04:45:42,503 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 177 transitions. Word has length 134 [2018-10-27 04:45:42,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:42,503 INFO L481 AbstractCegarLoop]: Abstraction has 175 states and 177 transitions. [2018-10-27 04:45:42,503 INFO L482 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-10-27 04:45:42,504 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 177 transitions. [2018-10-27 04:45:42,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 172 [2018-10-27 04:45:42,509 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:42,509 INFO L375 BasicCegarLoop]: trace histogram [22, 18, 18, 17, 17, 17, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:42,509 INFO L424 AbstractCegarLoop]: === Iteration 18 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:42,509 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:42,509 INFO L82 PathProgramCache]: Analyzing trace with hash 2091475174, now seen corresponding path program 4 times [2018-10-27 04:45:42,509 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:42,509 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:42,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:42,510 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:42,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:42,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:43,152 INFO L134 CoverageAnalysis]: Checked inductivity of 1122 backedges. 777 proven. 189 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-10-27 04:45:43,152 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:43,152 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:43,161 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:45:43,191 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:45:43,191 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:45:43,193 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:43,299 INFO L134 CoverageAnalysis]: Checked inductivity of 1122 backedges. 735 proven. 44 refuted. 0 times theorem prover too weak. 343 trivial. 0 not checked. [2018-10-27 04:45:43,315 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:43,315 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 12] total 23 [2018-10-27 04:45:43,315 INFO L460 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-10-27 04:45:43,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-10-27 04:45:43,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=412, Unknown=0, NotChecked=0, Total=506 [2018-10-27 04:45:43,316 INFO L87 Difference]: Start difference. First operand 175 states and 177 transitions. Second operand 23 states. [2018-10-27 04:45:43,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:43,693 INFO L93 Difference]: Finished difference Result 200 states and 202 transitions. [2018-10-27 04:45:43,694 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-10-27 04:45:43,695 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 171 [2018-10-27 04:45:43,695 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:43,696 INFO L225 Difference]: With dead ends: 200 [2018-10-27 04:45:43,696 INFO L226 Difference]: Without dead ends: 194 [2018-10-27 04:45:43,696 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 201 GetRequests, 167 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 255 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=263, Invalid=997, Unknown=0, NotChecked=0, Total=1260 [2018-10-27 04:45:43,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states. [2018-10-27 04:45:43,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 185. [2018-10-27 04:45:43,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-10-27 04:45:43,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 187 transitions. [2018-10-27 04:45:43,700 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 187 transitions. Word has length 171 [2018-10-27 04:45:43,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:43,702 INFO L481 AbstractCegarLoop]: Abstraction has 185 states and 187 transitions. [2018-10-27 04:45:43,702 INFO L482 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-10-27 04:45:43,702 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 187 transitions. [2018-10-27 04:45:43,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 178 [2018-10-27 04:45:43,703 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:43,704 INFO L375 BasicCegarLoop]: trace histogram [23, 19, 19, 18, 18, 18, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:43,704 INFO L424 AbstractCegarLoop]: === Iteration 19 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:43,704 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:43,704 INFO L82 PathProgramCache]: Analyzing trace with hash -1551472930, now seen corresponding path program 5 times [2018-10-27 04:45:43,704 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:43,704 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:43,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:43,705 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:43,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:43,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:43,928 INFO L134 CoverageAnalysis]: Checked inductivity of 1236 backedges. 436 proven. 52 refuted. 0 times theorem prover too weak. 748 trivial. 0 not checked. [2018-10-27 04:45:43,928 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:43,928 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:43,938 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:45:44,000 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-10-27 04:45:44,000 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:45:44,005 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:44,019 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:45:44,020 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:44,035 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:45:44,035 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:45:44,299 INFO L134 CoverageAnalysis]: Checked inductivity of 1236 backedges. 436 proven. 52 refuted. 0 times theorem prover too weak. 748 trivial. 0 not checked. [2018-10-27 04:45:44,315 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:44,315 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10] total 15 [2018-10-27 04:45:44,315 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-10-27 04:45:44,316 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-10-27 04:45:44,316 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=167, Unknown=0, NotChecked=0, Total=240 [2018-10-27 04:45:44,316 INFO L87 Difference]: Start difference. First operand 185 states and 187 transitions. Second operand 16 states. [2018-10-27 04:45:44,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:44,472 INFO L93 Difference]: Finished difference Result 193 states and 195 transitions. [2018-10-27 04:45:44,472 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-10-27 04:45:44,472 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 177 [2018-10-27 04:45:44,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:44,473 INFO L225 Difference]: With dead ends: 193 [2018-10-27 04:45:44,473 INFO L226 Difference]: Without dead ends: 193 [2018-10-27 04:45:44,474 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 191 GetRequests, 161 SyntacticMatches, 11 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 99 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=118, Invalid=302, Unknown=0, NotChecked=0, Total=420 [2018-10-27 04:45:44,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states. [2018-10-27 04:45:44,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 187. [2018-10-27 04:45:44,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-10-27 04:45:44,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 189 transitions. [2018-10-27 04:45:44,478 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 189 transitions. Word has length 177 [2018-10-27 04:45:44,478 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:44,478 INFO L481 AbstractCegarLoop]: Abstraction has 187 states and 189 transitions. [2018-10-27 04:45:44,478 INFO L482 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-10-27 04:45:44,478 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 189 transitions. [2018-10-27 04:45:44,479 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2018-10-27 04:45:44,480 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:44,480 INFO L375 BasicCegarLoop]: trace histogram [24, 20, 20, 19, 19, 19, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:44,480 INFO L424 AbstractCegarLoop]: === Iteration 20 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:44,484 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:44,485 INFO L82 PathProgramCache]: Analyzing trace with hash -1232218074, now seen corresponding path program 6 times [2018-10-27 04:45:44,485 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:44,485 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:44,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:44,485 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:44,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:44,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:44,798 INFO L134 CoverageAnalysis]: Checked inductivity of 1356 backedges. 528 proven. 80 refuted. 0 times theorem prover too weak. 748 trivial. 0 not checked. [2018-10-27 04:45:44,799 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:44,799 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:44,805 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-10-27 04:45:44,851 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-10-27 04:45:44,852 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:45:44,854 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:44,856 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:45:44,856 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:44,859 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:45:44,859 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:45:45,276 INFO L134 CoverageAnalysis]: Checked inductivity of 1356 backedges. 705 proven. 246 refuted. 0 times theorem prover too weak. 405 trivial. 0 not checked. [2018-10-27 04:45:45,292 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:45,292 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 17] total 23 [2018-10-27 04:45:45,293 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-10-27 04:45:45,293 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-10-27 04:45:45,293 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=450, Unknown=0, NotChecked=0, Total=552 [2018-10-27 04:45:45,293 INFO L87 Difference]: Start difference. First operand 187 states and 189 transitions. Second operand 24 states. [2018-10-27 04:45:46,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:46,620 INFO L93 Difference]: Finished difference Result 262 states and 269 transitions. [2018-10-27 04:45:46,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-10-27 04:45:46,621 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 183 [2018-10-27 04:45:46,621 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:46,622 INFO L225 Difference]: With dead ends: 262 [2018-10-27 04:45:46,622 INFO L226 Difference]: Without dead ends: 262 [2018-10-27 04:45:46,623 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 234 GetRequests, 162 SyntacticMatches, 10 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1318 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=876, Invalid=3156, Unknown=0, NotChecked=0, Total=4032 [2018-10-27 04:45:46,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262 states. [2018-10-27 04:45:46,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262 to 245. [2018-10-27 04:45:46,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245 states. [2018-10-27 04:45:46,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 251 transitions. [2018-10-27 04:45:46,628 INFO L78 Accepts]: Start accepts. Automaton has 245 states and 251 transitions. Word has length 183 [2018-10-27 04:45:46,628 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:46,628 INFO L481 AbstractCegarLoop]: Abstraction has 245 states and 251 transitions. [2018-10-27 04:45:46,628 INFO L482 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-10-27 04:45:46,628 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 251 transitions. [2018-10-27 04:45:46,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 239 [2018-10-27 04:45:46,633 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:46,633 INFO L375 BasicCegarLoop]: trace histogram [32, 27, 27, 26, 26, 26, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:46,634 INFO L424 AbstractCegarLoop]: === Iteration 21 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:46,634 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:46,634 INFO L82 PathProgramCache]: Analyzing trace with hash 691291833, now seen corresponding path program 7 times [2018-10-27 04:45:46,634 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:46,634 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:46,635 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:46,635 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:46,635 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:46,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:46,876 INFO L134 CoverageAnalysis]: Checked inductivity of 2474 backedges. 875 proven. 114 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-10-27 04:45:46,877 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:46,877 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:46,883 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:46,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:46,935 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:46,964 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:45:46,965 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:46,967 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:45:46,968 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:45:47,308 INFO L134 CoverageAnalysis]: Checked inductivity of 2474 backedges. 875 proven. 114 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-10-27 04:45:47,324 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:47,325 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 18 [2018-10-27 04:45:47,325 INFO L460 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-10-27 04:45:47,325 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-10-27 04:45:47,325 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=241, Unknown=0, NotChecked=0, Total=342 [2018-10-27 04:45:47,325 INFO L87 Difference]: Start difference. First operand 245 states and 251 transitions. Second operand 19 states. [2018-10-27 04:45:47,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:47,603 INFO L93 Difference]: Finished difference Result 291 states and 301 transitions. [2018-10-27 04:45:47,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-10-27 04:45:47,604 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 238 [2018-10-27 04:45:47,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:47,605 INFO L225 Difference]: With dead ends: 291 [2018-10-27 04:45:47,605 INFO L226 Difference]: Without dead ends: 291 [2018-10-27 04:45:47,605 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 219 SyntacticMatches, 13 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=170, Invalid=480, Unknown=0, NotChecked=0, Total=650 [2018-10-27 04:45:47,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states. [2018-10-27 04:45:47,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 251. [2018-10-27 04:45:47,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 251 states. [2018-10-27 04:45:47,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 251 states to 251 states and 258 transitions. [2018-10-27 04:45:47,611 INFO L78 Accepts]: Start accepts. Automaton has 251 states and 258 transitions. Word has length 238 [2018-10-27 04:45:47,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:47,611 INFO L481 AbstractCegarLoop]: Abstraction has 251 states and 258 transitions. [2018-10-27 04:45:47,611 INFO L482 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-10-27 04:45:47,611 INFO L276 IsEmpty]: Start isEmpty. Operand 251 states and 258 transitions. [2018-10-27 04:45:47,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 245 [2018-10-27 04:45:47,616 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:47,616 INFO L375 BasicCegarLoop]: trace histogram [33, 28, 28, 27, 27, 27, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:47,616 INFO L424 AbstractCegarLoop]: === Iteration 22 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:47,617 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:47,617 INFO L82 PathProgramCache]: Analyzing trace with hash 1426925505, now seen corresponding path program 8 times [2018-10-27 04:45:47,617 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:47,617 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:47,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:47,617 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:45:47,618 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:47,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:48,053 INFO L134 CoverageAnalysis]: Checked inductivity of 2644 backedges. 1005 proven. 154 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-10-27 04:45:48,053 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:48,053 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:48,059 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:45:48,115 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:45:48,115 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:45:48,118 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:48,542 INFO L134 CoverageAnalysis]: Checked inductivity of 2644 backedges. 1159 proven. 85 refuted. 0 times theorem prover too weak. 1400 trivial. 0 not checked. [2018-10-27 04:45:48,558 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:48,558 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 17] total 28 [2018-10-27 04:45:48,559 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-10-27 04:45:48,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-10-27 04:45:48,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=630, Unknown=0, NotChecked=0, Total=756 [2018-10-27 04:45:48,559 INFO L87 Difference]: Start difference. First operand 251 states and 258 transitions. Second operand 28 states. [2018-10-27 04:45:50,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:50,240 INFO L93 Difference]: Finished difference Result 439 states and 458 transitions. [2018-10-27 04:45:50,242 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-10-27 04:45:50,242 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 244 [2018-10-27 04:45:50,242 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:50,243 INFO L225 Difference]: With dead ends: 439 [2018-10-27 04:45:50,244 INFO L226 Difference]: Without dead ends: 439 [2018-10-27 04:45:50,244 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 282 GetRequests, 229 SyntacticMatches, 1 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 654 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=487, Invalid=2375, Unknown=0, NotChecked=0, Total=2862 [2018-10-27 04:45:50,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 439 states. [2018-10-27 04:45:50,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 439 to 389. [2018-10-27 04:45:50,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389 states. [2018-10-27 04:45:50,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 405 transitions. [2018-10-27 04:45:50,252 INFO L78 Accepts]: Start accepts. Automaton has 389 states and 405 transitions. Word has length 244 [2018-10-27 04:45:50,253 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:50,253 INFO L481 AbstractCegarLoop]: Abstraction has 389 states and 405 transitions. [2018-10-27 04:45:50,253 INFO L482 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-10-27 04:45:50,253 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 405 transitions. [2018-10-27 04:45:50,254 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 294 [2018-10-27 04:45:50,254 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:50,255 INFO L375 BasicCegarLoop]: trace histogram [40, 34, 34, 33, 33, 33, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:50,255 INFO L424 AbstractCegarLoop]: === Iteration 23 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:50,255 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:50,255 INFO L82 PathProgramCache]: Analyzing trace with hash -1118632426, now seen corresponding path program 9 times [2018-10-27 04:45:50,255 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:50,255 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:50,256 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:50,261 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:50,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:50,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:50,970 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 1980 proven. 740 refuted. 0 times theorem prover too weak. 1207 trivial. 0 not checked. [2018-10-27 04:45:50,970 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:50,971 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:50,977 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:45:51,059 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-10-27 04:45:51,059 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:45:51,063 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:51,068 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:45:51,069 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:45:51,072 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:45:51,072 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:45:51,790 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 1929 proven. 448 refuted. 0 times theorem prover too weak. 1550 trivial. 0 not checked. [2018-10-27 04:45:51,817 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:51,817 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17] total 34 [2018-10-27 04:45:51,817 INFO L460 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-10-27 04:45:51,818 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-10-27 04:45:51,818 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=149, Invalid=973, Unknown=0, NotChecked=0, Total=1122 [2018-10-27 04:45:51,818 INFO L87 Difference]: Start difference. First operand 389 states and 405 transitions. Second operand 34 states. [2018-10-27 04:45:53,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:53,225 INFO L93 Difference]: Finished difference Result 544 states and 558 transitions. [2018-10-27 04:45:53,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-10-27 04:45:53,226 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 293 [2018-10-27 04:45:53,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:53,228 INFO L225 Difference]: With dead ends: 544 [2018-10-27 04:45:53,228 INFO L226 Difference]: Without dead ends: 532 [2018-10-27 04:45:53,229 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 353 GetRequests, 269 SyntacticMatches, 10 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1699 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=942, Invalid=4758, Unknown=0, NotChecked=0, Total=5700 [2018-10-27 04:45:53,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states. [2018-10-27 04:45:53,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 391. [2018-10-27 04:45:53,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 391 states. [2018-10-27 04:45:53,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 391 states and 400 transitions. [2018-10-27 04:45:53,238 INFO L78 Accepts]: Start accepts. Automaton has 391 states and 400 transitions. Word has length 293 [2018-10-27 04:45:53,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:53,238 INFO L481 AbstractCegarLoop]: Abstraction has 391 states and 400 transitions. [2018-10-27 04:45:53,239 INFO L482 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-10-27 04:45:53,239 INFO L276 IsEmpty]: Start isEmpty. Operand 391 states and 400 transitions. [2018-10-27 04:45:53,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 306 [2018-10-27 04:45:53,243 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:53,243 INFO L375 BasicCegarLoop]: trace histogram [42, 36, 36, 35, 35, 35, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:53,243 INFO L424 AbstractCegarLoop]: === Iteration 24 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:53,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:53,244 INFO L82 PathProgramCache]: Analyzing trace with hash 1230888790, now seen corresponding path program 10 times [2018-10-27 04:45:53,244 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:53,244 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:53,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:53,244 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:53,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:53,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:53,590 INFO L134 CoverageAnalysis]: Checked inductivity of 4361 backedges. 1695 proven. 146 refuted. 0 times theorem prover too weak. 2520 trivial. 0 not checked. [2018-10-27 04:45:53,590 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:53,590 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:53,597 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:45:53,644 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:45:53,644 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:45:53,649 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:54,953 INFO L134 CoverageAnalysis]: Checked inductivity of 4361 backedges. 1718 proven. 123 refuted. 0 times theorem prover too weak. 2520 trivial. 0 not checked. [2018-10-27 04:45:54,969 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:54,970 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 19] total 30 [2018-10-27 04:45:54,970 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-10-27 04:45:54,970 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-10-27 04:45:54,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=211, Invalid=659, Unknown=0, NotChecked=0, Total=870 [2018-10-27 04:45:54,971 INFO L87 Difference]: Start difference. First operand 391 states and 400 transitions. Second operand 30 states. [2018-10-27 04:45:55,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:55,967 INFO L93 Difference]: Finished difference Result 542 states and 555 transitions. [2018-10-27 04:45:55,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-10-27 04:45:55,968 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 305 [2018-10-27 04:45:55,969 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:55,970 INFO L225 Difference]: With dead ends: 542 [2018-10-27 04:45:55,970 INFO L226 Difference]: Without dead ends: 542 [2018-10-27 04:45:55,970 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 339 GetRequests, 296 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 293 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=538, Invalid=1442, Unknown=0, NotChecked=0, Total=1980 [2018-10-27 04:45:55,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 542 states. [2018-10-27 04:45:55,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 542 to 452. [2018-10-27 04:45:55,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 452 states. [2018-10-27 04:45:55,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 452 states to 452 states and 463 transitions. [2018-10-27 04:45:55,978 INFO L78 Accepts]: Start accepts. Automaton has 452 states and 463 transitions. Word has length 305 [2018-10-27 04:45:55,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:55,978 INFO L481 AbstractCegarLoop]: Abstraction has 452 states and 463 transitions. [2018-10-27 04:45:55,978 INFO L482 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-10-27 04:45:55,978 INFO L276 IsEmpty]: Start isEmpty. Operand 452 states and 463 transitions. [2018-10-27 04:45:55,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 355 [2018-10-27 04:45:55,980 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:55,980 INFO L375 BasicCegarLoop]: trace histogram [49, 42, 42, 41, 41, 41, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:55,984 INFO L424 AbstractCegarLoop]: === Iteration 25 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:55,984 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:55,985 INFO L82 PathProgramCache]: Analyzing trace with hash -1209033951, now seen corresponding path program 11 times [2018-10-27 04:45:55,985 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:55,985 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:55,985 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:55,985 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:55,985 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:56,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:56,295 INFO L134 CoverageAnalysis]: Checked inductivity of 5973 backedges. 2777 proven. 1019 refuted. 0 times theorem prover too weak. 2177 trivial. 0 not checked. [2018-10-27 04:45:56,295 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:56,295 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:56,301 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:45:56,413 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 20 check-sat command(s) [2018-10-27 04:45:56,413 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:45:56,418 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:56,632 INFO L134 CoverageAnalysis]: Checked inductivity of 5973 backedges. 3663 proven. 580 refuted. 0 times theorem prover too weak. 1730 trivial. 0 not checked. [2018-10-27 04:45:56,649 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:56,649 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 30 [2018-10-27 04:45:56,650 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-10-27 04:45:56,651 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-10-27 04:45:56,651 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=158, Invalid=712, Unknown=0, NotChecked=0, Total=870 [2018-10-27 04:45:56,651 INFO L87 Difference]: Start difference. First operand 452 states and 463 transitions. Second operand 30 states. [2018-10-27 04:45:57,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:57,022 INFO L93 Difference]: Finished difference Result 406 states and 412 transitions. [2018-10-27 04:45:57,022 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-10-27 04:45:57,023 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 354 [2018-10-27 04:45:57,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:57,024 INFO L225 Difference]: With dead ends: 406 [2018-10-27 04:45:57,024 INFO L226 Difference]: Without dead ends: 397 [2018-10-27 04:45:57,025 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 390 GetRequests, 346 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 478 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=468, Invalid=1602, Unknown=0, NotChecked=0, Total=2070 [2018-10-27 04:45:57,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 397 states. [2018-10-27 04:45:57,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 397 to 388. [2018-10-27 04:45:57,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 388 states. [2018-10-27 04:45:57,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 388 states to 388 states and 394 transitions. [2018-10-27 04:45:57,032 INFO L78 Accepts]: Start accepts. Automaton has 388 states and 394 transitions. Word has length 354 [2018-10-27 04:45:57,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:57,033 INFO L481 AbstractCegarLoop]: Abstraction has 388 states and 394 transitions. [2018-10-27 04:45:57,033 INFO L482 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-10-27 04:45:57,033 INFO L276 IsEmpty]: Start isEmpty. Operand 388 states and 394 transitions. [2018-10-27 04:45:57,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 361 [2018-10-27 04:45:57,037 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:57,037 INFO L375 BasicCegarLoop]: trace histogram [50, 43, 43, 42, 42, 42, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:57,037 INFO L424 AbstractCegarLoop]: === Iteration 26 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:57,038 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:57,038 INFO L82 PathProgramCache]: Analyzing trace with hash -541898711, now seen corresponding path program 12 times [2018-10-27 04:45:57,038 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:57,038 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:57,038 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:57,039 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:57,039 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:57,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:45:57,370 INFO L134 CoverageAnalysis]: Checked inductivity of 6237 backedges. 3273 proven. 794 refuted. 0 times theorem prover too weak. 2170 trivial. 0 not checked. [2018-10-27 04:45:57,371 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:45:57,371 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:45:57,378 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-10-27 04:45:57,586 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 17 check-sat command(s) [2018-10-27 04:45:57,586 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:45:57,590 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:45:57,929 INFO L134 CoverageAnalysis]: Checked inductivity of 6237 backedges. 3080 proven. 508 refuted. 0 times theorem prover too weak. 2649 trivial. 0 not checked. [2018-10-27 04:45:57,947 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:45:57,947 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 23] total 42 [2018-10-27 04:45:57,947 INFO L460 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-10-27 04:45:57,948 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-10-27 04:45:57,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=236, Invalid=1486, Unknown=0, NotChecked=0, Total=1722 [2018-10-27 04:45:57,948 INFO L87 Difference]: Start difference. First operand 388 states and 394 transitions. Second operand 42 states. [2018-10-27 04:45:58,497 WARN L179 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 15 DAG size of output: 12 [2018-10-27 04:45:59,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:45:59,569 INFO L93 Difference]: Finished difference Result 409 states and 413 transitions. [2018-10-27 04:45:59,570 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-10-27 04:45:59,570 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 360 [2018-10-27 04:45:59,571 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:45:59,571 INFO L225 Difference]: With dead ends: 409 [2018-10-27 04:45:59,571 INFO L226 Difference]: Without dead ends: 403 [2018-10-27 04:45:59,573 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 423 GetRequests, 342 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2041 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1017, Invalid=5789, Unknown=0, NotChecked=0, Total=6806 [2018-10-27 04:45:59,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 403 states. [2018-10-27 04:45:59,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 403 to 388. [2018-10-27 04:45:59,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 388 states. [2018-10-27 04:45:59,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 388 states to 388 states and 392 transitions. [2018-10-27 04:45:59,576 INFO L78 Accepts]: Start accepts. Automaton has 388 states and 392 transitions. Word has length 360 [2018-10-27 04:45:59,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:45:59,577 INFO L481 AbstractCegarLoop]: Abstraction has 388 states and 392 transitions. [2018-10-27 04:45:59,577 INFO L482 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-10-27 04:45:59,577 INFO L276 IsEmpty]: Start isEmpty. Operand 388 states and 392 transitions. [2018-10-27 04:45:59,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 367 [2018-10-27 04:45:59,578 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:45:59,579 INFO L375 BasicCegarLoop]: trace histogram [51, 44, 44, 43, 43, 43, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:45:59,579 INFO L424 AbstractCegarLoop]: === Iteration 27 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:45:59,579 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:45:59,579 INFO L82 PathProgramCache]: Analyzing trace with hash -1590722591, now seen corresponding path program 13 times [2018-10-27 04:45:59,579 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:45:59,579 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:45:59,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:59,585 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:45:59,585 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:45:59,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:00,072 WARN L179 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 11 [2018-10-27 04:46:00,434 WARN L179 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 17 DAG size of output: 12 [2018-10-27 04:46:00,628 INFO L134 CoverageAnalysis]: Checked inductivity of 6507 backedges. 1953 proven. 200 refuted. 0 times theorem prover too weak. 4354 trivial. 0 not checked. [2018-10-27 04:46:00,628 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:00,628 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:00,636 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:00,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:00,706 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:00,736 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:00,737 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:00,767 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:00,767 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:46:01,179 INFO L134 CoverageAnalysis]: Checked inductivity of 6507 backedges. 1953 proven. 200 refuted. 0 times theorem prover too weak. 4354 trivial. 0 not checked. [2018-10-27 04:46:01,196 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:01,196 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 22 [2018-10-27 04:46:01,197 INFO L460 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-10-27 04:46:01,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-10-27 04:46:01,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=145, Invalid=361, Unknown=0, NotChecked=0, Total=506 [2018-10-27 04:46:01,197 INFO L87 Difference]: Start difference. First operand 388 states and 392 transitions. Second operand 23 states. [2018-10-27 04:46:01,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:01,585 INFO L93 Difference]: Finished difference Result 408 states and 413 transitions. [2018-10-27 04:46:01,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-10-27 04:46:01,586 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 366 [2018-10-27 04:46:01,586 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:01,587 INFO L225 Difference]: With dead ends: 408 [2018-10-27 04:46:01,587 INFO L226 Difference]: Without dead ends: 408 [2018-10-27 04:46:01,588 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 388 GetRequests, 341 SyntacticMatches, 17 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 249 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=243, Invalid=749, Unknown=0, NotChecked=0, Total=992 [2018-10-27 04:46:01,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states. [2018-10-27 04:46:01,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 394. [2018-10-27 04:46:01,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 394 states. [2018-10-27 04:46:01,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 394 states to 394 states and 399 transitions. [2018-10-27 04:46:01,591 INFO L78 Accepts]: Start accepts. Automaton has 394 states and 399 transitions. Word has length 366 [2018-10-27 04:46:01,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:01,592 INFO L481 AbstractCegarLoop]: Abstraction has 394 states and 399 transitions. [2018-10-27 04:46:01,592 INFO L482 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-10-27 04:46:01,592 INFO L276 IsEmpty]: Start isEmpty. Operand 394 states and 399 transitions. [2018-10-27 04:46:01,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 373 [2018-10-27 04:46:01,598 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:01,598 INFO L375 BasicCegarLoop]: trace histogram [52, 45, 45, 44, 44, 44, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:01,598 INFO L424 AbstractCegarLoop]: === Iteration 28 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:01,598 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:01,598 INFO L82 PathProgramCache]: Analyzing trace with hash 737338089, now seen corresponding path program 14 times [2018-10-27 04:46:01,599 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:01,599 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:01,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:01,599 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:01,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:01,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:02,790 INFO L134 CoverageAnalysis]: Checked inductivity of 6783 backedges. 2403 proven. 194 refuted. 0 times theorem prover too weak. 4186 trivial. 0 not checked. [2018-10-27 04:46:02,791 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:02,791 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:02,797 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:46:02,862 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:46:02,863 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:02,867 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:03,107 INFO L134 CoverageAnalysis]: Checked inductivity of 6783 backedges. 2429 proven. 168 refuted. 0 times theorem prover too weak. 4186 trivial. 0 not checked. [2018-10-27 04:46:03,123 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:03,123 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21] total 33 [2018-10-27 04:46:03,124 INFO L460 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-10-27 04:46:03,124 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-10-27 04:46:03,124 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=254, Invalid=802, Unknown=0, NotChecked=0, Total=1056 [2018-10-27 04:46:03,124 INFO L87 Difference]: Start difference. First operand 394 states and 399 transitions. Second operand 33 states. [2018-10-27 04:46:03,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:03,608 INFO L93 Difference]: Finished difference Result 477 states and 483 transitions. [2018-10-27 04:46:03,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-10-27 04:46:03,609 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 372 [2018-10-27 04:46:03,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:03,611 INFO L225 Difference]: With dead ends: 477 [2018-10-27 04:46:03,611 INFO L226 Difference]: Without dead ends: 477 [2018-10-27 04:46:03,611 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 410 GetRequests, 362 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 371 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=659, Invalid=1791, Unknown=0, NotChecked=0, Total=2450 [2018-10-27 04:46:03,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 477 states. [2018-10-27 04:46:03,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 477 to 461. [2018-10-27 04:46:03,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-10-27 04:46:03,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 467 transitions. [2018-10-27 04:46:03,617 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 467 transitions. Word has length 372 [2018-10-27 04:46:03,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:03,618 INFO L481 AbstractCegarLoop]: Abstraction has 461 states and 467 transitions. [2018-10-27 04:46:03,618 INFO L482 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-10-27 04:46:03,618 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 467 transitions. [2018-10-27 04:46:03,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 434 [2018-10-27 04:46:03,623 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:03,623 INFO L375 BasicCegarLoop]: trace histogram [61, 53, 53, 52, 52, 52, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:03,623 INFO L424 AbstractCegarLoop]: === Iteration 29 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:03,623 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:03,623 INFO L82 PathProgramCache]: Analyzing trace with hash 737495678, now seen corresponding path program 15 times [2018-10-27 04:46:03,624 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:03,624 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:03,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:03,624 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:03,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:03,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:05,885 INFO L134 CoverageAnalysis]: Checked inductivity of 9408 backedges. 5831 proven. 669 refuted. 0 times theorem prover too weak. 2908 trivial. 0 not checked. [2018-10-27 04:46:05,885 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:05,885 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-10-27 04:46:05,905 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:06,050 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-10-27 04:46:06,050 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:06,056 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:06,628 INFO L134 CoverageAnalysis]: Checked inductivity of 9408 backedges. 4395 proven. 652 refuted. 0 times theorem prover too weak. 4361 trivial. 0 not checked. [2018-10-27 04:46:06,660 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:06,660 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 25] total 46 [2018-10-27 04:46:06,661 INFO L460 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-10-27 04:46:06,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-10-27 04:46:06,661 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=290, Invalid=1780, Unknown=0, NotChecked=0, Total=2070 [2018-10-27 04:46:06,662 INFO L87 Difference]: Start difference. First operand 461 states and 467 transitions. Second operand 46 states. [2018-10-27 04:46:07,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:07,945 INFO L93 Difference]: Finished difference Result 482 states and 486 transitions. [2018-10-27 04:46:07,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-10-27 04:46:07,946 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 433 [2018-10-27 04:46:07,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:07,948 INFO L225 Difference]: With dead ends: 482 [2018-10-27 04:46:07,948 INFO L226 Difference]: Without dead ends: 476 [2018-10-27 04:46:07,949 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 497 GetRequests, 413 SyntacticMatches, 0 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2083 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=1196, Invalid=6114, Unknown=0, NotChecked=0, Total=7310 [2018-10-27 04:46:07,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 476 states. [2018-10-27 04:46:07,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 476 to 461. [2018-10-27 04:46:07,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-10-27 04:46:07,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 465 transitions. [2018-10-27 04:46:07,957 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 465 transitions. Word has length 433 [2018-10-27 04:46:07,958 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:07,958 INFO L481 AbstractCegarLoop]: Abstraction has 461 states and 465 transitions. [2018-10-27 04:46:07,958 INFO L482 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-10-27 04:46:07,958 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 465 transitions. [2018-10-27 04:46:07,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 440 [2018-10-27 04:46:07,963 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:07,963 INFO L375 BasicCegarLoop]: trace histogram [62, 54, 54, 53, 53, 53, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:07,963 INFO L424 AbstractCegarLoop]: === Iteration 30 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:07,963 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:07,964 INFO L82 PathProgramCache]: Analyzing trace with hash 173730422, now seen corresponding path program 16 times [2018-10-27 04:46:07,964 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:07,964 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:07,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:07,964 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:07,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:07,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:08,469 WARN L179 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 11 [2018-10-27 04:46:08,788 INFO L134 CoverageAnalysis]: Checked inductivity of 9740 backedges. 2720 proven. 252 refuted. 0 times theorem prover too weak. 6768 trivial. 0 not checked. [2018-10-27 04:46:08,788 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:08,788 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:08,796 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:46:08,908 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:46:08,908 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:08,916 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:08,936 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:08,937 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:09,028 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:09,029 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:46:09,746 INFO L134 CoverageAnalysis]: Checked inductivity of 9740 backedges. 2720 proven. 252 refuted. 0 times theorem prover too weak. 6768 trivial. 0 not checked. [2018-10-27 04:46:09,762 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:09,762 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 24 [2018-10-27 04:46:09,763 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-10-27 04:46:09,763 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-10-27 04:46:09,763 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=170, Invalid=430, Unknown=0, NotChecked=0, Total=600 [2018-10-27 04:46:09,763 INFO L87 Difference]: Start difference. First operand 461 states and 465 transitions. Second operand 25 states. [2018-10-27 04:46:10,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:10,265 INFO L93 Difference]: Finished difference Result 481 states and 486 transitions. [2018-10-27 04:46:10,266 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-10-27 04:46:10,266 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 439 [2018-10-27 04:46:10,266 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:10,267 INFO L225 Difference]: With dead ends: 481 [2018-10-27 04:46:10,267 INFO L226 Difference]: Without dead ends: 481 [2018-10-27 04:46:10,268 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 463 GetRequests, 411 SyntacticMatches, 19 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 307 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=284, Invalid=906, Unknown=0, NotChecked=0, Total=1190 [2018-10-27 04:46:10,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-10-27 04:46:10,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 467. [2018-10-27 04:46:10,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 467 states. [2018-10-27 04:46:10,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 467 states to 467 states and 472 transitions. [2018-10-27 04:46:10,272 INFO L78 Accepts]: Start accepts. Automaton has 467 states and 472 transitions. Word has length 439 [2018-10-27 04:46:10,273 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:10,273 INFO L481 AbstractCegarLoop]: Abstraction has 467 states and 472 transitions. [2018-10-27 04:46:10,273 INFO L482 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-10-27 04:46:10,273 INFO L276 IsEmpty]: Start isEmpty. Operand 467 states and 472 transitions. [2018-10-27 04:46:10,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 446 [2018-10-27 04:46:10,275 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:10,275 INFO L375 BasicCegarLoop]: trace histogram [63, 55, 55, 54, 54, 54, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:10,280 INFO L424 AbstractCegarLoop]: === Iteration 31 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:10,280 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:10,280 INFO L82 PathProgramCache]: Analyzing trace with hash -412661314, now seen corresponding path program 17 times [2018-10-27 04:46:10,281 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:10,282 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:10,282 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:10,282 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:10,282 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:10,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:10,653 INFO L134 CoverageAnalysis]: Checked inductivity of 10078 backedges. 3281 proven. 249 refuted. 0 times theorem prover too weak. 6548 trivial. 0 not checked. [2018-10-27 04:46:10,654 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:10,654 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:10,659 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:46:10,858 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-10-27 04:46:10,858 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:10,864 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:12,184 INFO L134 CoverageAnalysis]: Checked inductivity of 10078 backedges. 3188 proven. 1003 refuted. 0 times theorem prover too weak. 5887 trivial. 0 not checked. [2018-10-27 04:46:12,201 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:12,201 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 28] total 40 [2018-10-27 04:46:12,201 INFO L460 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-10-27 04:46:12,202 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-10-27 04:46:12,202 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=313, Invalid=1247, Unknown=0, NotChecked=0, Total=1560 [2018-10-27 04:46:12,202 INFO L87 Difference]: Start difference. First operand 467 states and 472 transitions. Second operand 40 states. [2018-10-27 04:46:12,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:12,894 INFO L93 Difference]: Finished difference Result 556 states and 562 transitions. [2018-10-27 04:46:12,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-10-27 04:46:12,895 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 445 [2018-10-27 04:46:12,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:12,897 INFO L225 Difference]: With dead ends: 556 [2018-10-27 04:46:12,897 INFO L226 Difference]: Without dead ends: 556 [2018-10-27 04:46:12,898 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 489 GetRequests, 430 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 686 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=793, Invalid=2867, Unknown=0, NotChecked=0, Total=3660 [2018-10-27 04:46:12,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 556 states. [2018-10-27 04:46:12,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 556 to 540. [2018-10-27 04:46:12,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 540 states. [2018-10-27 04:46:12,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 540 states to 540 states and 546 transitions. [2018-10-27 04:46:12,906 INFO L78 Accepts]: Start accepts. Automaton has 540 states and 546 transitions. Word has length 445 [2018-10-27 04:46:12,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:12,906 INFO L481 AbstractCegarLoop]: Abstraction has 540 states and 546 transitions. [2018-10-27 04:46:12,906 INFO L482 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-10-27 04:46:12,907 INFO L276 IsEmpty]: Start isEmpty. Operand 540 states and 546 transitions. [2018-10-27 04:46:12,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 513 [2018-10-27 04:46:12,912 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:12,912 INFO L375 BasicCegarLoop]: trace histogram [73, 64, 64, 63, 63, 63, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:12,912 INFO L424 AbstractCegarLoop]: === Iteration 32 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:12,912 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:12,913 INFO L82 PathProgramCache]: Analyzing trace with hash -1526179631, now seen corresponding path program 18 times [2018-10-27 04:46:12,913 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:12,913 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:12,913 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:12,913 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:12,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:12,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:13,445 WARN L179 SmtUtils]: Spent 103.00 ms on a formula simplification that was a NOOP. DAG size: 12 [2018-10-27 04:46:13,860 INFO L134 CoverageAnalysis]: Checked inductivity of 13626 backedges. 3599 proven. 299 refuted. 0 times theorem prover too weak. 9728 trivial. 0 not checked. [2018-10-27 04:46:13,860 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:13,860 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:13,868 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-10-27 04:46:14,134 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2018-10-27 04:46:14,134 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:14,139 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:15,604 INFO L134 CoverageAnalysis]: Checked inductivity of 13626 backedges. 6036 proven. 814 refuted. 0 times theorem prover too weak. 6776 trivial. 0 not checked. [2018-10-27 04:46:15,621 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:15,621 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 27] total 42 [2018-10-27 04:46:15,622 INFO L460 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-10-27 04:46:15,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-10-27 04:46:15,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=256, Invalid=1466, Unknown=0, NotChecked=0, Total=1722 [2018-10-27 04:46:15,623 INFO L87 Difference]: Start difference. First operand 540 states and 546 transitions. Second operand 42 states. [2018-10-27 04:46:17,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:17,200 INFO L93 Difference]: Finished difference Result 723 states and 733 transitions. [2018-10-27 04:46:17,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-10-27 04:46:17,201 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 512 [2018-10-27 04:46:17,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:17,203 INFO L225 Difference]: With dead ends: 723 [2018-10-27 04:46:17,203 INFO L226 Difference]: Without dead ends: 723 [2018-10-27 04:46:17,204 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 567 GetRequests, 487 SyntacticMatches, 1 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2141 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=1150, Invalid=5330, Unknown=0, NotChecked=0, Total=6480 [2018-10-27 04:46:17,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 723 states. [2018-10-27 04:46:17,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 723 to 622. [2018-10-27 04:46:17,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2018-10-27 04:46:17,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 630 transitions. [2018-10-27 04:46:17,214 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 630 transitions. Word has length 512 [2018-10-27 04:46:17,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:17,215 INFO L481 AbstractCegarLoop]: Abstraction has 622 states and 630 transitions. [2018-10-27 04:46:17,215 INFO L482 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-10-27 04:46:17,215 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 630 transitions. [2018-10-27 04:46:17,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 592 [2018-10-27 04:46:17,220 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:17,220 INFO L375 BasicCegarLoop]: trace histogram [85, 75, 75, 74, 74, 74, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:17,220 INFO L424 AbstractCegarLoop]: === Iteration 33 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:17,221 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:17,221 INFO L82 PathProgramCache]: Analyzing trace with hash -1454320098, now seen corresponding path program 19 times [2018-10-27 04:46:17,221 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:17,221 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:17,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:17,222 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:17,226 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:17,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:18,567 INFO L134 CoverageAnalysis]: Checked inductivity of 18627 backedges. 10515 proven. 1017 refuted. 0 times theorem prover too weak. 7095 trivial. 0 not checked. [2018-10-27 04:46:18,568 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:18,568 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:18,574 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:18,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:18,680 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:19,261 INFO L134 CoverageAnalysis]: Checked inductivity of 18627 backedges. 8244 proven. 290 refuted. 0 times theorem prover too weak. 10093 trivial. 0 not checked. [2018-10-27 04:46:19,277 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:19,277 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 24] total 47 [2018-10-27 04:46:19,278 INFO L460 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-10-27 04:46:19,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-10-27 04:46:19,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=367, Invalid=1795, Unknown=0, NotChecked=0, Total=2162 [2018-10-27 04:46:19,278 INFO L87 Difference]: Start difference. First operand 622 states and 630 transitions. Second operand 47 states. [2018-10-27 04:46:20,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:20,381 INFO L93 Difference]: Finished difference Result 647 states and 652 transitions. [2018-10-27 04:46:20,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-10-27 04:46:20,381 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 591 [2018-10-27 04:46:20,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:20,383 INFO L225 Difference]: With dead ends: 647 [2018-10-27 04:46:20,383 INFO L226 Difference]: Without dead ends: 641 [2018-10-27 04:46:20,384 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 651 GetRequests, 575 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1758 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1049, Invalid=4957, Unknown=0, NotChecked=0, Total=6006 [2018-10-27 04:46:20,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2018-10-27 04:46:20,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 623. [2018-10-27 04:46:20,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 623 states. [2018-10-27 04:46:20,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 623 states to 623 states and 628 transitions. [2018-10-27 04:46:20,393 INFO L78 Accepts]: Start accepts. Automaton has 623 states and 628 transitions. Word has length 591 [2018-10-27 04:46:20,394 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:20,394 INFO L481 AbstractCegarLoop]: Abstraction has 623 states and 628 transitions. [2018-10-27 04:46:20,394 INFO L482 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-10-27 04:46:20,394 INFO L276 IsEmpty]: Start isEmpty. Operand 623 states and 628 transitions. [2018-10-27 04:46:20,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 598 [2018-10-27 04:46:20,400 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:20,401 INFO L375 BasicCegarLoop]: trace histogram [86, 76, 76, 75, 75, 75, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:20,401 INFO L424 AbstractCegarLoop]: === Iteration 34 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:20,401 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:20,401 INFO L82 PathProgramCache]: Analyzing trace with hash 1949006358, now seen corresponding path program 20 times [2018-10-27 04:46:20,401 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:20,401 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:20,402 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:20,402 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:20,402 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:20,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:21,066 INFO L134 CoverageAnalysis]: Checked inductivity of 19095 backedges. 4390 proven. 310 refuted. 0 times theorem prover too weak. 14395 trivial. 0 not checked. [2018-10-27 04:46:21,066 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:21,066 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:21,073 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:46:21,175 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:46:21,175 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:21,181 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:21,189 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:21,189 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:21,192 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:21,192 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:46:22,369 INFO L134 CoverageAnalysis]: Checked inductivity of 19095 backedges. 4390 proven. 310 refuted. 0 times theorem prover too weak. 14395 trivial. 0 not checked. [2018-10-27 04:46:22,385 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:22,386 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 26 [2018-10-27 04:46:22,386 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-10-27 04:46:22,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-10-27 04:46:22,386 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=505, Unknown=0, NotChecked=0, Total=702 [2018-10-27 04:46:22,386 INFO L87 Difference]: Start difference. First operand 623 states and 628 transitions. Second operand 27 states. [2018-10-27 04:46:22,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:22,981 INFO L93 Difference]: Finished difference Result 640 states and 645 transitions. [2018-10-27 04:46:22,981 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-10-27 04:46:22,982 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 597 [2018-10-27 04:46:22,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:22,983 INFO L225 Difference]: With dead ends: 640 [2018-10-27 04:46:22,983 INFO L226 Difference]: Without dead ends: 640 [2018-10-27 04:46:22,984 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 623 GetRequests, 564 SyntacticMatches, 23 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 374 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=328, Invalid=1078, Unknown=0, NotChecked=0, Total=1406 [2018-10-27 04:46:22,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 640 states. [2018-10-27 04:46:22,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 640 to 625. [2018-10-27 04:46:22,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 625 states. [2018-10-27 04:46:22,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 625 states to 625 states and 630 transitions. [2018-10-27 04:46:22,991 INFO L78 Accepts]: Start accepts. Automaton has 625 states and 630 transitions. Word has length 597 [2018-10-27 04:46:22,991 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:22,991 INFO L481 AbstractCegarLoop]: Abstraction has 625 states and 630 transitions. [2018-10-27 04:46:22,992 INFO L482 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-10-27 04:46:22,992 INFO L276 IsEmpty]: Start isEmpty. Operand 625 states and 630 transitions. [2018-10-27 04:46:22,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 604 [2018-10-27 04:46:22,999 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:22,999 INFO L375 BasicCegarLoop]: trace histogram [87, 77, 77, 76, 76, 76, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:22,999 INFO L424 AbstractCegarLoop]: === Iteration 35 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:22,999 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:22,999 INFO L82 PathProgramCache]: Analyzing trace with hash 1614127454, now seen corresponding path program 21 times [2018-10-27 04:46:23,000 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:23,000 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:23,000 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:23,000 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:23,000 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:23,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:23,864 WARN L179 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 17 DAG size of output: 12 [2018-10-27 04:46:24,217 INFO L134 CoverageAnalysis]: Checked inductivity of 19569 backedges. 4800 proven. 374 refuted. 0 times theorem prover too weak. 14395 trivial. 0 not checked. [2018-10-27 04:46:24,217 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:24,218 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:24,224 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:46:24,352 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-10-27 04:46:24,352 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:24,357 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:24,360 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:24,360 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:24,368 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:24,368 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:46:25,394 INFO L134 CoverageAnalysis]: Checked inductivity of 19569 backedges. 4800 proven. 374 refuted. 0 times theorem prover too weak. 14395 trivial. 0 not checked. [2018-10-27 04:46:25,410 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:25,410 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 28 [2018-10-27 04:46:25,410 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-10-27 04:46:25,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-10-27 04:46:25,411 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=226, Invalid=586, Unknown=0, NotChecked=0, Total=812 [2018-10-27 04:46:25,411 INFO L87 Difference]: Start difference. First operand 625 states and 630 transitions. Second operand 29 states. [2018-10-27 04:46:26,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:26,102 INFO L93 Difference]: Finished difference Result 658 states and 665 transitions. [2018-10-27 04:46:26,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-10-27 04:46:26,103 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 603 [2018-10-27 04:46:26,104 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:26,105 INFO L225 Difference]: With dead ends: 658 [2018-10-27 04:46:26,105 INFO L226 Difference]: Without dead ends: 658 [2018-10-27 04:46:26,105 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 631 GetRequests, 569 SyntacticMatches, 23 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 441 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=375, Invalid=1265, Unknown=0, NotChecked=0, Total=1640 [2018-10-27 04:46:26,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 658 states. [2018-10-27 04:46:26,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 658 to 631. [2018-10-27 04:46:26,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 631 states. [2018-10-27 04:46:26,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 631 states to 631 states and 637 transitions. [2018-10-27 04:46:26,113 INFO L78 Accepts]: Start accepts. Automaton has 631 states and 637 transitions. Word has length 603 [2018-10-27 04:46:26,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:26,113 INFO L481 AbstractCegarLoop]: Abstraction has 631 states and 637 transitions. [2018-10-27 04:46:26,113 INFO L482 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-10-27 04:46:26,113 INFO L276 IsEmpty]: Start isEmpty. Operand 631 states and 637 transitions. [2018-10-27 04:46:26,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 610 [2018-10-27 04:46:26,120 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:26,121 INFO L375 BasicCegarLoop]: trace histogram [88, 78, 78, 77, 77, 77, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:26,121 INFO L424 AbstractCegarLoop]: === Iteration 36 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:26,121 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:26,121 INFO L82 PathProgramCache]: Analyzing trace with hash -1870187866, now seen corresponding path program 22 times [2018-10-27 04:46:26,121 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:26,121 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:26,125 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:26,125 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:26,125 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:26,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:26,615 INFO L134 CoverageAnalysis]: Checked inductivity of 20049 backedges. 5619 proven. 380 refuted. 0 times theorem prover too weak. 14050 trivial. 0 not checked. [2018-10-27 04:46:26,616 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:26,616 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:26,623 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:46:26,713 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:46:26,714 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:26,718 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:27,079 INFO L134 CoverageAnalysis]: Checked inductivity of 20049 backedges. 5654 proven. 345 refuted. 0 times theorem prover too weak. 14050 trivial. 0 not checked. [2018-10-27 04:46:27,095 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:27,096 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 27] total 42 [2018-10-27 04:46:27,096 INFO L460 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-10-27 04:46:27,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-10-27 04:46:27,097 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=407, Invalid=1315, Unknown=0, NotChecked=0, Total=1722 [2018-10-27 04:46:27,097 INFO L87 Difference]: Start difference. First operand 631 states and 637 transitions. Second operand 42 states. [2018-10-27 04:46:27,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:27,876 INFO L93 Difference]: Finished difference Result 741 states and 748 transitions. [2018-10-27 04:46:27,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-10-27 04:46:27,877 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 609 [2018-10-27 04:46:27,878 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:27,879 INFO L225 Difference]: With dead ends: 741 [2018-10-27 04:46:27,879 INFO L226 Difference]: Without dead ends: 741 [2018-10-27 04:46:27,879 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 659 GetRequests, 596 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 659 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1094, Invalid=3066, Unknown=0, NotChecked=0, Total=4160 [2018-10-27 04:46:27,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 741 states. [2018-10-27 04:46:27,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 741 to 722. [2018-10-27 04:46:27,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 722 states. [2018-10-27 04:46:27,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 722 states and 729 transitions. [2018-10-27 04:46:27,887 INFO L78 Accepts]: Start accepts. Automaton has 722 states and 729 transitions. Word has length 609 [2018-10-27 04:46:27,888 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:27,888 INFO L481 AbstractCegarLoop]: Abstraction has 722 states and 729 transitions. [2018-10-27 04:46:27,888 INFO L482 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-10-27 04:46:27,888 INFO L276 IsEmpty]: Start isEmpty. Operand 722 states and 729 transitions. [2018-10-27 04:46:27,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 689 [2018-10-27 04:46:27,896 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:27,896 INFO L375 BasicCegarLoop]: trace histogram [100, 89, 89, 88, 88, 88, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:27,896 INFO L424 AbstractCegarLoop]: === Iteration 37 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:27,896 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:27,896 INFO L82 PathProgramCache]: Analyzing trace with hash 1990474489, now seen corresponding path program 23 times [2018-10-27 04:46:27,896 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:27,897 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:27,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:27,897 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:27,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:27,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:28,441 INFO L134 CoverageAnalysis]: Checked inductivity of 26037 backedges. 11003 proven. 1890 refuted. 0 times theorem prover too weak. 13144 trivial. 0 not checked. [2018-10-27 04:46:28,441 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:28,442 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:28,448 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:46:28,979 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 26 check-sat command(s) [2018-10-27 04:46:28,979 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:28,987 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:29,395 INFO L134 CoverageAnalysis]: Checked inductivity of 26037 backedges. 11008 proven. 1885 refuted. 0 times theorem prover too weak. 13144 trivial. 0 not checked. [2018-10-27 04:46:29,413 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:29,414 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 45 [2018-10-27 04:46:29,414 INFO L460 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-10-27 04:46:29,414 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-10-27 04:46:29,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=368, Invalid=1612, Unknown=0, NotChecked=0, Total=1980 [2018-10-27 04:46:29,415 INFO L87 Difference]: Start difference. First operand 722 states and 729 transitions. Second operand 45 states. [2018-10-27 04:46:30,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:30,145 INFO L93 Difference]: Finished difference Result 742 states and 747 transitions. [2018-10-27 04:46:30,146 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-10-27 04:46:30,146 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 688 [2018-10-27 04:46:30,146 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:30,147 INFO L225 Difference]: With dead ends: 742 [2018-10-27 04:46:30,147 INFO L226 Difference]: Without dead ends: 736 [2018-10-27 04:46:30,148 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 744 GetRequests, 675 SyntacticMatches, 0 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1398 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1103, Invalid=3867, Unknown=0, NotChecked=0, Total=4970 [2018-10-27 04:46:30,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 736 states. [2018-10-27 04:46:30,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 736 to 722. [2018-10-27 04:46:30,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 722 states. [2018-10-27 04:46:30,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 722 states and 727 transitions. [2018-10-27 04:46:30,155 INFO L78 Accepts]: Start accepts. Automaton has 722 states and 727 transitions. Word has length 688 [2018-10-27 04:46:30,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:30,158 INFO L481 AbstractCegarLoop]: Abstraction has 722 states and 727 transitions. [2018-10-27 04:46:30,158 INFO L482 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-10-27 04:46:30,158 INFO L276 IsEmpty]: Start isEmpty. Operand 722 states and 727 transitions. [2018-10-27 04:46:30,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 695 [2018-10-27 04:46:30,163 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:30,163 INFO L375 BasicCegarLoop]: trace histogram [101, 90, 90, 89, 89, 89, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:30,163 INFO L424 AbstractCegarLoop]: === Iteration 38 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:30,163 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:30,163 INFO L82 PathProgramCache]: Analyzing trace with hash 1191839409, now seen corresponding path program 24 times [2018-10-27 04:46:30,163 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:30,164 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:30,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:30,171 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:30,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:30,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:30,943 INFO L134 CoverageAnalysis]: Checked inductivity of 26591 backedges. 6149 proven. 444 refuted. 0 times theorem prover too weak. 19998 trivial. 0 not checked. [2018-10-27 04:46:30,944 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:30,944 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:30,950 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-10-27 04:46:31,500 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2018-10-27 04:46:31,500 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:31,509 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:31,512 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:31,513 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:31,521 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:31,521 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:46:33,374 INFO L134 CoverageAnalysis]: Checked inductivity of 26591 backedges. 10379 proven. 1380 refuted. 0 times theorem prover too weak. 14832 trivial. 0 not checked. [2018-10-27 04:46:33,393 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:33,393 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 24] total 37 [2018-10-27 04:46:33,394 INFO L460 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-10-27 04:46:33,394 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-10-27 04:46:33,394 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=270, Invalid=1136, Unknown=0, NotChecked=0, Total=1406 [2018-10-27 04:46:33,394 INFO L87 Difference]: Start difference. First operand 722 states and 727 transitions. Second operand 38 states. [2018-10-27 04:46:36,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:36,758 INFO L93 Difference]: Finished difference Result 841 states and 850 transitions. [2018-10-27 04:46:36,759 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-10-27 04:46:36,759 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 694 [2018-10-27 04:46:36,760 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:36,761 INFO L225 Difference]: With dead ends: 841 [2018-10-27 04:46:36,761 INFO L226 Difference]: Without dead ends: 841 [2018-10-27 04:46:36,762 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 794 GetRequests, 652 SyntacticMatches, 24 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5679 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=2913, Invalid=11367, Unknown=0, NotChecked=0, Total=14280 [2018-10-27 04:46:36,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 841 states. [2018-10-27 04:46:36,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 841 to 822. [2018-10-27 04:46:36,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 822 states. [2018-10-27 04:46:36,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 822 states to 822 states and 831 transitions. [2018-10-27 04:46:36,773 INFO L78 Accepts]: Start accepts. Automaton has 822 states and 831 transitions. Word has length 694 [2018-10-27 04:46:36,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:36,773 INFO L481 AbstractCegarLoop]: Abstraction has 822 states and 831 transitions. [2018-10-27 04:46:36,773 INFO L482 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-10-27 04:46:36,773 INFO L276 IsEmpty]: Start isEmpty. Operand 822 states and 831 transitions. [2018-10-27 04:46:36,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 792 [2018-10-27 04:46:36,782 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:36,783 INFO L375 BasicCegarLoop]: trace histogram [116, 104, 104, 103, 103, 103, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:36,783 INFO L424 AbstractCegarLoop]: === Iteration 39 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:36,783 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:36,783 INFO L82 PathProgramCache]: Analyzing trace with hash 627766982, now seen corresponding path program 25 times [2018-10-27 04:46:36,783 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:36,783 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:36,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:36,784 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:36,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:36,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:37,607 INFO L134 CoverageAnalysis]: Checked inductivity of 35332 backedges. 7728 proven. 520 refuted. 0 times theorem prover too weak. 27084 trivial. 0 not checked. [2018-10-27 04:46:37,607 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:37,607 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:37,614 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:37,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:37,752 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:37,756 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:37,756 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:37,759 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:37,759 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:46:38,786 INFO L134 CoverageAnalysis]: Checked inductivity of 35332 backedges. 7728 proven. 520 refuted. 0 times theorem prover too weak. 27084 trivial. 0 not checked. [2018-10-27 04:46:38,803 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:38,803 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 32 [2018-10-27 04:46:38,804 INFO L460 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-10-27 04:46:38,804 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-10-27 04:46:38,804 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=290, Invalid=766, Unknown=0, NotChecked=0, Total=1056 [2018-10-27 04:46:38,804 INFO L87 Difference]: Start difference. First operand 822 states and 831 transitions. Second operand 33 states. [2018-10-27 04:46:39,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:39,588 INFO L93 Difference]: Finished difference Result 858 states and 869 transitions. [2018-10-27 04:46:39,589 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-10-27 04:46:39,589 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 791 [2018-10-27 04:46:39,589 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:39,591 INFO L225 Difference]: With dead ends: 858 [2018-10-27 04:46:39,591 INFO L226 Difference]: Without dead ends: 858 [2018-10-27 04:46:39,591 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 823 GetRequests, 751 SyntacticMatches, 27 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 599 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=478, Invalid=1684, Unknown=0, NotChecked=0, Total=2162 [2018-10-27 04:46:39,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 858 states. [2018-10-27 04:46:39,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 858 to 828. [2018-10-27 04:46:39,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 828 states. [2018-10-27 04:46:39,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 828 states to 828 states and 838 transitions. [2018-10-27 04:46:39,599 INFO L78 Accepts]: Start accepts. Automaton has 828 states and 838 transitions. Word has length 791 [2018-10-27 04:46:39,600 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:39,600 INFO L481 AbstractCegarLoop]: Abstraction has 828 states and 838 transitions. [2018-10-27 04:46:39,600 INFO L482 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-10-27 04:46:39,600 INFO L276 IsEmpty]: Start isEmpty. Operand 828 states and 838 transitions. [2018-10-27 04:46:39,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 798 [2018-10-27 04:46:39,609 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:39,609 INFO L375 BasicCegarLoop]: trace histogram [117, 105, 105, 104, 104, 104, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:39,609 INFO L424 AbstractCegarLoop]: === Iteration 40 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:39,609 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:39,609 INFO L82 PathProgramCache]: Analyzing trace with hash -919545330, now seen corresponding path program 26 times [2018-10-27 04:46:39,609 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:39,610 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:39,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:39,610 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:46:39,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:39,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:40,343 INFO L134 CoverageAnalysis]: Checked inductivity of 35978 backedges. 8853 proven. 539 refuted. 0 times theorem prover too weak. 26586 trivial. 0 not checked. [2018-10-27 04:46:40,343 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:40,344 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:40,350 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:46:40,482 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:46:40,482 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:40,489 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:41,044 INFO L134 CoverageAnalysis]: Checked inductivity of 35978 backedges. 8894 proven. 498 refuted. 0 times theorem prover too weak. 26586 trivial. 0 not checked. [2018-10-27 04:46:41,061 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:41,062 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 31] total 48 [2018-10-27 04:46:41,062 INFO L460 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-10-27 04:46:41,062 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-10-27 04:46:41,063 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=529, Invalid=1727, Unknown=0, NotChecked=0, Total=2256 [2018-10-27 04:46:41,063 INFO L87 Difference]: Start difference. First operand 828 states and 838 transitions. Second operand 48 states. [2018-10-27 04:46:42,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:42,016 INFO L93 Difference]: Finished difference Result 1058 states and 1076 transitions. [2018-10-27 04:46:42,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-10-27 04:46:42,018 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 797 [2018-10-27 04:46:42,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:42,020 INFO L225 Difference]: With dead ends: 1058 [2018-10-27 04:46:42,020 INFO L226 Difference]: Without dead ends: 1058 [2018-10-27 04:46:42,021 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 855 GetRequests, 782 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 896 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1444, Invalid=4106, Unknown=0, NotChecked=0, Total=5550 [2018-10-27 04:46:42,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1058 states. [2018-10-27 04:46:42,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1058 to 1032. [2018-10-27 04:46:42,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1032 states. [2018-10-27 04:46:42,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1032 states to 1032 states and 1049 transitions. [2018-10-27 04:46:42,031 INFO L78 Accepts]: Start accepts. Automaton has 1032 states and 1049 transitions. Word has length 797 [2018-10-27 04:46:42,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:42,031 INFO L481 AbstractCegarLoop]: Abstraction has 1032 states and 1049 transitions. [2018-10-27 04:46:42,031 INFO L482 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-10-27 04:46:42,031 INFO L276 IsEmpty]: Start isEmpty. Operand 1032 states and 1049 transitions. [2018-10-27 04:46:42,042 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 883 [2018-10-27 04:46:42,043 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:42,043 INFO L375 BasicCegarLoop]: trace histogram [130, 117, 117, 116, 116, 116, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:42,043 INFO L424 AbstractCegarLoop]: === Iteration 41 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:42,043 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:42,043 INFO L82 PathProgramCache]: Analyzing trace with hash 1892148121, now seen corresponding path program 27 times [2018-10-27 04:46:42,043 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:42,044 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:42,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:42,048 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:42,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:42,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:42,736 INFO L134 CoverageAnalysis]: Checked inductivity of 44592 backedges. 15776 proven. 3491 refuted. 0 times theorem prover too weak. 25325 trivial. 0 not checked. [2018-10-27 04:46:42,737 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:42,737 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:42,743 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:46:42,948 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-10-27 04:46:42,948 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:42,954 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:43,799 INFO L134 CoverageAnalysis]: Checked inductivity of 44592 backedges. 16412 proven. 1642 refuted. 0 times theorem prover too weak. 26538 trivial. 0 not checked. [2018-10-27 04:46:43,815 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:43,815 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 35] total 65 [2018-10-27 04:46:43,816 INFO L460 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-10-27 04:46:43,816 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-10-27 04:46:43,816 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=567, Invalid=3593, Unknown=0, NotChecked=0, Total=4160 [2018-10-27 04:46:43,817 INFO L87 Difference]: Start difference. First operand 1032 states and 1049 transitions. Second operand 65 states. [2018-10-27 04:46:46,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:46,057 INFO L93 Difference]: Finished difference Result 1167 states and 1178 transitions. [2018-10-27 04:46:46,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2018-10-27 04:46:46,057 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 882 [2018-10-27 04:46:46,058 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:46,060 INFO L225 Difference]: With dead ends: 1167 [2018-10-27 04:46:46,060 INFO L226 Difference]: Without dead ends: 1155 [2018-10-27 04:46:46,061 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 986 GetRequests, 851 SyntacticMatches, 0 SemanticMatches, 135 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6168 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2580, Invalid=16052, Unknown=0, NotChecked=0, Total=18632 [2018-10-27 04:46:46,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1155 states. [2018-10-27 04:46:46,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1155 to 934. [2018-10-27 04:46:46,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 934 states. [2018-10-27 04:46:46,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 934 states to 934 states and 942 transitions. [2018-10-27 04:46:46,070 INFO L78 Accepts]: Start accepts. Automaton has 934 states and 942 transitions. Word has length 882 [2018-10-27 04:46:46,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:46,070 INFO L481 AbstractCegarLoop]: Abstraction has 934 states and 942 transitions. [2018-10-27 04:46:46,070 INFO L482 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-10-27 04:46:46,071 INFO L276 IsEmpty]: Start isEmpty. Operand 934 states and 942 transitions. [2018-10-27 04:46:46,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 895 [2018-10-27 04:46:46,080 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:46,081 INFO L375 BasicCegarLoop]: trace histogram [132, 119, 119, 118, 118, 118, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:46,081 INFO L424 AbstractCegarLoop]: === Iteration 42 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:46,081 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:46,081 INFO L82 PathProgramCache]: Analyzing trace with hash -442575783, now seen corresponding path program 28 times [2018-10-27 04:46:46,081 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:46,081 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:46,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:46,082 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:46,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:46,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:46,915 INFO L134 CoverageAnalysis]: Checked inductivity of 46050 backedges. 9555 proven. 602 refuted. 0 times theorem prover too weak. 35893 trivial. 0 not checked. [2018-10-27 04:46:46,915 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:46,915 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:46,922 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:46:47,128 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:46:47,128 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:47,136 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:47,138 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:47,138 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:47,149 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:47,149 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:46:48,828 INFO L134 CoverageAnalysis]: Checked inductivity of 46050 backedges. 9555 proven. 602 refuted. 0 times theorem prover too weak. 35893 trivial. 0 not checked. [2018-10-27 04:46:48,846 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:48,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 34 [2018-10-27 04:46:48,847 INFO L460 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-10-27 04:46:48,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-10-27 04:46:48,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=865, Unknown=0, NotChecked=0, Total=1190 [2018-10-27 04:46:48,847 INFO L87 Difference]: Start difference. First operand 934 states and 942 transitions. Second operand 35 states. [2018-10-27 04:46:49,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:49,743 INFO L93 Difference]: Finished difference Result 960 states and 969 transitions. [2018-10-27 04:46:49,744 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-10-27 04:46:49,744 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 894 [2018-10-27 04:46:49,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:49,746 INFO L225 Difference]: With dead ends: 960 [2018-10-27 04:46:49,746 INFO L226 Difference]: Without dead ends: 960 [2018-10-27 04:46:49,747 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 928 GetRequests, 851 SyntacticMatches, 29 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 687 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=534, Invalid=1916, Unknown=0, NotChecked=0, Total=2450 [2018-10-27 04:46:49,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 960 states. [2018-10-27 04:46:49,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 960 to 940. [2018-10-27 04:46:49,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 940 states. [2018-10-27 04:46:49,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 940 states to 940 states and 949 transitions. [2018-10-27 04:46:49,753 INFO L78 Accepts]: Start accepts. Automaton has 940 states and 949 transitions. Word has length 894 [2018-10-27 04:46:49,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:49,753 INFO L481 AbstractCegarLoop]: Abstraction has 940 states and 949 transitions. [2018-10-27 04:46:49,753 INFO L482 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-10-27 04:46:49,753 INFO L276 IsEmpty]: Start isEmpty. Operand 940 states and 949 transitions. [2018-10-27 04:46:49,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 901 [2018-10-27 04:46:49,764 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:49,765 INFO L375 BasicCegarLoop]: trace histogram [133, 120, 120, 119, 119, 119, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:49,765 INFO L424 AbstractCegarLoop]: === Iteration 43 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:49,765 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:49,765 INFO L82 PathProgramCache]: Analyzing trace with hash 2021588321, now seen corresponding path program 29 times [2018-10-27 04:46:49,766 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:49,766 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:49,766 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:49,766 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:49,766 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:49,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:50,606 INFO L134 CoverageAnalysis]: Checked inductivity of 46788 backedges. 10851 proven. 629 refuted. 0 times theorem prover too weak. 35308 trivial. 0 not checked. [2018-10-27 04:46:50,606 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:50,606 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:50,612 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:46:51,254 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-10-27 04:46:51,254 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:51,264 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:51,949 INFO L134 CoverageAnalysis]: Checked inductivity of 46788 backedges. 10718 proven. 2308 refuted. 0 times theorem prover too weak. 33762 trivial. 0 not checked. [2018-10-27 04:46:51,967 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:51,967 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 38] total 55 [2018-10-27 04:46:51,968 INFO L460 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-10-27 04:46:51,968 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-10-27 04:46:51,968 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=608, Invalid=2362, Unknown=0, NotChecked=0, Total=2970 [2018-10-27 04:46:51,968 INFO L87 Difference]: Start difference. First operand 940 states and 949 transitions. Second operand 55 states. [2018-10-27 04:46:53,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:53,065 INFO L93 Difference]: Finished difference Result 1179 states and 1193 transitions. [2018-10-27 04:46:53,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-10-27 04:46:53,067 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 900 [2018-10-27 04:46:53,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:53,069 INFO L225 Difference]: With dead ends: 1179 [2018-10-27 04:46:53,069 INFO L226 Difference]: Without dead ends: 1179 [2018-10-27 04:46:53,070 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 964 GetRequests, 880 SyntacticMatches, 0 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1376 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1613, Invalid=5697, Unknown=0, NotChecked=0, Total=7310 [2018-10-27 04:46:53,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1179 states. [2018-10-27 04:46:53,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1179 to 1153. [2018-10-27 04:46:53,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1153 states. [2018-10-27 04:46:53,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1153 states to 1153 states and 1167 transitions. [2018-10-27 04:46:53,078 INFO L78 Accepts]: Start accepts. Automaton has 1153 states and 1167 transitions. Word has length 900 [2018-10-27 04:46:53,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:53,079 INFO L481 AbstractCegarLoop]: Abstraction has 1153 states and 1167 transitions. [2018-10-27 04:46:53,079 INFO L482 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-10-27 04:46:53,079 INFO L276 IsEmpty]: Start isEmpty. Operand 1153 states and 1167 transitions. [2018-10-27 04:46:53,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 992 [2018-10-27 04:46:53,089 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:53,089 INFO L375 BasicCegarLoop]: trace histogram [147, 133, 133, 132, 132, 132, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:53,089 INFO L424 AbstractCegarLoop]: === Iteration 44 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:53,089 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:53,090 INFO L82 PathProgramCache]: Analyzing trace with hash 1540673902, now seen corresponding path program 30 times [2018-10-27 04:46:53,090 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:53,090 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:53,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:53,090 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:53,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:53,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:46:54,064 INFO L134 CoverageAnalysis]: Checked inductivity of 57367 backedges. 11460 proven. 690 refuted. 0 times theorem prover too weak. 45217 trivial. 0 not checked. [2018-10-27 04:46:54,064 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:46:54,064 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:46:54,071 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-10-27 04:46:55,442 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 26 check-sat command(s) [2018-10-27 04:46:55,443 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:46:55,453 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:46:55,459 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:46:55,459 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:46:55,462 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:46:55,462 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:46:57,295 INFO L134 CoverageAnalysis]: Checked inductivity of 57367 backedges. 19440 proven. 2057 refuted. 0 times theorem prover too weak. 35870 trivial. 0 not checked. [2018-10-27 04:46:57,313 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:46:57,313 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 25] total 41 [2018-10-27 04:46:57,314 INFO L460 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-10-27 04:46:57,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-10-27 04:46:57,314 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=366, Invalid=1356, Unknown=0, NotChecked=0, Total=1722 [2018-10-27 04:46:57,314 INFO L87 Difference]: Start difference. First operand 1153 states and 1167 transitions. Second operand 42 states. [2018-10-27 04:46:59,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:46:59,851 INFO L93 Difference]: Finished difference Result 1393 states and 1418 transitions. [2018-10-27 04:46:59,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2018-10-27 04:46:59,852 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 991 [2018-10-27 04:46:59,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:46:59,855 INFO L225 Difference]: With dead ends: 1393 [2018-10-27 04:46:59,855 INFO L226 Difference]: Without dead ends: 1393 [2018-10-27 04:46:59,856 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1080 GetRequests, 942 SyntacticMatches, 30 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4704 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=2744, Invalid=9246, Unknown=0, NotChecked=0, Total=11990 [2018-10-27 04:46:59,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1393 states. [2018-10-27 04:46:59,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1393 to 1271. [2018-10-27 04:46:59,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1271 states. [2018-10-27 04:46:59,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1271 states to 1271 states and 1292 transitions. [2018-10-27 04:46:59,865 INFO L78 Accepts]: Start accepts. Automaton has 1271 states and 1292 transitions. Word has length 991 [2018-10-27 04:46:59,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:46:59,865 INFO L481 AbstractCegarLoop]: Abstraction has 1271 states and 1292 transitions. [2018-10-27 04:46:59,865 INFO L482 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-10-27 04:46:59,865 INFO L276 IsEmpty]: Start isEmpty. Operand 1271 states and 1292 transitions. [2018-10-27 04:46:59,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1089 [2018-10-27 04:46:59,877 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:46:59,877 INFO L375 BasicCegarLoop]: trace histogram [162, 147, 147, 146, 146, 146, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:46:59,878 INFO L424 AbstractCegarLoop]: === Iteration 45 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:46:59,878 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:46:59,878 INFO L82 PathProgramCache]: Analyzing trace with hash -1641963447, now seen corresponding path program 31 times [2018-10-27 04:46:59,878 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:46:59,878 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:46:59,879 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:59,879 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:46:59,879 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:46:59,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:00,731 INFO L134 CoverageAnalysis]: Checked inductivity of 69929 backedges. 29329 proven. 3976 refuted. 0 times theorem prover too weak. 36624 trivial. 0 not checked. [2018-10-27 04:47:00,731 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:00,731 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:00,738 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:00,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:00,922 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:01,681 INFO L134 CoverageAnalysis]: Checked inductivity of 69929 backedges. 37042 proven. 494 refuted. 0 times theorem prover too weak. 32393 trivial. 0 not checked. [2018-10-27 04:47:01,698 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:47:01,699 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 30] total 59 [2018-10-27 04:47:01,699 INFO L460 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-10-27 04:47:01,699 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-10-27 04:47:01,700 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=571, Invalid=2851, Unknown=0, NotChecked=0, Total=3422 [2018-10-27 04:47:01,700 INFO L87 Difference]: Start difference. First operand 1271 states and 1292 transitions. Second operand 59 states. [2018-10-27 04:47:03,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:03,167 INFO L93 Difference]: Finished difference Result 1179 states and 1193 transitions. [2018-10-27 04:47:03,169 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-10-27 04:47:03,169 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 1088 [2018-10-27 04:47:03,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:03,172 INFO L225 Difference]: With dead ends: 1179 [2018-10-27 04:47:03,172 INFO L226 Difference]: Without dead ends: 1170 [2018-10-27 04:47:03,173 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1162 GetRequests, 1065 SyntacticMatches, 0 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3009 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1631, Invalid=8071, Unknown=0, NotChecked=0, Total=9702 [2018-10-27 04:47:03,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states. [2018-10-27 04:47:03,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1155. [2018-10-27 04:47:03,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1155 states. [2018-10-27 04:47:03,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1155 states to 1155 states and 1168 transitions. [2018-10-27 04:47:03,180 INFO L78 Accepts]: Start accepts. Automaton has 1155 states and 1168 transitions. Word has length 1088 [2018-10-27 04:47:03,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:03,180 INFO L481 AbstractCegarLoop]: Abstraction has 1155 states and 1168 transitions. [2018-10-27 04:47:03,180 INFO L482 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-10-27 04:47:03,181 INFO L276 IsEmpty]: Start isEmpty. Operand 1155 states and 1168 transitions. [2018-10-27 04:47:03,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1101 [2018-10-27 04:47:03,192 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:03,192 INFO L375 BasicCegarLoop]: trace histogram [164, 149, 149, 148, 148, 148, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:03,192 INFO L424 AbstractCegarLoop]: === Iteration 46 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:47:03,192 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:03,193 INFO L82 PathProgramCache]: Analyzing trace with hash -1416827127, now seen corresponding path program 32 times [2018-10-27 04:47:03,193 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:47:03,193 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:47:03,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:03,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:03,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:03,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:04,266 INFO L134 CoverageAnalysis]: Checked inductivity of 71755 backedges. 23633 proven. 4513 refuted. 0 times theorem prover too weak. 43609 trivial. 0 not checked. [2018-10-27 04:47:04,266 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:04,266 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:04,273 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:47:04,454 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:47:04,454 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:47:04,462 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:05,100 INFO L134 CoverageAnalysis]: Checked inductivity of 71755 backedges. 33060 proven. 574 refuted. 0 times theorem prover too weak. 38121 trivial. 0 not checked. [2018-10-27 04:47:05,116 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:47:05,117 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 32] total 52 [2018-10-27 04:47:05,117 INFO L460 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-10-27 04:47:05,118 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-10-27 04:47:05,118 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=539, Invalid=2113, Unknown=0, NotChecked=0, Total=2652 [2018-10-27 04:47:05,118 INFO L87 Difference]: Start difference. First operand 1155 states and 1168 transitions. Second operand 52 states. [2018-10-27 04:47:06,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:06,066 INFO L93 Difference]: Finished difference Result 1176 states and 1187 transitions. [2018-10-27 04:47:06,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-10-27 04:47:06,067 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 1100 [2018-10-27 04:47:06,068 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:06,069 INFO L225 Difference]: With dead ends: 1176 [2018-10-27 04:47:06,069 INFO L226 Difference]: Without dead ends: 1170 [2018-10-27 04:47:06,070 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1168 GetRequests, 1086 SyntacticMatches, 0 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2103 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1523, Invalid=5449, Unknown=0, NotChecked=0, Total=6972 [2018-10-27 04:47:06,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states. [2018-10-27 04:47:06,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1155. [2018-10-27 04:47:06,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1155 states. [2018-10-27 04:47:06,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1155 states to 1155 states and 1165 transitions. [2018-10-27 04:47:06,078 INFO L78 Accepts]: Start accepts. Automaton has 1155 states and 1165 transitions. Word has length 1100 [2018-10-27 04:47:06,078 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:06,078 INFO L481 AbstractCegarLoop]: Abstraction has 1155 states and 1165 transitions. [2018-10-27 04:47:06,078 INFO L482 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-10-27 04:47:06,078 INFO L276 IsEmpty]: Start isEmpty. Operand 1155 states and 1165 transitions. [2018-10-27 04:47:06,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1113 [2018-10-27 04:47:06,084 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:06,085 INFO L375 BasicCegarLoop]: trace histogram [166, 151, 151, 150, 150, 150, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:06,085 INFO L424 AbstractCegarLoop]: === Iteration 47 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:47:06,085 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:06,085 INFO L82 PathProgramCache]: Analyzing trace with hash 1601893321, now seen corresponding path program 33 times [2018-10-27 04:47:06,085 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:47:06,085 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:47:06,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:06,086 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:47:06,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:06,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:07,540 INFO L134 CoverageAnalysis]: Checked inductivity of 73605 backedges. 25885 proven. 3402 refuted. 0 times theorem prover too weak. 44318 trivial. 0 not checked. [2018-10-27 04:47:07,540 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:07,540 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:07,546 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:47:07,834 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-10-27 04:47:07,834 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:47:07,841 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:08,957 INFO L134 CoverageAnalysis]: Checked inductivity of 73605 backedges. 24744 proven. 2164 refuted. 0 times theorem prover too weak. 46697 trivial. 0 not checked. [2018-10-27 04:47:08,974 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:47:08,974 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 39] total 74 [2018-10-27 04:47:08,975 INFO L460 AbstractCegarLoop]: Interpolant automaton has 74 states [2018-10-27 04:47:08,975 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2018-10-27 04:47:08,975 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=768, Invalid=4634, Unknown=0, NotChecked=0, Total=5402 [2018-10-27 04:47:08,976 INFO L87 Difference]: Start difference. First operand 1155 states and 1165 transitions. Second operand 74 states. [2018-10-27 04:47:11,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:11,235 INFO L93 Difference]: Finished difference Result 1179 states and 1185 transitions. [2018-10-27 04:47:11,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-10-27 04:47:11,236 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 1112 [2018-10-27 04:47:11,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:11,239 INFO L225 Difference]: With dead ends: 1179 [2018-10-27 04:47:11,239 INFO L226 Difference]: Without dead ends: 1173 [2018-10-27 04:47:11,240 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1231 GetRequests, 1078 SyntacticMatches, 0 SemanticMatches, 153 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8097 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=3309, Invalid=20561, Unknown=0, NotChecked=0, Total=23870 [2018-10-27 04:47:11,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1173 states. [2018-10-27 04:47:11,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1173 to 1152. [2018-10-27 04:47:11,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1152 states. [2018-10-27 04:47:11,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1152 states to 1152 states and 1158 transitions. [2018-10-27 04:47:11,251 INFO L78 Accepts]: Start accepts. Automaton has 1152 states and 1158 transitions. Word has length 1112 [2018-10-27 04:47:11,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:11,251 INFO L481 AbstractCegarLoop]: Abstraction has 1152 states and 1158 transitions. [2018-10-27 04:47:11,251 INFO L482 AbstractCegarLoop]: Interpolant automaton has 74 states. [2018-10-27 04:47:11,251 INFO L276 IsEmpty]: Start isEmpty. Operand 1152 states and 1158 transitions. [2018-10-27 04:47:11,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1119 [2018-10-27 04:47:11,257 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:11,258 INFO L375 BasicCegarLoop]: trace histogram [167, 152, 152, 151, 151, 151, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:11,258 INFO L424 AbstractCegarLoop]: === Iteration 48 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:47:11,258 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:11,258 INFO L82 PathProgramCache]: Analyzing trace with hash 923652993, now seen corresponding path program 34 times [2018-10-27 04:47:11,258 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:47:11,258 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:47:11,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:11,259 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:47:11,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:11,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:12,265 INFO L134 CoverageAnalysis]: Checked inductivity of 74539 backedges. 14025 proven. 784 refuted. 0 times theorem prover too weak. 59730 trivial. 0 not checked. [2018-10-27 04:47:12,265 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:12,266 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:12,272 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:47:12,549 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:47:12,549 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:47:12,560 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:12,564 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:12,565 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:12,573 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:12,573 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:14,499 INFO L134 CoverageAnalysis]: Checked inductivity of 74539 backedges. 14025 proven. 784 refuted. 0 times theorem prover too weak. 59730 trivial. 0 not checked. [2018-10-27 04:47:14,519 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:47:14,519 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 38 [2018-10-27 04:47:14,520 INFO L460 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-10-27 04:47:14,520 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-10-27 04:47:14,520 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=401, Invalid=1081, Unknown=0, NotChecked=0, Total=1482 [2018-10-27 04:47:14,520 INFO L87 Difference]: Start difference. First operand 1152 states and 1158 transitions. Second operand 39 states. [2018-10-27 04:47:15,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:15,400 INFO L93 Difference]: Finished difference Result 1178 states and 1185 transitions. [2018-10-27 04:47:15,401 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-10-27 04:47:15,401 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 1118 [2018-10-27 04:47:15,402 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:15,403 INFO L225 Difference]: With dead ends: 1178 [2018-10-27 04:47:15,403 INFO L226 Difference]: Without dead ends: 1178 [2018-10-27 04:47:15,404 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1156 GetRequests, 1069 SyntacticMatches, 33 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 881 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=655, Invalid=2425, Unknown=0, NotChecked=0, Total=3080 [2018-10-27 04:47:15,404 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1178 states. [2018-10-27 04:47:15,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1178 to 1158. [2018-10-27 04:47:15,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1158 states. [2018-10-27 04:47:15,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1158 states to 1158 states and 1165 transitions. [2018-10-27 04:47:15,411 INFO L78 Accepts]: Start accepts. Automaton has 1158 states and 1165 transitions. Word has length 1118 [2018-10-27 04:47:15,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:15,412 INFO L481 AbstractCegarLoop]: Abstraction has 1158 states and 1165 transitions. [2018-10-27 04:47:15,412 INFO L482 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-10-27 04:47:15,412 INFO L276 IsEmpty]: Start isEmpty. Operand 1158 states and 1165 transitions. [2018-10-27 04:47:15,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1125 [2018-10-27 04:47:15,418 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:15,418 INFO L375 BasicCegarLoop]: trace histogram [168, 153, 153, 152, 152, 152, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:15,418 INFO L424 AbstractCegarLoop]: === Iteration 49 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:47:15,419 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:15,419 INFO L82 PathProgramCache]: Analyzing trace with hash 409730697, now seen corresponding path program 35 times [2018-10-27 04:47:15,419 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:47:15,419 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:47:15,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:15,419 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:47:15,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:15,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:16,337 INFO L134 CoverageAnalysis]: Checked inductivity of 75479 backedges. 15699 proven. 830 refuted. 0 times theorem prover too weak. 58950 trivial. 0 not checked. [2018-10-27 04:47:16,337 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:16,338 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:16,346 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:47:17,336 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 32 check-sat command(s) [2018-10-27 04:47:17,336 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:47:17,349 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:18,256 INFO L134 CoverageAnalysis]: Checked inductivity of 75479 backedges. 15550 proven. 2977 refuted. 0 times theorem prover too weak. 56952 trivial. 0 not checked. [2018-10-27 04:47:18,275 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:47:18,276 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 42] total 61 [2018-10-27 04:47:18,277 INFO L460 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-10-27 04:47:18,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-10-27 04:47:18,277 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=754, Invalid=2906, Unknown=0, NotChecked=0, Total=3660 [2018-10-27 04:47:18,277 INFO L87 Difference]: Start difference. First operand 1158 states and 1165 transitions. Second operand 61 states. [2018-10-27 04:47:19,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:19,755 INFO L93 Difference]: Finished difference Result 1295 states and 1303 transitions. [2018-10-27 04:47:19,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-10-27 04:47:19,756 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 1124 [2018-10-27 04:47:19,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:19,759 INFO L225 Difference]: With dead ends: 1295 [2018-10-27 04:47:19,759 INFO L226 Difference]: Without dead ends: 1295 [2018-10-27 04:47:19,759 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1196 GetRequests, 1102 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1715 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2025, Invalid=7095, Unknown=0, NotChecked=0, Total=9120 [2018-10-27 04:47:19,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1295 states. [2018-10-27 04:47:19,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1295 to 1273. [2018-10-27 04:47:19,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1273 states. [2018-10-27 04:47:19,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1273 states to 1273 states and 1281 transitions. [2018-10-27 04:47:19,769 INFO L78 Accepts]: Start accepts. Automaton has 1273 states and 1281 transitions. Word has length 1124 [2018-10-27 04:47:19,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:19,770 INFO L481 AbstractCegarLoop]: Abstraction has 1273 states and 1281 transitions. [2018-10-27 04:47:19,770 INFO L482 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-10-27 04:47:19,770 INFO L276 IsEmpty]: Start isEmpty. Operand 1273 states and 1281 transitions. [2018-10-27 04:47:19,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1234 [2018-10-27 04:47:19,776 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:19,777 INFO L375 BasicCegarLoop]: trace histogram [185, 169, 169, 168, 168, 168, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:19,777 INFO L424 AbstractCegarLoop]: === Iteration 50 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:47:19,777 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:19,777 INFO L82 PathProgramCache]: Analyzing trace with hash 756348190, now seen corresponding path program 36 times [2018-10-27 04:47:19,777 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:47:19,778 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:47:19,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:19,778 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:47:19,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:19,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:21,001 INFO L134 CoverageAnalysis]: Checked inductivity of 91872 backedges. 41783 proven. 2493 refuted. 0 times theorem prover too weak. 47596 trivial. 0 not checked. [2018-10-27 04:47:21,001 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:21,001 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:21,009 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-10-27 04:47:23,106 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 30 check-sat command(s) [2018-10-27 04:47:23,106 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:47:23,119 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:23,122 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:23,122 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:23,132 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:23,133 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:25,981 INFO L134 CoverageAnalysis]: Checked inductivity of 91872 backedges. 16598 proven. 922 refuted. 0 times theorem prover too weak. 74352 trivial. 0 not checked. [2018-10-27 04:47:26,000 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:47:26,000 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 24] total 63 [2018-10-27 04:47:26,001 INFO L460 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-10-27 04:47:26,001 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-10-27 04:47:26,001 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=556, Invalid=3350, Unknown=0, NotChecked=0, Total=3906 [2018-10-27 04:47:26,002 INFO L87 Difference]: Start difference. First operand 1273 states and 1281 transitions. Second operand 63 states. [2018-10-27 04:47:28,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:28,940 INFO L93 Difference]: Finished difference Result 1428 states and 1436 transitions. [2018-10-27 04:47:28,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2018-10-27 04:47:28,941 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 1233 [2018-10-27 04:47:28,942 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:28,944 INFO L225 Difference]: With dead ends: 1428 [2018-10-27 04:47:28,944 INFO L226 Difference]: Without dead ends: 1419 [2018-10-27 04:47:28,945 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1337 GetRequests, 1181 SyntacticMatches, 31 SemanticMatches, 125 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6054 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=2191, Invalid=13811, Unknown=0, NotChecked=0, Total=16002 [2018-10-27 04:47:28,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1419 states. [2018-10-27 04:47:28,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1419 to 1388. [2018-10-27 04:47:28,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1388 states. [2018-10-27 04:47:28,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1388 states to 1388 states and 1395 transitions. [2018-10-27 04:47:28,953 INFO L78 Accepts]: Start accepts. Automaton has 1388 states and 1395 transitions. Word has length 1233 [2018-10-27 04:47:28,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:28,954 INFO L481 AbstractCegarLoop]: Abstraction has 1388 states and 1395 transitions. [2018-10-27 04:47:28,954 INFO L482 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-10-27 04:47:28,954 INFO L276 IsEmpty]: Start isEmpty. Operand 1388 states and 1395 transitions. [2018-10-27 04:47:28,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1355 [2018-10-27 04:47:28,962 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:28,962 INFO L375 BasicCegarLoop]: trace histogram [204, 187, 187, 186, 186, 186, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:28,962 INFO L424 AbstractCegarLoop]: === Iteration 51 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:47:28,963 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:28,963 INFO L82 PathProgramCache]: Analyzing trace with hash 1528311145, now seen corresponding path program 37 times [2018-10-27 04:47:28,963 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:47:28,963 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:47:28,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:28,964 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:47:28,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:29,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:30,100 INFO L134 CoverageAnalysis]: Checked inductivity of 112168 backedges. 35680 proven. 4314 refuted. 0 times theorem prover too weak. 72174 trivial. 0 not checked. [2018-10-27 04:47:30,100 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:30,100 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:30,108 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:30,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:30,337 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:31,243 INFO L134 CoverageAnalysis]: Checked inductivity of 112168 backedges. 35978 proven. 850 refuted. 0 times theorem prover too weak. 75340 trivial. 0 not checked. [2018-10-27 04:47:31,259 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:47:31,260 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 38] total 61 [2018-10-27 04:47:31,261 INFO L460 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-10-27 04:47:31,261 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-10-27 04:47:31,261 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=752, Invalid=2908, Unknown=0, NotChecked=0, Total=3660 [2018-10-27 04:47:31,261 INFO L87 Difference]: Start difference. First operand 1388 states and 1395 transitions. Second operand 61 states. [2018-10-27 04:47:32,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:32,153 INFO L93 Difference]: Finished difference Result 1428 states and 1435 transitions. [2018-10-27 04:47:32,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-10-27 04:47:32,154 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 1354 [2018-10-27 04:47:32,155 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:32,156 INFO L225 Difference]: With dead ends: 1428 [2018-10-27 04:47:32,157 INFO L226 Difference]: Without dead ends: 1422 [2018-10-27 04:47:32,157 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1435 GetRequests, 1338 SyntacticMatches, 0 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3039 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2120, Invalid=7582, Unknown=0, NotChecked=0, Total=9702 [2018-10-27 04:47:32,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1422 states. [2018-10-27 04:47:32,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1422 to 1398. [2018-10-27 04:47:32,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1398 states. [2018-10-27 04:47:32,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1398 states to 1398 states and 1405 transitions. [2018-10-27 04:47:32,165 INFO L78 Accepts]: Start accepts. Automaton has 1398 states and 1405 transitions. Word has length 1354 [2018-10-27 04:47:32,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:32,166 INFO L481 AbstractCegarLoop]: Abstraction has 1398 states and 1405 transitions. [2018-10-27 04:47:32,166 INFO L482 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-10-27 04:47:32,166 INFO L276 IsEmpty]: Start isEmpty. Operand 1398 states and 1405 transitions. [2018-10-27 04:47:32,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1361 [2018-10-27 04:47:32,174 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:32,174 INFO L375 BasicCegarLoop]: trace histogram [205, 188, 188, 187, 187, 187, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:32,175 INFO L424 AbstractCegarLoop]: === Iteration 52 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:47:32,175 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:32,175 INFO L82 PathProgramCache]: Analyzing trace with hash -275082975, now seen corresponding path program 38 times [2018-10-27 04:47:32,175 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:47:32,175 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:47:32,176 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:32,176 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:47:32,176 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:32,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:33,519 INFO L134 CoverageAnalysis]: Checked inductivity of 113322 backedges. 18649 proven. 884 refuted. 0 times theorem prover too weak. 93789 trivial. 0 not checked. [2018-10-27 04:47:33,519 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:33,519 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:33,526 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:47:33,752 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:47:33,752 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:47:33,763 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:33,764 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:33,765 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:33,773 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:33,773 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:36,174 INFO L134 CoverageAnalysis]: Checked inductivity of 113322 backedges. 18649 proven. 884 refuted. 0 times theorem prover too weak. 93789 trivial. 0 not checked. [2018-10-27 04:47:36,191 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:47:36,192 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 40 [2018-10-27 04:47:36,192 INFO L460 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-10-27 04:47:36,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-10-27 04:47:36,193 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=442, Invalid=1198, Unknown=0, NotChecked=0, Total=1640 [2018-10-27 04:47:36,193 INFO L87 Difference]: Start difference. First operand 1398 states and 1405 transitions. Second operand 41 states. [2018-10-27 04:47:37,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:37,239 INFO L93 Difference]: Finished difference Result 1421 states and 1428 transitions. [2018-10-27 04:47:37,240 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-10-27 04:47:37,240 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 1360 [2018-10-27 04:47:37,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:37,243 INFO L225 Difference]: With dead ends: 1421 [2018-10-27 04:47:37,243 INFO L226 Difference]: Without dead ends: 1421 [2018-10-27 04:47:37,243 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1400 GetRequests, 1306 SyntacticMatches, 37 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 990 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=720, Invalid=2702, Unknown=0, NotChecked=0, Total=3422 [2018-10-27 04:47:37,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1421 states. [2018-10-27 04:47:37,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1421 to 1400. [2018-10-27 04:47:37,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1400 states. [2018-10-27 04:47:37,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1400 states to 1400 states and 1407 transitions. [2018-10-27 04:47:37,252 INFO L78 Accepts]: Start accepts. Automaton has 1400 states and 1407 transitions. Word has length 1360 [2018-10-27 04:47:37,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:37,252 INFO L481 AbstractCegarLoop]: Abstraction has 1400 states and 1407 transitions. [2018-10-27 04:47:37,252 INFO L482 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-10-27 04:47:37,253 INFO L276 IsEmpty]: Start isEmpty. Operand 1400 states and 1407 transitions. [2018-10-27 04:47:37,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1367 [2018-10-27 04:47:37,261 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:37,261 INFO L375 BasicCegarLoop]: trace histogram [206, 189, 189, 188, 188, 188, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:37,261 INFO L424 AbstractCegarLoop]: === Iteration 53 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:47:37,261 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:37,262 INFO L82 PathProgramCache]: Analyzing trace with hash 1100743721, now seen corresponding path program 39 times [2018-10-27 04:47:37,262 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:47:37,262 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:47:37,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:37,262 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:47:37,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:37,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:38,664 INFO L134 CoverageAnalysis]: Checked inductivity of 114482 backedges. 19703 proven. 990 refuted. 0 times theorem prover too weak. 93789 trivial. 0 not checked. [2018-10-27 04:47:38,665 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:38,665 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:38,677 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:47:38,988 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 19 check-sat command(s) [2018-10-27 04:47:38,988 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:47:38,997 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:39,000 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:39,000 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,009 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:39,009 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:41,231 INFO L134 CoverageAnalysis]: Checked inductivity of 114482 backedges. 19703 proven. 990 refuted. 0 times theorem prover too weak. 93789 trivial. 0 not checked. [2018-10-27 04:47:41,247 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:47:41,248 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24] total 25 [2018-10-27 04:47:41,248 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-10-27 04:47:41,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-10-27 04:47:41,249 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=264, Invalid=386, Unknown=0, NotChecked=0, Total=650 [2018-10-27 04:47:41,249 INFO L87 Difference]: Start difference. First operand 1400 states and 1407 transitions. Second operand 26 states. [2018-10-27 04:47:41,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:41,774 INFO L93 Difference]: Finished difference Result 1439 states and 1448 transitions. [2018-10-27 04:47:41,776 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-10-27 04:47:41,776 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 1366 [2018-10-27 04:47:41,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:41,779 INFO L225 Difference]: With dead ends: 1439 [2018-10-27 04:47:41,779 INFO L226 Difference]: Without dead ends: 1439 [2018-10-27 04:47:41,779 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1408 GetRequests, 1328 SyntacticMatches, 37 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 314 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=721, Invalid=1259, Unknown=0, NotChecked=0, Total=1980 [2018-10-27 04:47:41,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1439 states. [2018-10-27 04:47:41,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1439 to 1406. [2018-10-27 04:47:41,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1406 states. [2018-10-27 04:47:41,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1406 states to 1406 states and 1414 transitions. [2018-10-27 04:47:41,792 INFO L78 Accepts]: Start accepts. Automaton has 1406 states and 1414 transitions. Word has length 1366 [2018-10-27 04:47:41,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:41,793 INFO L481 AbstractCegarLoop]: Abstraction has 1406 states and 1414 transitions. [2018-10-27 04:47:41,793 INFO L482 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-10-27 04:47:41,793 INFO L276 IsEmpty]: Start isEmpty. Operand 1406 states and 1414 transitions. [2018-10-27 04:47:41,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1373 [2018-10-27 04:47:41,801 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:41,801 INFO L375 BasicCegarLoop]: trace histogram [207, 190, 190, 189, 189, 189, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:41,802 INFO L424 AbstractCegarLoop]: === Iteration 54 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:47:41,802 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:41,802 INFO L82 PathProgramCache]: Analyzing trace with hash 1655509297, now seen corresponding path program 40 times [2018-10-27 04:47:41,802 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:47:41,802 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:47:41,803 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:41,803 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:47:41,803 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:41,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:42,864 INFO L134 CoverageAnalysis]: Checked inductivity of 115648 backedges. 21803 proven. 1059 refuted. 0 times theorem prover too weak. 92786 trivial. 0 not checked. [2018-10-27 04:47:42,865 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:42,865 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:42,872 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:47:43,070 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:47:43,070 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:47:43,079 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:44,177 INFO L134 CoverageAnalysis]: Checked inductivity of 115648 backedges. 21859 proven. 1003 refuted. 0 times theorem prover too weak. 92786 trivial. 0 not checked. [2018-10-27 04:47:44,194 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:47:44,194 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 41] total 63 [2018-10-27 04:47:44,195 INFO L460 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-10-27 04:47:44,195 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-10-27 04:47:44,195 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=904, Invalid=3002, Unknown=0, NotChecked=0, Total=3906 [2018-10-27 04:47:44,195 INFO L87 Difference]: Start difference. First operand 1406 states and 1414 transitions. Second operand 63 states. [2018-10-27 04:47:45,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:45,464 INFO L93 Difference]: Finished difference Result 1564 states and 1573 transitions. [2018-10-27 04:47:45,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-10-27 04:47:45,465 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 1372 [2018-10-27 04:47:45,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:45,468 INFO L225 Difference]: With dead ends: 1564 [2018-10-27 04:47:45,468 INFO L226 Difference]: Without dead ends: 1564 [2018-10-27 04:47:45,469 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1450 GetRequests, 1352 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1646 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=2529, Invalid=7371, Unknown=0, NotChecked=0, Total=9900 [2018-10-27 04:47:45,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1564 states. [2018-10-27 04:47:45,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1564 to 1539. [2018-10-27 04:47:45,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1539 states. [2018-10-27 04:47:45,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1539 states to 1539 states and 1548 transitions. [2018-10-27 04:47:45,483 INFO L78 Accepts]: Start accepts. Automaton has 1539 states and 1548 transitions. Word has length 1372 [2018-10-27 04:47:45,484 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:45,486 INFO L481 AbstractCegarLoop]: Abstraction has 1539 states and 1548 transitions. [2018-10-27 04:47:45,486 INFO L482 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-10-27 04:47:45,486 INFO L276 IsEmpty]: Start isEmpty. Operand 1539 states and 1548 transitions. [2018-10-27 04:47:45,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1494 [2018-10-27 04:47:45,503 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:45,503 INFO L375 BasicCegarLoop]: trace histogram [226, 208, 208, 207, 207, 207, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:45,504 INFO L424 AbstractCegarLoop]: === Iteration 55 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:47:45,504 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:45,504 INFO L82 PathProgramCache]: Analyzing trace with hash -230687738, now seen corresponding path program 41 times [2018-10-27 04:47:45,504 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:47:45,504 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:47:45,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:45,505 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:47:45,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:45,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:46,837 INFO L134 CoverageAnalysis]: Checked inductivity of 138303 backedges. 58711 proven. 3129 refuted. 0 times theorem prover too weak. 76463 trivial. 0 not checked. [2018-10-27 04:47:46,837 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:46,837 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:46,844 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:47:48,671 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 43 check-sat command(s) [2018-10-27 04:47:48,671 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:47:48,689 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:50,146 INFO L134 CoverageAnalysis]: Checked inductivity of 138303 backedges. 43131 proven. 4804 refuted. 0 times theorem prover too weak. 90368 trivial. 0 not checked. [2018-10-27 04:47:50,166 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:47:50,166 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 82 [2018-10-27 04:47:50,167 INFO L460 AbstractCegarLoop]: Interpolant automaton has 82 states [2018-10-27 04:47:50,168 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2018-10-27 04:47:50,168 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1013, Invalid=5629, Unknown=0, NotChecked=0, Total=6642 [2018-10-27 04:47:50,168 INFO L87 Difference]: Start difference. First operand 1539 states and 1548 transitions. Second operand 82 states. [2018-10-27 04:47:52,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:52,630 INFO L93 Difference]: Finished difference Result 1565 states and 1572 transitions. [2018-10-27 04:47:52,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 79 states. [2018-10-27 04:47:52,631 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 1493 [2018-10-27 04:47:52,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:52,634 INFO L225 Difference]: With dead ends: 1565 [2018-10-27 04:47:52,635 INFO L226 Difference]: Without dead ends: 1559 [2018-10-27 04:47:52,636 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1595 GetRequests, 1457 SyntacticMatches, 0 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6244 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=3231, Invalid=16229, Unknown=0, NotChecked=0, Total=19460 [2018-10-27 04:47:52,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1559 states. [2018-10-27 04:47:52,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1559 to 1539. [2018-10-27 04:47:52,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1539 states. [2018-10-27 04:47:52,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1539 states to 1539 states and 1546 transitions. [2018-10-27 04:47:52,646 INFO L78 Accepts]: Start accepts. Automaton has 1539 states and 1546 transitions. Word has length 1493 [2018-10-27 04:47:52,646 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:52,647 INFO L481 AbstractCegarLoop]: Abstraction has 1539 states and 1546 transitions. [2018-10-27 04:47:52,647 INFO L482 AbstractCegarLoop]: Interpolant automaton has 82 states. [2018-10-27 04:47:52,647 INFO L276 IsEmpty]: Start isEmpty. Operand 1539 states and 1546 transitions. [2018-10-27 04:47:52,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1500 [2018-10-27 04:47:52,656 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:52,657 INFO L375 BasicCegarLoop]: trace histogram [227, 209, 209, 208, 208, 208, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:52,657 INFO L424 AbstractCegarLoop]: === Iteration 56 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:47:52,657 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:52,657 INFO L82 PathProgramCache]: Analyzing trace with hash -524440066, now seen corresponding path program 42 times [2018-10-27 04:47:52,657 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:47:52,658 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:47:52,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:52,658 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:47:52,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:52,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:47:54,121 INFO L134 CoverageAnalysis]: Checked inductivity of 139585 backedges. 23040 proven. 1102 refuted. 0 times theorem prover too weak. 115443 trivial. 0 not checked. [2018-10-27 04:47:54,121 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:47:54,121 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:47:54,128 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-10-27 04:47:55,728 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 39 check-sat command(s) [2018-10-27 04:47:55,729 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:47:55,744 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:47:55,746 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:47:55,746 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:47:55,756 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:47:55,756 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:47:58,596 INFO L134 CoverageAnalysis]: Checked inductivity of 139585 backedges. 23040 proven. 1102 refuted. 0 times theorem prover too weak. 115443 trivial. 0 not checked. [2018-10-27 04:47:58,614 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:47:58,615 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 44 [2018-10-27 04:47:58,616 INFO L460 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-10-27 04:47:58,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-10-27 04:47:58,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=530, Invalid=1450, Unknown=0, NotChecked=0, Total=1980 [2018-10-27 04:47:58,616 INFO L87 Difference]: Start difference. First operand 1539 states and 1546 transitions. Second operand 45 states. [2018-10-27 04:47:59,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:47:59,838 INFO L93 Difference]: Finished difference Result 1568 states and 1576 transitions. [2018-10-27 04:47:59,839 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-10-27 04:47:59,839 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 1499 [2018-10-27 04:47:59,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:47:59,842 INFO L225 Difference]: With dead ends: 1568 [2018-10-27 04:47:59,842 INFO L226 Difference]: Without dead ends: 1568 [2018-10-27 04:47:59,842 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1543 GetRequests, 1441 SyntacticMatches, 39 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1217 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=859, Invalid=3301, Unknown=0, NotChecked=0, Total=4160 [2018-10-27 04:47:59,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1568 states. [2018-10-27 04:47:59,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1568 to 1545. [2018-10-27 04:47:59,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1545 states. [2018-10-27 04:47:59,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1545 states to 1545 states and 1553 transitions. [2018-10-27 04:47:59,850 INFO L78 Accepts]: Start accepts. Automaton has 1545 states and 1553 transitions. Word has length 1499 [2018-10-27 04:47:59,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:47:59,851 INFO L481 AbstractCegarLoop]: Abstraction has 1545 states and 1553 transitions. [2018-10-27 04:47:59,851 INFO L482 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-10-27 04:47:59,851 INFO L276 IsEmpty]: Start isEmpty. Operand 1545 states and 1553 transitions. [2018-10-27 04:47:59,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1506 [2018-10-27 04:47:59,860 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:47:59,861 INFO L375 BasicCegarLoop]: trace histogram [228, 210, 210, 209, 209, 209, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:47:59,861 INFO L424 AbstractCegarLoop]: === Iteration 57 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:47:59,861 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:47:59,861 INFO L82 PathProgramCache]: Analyzing trace with hash 1706772294, now seen corresponding path program 43 times [2018-10-27 04:47:59,862 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:47:59,862 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:47:59,862 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:59,862 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:47:59,862 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:47:59,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:01,085 INFO L134 CoverageAnalysis]: Checked inductivity of 140873 backedges. 25371 proven. 1184 refuted. 0 times theorem prover too weak. 114318 trivial. 0 not checked. [2018-10-27 04:48:01,085 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:01,085 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:01,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:48:01,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:01,347 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:02,588 INFO L134 CoverageAnalysis]: Checked inductivity of 140873 backedges. 25430 proven. 1125 refuted. 0 times theorem prover too weak. 114318 trivial. 0 not checked. [2018-10-27 04:48:02,605 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:02,605 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 43] total 66 [2018-10-27 04:48:02,606 INFO L460 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-10-27 04:48:02,606 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-10-27 04:48:02,607 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=991, Invalid=3299, Unknown=0, NotChecked=0, Total=4290 [2018-10-27 04:48:02,607 INFO L87 Difference]: Start difference. First operand 1545 states and 1553 transitions. Second operand 66 states. [2018-10-27 04:48:03,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:03,924 INFO L93 Difference]: Finished difference Result 1703 states and 1712 transitions. [2018-10-27 04:48:03,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-10-27 04:48:03,925 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 1505 [2018-10-27 04:48:03,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:03,928 INFO L225 Difference]: With dead ends: 1703 [2018-10-27 04:48:03,928 INFO L226 Difference]: Without dead ends: 1703 [2018-10-27 04:48:03,929 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1587 GetRequests, 1484 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1823 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2782, Invalid=8138, Unknown=0, NotChecked=0, Total=10920 [2018-10-27 04:48:03,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1703 states. [2018-10-27 04:48:03,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1703 to 1678. [2018-10-27 04:48:03,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1678 states. [2018-10-27 04:48:03,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1678 states to 1678 states and 1687 transitions. [2018-10-27 04:48:03,937 INFO L78 Accepts]: Start accepts. Automaton has 1678 states and 1687 transitions. Word has length 1505 [2018-10-27 04:48:03,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:03,938 INFO L481 AbstractCegarLoop]: Abstraction has 1678 states and 1687 transitions. [2018-10-27 04:48:03,938 INFO L482 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-10-27 04:48:03,938 INFO L276 IsEmpty]: Start isEmpty. Operand 1678 states and 1687 transitions. [2018-10-27 04:48:03,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1633 [2018-10-27 04:48:03,948 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:03,949 INFO L375 BasicCegarLoop]: trace histogram [248, 229, 229, 228, 228, 228, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:03,949 INFO L424 AbstractCegarLoop]: === Iteration 58 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:48:03,949 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:03,949 INFO L82 PathProgramCache]: Analyzing trace with hash 1505063577, now seen corresponding path program 44 times [2018-10-27 04:48:03,950 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:48:03,950 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:48:03,950 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:03,950 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:48:03,950 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:04,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:05,930 INFO L134 CoverageAnalysis]: Checked inductivity of 167181 backedges. 50223 proven. 5330 refuted. 0 times theorem prover too weak. 111628 trivial. 0 not checked. [2018-10-27 04:48:05,930 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:05,930 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:05,937 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:48:06,204 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:48:06,204 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:48:06,217 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:07,383 INFO L134 CoverageAnalysis]: Checked inductivity of 167181 backedges. 50561 proven. 1064 refuted. 0 times theorem prover too weak. 115556 trivial. 0 not checked. [2018-10-27 04:48:07,401 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:07,402 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 42] total 67 [2018-10-27 04:48:07,402 INFO L460 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-10-27 04:48:07,403 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-10-27 04:48:07,403 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=914, Invalid=3508, Unknown=0, NotChecked=0, Total=4422 [2018-10-27 04:48:07,403 INFO L87 Difference]: Start difference. First operand 1678 states and 1687 transitions. Second operand 67 states. [2018-10-27 04:48:08,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:08,863 INFO L93 Difference]: Finished difference Result 1704 states and 1711 transitions. [2018-10-27 04:48:08,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2018-10-27 04:48:08,864 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 1632 [2018-10-27 04:48:08,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:08,867 INFO L225 Difference]: With dead ends: 1704 [2018-10-27 04:48:08,867 INFO L226 Difference]: Without dead ends: 1698 [2018-10-27 04:48:08,868 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1720 GetRequests, 1613 SyntacticMatches, 0 SemanticMatches, 107 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3758 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=2573, Invalid=9199, Unknown=0, NotChecked=0, Total=11772 [2018-10-27 04:48:08,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1698 states. [2018-10-27 04:48:08,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1698 to 1678. [2018-10-27 04:48:08,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1678 states. [2018-10-27 04:48:08,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1678 states to 1678 states and 1685 transitions. [2018-10-27 04:48:08,879 INFO L78 Accepts]: Start accepts. Automaton has 1678 states and 1685 transitions. Word has length 1632 [2018-10-27 04:48:08,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:08,879 INFO L481 AbstractCegarLoop]: Abstraction has 1678 states and 1685 transitions. [2018-10-27 04:48:08,879 INFO L482 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-10-27 04:48:08,880 INFO L276 IsEmpty]: Start isEmpty. Operand 1678 states and 1685 transitions. [2018-10-27 04:48:08,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1639 [2018-10-27 04:48:08,901 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:08,901 INFO L375 BasicCegarLoop]: trace histogram [249, 230, 230, 229, 229, 229, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:08,902 INFO L424 AbstractCegarLoop]: === Iteration 59 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:48:08,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:08,902 INFO L82 PathProgramCache]: Analyzing trace with hash -1975982511, now seen corresponding path program 45 times [2018-10-27 04:48:08,902 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:48:08,902 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:48:08,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:08,903 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:48:08,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:08,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:10,592 INFO L134 CoverageAnalysis]: Checked inductivity of 168591 backedges. 26733 proven. 1220 refuted. 0 times theorem prover too weak. 140638 trivial. 0 not checked. [2018-10-27 04:48:10,592 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:10,592 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:10,600 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:48:10,973 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-10-27 04:48:10,973 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:48:10,983 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:10,988 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:10,988 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:10,993 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:10,994 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:48:14,186 INFO L134 CoverageAnalysis]: Checked inductivity of 168591 backedges. 26733 proven. 1220 refuted. 0 times theorem prover too weak. 140638 trivial. 0 not checked. [2018-10-27 04:48:14,203 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:14,203 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26] total 27 [2018-10-27 04:48:14,204 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-10-27 04:48:14,204 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-10-27 04:48:14,205 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=445, Unknown=0, NotChecked=0, Total=756 [2018-10-27 04:48:14,205 INFO L87 Difference]: Start difference. First operand 1678 states and 1685 transitions. Second operand 28 states. [2018-10-27 04:48:14,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:14,785 INFO L93 Difference]: Finished difference Result 1707 states and 1715 transitions. [2018-10-27 04:48:14,786 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-10-27 04:48:14,786 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 1638 [2018-10-27 04:48:14,787 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:14,790 INFO L225 Difference]: With dead ends: 1707 [2018-10-27 04:48:14,790 INFO L226 Difference]: Without dead ends: 1707 [2018-10-27 04:48:14,790 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1684 GetRequests, 1596 SyntacticMatches, 41 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 369 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=858, Invalid=1494, Unknown=0, NotChecked=0, Total=2352 [2018-10-27 04:48:14,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1707 states. [2018-10-27 04:48:14,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1707 to 1684. [2018-10-27 04:48:14,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1684 states. [2018-10-27 04:48:14,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1684 states to 1684 states and 1692 transitions. [2018-10-27 04:48:14,806 INFO L78 Accepts]: Start accepts. Automaton has 1684 states and 1692 transitions. Word has length 1638 [2018-10-27 04:48:14,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:14,807 INFO L481 AbstractCegarLoop]: Abstraction has 1684 states and 1692 transitions. [2018-10-27 04:48:14,807 INFO L482 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-10-27 04:48:14,807 INFO L276 IsEmpty]: Start isEmpty. Operand 1684 states and 1692 transitions. [2018-10-27 04:48:14,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1645 [2018-10-27 04:48:14,827 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:14,827 INFO L375 BasicCegarLoop]: trace histogram [250, 231, 231, 230, 230, 230, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:14,827 INFO L424 AbstractCegarLoop]: === Iteration 60 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:48:14,828 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:14,828 INFO L82 PathProgramCache]: Analyzing trace with hash 1251063129, now seen corresponding path program 46 times [2018-10-27 04:48:14,831 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:48:14,831 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:48:14,832 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:14,832 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:48:14,832 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:14,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:16,246 INFO L134 CoverageAnalysis]: Checked inductivity of 170007 backedges. 29307 proven. 1316 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-10-27 04:48:16,246 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:16,246 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:16,254 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:48:16,489 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:48:16,489 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:48:16,500 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:17,926 INFO L134 CoverageAnalysis]: Checked inductivity of 170007 backedges. 29369 proven. 1254 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-10-27 04:48:17,943 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:17,943 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 45] total 69 [2018-10-27 04:48:17,944 INFO L460 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-10-27 04:48:17,944 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-10-27 04:48:17,945 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1082, Invalid=3610, Unknown=0, NotChecked=0, Total=4692 [2018-10-27 04:48:17,945 INFO L87 Difference]: Start difference. First operand 1684 states and 1692 transitions. Second operand 69 states. [2018-10-27 04:48:19,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:19,378 INFO L93 Difference]: Finished difference Result 1848 states and 1857 transitions. [2018-10-27 04:48:19,379 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-10-27 04:48:19,379 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 1644 [2018-10-27 04:48:19,380 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:19,383 INFO L225 Difference]: With dead ends: 1848 [2018-10-27 04:48:19,383 INFO L226 Difference]: Without dead ends: 1848 [2018-10-27 04:48:19,384 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1730 GetRequests, 1622 SyntacticMatches, 0 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2009 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=3047, Invalid=8943, Unknown=0, NotChecked=0, Total=11990 [2018-10-27 04:48:19,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1848 states. [2018-10-27 04:48:19,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1848 to 1823. [2018-10-27 04:48:19,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1823 states. [2018-10-27 04:48:19,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1823 states to 1823 states and 1832 transitions. [2018-10-27 04:48:19,399 INFO L78 Accepts]: Start accepts. Automaton has 1823 states and 1832 transitions. Word has length 1644 [2018-10-27 04:48:19,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:19,400 INFO L481 AbstractCegarLoop]: Abstraction has 1823 states and 1832 transitions. [2018-10-27 04:48:19,400 INFO L482 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-10-27 04:48:19,400 INFO L276 IsEmpty]: Start isEmpty. Operand 1823 states and 1832 transitions. [2018-10-27 04:48:19,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1778 [2018-10-27 04:48:19,424 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:19,425 INFO L375 BasicCegarLoop]: trace histogram [271, 251, 251, 250, 250, 250, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:19,425 INFO L424 AbstractCegarLoop]: === Iteration 61 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:48:19,425 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:19,426 INFO L82 PathProgramCache]: Analyzing trace with hash -248086162, now seen corresponding path program 47 times [2018-10-27 04:48:19,426 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:48:19,426 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:48:19,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:19,426 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:48:19,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:19,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:21,204 INFO L134 CoverageAnalysis]: Checked inductivity of 200340 backedges. 79679 proven. 3837 refuted. 0 times theorem prover too weak. 116824 trivial. 0 not checked. [2018-10-27 04:48:21,204 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:21,205 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:21,212 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:48:23,709 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 54 check-sat command(s) [2018-10-27 04:48:23,709 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:48:23,731 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:25,599 INFO L134 CoverageAnalysis]: Checked inductivity of 200340 backedges. 58047 proven. 7141 refuted. 0 times theorem prover too weak. 135152 trivial. 0 not checked. [2018-10-27 04:48:25,621 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:25,621 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 90 [2018-10-27 04:48:25,622 INFO L460 AbstractCegarLoop]: Interpolant automaton has 90 states [2018-10-27 04:48:25,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2018-10-27 04:48:25,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1212, Invalid=6798, Unknown=0, NotChecked=0, Total=8010 [2018-10-27 04:48:25,623 INFO L87 Difference]: Start difference. First operand 1823 states and 1832 transitions. Second operand 90 states. [2018-10-27 04:48:28,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:28,340 INFO L93 Difference]: Finished difference Result 1849 states and 1856 transitions. [2018-10-27 04:48:28,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2018-10-27 04:48:28,341 INFO L78 Accepts]: Start accepts. Automaton has 90 states. Word has length 1777 [2018-10-27 04:48:28,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:28,344 INFO L225 Difference]: With dead ends: 1849 [2018-10-27 04:48:28,344 INFO L226 Difference]: Without dead ends: 1843 [2018-10-27 04:48:28,346 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1890 GetRequests, 1737 SyntacticMatches, 0 SemanticMatches, 153 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7710 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=3955, Invalid=19915, Unknown=0, NotChecked=0, Total=23870 [2018-10-27 04:48:28,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1843 states. [2018-10-27 04:48:28,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1843 to 1823. [2018-10-27 04:48:28,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1823 states. [2018-10-27 04:48:28,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1823 states to 1823 states and 1830 transitions. [2018-10-27 04:48:28,359 INFO L78 Accepts]: Start accepts. Automaton has 1823 states and 1830 transitions. Word has length 1777 [2018-10-27 04:48:28,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:28,360 INFO L481 AbstractCegarLoop]: Abstraction has 1823 states and 1830 transitions. [2018-10-27 04:48:28,360 INFO L482 AbstractCegarLoop]: Interpolant automaton has 90 states. [2018-10-27 04:48:28,360 INFO L276 IsEmpty]: Start isEmpty. Operand 1823 states and 1830 transitions. [2018-10-27 04:48:28,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1784 [2018-10-27 04:48:28,385 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:28,385 INFO L375 BasicCegarLoop]: trace histogram [272, 252, 252, 251, 251, 251, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:28,385 INFO L424 AbstractCegarLoop]: === Iteration 62 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:48:28,385 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:28,386 INFO L82 PathProgramCache]: Analyzing trace with hash 40631654, now seen corresponding path program 48 times [2018-10-27 04:48:28,386 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:48:28,386 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:48:28,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:28,386 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:48:28,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:28,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:30,296 INFO L134 CoverageAnalysis]: Checked inductivity of 201884 backedges. 30800 proven. 1344 refuted. 0 times theorem prover too weak. 169740 trivial. 0 not checked. [2018-10-27 04:48:30,297 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:30,297 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:30,304 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-10-27 04:48:31,598 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-10-27 04:48:31,599 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:48:31,613 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:31,616 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:31,616 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:31,628 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:31,629 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:48:35,608 INFO L134 CoverageAnalysis]: Checked inductivity of 201884 backedges. 30800 proven. 1344 refuted. 0 times theorem prover too weak. 169740 trivial. 0 not checked. [2018-10-27 04:48:35,627 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:35,627 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 27] total 28 [2018-10-27 04:48:35,628 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-10-27 04:48:35,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-10-27 04:48:35,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=336, Invalid=476, Unknown=0, NotChecked=0, Total=812 [2018-10-27 04:48:35,628 INFO L87 Difference]: Start difference. First operand 1823 states and 1830 transitions. Second operand 29 states. [2018-10-27 04:48:36,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:36,260 INFO L93 Difference]: Finished difference Result 1852 states and 1860 transitions. [2018-10-27 04:48:36,262 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-10-27 04:48:36,262 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 1783 [2018-10-27 04:48:36,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:36,265 INFO L225 Difference]: With dead ends: 1852 [2018-10-27 04:48:36,265 INFO L226 Difference]: Without dead ends: 1852 [2018-10-27 04:48:36,265 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1831 GetRequests, 1739 SyntacticMatches, 43 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 398 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=931, Invalid=1619, Unknown=0, NotChecked=0, Total=2550 [2018-10-27 04:48:36,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1852 states. [2018-10-27 04:48:36,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1852 to 1829. [2018-10-27 04:48:36,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1829 states. [2018-10-27 04:48:36,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1829 states to 1829 states and 1837 transitions. [2018-10-27 04:48:36,279 INFO L78 Accepts]: Start accepts. Automaton has 1829 states and 1837 transitions. Word has length 1783 [2018-10-27 04:48:36,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:36,280 INFO L481 AbstractCegarLoop]: Abstraction has 1829 states and 1837 transitions. [2018-10-27 04:48:36,280 INFO L482 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-10-27 04:48:36,280 INFO L276 IsEmpty]: Start isEmpty. Operand 1829 states and 1837 transitions. [2018-10-27 04:48:36,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1790 [2018-10-27 04:48:36,304 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:36,304 INFO L375 BasicCegarLoop]: trace histogram [273, 253, 253, 252, 252, 252, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:36,305 INFO L424 AbstractCegarLoop]: === Iteration 63 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:48:36,305 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:36,305 INFO L82 PathProgramCache]: Analyzing trace with hash -1766168402, now seen corresponding path program 49 times [2018-10-27 04:48:36,305 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:48:36,305 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:48:36,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:36,306 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:48:36,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:36,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:37,911 INFO L134 CoverageAnalysis]: Checked inductivity of 203434 backedges. 33629 proven. 1455 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-10-27 04:48:37,911 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:37,911 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:37,918 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:48:38,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:38,224 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:39,814 INFO L134 CoverageAnalysis]: Checked inductivity of 203434 backedges. 33694 proven. 1390 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-10-27 04:48:39,832 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:39,833 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 47] total 72 [2018-10-27 04:48:39,833 INFO L460 AbstractCegarLoop]: Interpolant automaton has 72 states [2018-10-27 04:48:39,834 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2018-10-27 04:48:39,834 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1177, Invalid=3935, Unknown=0, NotChecked=0, Total=5112 [2018-10-27 04:48:39,834 INFO L87 Difference]: Start difference. First operand 1829 states and 1837 transitions. Second operand 72 states. [2018-10-27 04:48:41,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:41,339 INFO L93 Difference]: Finished difference Result 1999 states and 2008 transitions. [2018-10-27 04:48:41,340 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-10-27 04:48:41,340 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 1789 [2018-10-27 04:48:41,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:41,344 INFO L225 Difference]: With dead ends: 1999 [2018-10-27 04:48:41,344 INFO L226 Difference]: Without dead ends: 1999 [2018-10-27 04:48:41,346 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1879 GetRequests, 1766 SyntacticMatches, 0 SemanticMatches, 113 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2204 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=3324, Invalid=9786, Unknown=0, NotChecked=0, Total=13110 [2018-10-27 04:48:41,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1999 states. [2018-10-27 04:48:41,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1999 to 1974. [2018-10-27 04:48:41,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1974 states. [2018-10-27 04:48:41,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1974 states to 1974 states and 1983 transitions. [2018-10-27 04:48:41,359 INFO L78 Accepts]: Start accepts. Automaton has 1974 states and 1983 transitions. Word has length 1789 [2018-10-27 04:48:41,359 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:41,360 INFO L481 AbstractCegarLoop]: Abstraction has 1974 states and 1983 transitions. [2018-10-27 04:48:41,360 INFO L482 AbstractCegarLoop]: Interpolant automaton has 72 states. [2018-10-27 04:48:41,360 INFO L276 IsEmpty]: Start isEmpty. Operand 1974 states and 1983 transitions. [2018-10-27 04:48:41,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1929 [2018-10-27 04:48:41,409 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:41,409 INFO L375 BasicCegarLoop]: trace histogram [295, 274, 274, 273, 273, 273, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:41,410 INFO L424 AbstractCegarLoop]: === Iteration 64 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:48:41,410 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:41,410 INFO L82 PathProgramCache]: Analyzing trace with hash -1315607487, now seen corresponding path program 50 times [2018-10-27 04:48:41,410 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:48:41,410 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:48:41,411 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:41,411 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:48:41,411 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:41,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:43,309 INFO L134 CoverageAnalysis]: Checked inductivity of 238182 backedges. 66658 proven. 6450 refuted. 0 times theorem prover too weak. 165074 trivial. 0 not checked. [2018-10-27 04:48:43,309 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:43,309 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:43,318 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:48:43,639 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:48:43,639 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:48:43,654 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:45,229 INFO L134 CoverageAnalysis]: Checked inductivity of 238182 backedges. 67036 proven. 1302 refuted. 0 times theorem prover too weak. 169844 trivial. 0 not checked. [2018-10-27 04:48:45,248 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:45,248 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 46] total 73 [2018-10-27 04:48:45,249 INFO L460 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-10-27 04:48:45,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-10-27 04:48:45,249 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1092, Invalid=4164, Unknown=0, NotChecked=0, Total=5256 [2018-10-27 04:48:45,250 INFO L87 Difference]: Start difference. First operand 1974 states and 1983 transitions. Second operand 73 states. [2018-10-27 04:48:46,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:46,781 INFO L93 Difference]: Finished difference Result 2000 states and 2007 transitions. [2018-10-27 04:48:46,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2018-10-27 04:48:46,782 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1928 [2018-10-27 04:48:46,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:46,786 INFO L225 Difference]: With dead ends: 2000 [2018-10-27 04:48:46,786 INFO L226 Difference]: Without dead ends: 1994 [2018-10-27 04:48:46,787 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2024 GetRequests, 1907 SyntacticMatches, 0 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4553 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=3070, Invalid=10972, Unknown=0, NotChecked=0, Total=14042 [2018-10-27 04:48:46,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1994 states. [2018-10-27 04:48:46,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1994 to 1974. [2018-10-27 04:48:46,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1974 states. [2018-10-27 04:48:46,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1974 states to 1974 states and 1981 transitions. [2018-10-27 04:48:46,798 INFO L78 Accepts]: Start accepts. Automaton has 1974 states and 1981 transitions. Word has length 1928 [2018-10-27 04:48:46,799 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:46,799 INFO L481 AbstractCegarLoop]: Abstraction has 1974 states and 1981 transitions. [2018-10-27 04:48:46,799 INFO L482 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-10-27 04:48:46,799 INFO L276 IsEmpty]: Start isEmpty. Operand 1974 states and 1981 transitions. [2018-10-27 04:48:46,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1935 [2018-10-27 04:48:46,815 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:46,816 INFO L375 BasicCegarLoop]: trace histogram [296, 275, 275, 274, 274, 274, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:46,816 INFO L424 AbstractCegarLoop]: === Iteration 65 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:48:46,816 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:46,816 INFO L82 PathProgramCache]: Analyzing trace with hash -520193543, now seen corresponding path program 51 times [2018-10-27 04:48:46,816 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:48:46,816 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:48:46,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:46,817 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:48:46,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:46,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:48,987 INFO L134 CoverageAnalysis]: Checked inductivity of 239866 backedges. 35259 proven. 1474 refuted. 0 times theorem prover too weak. 203133 trivial. 0 not checked. [2018-10-27 04:48:48,987 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:48,987 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:48,994 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:48:49,791 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2018-10-27 04:48:49,792 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:48:49,807 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:49,827 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:48:49,827 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:48:49,861 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:48:49,862 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:48:53,988 INFO L134 CoverageAnalysis]: Checked inductivity of 239866 backedges. 35259 proven. 1474 refuted. 0 times theorem prover too weak. 203133 trivial. 0 not checked. [2018-10-27 04:48:54,006 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:54,007 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28] total 29 [2018-10-27 04:48:54,007 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-10-27 04:48:54,007 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-10-27 04:48:54,008 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=362, Invalid=508, Unknown=0, NotChecked=0, Total=870 [2018-10-27 04:48:54,008 INFO L87 Difference]: Start difference. First operand 1974 states and 1981 transitions. Second operand 30 states. [2018-10-27 04:48:54,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:48:54,690 INFO L93 Difference]: Finished difference Result 2003 states and 2011 transitions. [2018-10-27 04:48:54,691 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-10-27 04:48:54,691 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 1934 [2018-10-27 04:48:54,692 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:48:54,695 INFO L225 Difference]: With dead ends: 2003 [2018-10-27 04:48:54,695 INFO L226 Difference]: Without dead ends: 2003 [2018-10-27 04:48:54,695 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1984 GetRequests, 1888 SyntacticMatches, 45 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 428 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1007, Invalid=1749, Unknown=0, NotChecked=0, Total=2756 [2018-10-27 04:48:54,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2003 states. [2018-10-27 04:48:54,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2003 to 1980. [2018-10-27 04:48:54,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1980 states. [2018-10-27 04:48:54,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1980 states to 1980 states and 1988 transitions. [2018-10-27 04:48:54,708 INFO L78 Accepts]: Start accepts. Automaton has 1980 states and 1988 transitions. Word has length 1934 [2018-10-27 04:48:54,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:48:54,711 INFO L481 AbstractCegarLoop]: Abstraction has 1980 states and 1988 transitions. [2018-10-27 04:48:54,711 INFO L482 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-10-27 04:48:54,711 INFO L276 IsEmpty]: Start isEmpty. Operand 1980 states and 1988 transitions. [2018-10-27 04:48:54,726 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1941 [2018-10-27 04:48:54,726 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:48:54,726 INFO L375 BasicCegarLoop]: trace histogram [297, 276, 276, 275, 275, 275, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:48:54,726 INFO L424 AbstractCegarLoop]: === Iteration 66 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:48:54,726 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:48:54,727 INFO L82 PathProgramCache]: Analyzing trace with hash -1531712767, now seen corresponding path program 52 times [2018-10-27 04:48:54,727 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:48:54,727 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:48:54,727 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:54,727 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:48:54,728 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:48:54,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:48:56,516 INFO L134 CoverageAnalysis]: Checked inductivity of 241556 backedges. 38355 proven. 1601 refuted. 0 times theorem prover too weak. 201600 trivial. 0 not checked. [2018-10-27 04:48:56,516 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:48:56,517 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:48:56,526 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:48:56,854 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:48:56,854 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:48:56,868 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:48:58,661 INFO L134 CoverageAnalysis]: Checked inductivity of 241556 backedges. 38423 proven. 1533 refuted. 0 times theorem prover too weak. 201600 trivial. 0 not checked. [2018-10-27 04:48:58,679 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:48:58,679 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 49] total 75 [2018-10-27 04:48:58,680 INFO L460 AbstractCegarLoop]: Interpolant automaton has 75 states [2018-10-27 04:48:58,680 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2018-10-27 04:48:58,680 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1276, Invalid=4274, Unknown=0, NotChecked=0, Total=5550 [2018-10-27 04:48:58,681 INFO L87 Difference]: Start difference. First operand 1980 states and 1988 transitions. Second operand 75 states. [2018-10-27 04:49:00,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:49:00,187 INFO L93 Difference]: Finished difference Result 2156 states and 2165 transitions. [2018-10-27 04:49:00,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-10-27 04:49:00,188 INFO L78 Accepts]: Start accepts. Automaton has 75 states. Word has length 1940 [2018-10-27 04:49:00,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:49:00,191 INFO L225 Difference]: With dead ends: 2156 [2018-10-27 04:49:00,191 INFO L226 Difference]: Without dead ends: 2156 [2018-10-27 04:49:00,192 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2034 GetRequests, 1916 SyntacticMatches, 0 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2408 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3613, Invalid=10667, Unknown=0, NotChecked=0, Total=14280 [2018-10-27 04:49:00,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2156 states. [2018-10-27 04:49:00,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2156 to 2131. [2018-10-27 04:49:00,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2131 states. [2018-10-27 04:49:00,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2131 states to 2131 states and 2140 transitions. [2018-10-27 04:49:00,203 INFO L78 Accepts]: Start accepts. Automaton has 2131 states and 2140 transitions. Word has length 1940 [2018-10-27 04:49:00,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:49:00,205 INFO L481 AbstractCegarLoop]: Abstraction has 2131 states and 2140 transitions. [2018-10-27 04:49:00,205 INFO L482 AbstractCegarLoop]: Interpolant automaton has 75 states. [2018-10-27 04:49:00,205 INFO L276 IsEmpty]: Start isEmpty. Operand 2131 states and 2140 transitions. [2018-10-27 04:49:00,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2086 [2018-10-27 04:49:00,221 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:49:00,221 INFO L375 BasicCegarLoop]: trace histogram [320, 298, 298, 297, 297, 297, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:49:00,222 INFO L424 AbstractCegarLoop]: === Iteration 67 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:49:00,222 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:49:00,222 INFO L82 PathProgramCache]: Analyzing trace with hash -1767422634, now seen corresponding path program 53 times [2018-10-27 04:49:00,222 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:49:00,222 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:49:00,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:49:00,223 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:49:00,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:49:00,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:49:02,742 INFO L134 CoverageAnalysis]: Checked inductivity of 281127 backedges. 39986 proven. 1610 refuted. 0 times theorem prover too weak. 239531 trivial. 0 not checked. [2018-10-27 04:49:02,743 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:49:02,743 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:49:02,773 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:49:07,095 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 57 check-sat command(s) [2018-10-27 04:49:07,095 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:49:07,124 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:49:09,592 INFO L134 CoverageAnalysis]: Checked inductivity of 281127 backedges. 76048 proven. 8587 refuted. 0 times theorem prover too weak. 196492 trivial. 0 not checked. [2018-10-27 04:49:09,615 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:49:09,616 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 52] total 79 [2018-10-27 04:49:09,616 INFO L460 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-10-27 04:49:09,617 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-10-27 04:49:09,617 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=886, Invalid=5276, Unknown=0, NotChecked=0, Total=6162 [2018-10-27 04:49:09,617 INFO L87 Difference]: Start difference. First operand 2131 states and 2140 transitions. Second operand 79 states. [2018-10-27 04:49:13,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:49:13,231 INFO L93 Difference]: Finished difference Result 2166 states and 2174 transitions. [2018-10-27 04:49:13,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-10-27 04:49:13,232 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 2085 [2018-10-27 04:49:13,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:49:13,235 INFO L225 Difference]: With dead ends: 2166 [2018-10-27 04:49:13,236 INFO L226 Difference]: Without dead ends: 2160 [2018-10-27 04:49:13,239 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2185 GetRequests, 2036 SyntacticMatches, 1 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5621 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=3766, Invalid=18584, Unknown=0, NotChecked=0, Total=22350 [2018-10-27 04:49:13,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2160 states. [2018-10-27 04:49:13,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2160 to 2137. [2018-10-27 04:49:13,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2137 states. [2018-10-27 04:49:13,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2137 states to 2137 states and 2145 transitions. [2018-10-27 04:49:13,253 INFO L78 Accepts]: Start accepts. Automaton has 2137 states and 2145 transitions. Word has length 2085 [2018-10-27 04:49:13,254 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:49:13,255 INFO L481 AbstractCegarLoop]: Abstraction has 2137 states and 2145 transitions. [2018-10-27 04:49:13,255 INFO L482 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-10-27 04:49:13,255 INFO L276 IsEmpty]: Start isEmpty. Operand 2137 states and 2145 transitions. [2018-10-27 04:49:13,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2098 [2018-10-27 04:49:13,274 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:49:13,274 INFO L375 BasicCegarLoop]: trace histogram [322, 300, 300, 299, 299, 299, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:49:13,275 INFO L424 AbstractCegarLoop]: === Iteration 68 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:49:13,275 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:49:13,275 INFO L82 PathProgramCache]: Analyzing trace with hash 869664918, now seen corresponding path program 54 times [2018-10-27 04:49:13,275 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:49:13,275 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:49:13,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:49:13,276 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:49:13,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:49:13,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:49:15,868 INFO L134 CoverageAnalysis]: Checked inductivity of 284793 backedges. 41822 proven. 1752 refuted. 0 times theorem prover too weak. 241219 trivial. 0 not checked. [2018-10-27 04:49:15,869 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:49:15,869 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:49:15,876 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-10-27 04:49:18,832 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-10-27 04:49:18,832 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:49:18,852 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:49:21,795 INFO L134 CoverageAnalysis]: Checked inductivity of 284793 backedges. 68511 proven. 10293 refuted. 0 times theorem prover too weak. 205989 trivial. 0 not checked. [2018-10-27 04:49:21,815 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:49:21,816 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 55] total 83 [2018-10-27 04:49:21,816 INFO L460 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-10-27 04:49:21,817 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-10-27 04:49:21,817 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1003, Invalid=5803, Unknown=0, NotChecked=0, Total=6806 [2018-10-27 04:49:21,817 INFO L87 Difference]: Start difference. First operand 2137 states and 2145 transitions. Second operand 83 states. [2018-10-27 04:49:26,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:49:26,142 INFO L93 Difference]: Finished difference Result 2333 states and 2343 transitions. [2018-10-27 04:49:26,143 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-10-27 04:49:26,143 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 2097 [2018-10-27 04:49:26,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:49:26,146 INFO L225 Difference]: With dead ends: 2333 [2018-10-27 04:49:26,146 INFO L226 Difference]: Without dead ends: 2333 [2018-10-27 04:49:26,148 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2206 GetRequests, 2044 SyntacticMatches, 1 SemanticMatches, 161 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6883 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=4849, Invalid=21557, Unknown=0, NotChecked=0, Total=26406 [2018-10-27 04:49:26,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2333 states. [2018-10-27 04:49:26,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2333 to 2300. [2018-10-27 04:49:26,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2300 states. [2018-10-27 04:49:26,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2300 states to 2300 states and 2310 transitions. [2018-10-27 04:49:26,161 INFO L78 Accepts]: Start accepts. Automaton has 2300 states and 2310 transitions. Word has length 2097 [2018-10-27 04:49:26,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:49:26,162 INFO L481 AbstractCegarLoop]: Abstraction has 2300 states and 2310 transitions. [2018-10-27 04:49:26,162 INFO L482 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-10-27 04:49:26,162 INFO L276 IsEmpty]: Start isEmpty. Operand 2300 states and 2310 transitions. [2018-10-27 04:49:26,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2255 [2018-10-27 04:49:26,181 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:49:26,182 INFO L375 BasicCegarLoop]: trace histogram [347, 324, 324, 323, 323, 323, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:49:26,182 INFO L424 AbstractCegarLoop]: === Iteration 69 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:49:26,182 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:49:26,183 INFO L82 PathProgramCache]: Analyzing trace with hash 1036473457, now seen corresponding path program 55 times [2018-10-27 04:49:26,183 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:49:26,183 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:49:26,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:49:26,183 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:49:26,184 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:49:26,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:49:28,621 INFO L134 CoverageAnalysis]: Checked inductivity of 331595 backedges. 88155 proven. 7674 refuted. 0 times theorem prover too weak. 235766 trivial. 0 not checked. [2018-10-27 04:49:28,621 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:49:28,622 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:49:28,629 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:49:29,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:49:29,019 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:49:31,020 INFO L134 CoverageAnalysis]: Checked inductivity of 331595 backedges. 88573 proven. 1564 refuted. 0 times theorem prover too weak. 241458 trivial. 0 not checked. [2018-10-27 04:49:31,039 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:49:31,039 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 50] total 79 [2018-10-27 04:49:31,040 INFO L460 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-10-27 04:49:31,040 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-10-27 04:49:31,041 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1286, Invalid=4876, Unknown=0, NotChecked=0, Total=6162 [2018-10-27 04:49:31,041 INFO L87 Difference]: Start difference. First operand 2300 states and 2310 transitions. Second operand 79 states. [2018-10-27 04:49:32,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:49:32,915 INFO L93 Difference]: Finished difference Result 2324 states and 2332 transitions. [2018-10-27 04:49:32,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2018-10-27 04:49:32,916 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 2254 [2018-10-27 04:49:32,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:49:32,919 INFO L225 Difference]: With dead ends: 2324 [2018-10-27 04:49:32,920 INFO L226 Difference]: Without dead ends: 2318 [2018-10-27 04:49:32,921 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2358 GetRequests, 2231 SyntacticMatches, 0 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5424 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3611, Invalid=12901, Unknown=0, NotChecked=0, Total=16512 [2018-10-27 04:49:32,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2318 states. [2018-10-27 04:49:32,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2318 to 2300. [2018-10-27 04:49:32,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2300 states. [2018-10-27 04:49:32,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2300 states to 2300 states and 2308 transitions. [2018-10-27 04:49:32,934 INFO L78 Accepts]: Start accepts. Automaton has 2300 states and 2308 transitions. Word has length 2254 [2018-10-27 04:49:32,935 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:49:32,935 INFO L481 AbstractCegarLoop]: Abstraction has 2300 states and 2308 transitions. [2018-10-27 04:49:32,935 INFO L482 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-10-27 04:49:32,935 INFO L276 IsEmpty]: Start isEmpty. Operand 2300 states and 2308 transitions. [2018-10-27 04:49:32,954 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2261 [2018-10-27 04:49:32,954 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:49:32,954 INFO L375 BasicCegarLoop]: trace histogram [348, 325, 325, 324, 324, 324, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:49:32,954 INFO L424 AbstractCegarLoop]: === Iteration 70 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:49:32,955 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:49:32,955 INFO L82 PathProgramCache]: Analyzing trace with hash -1644678615, now seen corresponding path program 56 times [2018-10-27 04:49:32,955 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:49:32,955 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:49:32,955 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:49:32,956 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:49:32,956 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:49:33,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:49:35,235 INFO L134 CoverageAnalysis]: Checked inductivity of 333583 backedges. 49091 proven. 1914 refuted. 0 times theorem prover too weak. 282578 trivial. 0 not checked. [2018-10-27 04:49:35,235 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:49:35,235 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:49:35,245 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:49:35,623 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:49:35,623 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:49:35,640 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:49:37,942 INFO L134 CoverageAnalysis]: Checked inductivity of 333583 backedges. 49165 proven. 1840 refuted. 0 times theorem prover too weak. 282578 trivial. 0 not checked. [2018-10-27 04:49:37,960 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:49:37,961 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 53] total 81 [2018-10-27 04:49:37,962 INFO L460 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-10-27 04:49:37,962 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-10-27 04:49:37,963 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1486, Invalid=4994, Unknown=0, NotChecked=0, Total=6480 [2018-10-27 04:49:37,963 INFO L87 Difference]: Start difference. First operand 2300 states and 2308 transitions. Second operand 81 states. [2018-10-27 04:49:39,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:49:39,977 INFO L93 Difference]: Finished difference Result 2488 states and 2497 transitions. [2018-10-27 04:49:39,978 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-10-27 04:49:39,979 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 2260 [2018-10-27 04:49:39,980 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:49:39,982 INFO L225 Difference]: With dead ends: 2488 [2018-10-27 04:49:39,982 INFO L226 Difference]: Without dead ends: 2488 [2018-10-27 04:49:39,983 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2362 GetRequests, 2234 SyntacticMatches, 0 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2843 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=4227, Invalid=12543, Unknown=0, NotChecked=0, Total=16770 [2018-10-27 04:49:39,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2488 states. [2018-10-27 04:49:39,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2488 to 2463. [2018-10-27 04:49:39,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2463 states. [2018-10-27 04:49:39,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2463 states to 2463 states and 2472 transitions. [2018-10-27 04:49:39,997 INFO L78 Accepts]: Start accepts. Automaton has 2463 states and 2472 transitions. Word has length 2260 [2018-10-27 04:49:39,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:49:39,998 INFO L481 AbstractCegarLoop]: Abstraction has 2463 states and 2472 transitions. [2018-10-27 04:49:39,998 INFO L482 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-10-27 04:49:39,998 INFO L276 IsEmpty]: Start isEmpty. Operand 2463 states and 2472 transitions. [2018-10-27 04:49:40,020 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2418 [2018-10-27 04:49:40,020 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:49:40,020 INFO L375 BasicCegarLoop]: trace histogram [373, 349, 349, 348, 348, 348, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:49:40,021 INFO L424 AbstractCegarLoop]: === Iteration 71 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:49:40,021 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:49:40,021 INFO L82 PathProgramCache]: Analyzing trace with hash -1765374018, now seen corresponding path program 57 times [2018-10-27 04:49:40,021 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:49:40,021 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:49:40,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:49:40,022 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:49:40,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:49:40,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:49:42,911 INFO L134 CoverageAnalysis]: Checked inductivity of 384096 backedges. 135463 proven. 5469 refuted. 0 times theorem prover too weak. 243164 trivial. 0 not checked. [2018-10-27 04:49:42,912 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:49:42,912 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:49:42,920 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:49:44,029 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 26 check-sat command(s) [2018-10-27 04:49:44,030 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:49:44,045 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:49:47,343 INFO L134 CoverageAnalysis]: Checked inductivity of 384096 backedges. 94251 proven. 5404 refuted. 0 times theorem prover too weak. 284441 trivial. 0 not checked. [2018-10-27 04:49:47,361 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:49:47,362 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 57] total 110 [2018-10-27 04:49:47,363 INFO L460 AbstractCegarLoop]: Interpolant automaton has 110 states [2018-10-27 04:49:47,363 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 110 interpolants. [2018-10-27 04:49:47,364 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1770, Invalid=10220, Unknown=0, NotChecked=0, Total=11990 [2018-10-27 04:49:47,364 INFO L87 Difference]: Start difference. First operand 2463 states and 2472 transitions. Second operand 110 states. [2018-10-27 04:49:51,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:49:51,673 INFO L93 Difference]: Finished difference Result 2493 states and 2500 transitions. [2018-10-27 04:49:51,674 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 112 states. [2018-10-27 04:49:51,674 INFO L78 Accepts]: Start accepts. Automaton has 110 states. Word has length 2417 [2018-10-27 04:49:51,675 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:49:51,678 INFO L225 Difference]: With dead ends: 2493 [2018-10-27 04:49:51,678 INFO L226 Difference]: Without dead ends: 2487 [2018-10-27 04:49:51,680 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2577 GetRequests, 2365 SyntacticMatches, 0 SemanticMatches, 212 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14779 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=7244, Invalid=38338, Unknown=0, NotChecked=0, Total=45582 [2018-10-27 04:49:51,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2487 states. [2018-10-27 04:49:51,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2487 to 2463. [2018-10-27 04:49:51,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2463 states. [2018-10-27 04:49:51,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2463 states to 2463 states and 2470 transitions. [2018-10-27 04:49:51,692 INFO L78 Accepts]: Start accepts. Automaton has 2463 states and 2470 transitions. Word has length 2417 [2018-10-27 04:49:51,693 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:49:51,693 INFO L481 AbstractCegarLoop]: Abstraction has 2463 states and 2470 transitions. [2018-10-27 04:49:51,693 INFO L482 AbstractCegarLoop]: Interpolant automaton has 110 states. [2018-10-27 04:49:51,694 INFO L276 IsEmpty]: Start isEmpty. Operand 2463 states and 2470 transitions. [2018-10-27 04:49:51,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2424 [2018-10-27 04:49:51,716 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:49:51,716 INFO L375 BasicCegarLoop]: trace histogram [374, 350, 350, 349, 349, 349, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:49:51,716 INFO L424 AbstractCegarLoop]: === Iteration 72 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:49:51,716 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:49:51,717 INFO L82 PathProgramCache]: Analyzing trace with hash -1027278922, now seen corresponding path program 58 times [2018-10-27 04:49:51,717 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:49:51,717 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:49:51,717 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:49:51,718 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:49:51,718 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:49:51,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:49:54,876 INFO L134 CoverageAnalysis]: Checked inductivity of 386236 backedges. 51168 proven. 1900 refuted. 0 times theorem prover too weak. 333168 trivial. 0 not checked. [2018-10-27 04:49:54,876 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:49:54,876 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:49:54,884 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:49:55,805 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:49:55,805 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:49:55,842 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:49:55,848 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:49:55,849 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:49:55,861 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:49:55,861 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:50:03,031 INFO L134 CoverageAnalysis]: Checked inductivity of 386236 backedges. 51168 proven. 1900 refuted. 0 times theorem prover too weak. 333168 trivial. 0 not checked. [2018-10-27 04:50:03,054 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:50:03,055 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 56 [2018-10-27 04:50:03,055 INFO L460 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-10-27 04:50:03,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-10-27 04:50:03,056 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=842, Invalid=2350, Unknown=0, NotChecked=0, Total=3192 [2018-10-27 04:50:03,056 INFO L87 Difference]: Start difference. First operand 2463 states and 2470 transitions. Second operand 57 states. [2018-10-27 04:50:05,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:50:05,177 INFO L93 Difference]: Finished difference Result 2492 states and 2500 transitions. [2018-10-27 04:50:05,178 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-10-27 04:50:05,178 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 2423 [2018-10-27 04:50:05,180 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:50:05,182 INFO L225 Difference]: With dead ends: 2492 [2018-10-27 04:50:05,182 INFO L226 Difference]: Without dead ends: 2492 [2018-10-27 04:50:05,183 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2479 GetRequests, 2347 SyntacticMatches, 51 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2051 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1348, Invalid=5458, Unknown=0, NotChecked=0, Total=6806 [2018-10-27 04:50:05,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2492 states. [2018-10-27 04:50:05,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2492 to 2469. [2018-10-27 04:50:05,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2469 states. [2018-10-27 04:50:05,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2469 states to 2469 states and 2477 transitions. [2018-10-27 04:50:05,195 INFO L78 Accepts]: Start accepts. Automaton has 2469 states and 2477 transitions. Word has length 2423 [2018-10-27 04:50:05,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:50:05,196 INFO L481 AbstractCegarLoop]: Abstraction has 2469 states and 2477 transitions. [2018-10-27 04:50:05,196 INFO L482 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-10-27 04:50:05,196 INFO L276 IsEmpty]: Start isEmpty. Operand 2469 states and 2477 transitions. [2018-10-27 04:50:05,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2430 [2018-10-27 04:50:05,218 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:50:05,218 INFO L375 BasicCegarLoop]: trace histogram [375, 351, 351, 350, 350, 350, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:50:05,219 INFO L424 AbstractCegarLoop]: === Iteration 73 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:50:05,219 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:50:05,219 INFO L82 PathProgramCache]: Analyzing trace with hash 316827390, now seen corresponding path program 59 times [2018-10-27 04:50:05,219 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:50:05,219 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:50:05,220 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:50:05,220 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:50:05,220 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:50:05,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:50:07,855 INFO L134 CoverageAnalysis]: Checked inductivity of 388382 backedges. 55137 proven. 2081 refuted. 0 times theorem prover too weak. 331164 trivial. 0 not checked. [2018-10-27 04:50:07,856 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:50:07,856 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:50:07,863 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:50:21,768 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 60 check-sat command(s) [2018-10-27 04:50:21,768 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:50:21,808 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:50:24,558 INFO L134 CoverageAnalysis]: Checked inductivity of 388382 backedges. 54916 proven. 7027 refuted. 0 times theorem prover too weak. 326439 trivial. 0 not checked. [2018-10-27 04:50:24,585 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:50:24,586 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 60] total 88 [2018-10-27 04:50:24,587 INFO L460 AbstractCegarLoop]: Interpolant automaton has 88 states [2018-10-27 04:50:24,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2018-10-27 04:50:24,588 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1609, Invalid=6047, Unknown=0, NotChecked=0, Total=7656 [2018-10-27 04:50:24,588 INFO L87 Difference]: Start difference. First operand 2469 states and 2477 transitions. Second operand 88 states. [2018-10-27 04:50:27,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:50:27,233 INFO L93 Difference]: Finished difference Result 2663 states and 2672 transitions. [2018-10-27 04:50:27,235 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2018-10-27 04:50:27,235 INFO L78 Accepts]: Start accepts. Automaton has 88 states. Word has length 2429 [2018-10-27 04:50:27,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:50:27,238 INFO L225 Difference]: With dead ends: 2663 [2018-10-27 04:50:27,238 INFO L226 Difference]: Without dead ends: 2663 [2018-10-27 04:50:27,239 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2537 GetRequests, 2398 SyntacticMatches, 0 SemanticMatches, 139 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3686 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=4473, Invalid=15267, Unknown=0, NotChecked=0, Total=19740 [2018-10-27 04:50:27,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2663 states. [2018-10-27 04:50:27,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2663 to 2638. [2018-10-27 04:50:27,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2638 states. [2018-10-27 04:50:27,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2638 states to 2638 states and 2647 transitions. [2018-10-27 04:50:27,256 INFO L78 Accepts]: Start accepts. Automaton has 2638 states and 2647 transitions. Word has length 2429 [2018-10-27 04:50:27,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:50:27,260 INFO L481 AbstractCegarLoop]: Abstraction has 2638 states and 2647 transitions. [2018-10-27 04:50:27,260 INFO L482 AbstractCegarLoop]: Interpolant automaton has 88 states. [2018-10-27 04:50:27,260 INFO L276 IsEmpty]: Start isEmpty. Operand 2638 states and 2647 transitions. [2018-10-27 04:50:27,284 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2593 [2018-10-27 04:50:27,284 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:50:27,284 INFO L375 BasicCegarLoop]: trace histogram [401, 376, 376, 375, 375, 375, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:50:27,284 INFO L424 AbstractCegarLoop]: === Iteration 74 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:50:27,285 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:50:27,285 INFO L82 PathProgramCache]: Analyzing trace with hash 277959697, now seen corresponding path program 60 times [2018-10-27 04:50:27,285 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:50:27,285 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:50:27,286 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:50:27,286 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:50:27,286 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:50:27,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:50:30,318 INFO L134 CoverageAnalysis]: Checked inductivity of 445050 backedges. 109500 proven. 9002 refuted. 0 times theorem prover too weak. 326548 trivial. 0 not checked. [2018-10-27 04:50:30,318 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:50:30,318 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:50:30,326 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-10-27 04:50:38,028 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 53 check-sat command(s) [2018-10-27 04:50:38,028 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:50:38,057 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:50:41,658 INFO L134 CoverageAnalysis]: Checked inductivity of 445050 backedges. 106004 proven. 5854 refuted. 0 times theorem prover too weak. 333192 trivial. 0 not checked. [2018-10-27 04:50:41,680 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:50:41,681 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 59] total 114 [2018-10-27 04:50:41,682 INFO L460 AbstractCegarLoop]: Interpolant automaton has 114 states [2018-10-27 04:50:41,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 114 interpolants. [2018-10-27 04:50:41,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1883, Invalid=10999, Unknown=0, NotChecked=0, Total=12882 [2018-10-27 04:50:41,683 INFO L87 Difference]: Start difference. First operand 2638 states and 2647 transitions. Second operand 114 states. [2018-10-27 04:50:46,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:50:46,619 INFO L93 Difference]: Finished difference Result 2668 states and 2675 transitions. [2018-10-27 04:50:46,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 139 states. [2018-10-27 04:50:46,620 INFO L78 Accepts]: Start accepts. Automaton has 114 states. Word has length 2592 [2018-10-27 04:50:46,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:50:46,624 INFO L225 Difference]: With dead ends: 2668 [2018-10-27 04:50:46,624 INFO L226 Difference]: Without dead ends: 2662 [2018-10-27 04:50:46,627 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2781 GetRequests, 2538 SyntacticMatches, 0 SemanticMatches, 243 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21247 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=8064, Invalid=51716, Unknown=0, NotChecked=0, Total=59780 [2018-10-27 04:50:46,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2662 states. [2018-10-27 04:50:46,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2662 to 2638. [2018-10-27 04:50:46,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2638 states. [2018-10-27 04:50:46,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2638 states to 2638 states and 2645 transitions. [2018-10-27 04:50:46,639 INFO L78 Accepts]: Start accepts. Automaton has 2638 states and 2645 transitions. Word has length 2592 [2018-10-27 04:50:46,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:50:46,641 INFO L481 AbstractCegarLoop]: Abstraction has 2638 states and 2645 transitions. [2018-10-27 04:50:46,641 INFO L482 AbstractCegarLoop]: Interpolant automaton has 114 states. [2018-10-27 04:50:46,641 INFO L276 IsEmpty]: Start isEmpty. Operand 2638 states and 2645 transitions. [2018-10-27 04:50:46,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2599 [2018-10-27 04:50:46,664 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:50:46,665 INFO L375 BasicCegarLoop]: trace histogram [402, 377, 377, 376, 376, 376, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:50:46,665 INFO L424 AbstractCegarLoop]: === Iteration 75 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:50:46,665 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:50:46,665 INFO L82 PathProgramCache]: Analyzing trace with hash -1514129975, now seen corresponding path program 61 times [2018-10-27 04:50:46,665 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:50:46,666 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:50:46,666 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:50:46,666 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:50:46,666 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:50:46,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:50:50,280 INFO L134 CoverageAnalysis]: Checked inductivity of 447354 backedges. 57375 proven. 2054 refuted. 0 times theorem prover too weak. 387925 trivial. 0 not checked. [2018-10-27 04:50:50,280 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:50:50,280 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:50:50,288 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:50:50,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:50:50,758 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:50:50,771 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:50:50,771 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:50:50,776 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:50:50,776 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:50:58,841 INFO L134 CoverageAnalysis]: Checked inductivity of 447354 backedges. 57375 proven. 2054 refuted. 0 times theorem prover too weak. 387925 trivial. 0 not checked. [2018-10-27 04:50:58,861 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:50:58,862 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 58 [2018-10-27 04:50:58,863 INFO L460 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-10-27 04:50:58,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-10-27 04:50:58,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=901, Invalid=2521, Unknown=0, NotChecked=0, Total=3422 [2018-10-27 04:50:58,863 INFO L87 Difference]: Start difference. First operand 2638 states and 2645 transitions. Second operand 59 states. [2018-10-27 04:51:01,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:51:01,247 INFO L93 Difference]: Finished difference Result 2667 states and 2675 transitions. [2018-10-27 04:51:01,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-10-27 04:51:01,249 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 2598 [2018-10-27 04:51:01,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:51:01,253 INFO L225 Difference]: With dead ends: 2667 [2018-10-27 04:51:01,253 INFO L226 Difference]: Without dead ends: 2667 [2018-10-27 04:51:01,253 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2656 GetRequests, 2519 SyntacticMatches, 53 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2211 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1440, Invalid=5870, Unknown=0, NotChecked=0, Total=7310 [2018-10-27 04:51:01,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2667 states. [2018-10-27 04:51:01,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2667 to 2644. [2018-10-27 04:51:01,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2644 states. [2018-10-27 04:51:01,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2644 states to 2644 states and 2652 transitions. [2018-10-27 04:51:01,275 INFO L78 Accepts]: Start accepts. Automaton has 2644 states and 2652 transitions. Word has length 2598 [2018-10-27 04:51:01,277 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:51:01,277 INFO L481 AbstractCegarLoop]: Abstraction has 2644 states and 2652 transitions. [2018-10-27 04:51:01,277 INFO L482 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-10-27 04:51:01,277 INFO L276 IsEmpty]: Start isEmpty. Operand 2644 states and 2652 transitions. [2018-10-27 04:51:01,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2605 [2018-10-27 04:51:01,320 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:51:01,321 INFO L375 BasicCegarLoop]: trace histogram [403, 378, 378, 377, 377, 377, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:51:01,321 INFO L424 AbstractCegarLoop]: === Iteration 76 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:51:01,321 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:51:01,321 INFO L82 PathProgramCache]: Analyzing trace with hash 1024297681, now seen corresponding path program 62 times [2018-10-27 04:51:01,321 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:51:01,321 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:51:01,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:51:01,322 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:51:01,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:51:01,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:51:04,501 INFO L134 CoverageAnalysis]: Checked inductivity of 449664 backedges. 61659 proven. 2255 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-10-27 04:51:04,501 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:51:04,501 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:51:04,509 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:51:04,945 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:51:04,945 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:51:04,964 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:51:07,900 INFO L134 CoverageAnalysis]: Checked inductivity of 449664 backedges. 61739 proven. 2175 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-10-27 04:51:07,919 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:51:07,919 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 57] total 87 [2018-10-27 04:51:07,920 INFO L460 AbstractCegarLoop]: Interpolant automaton has 87 states [2018-10-27 04:51:07,920 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2018-10-27 04:51:07,921 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1712, Invalid=5770, Unknown=0, NotChecked=0, Total=7482 [2018-10-27 04:51:07,921 INFO L87 Difference]: Start difference. First operand 2644 states and 2652 transitions. Second operand 87 states. [2018-10-27 04:51:09,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:51:09,934 INFO L93 Difference]: Finished difference Result 2844 states and 2853 transitions. [2018-10-27 04:51:09,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-10-27 04:51:09,935 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 2604 [2018-10-27 04:51:09,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:51:09,939 INFO L225 Difference]: With dead ends: 2844 [2018-10-27 04:51:09,939 INFO L226 Difference]: Without dead ends: 2844 [2018-10-27 04:51:09,941 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2714 GetRequests, 2576 SyntacticMatches, 0 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3314 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=4889, Invalid=14571, Unknown=0, NotChecked=0, Total=19460 [2018-10-27 04:51:09,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2844 states. [2018-10-27 04:51:09,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2844 to 2819. [2018-10-27 04:51:09,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2819 states. [2018-10-27 04:51:09,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2819 states to 2819 states and 2828 transitions. [2018-10-27 04:51:09,959 INFO L78 Accepts]: Start accepts. Automaton has 2819 states and 2828 transitions. Word has length 2604 [2018-10-27 04:51:09,964 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:51:09,964 INFO L481 AbstractCegarLoop]: Abstraction has 2819 states and 2828 transitions. [2018-10-27 04:51:09,964 INFO L482 AbstractCegarLoop]: Interpolant automaton has 87 states. [2018-10-27 04:51:09,964 INFO L276 IsEmpty]: Start isEmpty. Operand 2819 states and 2828 transitions. [2018-10-27 04:51:09,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2774 [2018-10-27 04:51:09,994 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:51:09,994 INFO L375 BasicCegarLoop]: trace histogram [430, 404, 404, 403, 403, 403, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:51:09,994 INFO L424 AbstractCegarLoop]: === Iteration 77 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:51:09,994 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:51:09,995 INFO L82 PathProgramCache]: Analyzing trace with hash 1317931174, now seen corresponding path program 63 times [2018-10-27 04:51:09,995 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:51:09,995 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:51:09,995 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:51:09,995 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:51:09,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:51:10,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:51:13,582 INFO L134 CoverageAnalysis]: Checked inductivity of 512967 backedges. 171143 proven. 6393 refuted. 0 times theorem prover too weak. 335431 trivial. 0 not checked. [2018-10-27 04:51:13,582 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:51:13,582 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:51:13,618 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:51:15,663 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-10-27 04:51:15,664 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:51:15,680 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:51:19,624 INFO L134 CoverageAnalysis]: Checked inductivity of 512967 backedges. 118695 proven. 6322 refuted. 0 times theorem prover too weak. 387950 trivial. 0 not checked. [2018-10-27 04:51:19,643 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:51:19,643 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 61] total 118 [2018-10-27 04:51:19,644 INFO L460 AbstractCegarLoop]: Interpolant automaton has 118 states [2018-10-27 04:51:19,644 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 118 interpolants. [2018-10-27 04:51:19,645 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2045, Invalid=11761, Unknown=0, NotChecked=0, Total=13806 [2018-10-27 04:51:19,645 INFO L87 Difference]: Start difference. First operand 2819 states and 2828 transitions. Second operand 118 states. [2018-10-27 04:51:24,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:51:24,034 INFO L93 Difference]: Finished difference Result 2849 states and 2856 transitions. [2018-10-27 04:51:24,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 120 states. [2018-10-27 04:51:24,036 INFO L78 Accepts]: Start accepts. Automaton has 118 states. Word has length 2773 [2018-10-27 04:51:24,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:51:24,040 INFO L225 Difference]: With dead ends: 2849 [2018-10-27 04:51:24,040 INFO L226 Difference]: Without dead ends: 2843 [2018-10-27 04:51:24,047 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2945 GetRequests, 2717 SyntacticMatches, 0 SemanticMatches, 228 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17176 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=8360, Invalid=44310, Unknown=0, NotChecked=0, Total=52670 [2018-10-27 04:51:24,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2843 states. [2018-10-27 04:51:24,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2843 to 2819. [2018-10-27 04:51:24,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2819 states. [2018-10-27 04:51:24,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2819 states to 2819 states and 2826 transitions. [2018-10-27 04:51:24,067 INFO L78 Accepts]: Start accepts. Automaton has 2819 states and 2826 transitions. Word has length 2773 [2018-10-27 04:51:24,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:51:24,072 INFO L481 AbstractCegarLoop]: Abstraction has 2819 states and 2826 transitions. [2018-10-27 04:51:24,072 INFO L482 AbstractCegarLoop]: Interpolant automaton has 118 states. [2018-10-27 04:51:24,072 INFO L276 IsEmpty]: Start isEmpty. Operand 2819 states and 2826 transitions. [2018-10-27 04:51:24,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2780 [2018-10-27 04:51:24,118 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:51:24,119 INFO L375 BasicCegarLoop]: trace histogram [431, 405, 405, 404, 404, 404, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:51:24,119 INFO L424 AbstractCegarLoop]: === Iteration 78 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:51:24,119 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:51:24,119 INFO L82 PathProgramCache]: Analyzing trace with hash 1948099230, now seen corresponding path program 64 times [2018-10-27 04:51:24,119 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:51:24,119 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:51:24,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:51:24,127 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:51:24,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:51:24,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:51:28,093 INFO L134 CoverageAnalysis]: Checked inductivity of 515441 backedges. 64064 proven. 2214 refuted. 0 times theorem prover too weak. 449163 trivial. 0 not checked. [2018-10-27 04:51:28,093 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:51:28,093 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:51:28,101 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:51:29,245 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:51:29,245 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:51:29,276 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:51:29,280 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:51:29,281 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:51:29,292 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:51:29,293 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:51:38,259 INFO L134 CoverageAnalysis]: Checked inductivity of 515441 backedges. 64064 proven. 2214 refuted. 0 times theorem prover too weak. 449163 trivial. 0 not checked. [2018-10-27 04:51:38,284 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:51:38,284 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 60 [2018-10-27 04:51:38,285 INFO L460 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-10-27 04:51:38,285 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-10-27 04:51:38,286 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=962, Invalid=2698, Unknown=0, NotChecked=0, Total=3660 [2018-10-27 04:51:38,286 INFO L87 Difference]: Start difference. First operand 2819 states and 2826 transitions. Second operand 61 states. [2018-10-27 04:51:40,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:51:40,697 INFO L93 Difference]: Finished difference Result 2848 states and 2856 transitions. [2018-10-27 04:51:40,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-10-27 04:51:40,698 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 2779 [2018-10-27 04:51:40,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:51:40,703 INFO L225 Difference]: With dead ends: 2848 [2018-10-27 04:51:40,703 INFO L226 Difference]: Without dead ends: 2848 [2018-10-27 04:51:40,703 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2839 GetRequests, 2697 SyntacticMatches, 55 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2377 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1535, Invalid=6297, Unknown=0, NotChecked=0, Total=7832 [2018-10-27 04:51:40,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2848 states. [2018-10-27 04:51:40,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2848 to 2825. [2018-10-27 04:51:40,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2825 states. [2018-10-27 04:51:40,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2825 states to 2825 states and 2833 transitions. [2018-10-27 04:51:40,716 INFO L78 Accepts]: Start accepts. Automaton has 2825 states and 2833 transitions. Word has length 2779 [2018-10-27 04:51:40,717 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:51:40,717 INFO L481 AbstractCegarLoop]: Abstraction has 2825 states and 2833 transitions. [2018-10-27 04:51:40,717 INFO L482 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-10-27 04:51:40,717 INFO L276 IsEmpty]: Start isEmpty. Operand 2825 states and 2833 transitions. [2018-10-27 04:51:40,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2786 [2018-10-27 04:51:40,744 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:51:40,745 INFO L375 BasicCegarLoop]: trace histogram [432, 406, 406, 405, 405, 405, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:51:40,745 INFO L424 AbstractCegarLoop]: === Iteration 79 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:51:40,745 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:51:40,745 INFO L82 PathProgramCache]: Analyzing trace with hash 909722598, now seen corresponding path program 65 times [2018-10-27 04:51:40,745 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:51:40,746 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:51:40,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:51:40,746 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:51:40,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:51:40,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:51:44,081 INFO L134 CoverageAnalysis]: Checked inductivity of 517921 backedges. 68675 proven. 2436 refuted. 0 times theorem prover too weak. 446810 trivial. 0 not checked. [2018-10-27 04:51:44,081 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:51:44,081 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:51:44,090 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:51:54,992 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 62 check-sat command(s) [2018-10-27 04:51:54,992 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:51:55,029 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:51:58,397 INFO L134 CoverageAnalysis]: Checked inductivity of 517921 backedges. 68438 proven. 8158 refuted. 0 times theorem prover too weak. 441325 trivial. 0 not checked. [2018-10-27 04:51:58,428 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:51:58,428 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 64] total 94 [2018-10-27 04:51:58,429 INFO L460 AbstractCegarLoop]: Interpolant automaton has 94 states [2018-10-27 04:51:58,429 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2018-10-27 04:51:58,429 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1843, Invalid=6899, Unknown=0, NotChecked=0, Total=8742 [2018-10-27 04:51:58,430 INFO L87 Difference]: Start difference. First operand 2825 states and 2833 transitions. Second operand 94 states. [2018-10-27 04:52:00,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:52:00,867 INFO L93 Difference]: Finished difference Result 3031 states and 3040 transitions. [2018-10-27 04:52:00,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2018-10-27 04:52:00,868 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 2785 [2018-10-27 04:52:00,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:52:00,872 INFO L225 Difference]: With dead ends: 3031 [2018-10-27 04:52:00,872 INFO L226 Difference]: Without dead ends: 3031 [2018-10-27 04:52:00,873 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2901 GetRequests, 2752 SyntacticMatches, 0 SemanticMatches, 149 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4223 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=5149, Invalid=17501, Unknown=0, NotChecked=0, Total=22650 [2018-10-27 04:52:00,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3031 states. [2018-10-27 04:52:00,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3031 to 3006. [2018-10-27 04:52:00,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3006 states. [2018-10-27 04:52:00,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3006 states to 3006 states and 3015 transitions. [2018-10-27 04:52:00,886 INFO L78 Accepts]: Start accepts. Automaton has 3006 states and 3015 transitions. Word has length 2785 [2018-10-27 04:52:00,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:52:00,887 INFO L481 AbstractCegarLoop]: Abstraction has 3006 states and 3015 transitions. [2018-10-27 04:52:00,888 INFO L482 AbstractCegarLoop]: Interpolant automaton has 94 states. [2018-10-27 04:52:00,888 INFO L276 IsEmpty]: Start isEmpty. Operand 3006 states and 3015 transitions. [2018-10-27 04:52:00,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2961 [2018-10-27 04:52:00,917 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:52:00,918 INFO L375 BasicCegarLoop]: trace histogram [460, 433, 433, 432, 432, 432, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:52:00,918 INFO L424 AbstractCegarLoop]: === Iteration 80 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:52:00,918 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:52:00,918 INFO L82 PathProgramCache]: Analyzing trace with hash 127255097, now seen corresponding path program 66 times [2018-10-27 04:52:00,919 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:52:00,919 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:52:00,919 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:52:00,919 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:52:00,919 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:52:01,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:52:05,190 INFO L134 CoverageAnalysis]: Checked inductivity of 588357 backedges. 136483 proven. 10434 refuted. 0 times theorem prover too weak. 441440 trivial. 0 not checked. [2018-10-27 04:52:05,191 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:52:05,191 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:52:05,199 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-10-27 04:52:27,297 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 57 check-sat command(s) [2018-10-27 04:52:27,297 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:52:27,330 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:52:31,739 INFO L134 CoverageAnalysis]: Checked inductivity of 588357 backedges. 132360 proven. 6808 refuted. 0 times theorem prover too weak. 449189 trivial. 0 not checked. [2018-10-27 04:52:31,765 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:52:31,765 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 63] total 122 [2018-10-27 04:52:31,766 INFO L460 AbstractCegarLoop]: Interpolant automaton has 122 states [2018-10-27 04:52:31,767 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 122 interpolants. [2018-10-27 04:52:31,767 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2166, Invalid=12596, Unknown=0, NotChecked=0, Total=14762 [2018-10-27 04:52:31,768 INFO L87 Difference]: Start difference. First operand 3006 states and 3015 transitions. Second operand 122 states. [2018-10-27 04:52:36,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:52:36,965 INFO L93 Difference]: Finished difference Result 3036 states and 3043 transitions. [2018-10-27 04:52:36,966 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 149 states. [2018-10-27 04:52:36,967 INFO L78 Accepts]: Start accepts. Automaton has 122 states. Word has length 2960 [2018-10-27 04:52:36,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:52:36,971 INFO L225 Difference]: With dead ends: 3036 [2018-10-27 04:52:36,971 INFO L226 Difference]: Without dead ends: 3030 [2018-10-27 04:52:36,974 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3163 GetRequests, 2902 SyntacticMatches, 0 SemanticMatches, 261 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24621 ImplicationChecksByTransitivity, 5.7s TimeCoverageRelationStatistics Valid=9267, Invalid=59639, Unknown=0, NotChecked=0, Total=68906 [2018-10-27 04:52:36,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3030 states. [2018-10-27 04:52:36,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3030 to 3006. [2018-10-27 04:52:36,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3006 states. [2018-10-27 04:52:36,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3006 states to 3006 states and 3013 transitions. [2018-10-27 04:52:36,994 INFO L78 Accepts]: Start accepts. Automaton has 3006 states and 3013 transitions. Word has length 2960 [2018-10-27 04:52:36,995 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:52:36,995 INFO L481 AbstractCegarLoop]: Abstraction has 3006 states and 3013 transitions. [2018-10-27 04:52:36,995 INFO L482 AbstractCegarLoop]: Interpolant automaton has 122 states. [2018-10-27 04:52:36,995 INFO L276 IsEmpty]: Start isEmpty. Operand 3006 states and 3013 transitions. [2018-10-27 04:52:37,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2967 [2018-10-27 04:52:37,025 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:52:37,026 INFO L375 BasicCegarLoop]: trace histogram [461, 434, 434, 433, 433, 433, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:52:37,026 INFO L424 AbstractCegarLoop]: === Iteration 81 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:52:37,026 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:52:37,027 INFO L82 PathProgramCache]: Analyzing trace with hash -1354441231, now seen corresponding path program 67 times [2018-10-27 04:52:37,027 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:52:37,027 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:52:37,027 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:52:37,027 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:52:37,027 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:52:37,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:52:41,309 INFO L134 CoverageAnalysis]: Checked inductivity of 591007 backedges. 71253 proven. 2380 refuted. 0 times theorem prover too weak. 517374 trivial. 0 not checked. [2018-10-27 04:52:41,310 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:52:41,310 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:52:41,321 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:52:41,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:52:41,874 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:52:41,876 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:52:41,876 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:52:41,888 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:52:41,889 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:52:51,799 INFO L134 CoverageAnalysis]: Checked inductivity of 591007 backedges. 71253 proven. 2380 refuted. 0 times theorem prover too weak. 517374 trivial. 0 not checked. [2018-10-27 04:52:51,818 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:52:51,818 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 62 [2018-10-27 04:52:51,819 INFO L460 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-10-27 04:52:51,819 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-10-27 04:52:51,819 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1025, Invalid=2881, Unknown=0, NotChecked=0, Total=3906 [2018-10-27 04:52:51,820 INFO L87 Difference]: Start difference. First operand 3006 states and 3013 transitions. Second operand 63 states. [2018-10-27 04:52:54,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:52:54,519 INFO L93 Difference]: Finished difference Result 3035 states and 3043 transitions. [2018-10-27 04:52:54,520 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-10-27 04:52:54,520 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 2966 [2018-10-27 04:52:54,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:52:54,525 INFO L225 Difference]: With dead ends: 3035 [2018-10-27 04:52:54,525 INFO L226 Difference]: Without dead ends: 3035 [2018-10-27 04:52:54,526 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3028 GetRequests, 2881 SyntacticMatches, 57 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2549 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1633, Invalid=6739, Unknown=0, NotChecked=0, Total=8372 [2018-10-27 04:52:54,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3035 states. [2018-10-27 04:52:54,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3035 to 3012. [2018-10-27 04:52:54,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3012 states. [2018-10-27 04:52:54,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3012 states to 3012 states and 3020 transitions. [2018-10-27 04:52:54,540 INFO L78 Accepts]: Start accepts. Automaton has 3012 states and 3020 transitions. Word has length 2966 [2018-10-27 04:52:54,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:52:54,541 INFO L481 AbstractCegarLoop]: Abstraction has 3012 states and 3020 transitions. [2018-10-27 04:52:54,541 INFO L482 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-10-27 04:52:54,541 INFO L276 IsEmpty]: Start isEmpty. Operand 3012 states and 3020 transitions. [2018-10-27 04:52:54,571 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2973 [2018-10-27 04:52:54,571 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:52:54,572 INFO L375 BasicCegarLoop]: trace histogram [462, 435, 435, 434, 434, 434, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:52:54,572 INFO L424 AbstractCegarLoop]: === Iteration 82 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:52:54,572 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:52:54,573 INFO L82 PathProgramCache]: Analyzing trace with hash 1852667129, now seen corresponding path program 68 times [2018-10-27 04:52:54,573 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:52:54,573 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:52:54,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:52:54,573 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:52:54,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:52:54,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:52:58,194 INFO L134 CoverageAnalysis]: Checked inductivity of 593663 backedges. 76203 proven. 2624 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-10-27 04:52:58,194 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:52:58,194 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:52:58,202 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:52:58,755 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:52:58,755 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:52:58,775 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:53:02,374 INFO L134 CoverageAnalysis]: Checked inductivity of 593663 backedges. 76289 proven. 2538 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-10-27 04:53:02,393 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:53:02,394 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 61] total 93 [2018-10-27 04:53:02,395 INFO L460 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-10-27 04:53:02,395 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-10-27 04:53:02,396 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1954, Invalid=6602, Unknown=0, NotChecked=0, Total=8556 [2018-10-27 04:53:02,396 INFO L87 Difference]: Start difference. First operand 3012 states and 3020 transitions. Second operand 93 states. [2018-10-27 04:53:04,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:53:04,693 INFO L93 Difference]: Finished difference Result 3224 states and 3233 transitions. [2018-10-27 04:53:04,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-10-27 04:53:04,695 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 2972 [2018-10-27 04:53:04,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:53:04,699 INFO L225 Difference]: With dead ends: 3224 [2018-10-27 04:53:04,699 INFO L226 Difference]: Without dead ends: 3224 [2018-10-27 04:53:04,700 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3090 GetRequests, 2942 SyntacticMatches, 0 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3821 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=5599, Invalid=16751, Unknown=0, NotChecked=0, Total=22350 [2018-10-27 04:53:04,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3224 states. [2018-10-27 04:53:04,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3224 to 3199. [2018-10-27 04:53:04,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3199 states. [2018-10-27 04:53:04,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3199 states to 3199 states and 3208 transitions. [2018-10-27 04:53:04,715 INFO L78 Accepts]: Start accepts. Automaton has 3199 states and 3208 transitions. Word has length 2972 [2018-10-27 04:53:04,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:53:04,716 INFO L481 AbstractCegarLoop]: Abstraction has 3199 states and 3208 transitions. [2018-10-27 04:53:04,717 INFO L482 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-10-27 04:53:04,717 INFO L276 IsEmpty]: Start isEmpty. Operand 3199 states and 3208 transitions. [2018-10-27 04:53:04,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3154 [2018-10-27 04:53:04,750 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:53:04,751 INFO L375 BasicCegarLoop]: trace histogram [491, 463, 463, 462, 462, 462, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:53:04,751 INFO L424 AbstractCegarLoop]: === Iteration 83 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:53:04,751 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:53:04,751 INFO L82 PathProgramCache]: Analyzing trace with hash 1249708046, now seen corresponding path program 69 times [2018-10-27 04:53:04,751 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:53:04,751 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:53:04,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:53:04,752 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:53:04,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:53:04,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:53:09,224 INFO L134 CoverageAnalysis]: Checked inductivity of 671748 backedges. 212591 proven. 7389 refuted. 0 times theorem prover too weak. 451768 trivial. 0 not checked. [2018-10-27 04:53:09,224 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:53:09,224 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:53:09,232 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:53:12,307 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-10-27 04:53:12,307 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:53:12,332 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:53:17,252 INFO L134 CoverageAnalysis]: Checked inductivity of 671748 backedges. 147035 proven. 7312 refuted. 0 times theorem prover too weak. 517401 trivial. 0 not checked. [2018-10-27 04:53:17,272 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:53:17,273 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 65] total 126 [2018-10-27 04:53:17,273 INFO L460 AbstractCegarLoop]: Interpolant automaton has 126 states [2018-10-27 04:53:17,274 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 126 interpolants. [2018-10-27 04:53:17,274 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2340, Invalid=13410, Unknown=0, NotChecked=0, Total=15750 [2018-10-27 04:53:17,275 INFO L87 Difference]: Start difference. First operand 3199 states and 3208 transitions. Second operand 126 states. [2018-10-27 04:53:21,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:53:21,662 INFO L93 Difference]: Finished difference Result 3229 states and 3236 transitions. [2018-10-27 04:53:21,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 128 states. [2018-10-27 04:53:21,664 INFO L78 Accepts]: Start accepts. Automaton has 126 states. Word has length 3153 [2018-10-27 04:53:21,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:53:21,668 INFO L225 Difference]: With dead ends: 3229 [2018-10-27 04:53:21,668 INFO L226 Difference]: Without dead ends: 3223 [2018-10-27 04:53:21,671 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3337 GetRequests, 3093 SyntacticMatches, 0 SemanticMatches, 244 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19753 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=9556, Invalid=50714, Unknown=0, NotChecked=0, Total=60270 [2018-10-27 04:53:21,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3223 states. [2018-10-27 04:53:21,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3223 to 3199. [2018-10-27 04:53:21,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3199 states. [2018-10-27 04:53:21,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3199 states to 3199 states and 3206 transitions. [2018-10-27 04:53:21,694 INFO L78 Accepts]: Start accepts. Automaton has 3199 states and 3206 transitions. Word has length 3153 [2018-10-27 04:53:21,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:53:21,696 INFO L481 AbstractCegarLoop]: Abstraction has 3199 states and 3206 transitions. [2018-10-27 04:53:21,696 INFO L482 AbstractCegarLoop]: Interpolant automaton has 126 states. [2018-10-27 04:53:21,696 INFO L276 IsEmpty]: Start isEmpty. Operand 3199 states and 3206 transitions. [2018-10-27 04:53:21,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3160 [2018-10-27 04:53:21,730 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:53:21,730 INFO L375 BasicCegarLoop]: trace histogram [492, 464, 464, 463, 463, 463, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:53:21,730 INFO L424 AbstractCegarLoop]: === Iteration 84 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:53:21,730 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:53:21,731 INFO L82 PathProgramCache]: Analyzing trace with hash 657517574, now seen corresponding path program 70 times [2018-10-27 04:53:21,731 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:53:21,731 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:53:21,731 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:53:21,731 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:53:21,732 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:53:22,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:53:26,531 INFO L134 CoverageAnalysis]: Checked inductivity of 674580 backedges. 78960 proven. 2552 refuted. 0 times theorem prover too weak. 593068 trivial. 0 not checked. [2018-10-27 04:53:26,531 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:53:26,531 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:53:26,539 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:53:27,995 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:53:27,995 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:53:28,035 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:53:28,040 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:53:28,041 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:53:28,052 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:53:28,053 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:53:39,565 INFO L134 CoverageAnalysis]: Checked inductivity of 674580 backedges. 78960 proven. 2552 refuted. 0 times theorem prover too weak. 593068 trivial. 0 not checked. [2018-10-27 04:53:39,591 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:53:39,592 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 64 [2018-10-27 04:53:39,593 INFO L460 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-10-27 04:53:39,593 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-10-27 04:53:39,593 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1090, Invalid=3070, Unknown=0, NotChecked=0, Total=4160 [2018-10-27 04:53:39,594 INFO L87 Difference]: Start difference. First operand 3199 states and 3206 transitions. Second operand 65 states. [2018-10-27 04:53:42,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:53:42,317 INFO L93 Difference]: Finished difference Result 3228 states and 3236 transitions. [2018-10-27 04:53:42,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-10-27 04:53:42,318 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 3159 [2018-10-27 04:53:42,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:53:42,322 INFO L225 Difference]: With dead ends: 3228 [2018-10-27 04:53:42,323 INFO L226 Difference]: Without dead ends: 3228 [2018-10-27 04:53:42,323 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3223 GetRequests, 3071 SyntacticMatches, 59 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2727 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1734, Invalid=7196, Unknown=0, NotChecked=0, Total=8930 [2018-10-27 04:53:42,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3228 states. [2018-10-27 04:53:42,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3228 to 3205. [2018-10-27 04:53:42,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3205 states. [2018-10-27 04:53:42,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3205 states to 3205 states and 3213 transitions. [2018-10-27 04:53:42,338 INFO L78 Accepts]: Start accepts. Automaton has 3205 states and 3213 transitions. Word has length 3159 [2018-10-27 04:53:42,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:53:42,339 INFO L481 AbstractCegarLoop]: Abstraction has 3205 states and 3213 transitions. [2018-10-27 04:53:42,340 INFO L482 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-10-27 04:53:42,340 INFO L276 IsEmpty]: Start isEmpty. Operand 3205 states and 3213 transitions. [2018-10-27 04:53:42,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3166 [2018-10-27 04:53:42,388 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:53:42,389 INFO L375 BasicCegarLoop]: trace histogram [493, 465, 465, 464, 464, 464, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:53:42,389 INFO L424 AbstractCegarLoop]: === Iteration 85 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:53:42,389 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:53:42,390 INFO L82 PathProgramCache]: Analyzing trace with hash 863625038, now seen corresponding path program 71 times [2018-10-27 04:53:42,390 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:53:42,390 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:53:42,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:53:42,390 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:53:42,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:53:42,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:53:46,447 INFO L134 CoverageAnalysis]: Checked inductivity of 677418 backedges. 84261 proven. 2819 refuted. 0 times theorem prover too weak. 590338 trivial. 0 not checked. [2018-10-27 04:53:46,447 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:53:46,447 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:53:46,456 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:54:06,082 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 64 check-sat command(s) [2018-10-27 04:54:06,082 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:54:06,134 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:54:10,300 INFO L134 CoverageAnalysis]: Checked inductivity of 677418 backedges. 84008 proven. 9373 refuted. 0 times theorem prover too weak. 584037 trivial. 0 not checked. [2018-10-27 04:54:10,331 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:54:10,332 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 68] total 100 [2018-10-27 04:54:10,333 INFO L460 AbstractCegarLoop]: Interpolant automaton has 100 states [2018-10-27 04:54:10,333 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2018-10-27 04:54:10,334 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2093, Invalid=7807, Unknown=0, NotChecked=0, Total=9900 [2018-10-27 04:54:10,334 INFO L87 Difference]: Start difference. First operand 3205 states and 3213 transitions. Second operand 100 states. [2018-10-27 04:54:12,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:54:12,670 INFO L93 Difference]: Finished difference Result 3423 states and 3432 transitions. [2018-10-27 04:54:12,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2018-10-27 04:54:12,672 INFO L78 Accepts]: Start accepts. Automaton has 100 states. Word has length 3165 [2018-10-27 04:54:12,673 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:54:12,676 INFO L225 Difference]: With dead ends: 3423 [2018-10-27 04:54:12,676 INFO L226 Difference]: Without dead ends: 3423 [2018-10-27 04:54:12,678 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3289 GetRequests, 3130 SyntacticMatches, 0 SemanticMatches, 159 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4796 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=5873, Invalid=19887, Unknown=0, NotChecked=0, Total=25760 [2018-10-27 04:54:12,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3423 states. [2018-10-27 04:54:12,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3423 to 3398. [2018-10-27 04:54:12,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3398 states. [2018-10-27 04:54:12,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3398 states to 3398 states and 3407 transitions. [2018-10-27 04:54:12,695 INFO L78 Accepts]: Start accepts. Automaton has 3398 states and 3407 transitions. Word has length 3165 [2018-10-27 04:54:12,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:54:12,696 INFO L481 AbstractCegarLoop]: Abstraction has 3398 states and 3407 transitions. [2018-10-27 04:54:12,696 INFO L482 AbstractCegarLoop]: Interpolant automaton has 100 states. [2018-10-27 04:54:12,697 INFO L276 IsEmpty]: Start isEmpty. Operand 3398 states and 3407 transitions. [2018-10-27 04:54:12,739 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3353 [2018-10-27 04:54:12,739 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:54:12,740 INFO L375 BasicCegarLoop]: trace histogram [523, 494, 494, 493, 493, 493, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:54:12,740 INFO L424 AbstractCegarLoop]: === Iteration 86 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:54:12,740 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:54:12,741 INFO L82 PathProgramCache]: Analyzing trace with hash -951385631, now seen corresponding path program 72 times [2018-10-27 04:54:12,741 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:54:12,741 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:54:12,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:54:12,741 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:54:12,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:54:12,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:54:17,311 INFO L134 CoverageAnalysis]: Checked inductivity of 763686 backedges. 167558 proven. 11970 refuted. 0 times theorem prover too weak. 584158 trivial. 0 not checked. [2018-10-27 04:54:17,312 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:54:17,312 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:54:17,319 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-10-27 04:54:41,368 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 59 check-sat command(s) [2018-10-27 04:54:41,368 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:54:41,408 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:54:41,410 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:54:41,410 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:54:41,421 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:54:41,421 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:54:56,747 INFO L134 CoverageAnalysis]: Checked inductivity of 763686 backedges. 159855 proven. 8387 refuted. 0 times theorem prover too weak. 595444 trivial. 0 not checked. [2018-10-27 04:54:56,772 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:54:56,773 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 40] total 105 [2018-10-27 04:54:56,774 INFO L460 AbstractCegarLoop]: Interpolant automaton has 105 states [2018-10-27 04:54:56,774 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 105 interpolants. [2018-10-27 04:54:56,775 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1533, Invalid=9387, Unknown=0, NotChecked=0, Total=10920 [2018-10-27 04:54:56,775 INFO L87 Difference]: Start difference. First operand 3398 states and 3407 transitions. Second operand 105 states. [2018-10-27 04:55:08,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:55:08,106 INFO L93 Difference]: Finished difference Result 3633 states and 3642 transitions. [2018-10-27 04:55:08,108 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 220 states. [2018-10-27 04:55:08,108 INFO L78 Accepts]: Start accepts. Automaton has 105 states. Word has length 3352 [2018-10-27 04:55:08,110 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:55:08,112 INFO L225 Difference]: With dead ends: 3633 [2018-10-27 04:55:08,112 INFO L226 Difference]: Without dead ends: 3624 [2018-10-27 04:55:08,116 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3633 GetRequests, 3258 SyntacticMatches, 57 SemanticMatches, 318 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44391 ImplicationChecksByTransitivity, 13.6s TimeCoverageRelationStatistics Valid=15621, Invalid=86459, Unknown=0, NotChecked=0, Total=102080 [2018-10-27 04:55:08,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3624 states. [2018-10-27 04:55:08,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3624 to 3591. [2018-10-27 04:55:08,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3591 states. [2018-10-27 04:55:08,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3591 states to 3591 states and 3599 transitions. [2018-10-27 04:55:08,140 INFO L78 Accepts]: Start accepts. Automaton has 3591 states and 3599 transitions. Word has length 3352 [2018-10-27 04:55:08,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:55:08,142 INFO L481 AbstractCegarLoop]: Abstraction has 3591 states and 3599 transitions. [2018-10-27 04:55:08,142 INFO L482 AbstractCegarLoop]: Interpolant automaton has 105 states. [2018-10-27 04:55:08,142 INFO L276 IsEmpty]: Start isEmpty. Operand 3591 states and 3599 transitions. [2018-10-27 04:55:08,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3552 [2018-10-27 04:55:08,187 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:55:08,187 INFO L375 BasicCegarLoop]: trace histogram [555, 525, 525, 524, 524, 524, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:55:08,187 INFO L424 AbstractCegarLoop]: === Iteration 87 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:55:08,188 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:55:08,188 INFO L82 PathProgramCache]: Analyzing trace with hash 208367790, now seen corresponding path program 73 times [2018-10-27 04:55:08,188 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:55:08,188 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:55:08,189 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:55:08,189 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:55:08,189 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:55:08,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:55:13,614 INFO L134 CoverageAnalysis]: Checked inductivity of 861527 backedges. 257215 proven. 8457 refuted. 0 times theorem prover too weak. 595855 trivial. 0 not checked. [2018-10-27 04:55:13,614 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:55:13,614 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:55:13,622 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:55:14,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:55:14,231 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:55:19,896 INFO L134 CoverageAnalysis]: Checked inductivity of 861527 backedges. 182254 proven. 2670 refuted. 0 times theorem prover too weak. 676603 trivial. 0 not checked. [2018-10-27 04:55:19,915 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:55:19,916 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 64] total 127 [2018-10-27 04:55:19,917 INFO L460 AbstractCegarLoop]: Interpolant automaton has 127 states [2018-10-27 04:55:19,917 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 127 interpolants. [2018-10-27 04:55:19,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2577, Invalid=13425, Unknown=0, NotChecked=0, Total=16002 [2018-10-27 04:55:19,918 INFO L87 Difference]: Start difference. First operand 3591 states and 3599 transitions. Second operand 127 states. [2018-10-27 04:55:25,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:55:25,420 INFO L93 Difference]: Finished difference Result 3634 states and 3642 transitions. [2018-10-27 04:55:25,422 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 124 states. [2018-10-27 04:55:25,422 INFO L78 Accepts]: Start accepts. Automaton has 127 states. Word has length 3551 [2018-10-27 04:55:25,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:55:25,427 INFO L225 Difference]: With dead ends: 3634 [2018-10-27 04:55:25,427 INFO L226 Difference]: Without dead ends: 3628 [2018-10-27 04:55:25,429 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3711 GetRequests, 3495 SyntacticMatches, 0 SemanticMatches, 216 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16388 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=7309, Invalid=39997, Unknown=0, NotChecked=0, Total=47306 [2018-10-27 04:55:25,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3628 states. [2018-10-27 04:55:25,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3628 to 3601. [2018-10-27 04:55:25,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3601 states. [2018-10-27 04:55:25,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3601 states to 3601 states and 3609 transitions. [2018-10-27 04:55:25,451 INFO L78 Accepts]: Start accepts. Automaton has 3601 states and 3609 transitions. Word has length 3551 [2018-10-27 04:55:25,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:55:25,453 INFO L481 AbstractCegarLoop]: Abstraction has 3601 states and 3609 transitions. [2018-10-27 04:55:25,453 INFO L482 AbstractCegarLoop]: Interpolant automaton has 127 states. [2018-10-27 04:55:25,453 INFO L276 IsEmpty]: Start isEmpty. Operand 3601 states and 3609 transitions. [2018-10-27 04:55:25,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3558 [2018-10-27 04:55:25,525 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:55:25,526 INFO L375 BasicCegarLoop]: trace histogram [556, 526, 526, 525, 525, 525, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:55:25,526 INFO L424 AbstractCegarLoop]: === Iteration 88 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:55:25,526 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:55:25,527 INFO L82 PathProgramCache]: Analyzing trace with hash -1216964442, now seen corresponding path program 74 times [2018-10-27 04:55:25,527 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:55:25,527 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:55:25,527 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:55:25,527 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 04:55:25,527 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:55:25,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:55:31,310 INFO L134 CoverageAnalysis]: Checked inductivity of 864735 backedges. 92970 proven. 2730 refuted. 0 times theorem prover too weak. 769035 trivial. 0 not checked. [2018-10-27 04:55:31,310 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:55:31,310 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:55:31,319 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-10-27 04:55:31,925 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-10-27 04:55:31,925 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:55:31,953 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:55:31,954 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:55:31,954 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:55:31,969 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:55:31,969 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:55:46,394 INFO L134 CoverageAnalysis]: Checked inductivity of 864735 backedges. 92970 proven. 2730 refuted. 0 times theorem prover too weak. 769035 trivial. 0 not checked. [2018-10-27 04:55:46,446 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:55:46,447 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 66 [2018-10-27 04:55:46,448 INFO L460 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-10-27 04:55:46,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-10-27 04:55:46,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1157, Invalid=3265, Unknown=0, NotChecked=0, Total=4422 [2018-10-27 04:55:46,449 INFO L87 Difference]: Start difference. First operand 3601 states and 3609 transitions. Second operand 67 states. [2018-10-27 04:55:49,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:55:49,518 INFO L93 Difference]: Finished difference Result 3627 states and 3635 transitions. [2018-10-27 04:55:49,520 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-10-27 04:55:49,520 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 3557 [2018-10-27 04:55:49,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:55:49,525 INFO L225 Difference]: With dead ends: 3627 [2018-10-27 04:55:49,525 INFO L226 Difference]: Without dead ends: 3627 [2018-10-27 04:55:49,526 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3623 GetRequests, 3464 SyntacticMatches, 63 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2914 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1838, Invalid=7668, Unknown=0, NotChecked=0, Total=9506 [2018-10-27 04:55:49,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3627 states. [2018-10-27 04:55:49,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3627 to 3603. [2018-10-27 04:55:49,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3603 states. [2018-10-27 04:55:49,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3603 states to 3603 states and 3611 transitions. [2018-10-27 04:55:49,545 INFO L78 Accepts]: Start accepts. Automaton has 3603 states and 3611 transitions. Word has length 3557 [2018-10-27 04:55:49,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:55:49,547 INFO L481 AbstractCegarLoop]: Abstraction has 3603 states and 3611 transitions. [2018-10-27 04:55:49,547 INFO L482 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-10-27 04:55:49,547 INFO L276 IsEmpty]: Start isEmpty. Operand 3603 states and 3611 transitions. [2018-10-27 04:55:49,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3564 [2018-10-27 04:55:49,589 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:55:49,589 INFO L375 BasicCegarLoop]: trace histogram [557, 527, 527, 526, 526, 526, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:55:49,589 INFO L424 AbstractCegarLoop]: === Iteration 89 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:55:49,590 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:55:49,590 INFO L82 PathProgramCache]: Analyzing trace with hash 2075366382, now seen corresponding path program 75 times [2018-10-27 04:55:49,590 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:55:49,590 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:55:49,591 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:55:49,591 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:55:49,591 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:55:49,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:55:56,066 INFO L134 CoverageAnalysis]: Checked inductivity of 867949 backedges. 96000 proven. 2914 refuted. 0 times theorem prover too weak. 769035 trivial. 0 not checked. [2018-10-27 04:55:56,066 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:55:56,066 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:55:56,074 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-10-27 04:56:06,483 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 32 check-sat command(s) [2018-10-27 04:56:06,483 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:56:06,517 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:56:06,532 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-10-27 04:56:06,533 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-10-27 04:56:06,608 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-10-27 04:56:06,609 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-10-27 04:56:21,380 INFO L134 CoverageAnalysis]: Checked inductivity of 867949 backedges. 96000 proven. 2914 refuted. 0 times theorem prover too weak. 769035 trivial. 0 not checked. [2018-10-27 04:56:21,401 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:56:21,401 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 68 [2018-10-27 04:56:21,402 INFO L460 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-10-27 04:56:21,402 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-10-27 04:56:21,403 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1226, Invalid=3466, Unknown=0, NotChecked=0, Total=4692 [2018-10-27 04:56:21,403 INFO L87 Difference]: Start difference. First operand 3603 states and 3611 transitions. Second operand 69 states. [2018-10-27 04:56:24,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:56:24,611 INFO L93 Difference]: Finished difference Result 3645 states and 3655 transitions. [2018-10-27 04:56:24,613 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-10-27 04:56:24,613 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 3563 [2018-10-27 04:56:24,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:56:24,618 INFO L225 Difference]: With dead ends: 3645 [2018-10-27 04:56:24,618 INFO L226 Difference]: Without dead ends: 3645 [2018-10-27 04:56:24,618 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3631 GetRequests, 3469 SyntacticMatches, 63 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3101 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=1945, Invalid=8155, Unknown=0, NotChecked=0, Total=10100 [2018-10-27 04:56:24,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3645 states. [2018-10-27 04:56:24,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3645 to 3609. [2018-10-27 04:56:24,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3609 states. [2018-10-27 04:56:24,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3609 states to 3609 states and 3618 transitions. [2018-10-27 04:56:24,639 INFO L78 Accepts]: Start accepts. Automaton has 3609 states and 3618 transitions. Word has length 3563 [2018-10-27 04:56:24,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:56:24,641 INFO L481 AbstractCegarLoop]: Abstraction has 3609 states and 3618 transitions. [2018-10-27 04:56:24,641 INFO L482 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-10-27 04:56:24,641 INFO L276 IsEmpty]: Start isEmpty. Operand 3609 states and 3618 transitions. [2018-10-27 04:56:24,686 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3570 [2018-10-27 04:56:24,687 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:56:24,687 INFO L375 BasicCegarLoop]: trace histogram [558, 528, 528, 527, 527, 527, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:56:24,687 INFO L424 AbstractCegarLoop]: === Iteration 90 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:56:24,687 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:56:24,688 INFO L82 PathProgramCache]: Analyzing trace with hash -1077348042, now seen corresponding path program 76 times [2018-10-27 04:56:24,688 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:56:24,688 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:56:24,688 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:56:24,689 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:56:24,689 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:56:24,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:56:29,563 INFO L134 CoverageAnalysis]: Checked inductivity of 871169 backedges. 102039 proven. 3230 refuted. 0 times theorem prover too weak. 765900 trivial. 0 not checked. [2018-10-27 04:56:29,563 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:56:29,563 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:56:29,571 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-10-27 04:56:30,085 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-10-27 04:56:30,085 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:56:30,109 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:56:34,947 INFO L134 CoverageAnalysis]: Checked inductivity of 871169 backedges. 102134 proven. 3135 refuted. 0 times theorem prover too weak. 765900 trivial. 0 not checked. [2018-10-27 04:56:34,966 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:56:34,967 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 67] total 102 [2018-10-27 04:56:34,968 INFO L460 AbstractCegarLoop]: Interpolant automaton has 102 states [2018-10-27 04:56:34,969 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 102 interpolants. [2018-10-27 04:56:34,969 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2347, Invalid=7955, Unknown=0, NotChecked=0, Total=10302 [2018-10-27 04:56:34,969 INFO L87 Difference]: Start difference. First operand 3609 states and 3618 transitions. Second operand 102 states. [2018-10-27 04:56:38,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:56:38,174 INFO L93 Difference]: Finished difference Result 3848 states and 3858 transitions. [2018-10-27 04:56:38,176 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2018-10-27 04:56:38,176 INFO L78 Accepts]: Start accepts. Automaton has 102 states. Word has length 3569 [2018-10-27 04:56:38,178 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:56:38,180 INFO L225 Difference]: With dead ends: 3848 [2018-10-27 04:56:38,180 INFO L226 Difference]: Without dead ends: 3848 [2018-10-27 04:56:38,182 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3699 GetRequests, 3536 SyntacticMatches, 0 SemanticMatches, 163 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4649 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=6754, Invalid=20306, Unknown=0, NotChecked=0, Total=27060 [2018-10-27 04:56:38,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3848 states. [2018-10-27 04:56:38,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3848 to 3820. [2018-10-27 04:56:38,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3820 states. [2018-10-27 04:56:38,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3820 states to 3820 states and 3830 transitions. [2018-10-27 04:56:38,198 INFO L78 Accepts]: Start accepts. Automaton has 3820 states and 3830 transitions. Word has length 3569 [2018-10-27 04:56:38,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:56:38,200 INFO L481 AbstractCegarLoop]: Abstraction has 3820 states and 3830 transitions. [2018-10-27 04:56:38,200 INFO L482 AbstractCegarLoop]: Interpolant automaton has 102 states. [2018-10-27 04:56:38,200 INFO L276 IsEmpty]: Start isEmpty. Operand 3820 states and 3830 transitions. [2018-10-27 04:56:38,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3769 [2018-10-27 04:56:38,246 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:56:38,247 INFO L375 BasicCegarLoop]: trace histogram [590, 559, 559, 558, 558, 558, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:56:38,247 INFO L424 AbstractCegarLoop]: === Iteration 91 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:56:38,247 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:56:38,247 INFO L82 PathProgramCache]: Analyzing trace with hash 159355657, now seen corresponding path program 77 times [2018-10-27 04:56:38,247 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:56:38,247 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:56:38,248 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:56:38,248 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:56:38,248 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:56:38,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 04:56:43,948 INFO L134 CoverageAnalysis]: Checked inductivity of 975477 backedges. 203013 proven. 13610 refuted. 0 times theorem prover too weak. 758854 trivial. 0 not checked. [2018-10-27 04:56:43,948 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-10-27 04:56:43,948 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/z3 Starting monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-10-27 04:56:43,956 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-10-27 04:57:16,424 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 83 check-sat command(s) [2018-10-27 04:57:16,424 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-10-27 04:57:16,479 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 04:57:21,445 INFO L134 CoverageAnalysis]: Checked inductivity of 975477 backedges. 203150 proven. 10466 refuted. 0 times theorem prover too weak. 761861 trivial. 0 not checked. [2018-10-27 04:57:21,483 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-10-27 04:57:21,484 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 70] total 106 [2018-10-27 04:57:21,485 INFO L460 AbstractCegarLoop]: Interpolant automaton has 106 states [2018-10-27 04:57:21,485 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 106 interpolants. [2018-10-27 04:57:21,486 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2235, Invalid=8895, Unknown=0, NotChecked=0, Total=11130 [2018-10-27 04:57:21,486 INFO L87 Difference]: Start difference. First operand 3820 states and 3830 transitions. Second operand 106 states. [2018-10-27 04:57:24,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 04:57:24,161 INFO L93 Difference]: Finished difference Result 3849 states and 3857 transitions. [2018-10-27 04:57:24,163 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2018-10-27 04:57:24,163 INFO L78 Accepts]: Start accepts. Automaton has 106 states. Word has length 3768 [2018-10-27 04:57:24,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-10-27 04:57:24,168 INFO L225 Difference]: With dead ends: 3849 [2018-10-27 04:57:24,168 INFO L226 Difference]: Without dead ends: 3843 [2018-10-27 04:57:24,170 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3904 GetRequests, 3734 SyntacticMatches, 0 SemanticMatches, 170 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9954 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=6424, Invalid=22988, Unknown=0, NotChecked=0, Total=29412 [2018-10-27 04:57:24,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3843 states. [2018-10-27 04:57:24,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3843 to 3820. [2018-10-27 04:57:24,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3820 states. [2018-10-27 04:57:24,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3820 states to 3820 states and 3828 transitions. [2018-10-27 04:57:24,187 INFO L78 Accepts]: Start accepts. Automaton has 3820 states and 3828 transitions. Word has length 3768 [2018-10-27 04:57:24,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-10-27 04:57:24,189 INFO L481 AbstractCegarLoop]: Abstraction has 3820 states and 3828 transitions. [2018-10-27 04:57:24,189 INFO L482 AbstractCegarLoop]: Interpolant automaton has 106 states. [2018-10-27 04:57:24,189 INFO L276 IsEmpty]: Start isEmpty. Operand 3820 states and 3828 transitions. [2018-10-27 04:57:24,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3775 [2018-10-27 04:57:24,235 INFO L367 BasicCegarLoop]: Found error trace [2018-10-27 04:57:24,236 INFO L375 BasicCegarLoop]: trace histogram [591, 560, 560, 559, 559, 559, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 04:57:24,236 INFO L424 AbstractCegarLoop]: === Iteration 92 === [fooErr1REQUIRES_VIOLATION, fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION]=== [2018-10-27 04:57:24,236 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 04:57:24,236 INFO L82 PathProgramCache]: Analyzing trace with hash -328613183, now seen corresponding path program 78 times [2018-10-27 04:57:24,236 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 04:57:24,236 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 04:57:24,237 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:57:24,237 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 04:57:24,237 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 04:57:25,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 04:57:26,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 04:57:27,188 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-10-27 04:57:27,620 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.10 04:57:27 BoogieIcfgContainer [2018-10-27 04:57:27,623 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-10-27 04:57:27,624 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-10-27 04:57:27,624 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-10-27 04:57:27,625 INFO L276 PluginConnector]: Witness Printer initialized [2018-10-27 04:57:27,625 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 04:45:32" (3/4) ... [2018-10-27 04:57:27,627 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-10-27 04:57:28,099 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_6a3ab8d5-0e3d-4978-ab86-58224b4dfa68/bin-2019/uautomizer/witness.graphml [2018-10-27 04:57:28,103 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-10-27 04:57:28,104 INFO L168 Benchmark]: Toolchain (without parser) took 716169.64 ms. Allocated memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: 4.0 GB). Free memory was 955.8 MB in the beginning and 3.5 GB in the end (delta: -2.6 GB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2018-10-27 04:57:28,104 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 977.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-27 04:57:28,104 INFO L168 Benchmark]: CACSL2BoogieTranslator took 174.93 ms. Allocated memory is still 1.0 GB. Free memory was 955.8 MB in the beginning and 945.0 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2018-10-27 04:57:28,104 INFO L168 Benchmark]: Boogie Preprocessor took 30.63 ms. Allocated memory is still 1.0 GB. Free memory was 945.0 MB in the beginning and 939.7 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-10-27 04:57:28,105 INFO L168 Benchmark]: RCFGBuilder took 502.69 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 133.2 MB). Free memory was 939.7 MB in the beginning and 1.1 GB in the end (delta: -166.5 MB). Peak memory consumption was 20.8 MB. Max. memory is 11.5 GB. [2018-10-27 04:57:28,110 INFO L168 Benchmark]: TraceAbstraction took 714978.24 ms. Allocated memory was 1.2 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 3.6 GB in the end (delta: -2.5 GB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2018-10-27 04:57:28,110 INFO L168 Benchmark]: Witness Printer took 478.55 ms. Allocated memory is still 5.0 GB. Free memory was 3.6 GB in the beginning and 3.5 GB in the end (delta: 82.7 MB). Peak memory consumption was 82.7 MB. Max. memory is 11.5 GB. [2018-10-27 04:57:28,111 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 977.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 174.93 ms. Allocated memory is still 1.0 GB. Free memory was 955.8 MB in the beginning and 945.0 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 30.63 ms. Allocated memory is still 1.0 GB. Free memory was 945.0 MB in the beginning and 939.7 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 502.69 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 133.2 MB). Free memory was 939.7 MB in the beginning and 1.1 GB in the end (delta: -166.5 MB). Peak memory consumption was 20.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 714978.24 ms. Allocated memory was 1.2 GB in the beginning and 5.0 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 3.6 GB in the end (delta: -2.5 GB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. * Witness Printer took 478.55 ms. Allocated memory is still 5.0 GB. Free memory was 3.6 GB in the beginning and 3.5 GB in the end (delta: 82.7 MB). Peak memory consumption was 82.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: pointer dereference may fail pointer dereference may fail We found a FailurePath: [L24] int i, b[32]; VAL [b={158:0}] [L25] FCALL char mask[32]; VAL [b={158:0}, mask={160:0}] [L26] i = 0 VAL [b={158:0}, i=0, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=0, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=0, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=0, b={160:0}, b={160:0}, i=0, size=0] [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={160:0}, b={160:0}, i=0, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={160:0}, b={160:0}, i=0, size=0] [L18] EXPR, FCALL b[i] VAL [\old(size)=0, b={160:0}, b={160:0}, b[i]=129, i=0, size=0] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=0, b={160:0}, b={160:0}, i=1, size=0] [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={160:0}, b={160:0}, i=1, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={160:0}, b={160:0}, i=1, size=0] [L18] EXPR, FCALL b[i] VAL [\old(size)=0, b={160:0}, b={160:0}, b[i]=144, i=1, size=0] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=0, b={160:0}, b={160:0}, i=2, size=0] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=0, b={160:0}, b={160:0}, i=2, size=0] [L20] RET return i; VAL [\old(size)=0, \result=2, b={160:0}, b={160:0}, i=2, size=0] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=2, i=0, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=2, i=0, mask={160:0}] [L26] i++ VAL [b={158:0}, i=1, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=1, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=1, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={160:0}, b={160:0}, i=0, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={160:0}, b={160:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={160:0}, b={160:0}, i=0, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={160:0}, b={160:0}, b[i]=129, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={160:0}, b={160:0}, i=1, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={160:0}, b={160:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={160:0}, b={160:0}, i=1, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={160:0}, b={160:0}, b[i]=144, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={160:0}, b={160:0}, i=2, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={160:0}, b={160:0}, i=2, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={160:0}, b={160:0}, i=2, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={160:0}, b={160:0}, b[i]=134, i=2, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={160:0}, b={160:0}, i=3, size=1] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=1, b={160:0}, b={160:0}, i=3, size=1] [L20] RET return i; VAL [\old(size)=1, \result=3, b={160:0}, b={160:0}, i=3, size=1] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=3, i=1, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=3, i=1, mask={160:0}] [L26] i++ VAL [b={158:0}, i=2, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=2, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=2, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={160:0}, b={160:0}, i=0, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={160:0}, b={160:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={160:0}, b={160:0}, i=0, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={160:0}, b={160:0}, b[i]=129, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={160:0}, b={160:0}, i=1, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={160:0}, b={160:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={160:0}, b={160:0}, i=1, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={160:0}, b={160:0}, b[i]=144, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={160:0}, b={160:0}, i=2, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={160:0}, b={160:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={160:0}, b={160:0}, i=2, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={160:0}, b={160:0}, b[i]=134, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={160:0}, b={160:0}, i=3, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={160:0}, b={160:0}, i=3, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={160:0}, b={160:0}, i=3, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={160:0}, b={160:0}, b[i]=132, i=3, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={160:0}, b={160:0}, i=4, size=2] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=2, b={160:0}, b={160:0}, i=4, size=2] [L20] RET return i; VAL [\old(size)=2, \result=4, b={160:0}, b={160:0}, i=4, size=2] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=4, i=2, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=4, i=2, mask={160:0}] [L26] i++ VAL [b={158:0}, i=3, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=3, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=3, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={160:0}, b={160:0}, i=0, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={160:0}, b={160:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={160:0}, b={160:0}, i=0, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={160:0}, b={160:0}, b[i]=129, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={160:0}, b={160:0}, i=1, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={160:0}, b={160:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={160:0}, b={160:0}, i=1, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={160:0}, b={160:0}, b[i]=144, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={160:0}, b={160:0}, i=2, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={160:0}, b={160:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={160:0}, b={160:0}, i=2, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={160:0}, b={160:0}, b[i]=134, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={160:0}, b={160:0}, i=3, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={160:0}, b={160:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={160:0}, b={160:0}, i=3, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={160:0}, b={160:0}, b[i]=132, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={160:0}, b={160:0}, i=4, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={160:0}, b={160:0}, i=4, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={160:0}, b={160:0}, i=4, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={160:0}, b={160:0}, b[i]=141, i=4, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={160:0}, b={160:0}, i=5, size=3] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=3, b={160:0}, b={160:0}, i=5, size=3] [L20] RET return i; VAL [\old(size)=3, \result=5, b={160:0}, b={160:0}, i=5, size=3] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=5, i=3, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=5, i=3, mask={160:0}] [L26] i++ VAL [b={158:0}, i=4, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=4, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=4, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={160:0}, b={160:0}, i=0, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={160:0}, b={160:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={160:0}, b={160:0}, i=0, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={160:0}, b={160:0}, b[i]=129, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={160:0}, b={160:0}, i=1, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={160:0}, b={160:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={160:0}, b={160:0}, i=1, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={160:0}, b={160:0}, b[i]=144, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={160:0}, b={160:0}, i=2, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={160:0}, b={160:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={160:0}, b={160:0}, i=2, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={160:0}, b={160:0}, b[i]=134, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={160:0}, b={160:0}, i=3, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={160:0}, b={160:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={160:0}, b={160:0}, i=3, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={160:0}, b={160:0}, b[i]=132, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={160:0}, b={160:0}, i=4, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={160:0}, b={160:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={160:0}, b={160:0}, i=4, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={160:0}, b={160:0}, b[i]=141, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={160:0}, b={160:0}, i=5, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={160:0}, b={160:0}, i=5, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={160:0}, b={160:0}, i=5, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={160:0}, b={160:0}, b[i]=146, i=5, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={160:0}, b={160:0}, i=6, size=4] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=4, b={160:0}, b={160:0}, i=6, size=4] [L20] RET return i; VAL [\old(size)=4, \result=6, b={160:0}, b={160:0}, i=6, size=4] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=6, i=4, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=6, i=4, mask={160:0}] [L26] i++ VAL [b={158:0}, i=5, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=5, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=5, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={160:0}, b={160:0}, i=0, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={160:0}, b={160:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=0, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=129, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=1, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={160:0}, b={160:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=1, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=144, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=2, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={160:0}, b={160:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=2, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=134, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=3, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={160:0}, b={160:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=3, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=132, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=4, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={160:0}, b={160:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=4, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=141, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=5, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={160:0}, b={160:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=5, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=146, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=6, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={160:0}, b={160:0}, i=6, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=6, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=142, i=6, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=7, size=5] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=5, b={160:0}, b={160:0}, i=7, size=5] [L20] RET return i; VAL [\old(size)=5, \result=7, b={160:0}, b={160:0}, i=7, size=5] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=7, i=5, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=7, i=5, mask={160:0}] [L26] i++ VAL [b={158:0}, i=6, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=6, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=6, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={160:0}, b={160:0}, i=0, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={160:0}, b={160:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=0, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=129, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=1, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={160:0}, b={160:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=1, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=144, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=2, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={160:0}, b={160:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=2, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=134, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=3, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={160:0}, b={160:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=3, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=132, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=4, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={160:0}, b={160:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=4, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=141, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=5, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={160:0}, b={160:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=5, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=146, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=6, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={160:0}, b={160:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=6, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=142, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=7, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={160:0}, b={160:0}, i=7, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=7, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=157, i=7, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=8, size=6] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=6, b={160:0}, b={160:0}, i=8, size=6] [L20] RET return i; VAL [\old(size)=6, \result=8, b={160:0}, b={160:0}, i=8, size=6] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=8, i=6, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=8, i=6, mask={160:0}] [L26] i++ VAL [b={158:0}, i=7, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=7, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=7, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={160:0}, b={160:0}, i=0, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={160:0}, b={160:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=0, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=129, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=1, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={160:0}, b={160:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=1, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=144, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=2, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={160:0}, b={160:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=2, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=134, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=3, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={160:0}, b={160:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=3, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=132, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=4, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={160:0}, b={160:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=4, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=141, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=5, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={160:0}, b={160:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=5, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=146, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=6, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={160:0}, b={160:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=6, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=142, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=7, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={160:0}, b={160:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=7, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=157, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=8, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={160:0}, b={160:0}, i=8, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=8, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=145, i=8, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=9, size=7] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=7, b={160:0}, b={160:0}, i=9, size=7] [L20] RET return i; VAL [\old(size)=7, \result=9, b={160:0}, b={160:0}, i=9, size=7] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=9, i=7, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=9, i=7, mask={160:0}] [L26] i++ VAL [b={158:0}, i=8, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=8, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=8, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={160:0}, b={160:0}, i=0, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={160:0}, b={160:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=0, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=129, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=1, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={160:0}, b={160:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=1, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=144, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=2, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={160:0}, b={160:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=2, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=134, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=3, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={160:0}, b={160:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=3, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=132, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=4, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={160:0}, b={160:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=4, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=141, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=5, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={160:0}, b={160:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=5, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=146, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=6, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={160:0}, b={160:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=6, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=142, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=7, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={160:0}, b={160:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=7, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=157, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=8, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={160:0}, b={160:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=8, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=145, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=9, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={160:0}, b={160:0}, i=9, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=9, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=153, i=9, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=10, size=8] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=8, b={160:0}, b={160:0}, i=10, size=8] [L20] RET return i; VAL [\old(size)=8, \result=10, b={160:0}, b={160:0}, i=10, size=8] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=10, i=8, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=10, i=8, mask={160:0}] [L26] i++ VAL [b={158:0}, i=9, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=9, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=9, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={160:0}, b={160:0}, i=0, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={160:0}, b={160:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=0, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=129, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=1, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={160:0}, b={160:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=1, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=144, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=2, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={160:0}, b={160:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=2, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=134, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=3, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={160:0}, b={160:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=3, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=132, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=4, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={160:0}, b={160:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=4, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=141, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=5, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={160:0}, b={160:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=5, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=146, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=6, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={160:0}, b={160:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=6, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=142, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=7, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={160:0}, b={160:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=7, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=157, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=8, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={160:0}, b={160:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=8, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=145, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=9, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={160:0}, b={160:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=9, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=153, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=10, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={160:0}, b={160:0}, i=10, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=10, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=149, i=10, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=11, size=9] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=9, b={160:0}, b={160:0}, i=11, size=9] [L20] RET return i; VAL [\old(size)=9, \result=11, b={160:0}, b={160:0}, i=11, size=9] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=11, i=9, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=11, i=9, mask={160:0}] [L26] i++ VAL [b={158:0}, i=10, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=10, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=10, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={160:0}, b={160:0}, i=0, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={160:0}, b={160:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=0, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=129, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=1, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={160:0}, b={160:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=1, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=144, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=2, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={160:0}, b={160:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=2, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=134, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=3, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={160:0}, b={160:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=3, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=132, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=4, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={160:0}, b={160:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=4, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=141, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=5, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={160:0}, b={160:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=5, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=146, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=6, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={160:0}, b={160:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=6, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=142, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=7, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={160:0}, b={160:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=7, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=157, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=8, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={160:0}, b={160:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=8, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=145, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=9, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={160:0}, b={160:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=9, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=153, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=10, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={160:0}, b={160:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=10, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=149, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=11, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={160:0}, b={160:0}, i=11, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=11, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=135, i=11, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=12, size=10] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=10, b={160:0}, b={160:0}, i=12, size=10] [L20] RET return i; VAL [\old(size)=10, \result=12, b={160:0}, b={160:0}, i=12, size=10] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=12, i=10, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=12, i=10, mask={160:0}] [L26] i++ VAL [b={158:0}, i=11, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=11, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=11, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={160:0}, b={160:0}, i=0, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=0, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=129, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=1, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=1, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=144, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=2, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=2, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=134, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=3, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=3, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=132, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=4, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=4, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=141, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=5, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=5, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=146, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=6, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=6, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=142, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=7, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=7, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=157, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=8, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=8, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=145, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=9, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=9, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=153, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=10, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=10, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=149, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=11, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=11, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=135, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=12, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={160:0}, b={160:0}, i=12, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=12, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=139, i=12, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=13, size=11] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=11, b={160:0}, b={160:0}, i=13, size=11] [L20] RET return i; VAL [\old(size)=11, \result=13, b={160:0}, b={160:0}, i=13, size=11] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=13, i=11, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=13, i=11, mask={160:0}] [L26] i++ VAL [b={158:0}, i=12, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=12, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=12, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={160:0}, b={160:0}, i=0, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=0, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=129, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=1, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=1, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=144, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=2, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=2, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=134, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=3, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=3, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=132, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=4, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=4, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=141, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=5, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=5, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=146, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=6, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=6, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=142, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=7, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=7, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=157, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=8, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=8, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=145, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=9, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=9, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=153, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=10, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=10, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=149, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=11, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=11, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=135, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=12, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=12, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=139, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=13, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={160:0}, b={160:0}, i=13, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=13, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=136, i=13, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=14, size=12] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=12, b={160:0}, b={160:0}, i=14, size=12] [L20] RET return i; VAL [\old(size)=12, \result=14, b={160:0}, b={160:0}, i=14, size=12] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=14, i=12, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=14, i=12, mask={160:0}] [L26] i++ VAL [b={158:0}, i=13, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=13, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=13, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={160:0}, b={160:0}, i=0, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=0, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=129, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=1, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=1, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=144, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=2, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=2, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=134, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=3, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=3, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=132, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=4, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=4, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=141, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=5, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=5, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=146, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=6, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=6, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=142, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=7, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=7, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=157, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=8, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=8, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=145, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=9, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=9, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=153, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=10, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=10, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=149, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=11, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=11, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=135, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=12, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=12, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=139, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=13, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=13, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=136, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=14, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={160:0}, b={160:0}, i=14, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=14, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=152, i=14, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=15, size=13] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=13, b={160:0}, b={160:0}, i=15, size=13] [L20] RET return i; VAL [\old(size)=13, \result=15, b={160:0}, b={160:0}, i=15, size=13] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=15, i=13, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=15, i=13, mask={160:0}] [L26] i++ VAL [b={158:0}, i=14, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=14, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=14, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={160:0}, b={160:0}, i=0, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=0, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=129, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=1, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=1, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=144, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=2, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=2, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=134, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=3, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=3, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=132, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=4, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=4, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=141, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=5, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=5, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=146, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=6, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=6, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=142, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=7, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=7, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=157, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=8, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=8, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=145, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=9, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=9, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=153, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=10, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=10, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=149, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=11, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=11, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=135, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=12, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=12, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=139, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=13, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=13, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=136, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=14, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=14, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=152, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=15, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={160:0}, b={160:0}, i=15, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=15, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=150, i=15, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=16, size=14] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=14, b={160:0}, b={160:0}, i=16, size=14] [L20] RET return i; VAL [\old(size)=14, \result=16, b={160:0}, b={160:0}, i=16, size=14] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=16, i=14, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=16, i=14, mask={160:0}] [L26] i++ VAL [b={158:0}, i=15, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=15, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=15, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={160:0}, b={160:0}, i=0, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=0, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=129, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=1, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=1, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=144, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=2, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=2, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=134, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=3, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=3, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=132, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=4, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=4, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=141, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=5, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=5, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=146, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=6, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=6, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=142, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=7, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=7, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=157, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=8, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=8, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=145, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=9, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=9, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=153, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=10, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=10, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=149, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=11, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=11, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=135, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=12, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=12, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=139, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=13, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=13, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=136, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=14, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=14, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=152, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=15, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=15, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=150, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=16, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={160:0}, b={160:0}, i=16, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=16, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=156, i=16, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=17, size=15] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=15, b={160:0}, b={160:0}, i=17, size=15] [L20] RET return i; VAL [\old(size)=15, \result=17, b={160:0}, b={160:0}, i=17, size=15] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=17, i=15, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=17, i=15, mask={160:0}] [L26] i++ VAL [b={158:0}, i=16, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=16, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=16, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={160:0}, b={160:0}, i=0, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=0, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=129, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=1, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=1, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=144, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=2, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=2, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=134, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=3, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=3, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=132, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=4, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=4, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=141, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=5, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=5, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=146, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=6, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=6, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=142, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=7, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=7, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=157, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=8, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=8, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=145, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=9, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=9, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=153, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=10, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=10, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=149, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=11, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=11, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=135, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=12, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=12, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=139, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=13, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=13, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=136, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=14, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=14, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=152, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=15, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=15, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=150, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=16, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=16, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=156, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=17, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={160:0}, b={160:0}, i=17, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=17, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=161, i=17, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=18, size=16] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=16, b={160:0}, b={160:0}, i=18, size=16] [L20] RET return i; VAL [\old(size)=16, \result=18, b={160:0}, b={160:0}, i=18, size=16] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=18, i=16, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=18, i=16, mask={160:0}] [L26] i++ VAL [b={158:0}, i=17, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=17, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=17, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={160:0}, b={160:0}, i=0, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=0, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=129, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=1, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=1, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=144, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=2, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=2, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=134, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=3, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=3, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=132, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=4, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=4, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=141, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=5, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=5, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=146, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=6, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=6, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=142, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=7, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=7, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=157, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=8, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=8, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=145, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=9, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=9, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=153, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=10, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=10, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=149, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=11, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=11, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=135, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=12, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=12, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=139, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=13, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=13, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=136, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=14, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=14, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=152, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=15, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=15, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=150, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=16, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=16, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=156, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=17, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=17, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=161, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=18, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={160:0}, b={160:0}, i=18, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=18, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=154, i=18, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=19, size=17] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=17, b={160:0}, b={160:0}, i=19, size=17] [L20] RET return i; VAL [\old(size)=17, \result=19, b={160:0}, b={160:0}, i=19, size=17] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=19, i=17, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=19, i=17, mask={160:0}] [L26] i++ VAL [b={158:0}, i=18, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=18, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=18, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={160:0}, b={160:0}, i=0, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=0, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=129, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=1, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=1, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=144, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=2, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=2, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=134, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=3, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=3, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=132, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=4, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=4, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=141, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=5, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=5, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=146, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=6, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=6, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=142, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=7, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=7, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=157, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=8, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=8, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=145, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=9, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=9, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=153, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=10, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=10, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=149, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=11, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=11, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=135, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=12, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=12, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=139, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=13, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=13, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=136, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=14, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=14, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=152, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=15, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=15, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=150, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=16, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=16, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=156, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=17, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=17, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=161, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=18, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=18, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=154, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=19, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={160:0}, b={160:0}, i=19, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=19, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=162, i=19, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=20, size=18] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=18, b={160:0}, b={160:0}, i=20, size=18] [L20] RET return i; VAL [\old(size)=18, \result=20, b={160:0}, b={160:0}, i=20, size=18] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=20, i=18, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=20, i=18, mask={160:0}] [L26] i++ VAL [b={158:0}, i=19, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=19, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=19, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={160:0}, b={160:0}, i=0, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=0, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=129, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=1, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=1, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=144, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=2, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=2, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=134, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=3, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=3, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=132, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=4, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=4, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=141, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=5, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=5, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=146, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=6, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=6, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=142, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=7, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=7, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=157, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=8, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=8, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=145, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=9, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=9, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=153, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=10, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=10, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=149, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=11, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=11, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=135, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=12, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=12, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=139, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=13, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=13, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=136, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=14, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=14, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=152, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=15, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=15, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=150, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=16, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=16, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=156, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=17, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=17, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=161, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=18, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=18, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=154, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=19, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=19, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=162, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=20, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={160:0}, b={160:0}, i=20, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=20, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=148, i=20, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=21, size=19] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=19, b={160:0}, b={160:0}, i=21, size=19] [L20] RET return i; VAL [\old(size)=19, \result=21, b={160:0}, b={160:0}, i=21, size=19] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=21, i=19, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=21, i=19, mask={160:0}] [L26] i++ VAL [b={158:0}, i=20, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=20, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=20, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={160:0}, b={160:0}, i=0, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=0, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=129, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=1, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=1, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=144, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=2, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=2, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=134, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=3, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=3, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=132, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=4, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=4, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=141, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=5, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=5, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=146, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=6, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=6, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=142, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=7, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=7, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=157, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=8, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=8, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=145, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=9, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=9, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=153, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=10, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=10, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=149, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=11, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=11, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=135, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=12, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=12, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=139, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=13, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=13, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=136, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=14, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=14, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=152, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=15, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=15, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=150, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=16, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=16, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=156, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=17, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=17, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=161, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=18, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=18, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=154, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=19, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=19, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=162, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=20, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=20, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=148, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=21, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={160:0}, b={160:0}, i=21, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=21, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=137, i=21, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=22, size=20] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=20, b={160:0}, b={160:0}, i=22, size=20] [L20] RET return i; VAL [\old(size)=20, \result=22, b={160:0}, b={160:0}, i=22, size=20] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=22, i=20, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=22, i=20, mask={160:0}] [L26] i++ VAL [b={158:0}, i=21, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=21, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=21, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={160:0}, b={160:0}, i=0, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=0, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=129, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=1, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=1, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=144, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=2, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=2, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=134, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=3, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=3, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=132, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=4, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=4, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=141, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=5, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=5, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=146, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=6, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=6, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=142, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=7, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=7, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=157, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=8, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=8, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=145, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=9, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=9, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=153, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=10, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=10, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=149, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=11, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=11, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=135, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=12, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=12, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=139, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=13, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=13, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=136, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=14, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=14, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=152, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=15, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=15, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=150, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=16, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=16, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=156, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=17, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=17, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=161, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=18, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=18, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=154, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=19, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=19, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=162, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=20, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=20, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=148, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=21, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=21, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=137, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=22, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={160:0}, b={160:0}, i=22, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=22, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=151, i=22, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=23, size=21] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=21, b={160:0}, b={160:0}, i=23, size=21] [L20] RET return i; VAL [\old(size)=21, \result=23, b={160:0}, b={160:0}, i=23, size=21] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=23, i=21, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=23, i=21, mask={160:0}] [L26] i++ VAL [b={158:0}, i=22, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=22, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=22, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={160:0}, b={160:0}, i=0, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=0, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=129, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=1, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=1, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=144, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=2, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=2, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=134, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=3, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=3, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=132, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=4, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=4, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=141, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=5, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=5, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=146, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=6, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=6, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=142, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=7, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=7, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=157, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=8, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=8, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=145, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=9, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=9, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=153, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=10, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=10, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=149, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=11, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=11, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=135, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=12, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=12, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=139, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=13, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=13, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=136, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=14, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=14, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=152, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=15, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=15, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=150, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=16, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=16, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=156, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=17, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=17, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=161, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=18, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=18, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=154, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=19, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=19, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=162, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=20, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=20, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=148, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=21, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=21, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=137, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=22, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=22, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=151, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=23, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={160:0}, b={160:0}, i=23, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=23, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=163, i=23, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=24, size=22] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=22, b={160:0}, b={160:0}, i=24, size=22] [L20] RET return i; VAL [\old(size)=22, \result=24, b={160:0}, b={160:0}, i=24, size=22] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=24, i=22, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=24, i=22, mask={160:0}] [L26] i++ VAL [b={158:0}, i=23, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=23, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=23, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={160:0}, b={160:0}, i=0, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=0, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=129, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=1, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=1, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=144, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=2, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=2, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=134, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=3, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=3, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=132, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=4, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=4, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=141, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=5, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=5, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=146, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=6, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=6, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=142, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=7, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=7, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=157, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=8, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=8, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=145, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=9, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=9, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=153, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=10, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=10, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=149, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=11, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=11, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=135, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=12, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=12, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=139, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=13, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=13, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=136, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=14, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=14, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=152, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=15, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=15, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=150, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=16, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=16, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=156, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=17, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=17, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=161, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=18, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=18, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=154, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=19, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=19, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=162, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=20, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=20, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=148, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=21, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=21, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=137, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=22, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=22, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=151, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=23, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=23, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=163, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=24, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={160:0}, b={160:0}, i=24, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=24, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=131, i=24, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=25, size=23] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=23, b={160:0}, b={160:0}, i=25, size=23] [L20] RET return i; VAL [\old(size)=23, \result=25, b={160:0}, b={160:0}, i=25, size=23] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=25, i=23, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=25, i=23, mask={160:0}] [L26] i++ VAL [b={158:0}, i=24, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=24, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=24, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={160:0}, b={160:0}, i=0, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=0, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=129, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=1, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=1, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=144, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=2, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=2, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=134, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=3, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=3, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=132, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=4, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=4, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=141, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=5, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=5, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=146, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=6, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=6, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=142, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=7, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=7, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=157, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=8, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=8, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=145, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=9, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=9, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=153, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=10, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=10, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=149, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=11, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=11, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=135, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=12, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=12, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=139, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=13, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=13, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=136, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=14, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=14, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=152, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=15, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=15, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=150, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=16, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=16, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=156, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=17, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=17, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=161, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=18, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=18, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=154, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=19, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=19, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=162, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=20, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=20, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=148, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=21, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=21, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=137, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=22, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=22, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=151, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=23, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=23, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=163, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=24, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=24, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=131, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=25, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={160:0}, b={160:0}, i=25, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=25, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=133, i=25, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=26, size=24] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=24, b={160:0}, b={160:0}, i=26, size=24] [L20] RET return i; VAL [\old(size)=24, \result=26, b={160:0}, b={160:0}, i=26, size=24] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=26, i=24, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=26, i=24, mask={160:0}] [L26] i++ VAL [b={158:0}, i=25, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=25, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=25, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={160:0}, b={160:0}, i=0, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=0, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=129, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=1, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=1, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=144, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=2, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=2, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=134, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=3, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=3, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=132, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=4, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=4, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=141, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=5, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=5, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=146, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=6, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=6, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=142, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=7, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=7, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=157, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=8, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=8, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=145, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=9, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=9, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=153, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=10, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=10, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=149, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=11, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=11, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=135, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=12, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=12, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=139, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=13, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=13, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=136, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=14, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=14, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=152, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=15, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=15, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=150, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=16, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=16, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=156, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=17, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=17, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=161, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=18, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=18, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=154, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=19, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=19, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=162, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=20, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=20, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=148, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=21, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=21, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=137, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=22, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=22, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=151, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=23, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=23, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=163, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=24, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=24, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=131, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=25, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=25, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=133, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=26, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={160:0}, b={160:0}, i=26, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=26, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=130, i=26, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=27, size=25] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=25, b={160:0}, b={160:0}, i=27, size=25] [L20] RET return i; VAL [\old(size)=25, \result=27, b={160:0}, b={160:0}, i=27, size=25] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=27, i=25, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=27, i=25, mask={160:0}] [L26] i++ VAL [b={158:0}, i=26, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=26, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=26, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={160:0}, b={160:0}, i=0, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=0, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=129, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=1, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=1, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=144, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=2, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=2, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=134, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=3, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=3, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=132, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=4, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=4, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=141, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=5, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=5, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=146, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=6, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=6, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=142, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=7, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=7, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=157, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=8, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=8, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=145, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=9, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=9, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=153, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=10, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=10, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=149, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=11, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=11, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=135, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=12, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=12, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=139, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=13, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=13, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=136, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=14, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=14, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=152, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=15, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=15, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=150, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=16, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=16, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=156, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=17, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=17, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=161, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=18, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=18, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=154, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=19, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=19, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=162, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=20, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=20, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=148, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=21, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=21, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=137, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=22, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=22, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=151, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=23, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=23, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=163, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=24, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=24, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=131, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=25, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=25, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=133, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=26, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=26, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=130, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=27, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={160:0}, b={160:0}, i=27, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=27, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=138, i=27, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=28, size=26] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=26, b={160:0}, b={160:0}, i=28, size=26] [L20] RET return i; VAL [\old(size)=26, \result=28, b={160:0}, b={160:0}, i=28, size=26] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=28, i=26, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=28, i=26, mask={160:0}] [L26] i++ VAL [b={158:0}, i=27, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=27, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=27, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={160:0}, b={160:0}, i=0, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=0, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=129, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=1, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=1, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=144, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=2, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=2, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=134, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=3, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=3, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=132, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=4, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=4, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=141, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=5, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=5, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=146, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=6, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=6, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=142, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=7, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=7, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=157, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=8, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=8, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=145, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=9, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=9, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=153, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=10, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=10, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=149, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=11, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=11, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=135, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=12, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=12, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=139, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=13, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=13, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=136, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=14, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=14, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=152, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=15, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=15, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=150, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=16, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=16, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=156, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=17, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=17, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=161, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=18, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=18, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=154, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=19, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=19, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=162, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=20, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=20, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=148, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=21, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=21, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=137, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=22, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=22, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=151, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=23, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=23, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=163, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=24, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=24, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=131, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=25, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=25, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=133, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=26, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=26, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=130, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=27, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=27, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=138, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=28, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={160:0}, b={160:0}, i=28, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=28, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=143, i=28, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=29, size=27] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=27, b={160:0}, b={160:0}, i=29, size=27] [L20] RET return i; VAL [\old(size)=27, \result=29, b={160:0}, b={160:0}, i=29, size=27] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=29, i=27, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=29, i=27, mask={160:0}] [L26] i++ VAL [b={158:0}, i=28, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=28, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=28, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={160:0}, b={160:0}, i=0, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=0, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=129, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=1, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=1, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=144, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=2, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=2, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=134, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=3, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=3, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=132, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=4, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=4, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=141, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=5, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=5, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=146, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=6, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=6, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=142, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=7, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=7, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=157, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=8, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=8, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=145, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=9, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=9, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=153, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=10, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=10, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=149, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=11, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=11, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=135, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=12, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=12, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=139, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=13, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=13, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=136, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=14, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=14, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=152, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=15, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=15, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=150, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=16, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=16, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=156, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=17, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=17, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=161, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=18, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=18, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=154, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=19, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=19, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=162, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=20, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=20, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=148, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=21, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=21, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=137, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=22, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=22, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=151, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=23, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=23, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=163, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=24, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=24, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=131, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=25, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=25, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=133, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=26, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=26, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=130, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=27, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=27, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=138, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=28, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=28, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=143, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=29, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={160:0}, b={160:0}, i=29, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=29, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=155, i=29, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=30, size=28] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=28, b={160:0}, b={160:0}, i=30, size=28] [L20] RET return i; VAL [\old(size)=28, \result=30, b={160:0}, b={160:0}, i=30, size=28] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=30, i=28, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=30, i=28, mask={160:0}] [L26] i++ VAL [b={158:0}, i=29, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=29, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=29, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={160:0}, b={160:0}, i=0, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=0, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=129, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=1, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=1, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=144, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=2, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=2, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=134, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=3, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=3, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=132, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=4, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=4, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=141, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=5, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=5, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=146, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=6, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=6, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=142, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=7, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=7, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=157, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=8, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=8, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=145, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=9, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=9, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=153, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=10, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=10, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=149, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=11, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=11, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=135, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=12, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=12, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=139, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=13, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=13, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=136, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=14, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=14, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=152, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=15, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=15, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=150, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=16, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=16, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=156, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=17, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=17, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=161, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=18, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=18, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=154, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=19, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=19, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=162, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=20, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=20, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=148, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=21, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=21, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=137, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=22, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=22, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=151, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=23, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=23, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=163, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=24, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=24, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=131, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=25, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=25, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=133, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=26, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=26, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=130, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=27, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=27, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=138, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=28, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=28, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=143, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=29, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=29, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=155, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=30, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={160:0}, b={160:0}, i=30, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=30, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=164, i=30, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=31, size=29] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=29, b={160:0}, b={160:0}, i=31, size=29] [L20] RET return i; VAL [\old(size)=29, \result=31, b={160:0}, b={160:0}, i=31, size=29] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=31, i=29, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=31, i=29, mask={160:0}] [L26] i++ VAL [b={158:0}, i=30, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=30, mask={160:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=30, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={160:0}, b={160:0}, i=0, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=0, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=129, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=1, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=1, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=144, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=2, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=2, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=134, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=3, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=3, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=132, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=4, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=4, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=141, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=5, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=5, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=146, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=6, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=6, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=142, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=7, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=7, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=157, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=8, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=8, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=145, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=9, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=9, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=153, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=10, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=10, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=149, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=11, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=11, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=135, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=12, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=12, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=139, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=13, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=13, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=136, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=14, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=14, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=152, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=15, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=15, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=150, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=16, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=16, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=156, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=17, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=17, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=161, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=18, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=18, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=154, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=19, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=19, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=162, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=20, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=20, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=148, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=21, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=21, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=137, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=22, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=22, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=151, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=23, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=23, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=163, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=24, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=24, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=131, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=25, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=25, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=133, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=26, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=26, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=130, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=27, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=27, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=138, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=28, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=28, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=143, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=29, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=29, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=155, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=30, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=30, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=164, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=31, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={160:0}, b={160:0}, i=31, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=31, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=140, i=31, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=32, size=30] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=30, b={160:0}, b={160:0}, i=32, size=30] [L20] RET return i; VAL [\old(size)=30, \result=32, b={160:0}, b={160:0}, i=32, size=30] [L27] EXPR foo(mask, i) VAL [b={158:0}, foo(mask, i)=32, i=30, mask={160:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={158:0}, foo(mask, i)=32, i=30, mask={160:0}] [L26] i++ VAL [b={158:0}, i=31, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=31, mask={160:0}] [L27] CALL foo(mask, i) VAL [\old(size)=31, b={160:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={160:0}, b={160:0}, i=0, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=0, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=129, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=1, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=1, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=144, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=2, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=2, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=134, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=3, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=3, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=132, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=4, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=4, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=141, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=5, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=5, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=146, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=6, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=6, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=142, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=7, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=7, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=157, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=8, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=8, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=145, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=9, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=9, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=153, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=10, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=10, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=149, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=11, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=11, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=135, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=12, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=12, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=139, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=13, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=13, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=136, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=14, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=14, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=152, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=15, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=15, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=150, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=16, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=16, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=156, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=17, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=17, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=161, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=18, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=18, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=154, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=19, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=19, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=162, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=20, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=20, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=148, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=21, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=21, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=137, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=22, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=22, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=151, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=23, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=23, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=163, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=24, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=24, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=131, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=25, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=25, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=133, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=26, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=26, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=130, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=27, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=27, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=138, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=28, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=28, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=143, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=29, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=29, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=155, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=30, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=30, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=164, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=31, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=31, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=140, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=32, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={160:0}, b={160:0}, i=32, size=31] [L18] a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=32, size=31] [L18] FCALL b[i] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 54 locations, 8 error locations. UNSAFE Result, 714.9s OverallTime, 92 OverallIterations, 591 TraceHistogramMax, 152.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5524 SDtfs, 52235 SDslu, 78791 SDs, 0 SdLazy, 214673 SolverSat, 6728 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 65.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 125401 GetRequests, 116465 SyntacticMatches, 1021 SemanticMatches, 7915 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 330919 ImplicationChecksByTransitivity, 176.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3820occurred in iteration=90, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.9s AutomataMinimizationTime, 91 MinimizatonAttempts, 2514 StatesRemovedByMinimization, 88 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 4.9s SsaConstructionTime, 187.9s SatisfiabilityAnalysisTime, 276.9s InterpolantComputationTime, 242367 NumberOfCodeBlocks, 225403 NumberOfCodeBlocksAsserted, 1389 NumberOfCheckSat, 238418 ConstructedInterpolants, 36097 QuantifiedInterpolants, 1409172552 SizeOfPredicates, 296 NumberOfNonLiveVariables, 232109 ConjunctsInSsa, 3403 ConjunctsInUnsatCore, 175 InterpolantComputations, 7 PerfectInterpolantSequences, 35484991/35850538 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...