./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_2_true-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_2_true-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d321e3b1b642bcfc9c94c4888bd187898cb1af58 ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-10-27 06:09:46,649 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-27 06:09:46,650 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-27 06:09:46,662 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-27 06:09:46,664 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-27 06:09:46,665 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-27 06:09:46,668 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-27 06:09:46,670 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-27 06:09:46,673 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-27 06:09:46,675 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-27 06:09:46,677 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-27 06:09:46,678 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-27 06:09:46,679 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-27 06:09:46,681 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-27 06:09:46,688 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-27 06:09:46,689 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-27 06:09:46,690 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-27 06:09:46,691 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-27 06:09:46,693 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-27 06:09:46,696 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-27 06:09:46,699 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-27 06:09:46,701 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-27 06:09:46,704 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-27 06:09:46,706 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-27 06:09:46,707 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-27 06:09:46,707 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-27 06:09:46,708 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-27 06:09:46,709 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-27 06:09:46,710 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-27 06:09:46,710 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-27 06:09:46,711 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-27 06:09:46,711 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-27 06:09:46,713 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-27 06:09:46,714 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-27 06:09:46,715 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-27 06:09:46,716 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-27 06:09:46,718 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-10-27 06:09:46,735 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-27 06:09:46,736 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-27 06:09:46,737 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-10-27 06:09:46,738 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-10-27 06:09:46,738 INFO L133 SettingsManager]: * Use SBE=true [2018-10-27 06:09:46,739 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-10-27 06:09:46,739 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-10-27 06:09:46,739 INFO L133 SettingsManager]: * Use old map elimination=false [2018-10-27 06:09:46,739 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-10-27 06:09:46,739 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-10-27 06:09:46,739 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-10-27 06:09:46,740 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-27 06:09:46,740 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-27 06:09:46,740 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-10-27 06:09:46,740 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-27 06:09:46,740 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-27 06:09:46,740 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-27 06:09:46,741 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-10-27 06:09:46,741 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-10-27 06:09:46,741 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-10-27 06:09:46,741 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-27 06:09:46,741 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-27 06:09:46,741 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-10-27 06:09:46,742 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-10-27 06:09:46,742 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-27 06:09:46,742 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-10-27 06:09:46,742 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-10-27 06:09:46,742 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-27 06:09:46,742 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-10-27 06:09:46,743 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-10-27 06:09:46,747 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-10-27 06:09:46,748 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d321e3b1b642bcfc9c94c4888bd187898cb1af58 [2018-10-27 06:09:46,796 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-27 06:09:46,813 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-27 06:09:46,816 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-27 06:09:46,818 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-27 06:09:46,818 INFO L276 PluginConnector]: CDTParser initialized [2018-10-27 06:09:46,819 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/pc_sfifo_2_true-unreach-call_false-termination.cil.c [2018-10-27 06:09:46,877 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/data/bf03ae794/00895485f2b4472d907e8e69f4431c72/FLAG908d1c39d [2018-10-27 06:09:47,281 INFO L298 CDTParser]: Found 1 translation units. [2018-10-27 06:09:47,283 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/sv-benchmarks/c/systemc/pc_sfifo_2_true-unreach-call_false-termination.cil.c [2018-10-27 06:09:47,294 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/data/bf03ae794/00895485f2b4472d907e8e69f4431c72/FLAG908d1c39d [2018-10-27 06:09:47,306 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/data/bf03ae794/00895485f2b4472d907e8e69f4431c72 [2018-10-27 06:09:47,309 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-27 06:09:47,311 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-27 06:09:47,311 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-27 06:09:47,312 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-27 06:09:47,316 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-27 06:09:47,316 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.10 06:09:47" (1/1) ... [2018-10-27 06:09:47,320 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2b26c5b4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47, skipping insertion in model container [2018-10-27 06:09:47,320 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.10 06:09:47" (1/1) ... [2018-10-27 06:09:47,329 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-27 06:09:47,361 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-27 06:09:47,536 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-27 06:09:47,541 INFO L189 MainTranslator]: Completed pre-run [2018-10-27 06:09:47,576 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-27 06:09:47,596 INFO L193 MainTranslator]: Completed translation [2018-10-27 06:09:47,596 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47 WrapperNode [2018-10-27 06:09:47,597 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-27 06:09:47,597 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-27 06:09:47,597 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-27 06:09:47,598 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-27 06:09:47,607 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47" (1/1) ... [2018-10-27 06:09:47,615 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47" (1/1) ... [2018-10-27 06:09:47,655 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-27 06:09:47,666 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-27 06:09:47,667 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-27 06:09:47,667 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-27 06:09:47,678 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47" (1/1) ... [2018-10-27 06:09:47,679 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47" (1/1) ... [2018-10-27 06:09:47,682 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47" (1/1) ... [2018-10-27 06:09:47,690 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47" (1/1) ... [2018-10-27 06:09:47,704 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47" (1/1) ... [2018-10-27 06:09:47,712 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47" (1/1) ... [2018-10-27 06:09:47,713 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47" (1/1) ... [2018-10-27 06:09:47,728 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-27 06:09:47,729 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-27 06:09:47,729 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-27 06:09:47,729 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-27 06:09:47,731 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-10-27 06:09:47,933 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-27 06:09:47,933 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-27 06:09:48,873 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-27 06:09:48,874 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 06:09:48 BoogieIcfgContainer [2018-10-27 06:09:48,874 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-27 06:09:48,875 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-10-27 06:09:48,875 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-10-27 06:09:48,879 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-10-27 06:09:48,880 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-10-27 06:09:48,881 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 27.10 06:09:47" (1/3) ... [2018-10-27 06:09:48,882 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6f3d25e8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 27.10 06:09:48, skipping insertion in model container [2018-10-27 06:09:48,882 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-10-27 06:09:48,882 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:09:47" (2/3) ... [2018-10-27 06:09:48,884 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6f3d25e8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 27.10 06:09:48, skipping insertion in model container [2018-10-27 06:09:48,884 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-10-27 06:09:48,884 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 06:09:48" (3/3) ... [2018-10-27 06:09:48,886 INFO L375 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2_true-unreach-call_false-termination.cil.c [2018-10-27 06:09:48,979 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-10-27 06:09:48,980 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-10-27 06:09:48,980 INFO L375 BuchiCegarLoop]: Hoare is false [2018-10-27 06:09:48,980 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-10-27 06:09:48,980 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-10-27 06:09:48,981 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-10-27 06:09:48,981 INFO L379 BuchiCegarLoop]: Difference is false [2018-10-27 06:09:48,981 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-10-27 06:09:48,981 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-10-27 06:09:48,996 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 107 states. [2018-10-27 06:09:49,024 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2018-10-27 06:09:49,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:49,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:49,034 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:49,034 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:49,035 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-10-27 06:09:49,035 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 107 states. [2018-10-27 06:09:49,041 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2018-10-27 06:09:49,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:49,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:49,042 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:49,043 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:49,052 INFO L793 eck$LassoCheckResult]: Stem: 72#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 37#L452true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 50#L212true assume !(~q_req_up~0 == 1); 48#L212-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19#L227true assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 16#L227-2true assume !(~c_dr_i~0 == 1);~c_dr_st~0 := 2; 26#L232-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28#L265true assume !(~q_read_ev~0 == 0); 27#L265-2true assume !(~q_write_ev~0 == 0); 59#L270-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 75#L55true assume !(~p_dw_pc~0 == 1); 70#L55-2true is_do_write_p_triggered_~__retres1~0 := 0; 76#L66true is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 35#L67true activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 94#L305true assume !(activate_threads_~tmp~1 != 0); 98#L305-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 89#L74true assume ~c_dr_pc~0 == 1; 42#L75true assume ~q_write_ev~0 == 1;is_do_read_c_triggered_~__retres1~1 := 1; 90#L85true is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 43#L86true activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 99#L313true assume !(activate_threads_~tmp___0~1 != 0); 100#L313-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82#L283true assume !(~q_read_ev~0 == 1); 97#L283-2true assume ~q_write_ev~0 == 1;~q_write_ev~0 := 2; 8#L288-1true assume { :end_inline_reset_delta_events } true; 6#L409-3true [2018-10-27 06:09:49,053 INFO L795 eck$LassoCheckResult]: Loop: 6#L409-3true assume true; 3#L409-1true assume !false; 78#L410true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 4#L354true assume !true; 17#L370true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 47#L212-3true assume !(~q_req_up~0 == 1); 46#L212-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 23#L265-3true assume ~q_read_ev~0 == 0;~q_read_ev~0 := 1; 36#L265-5true assume ~q_write_ev~0 == 0;~q_write_ev~0 := 1; 53#L270-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 51#L55-3true assume ~p_dw_pc~0 == 1; 32#L56-1true assume ~q_read_ev~0 == 1;is_do_write_p_triggered_~__retres1~0 := 1; 74#L66-1true is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 33#L67-1true activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 81#L305-3true assume !(activate_threads_~tmp~1 != 0); 84#L305-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 65#L74-3true assume ~c_dr_pc~0 == 1; 39#L75-1true assume ~q_write_ev~0 == 1;is_do_read_c_triggered_~__retres1~1 := 1; 68#L85-1true is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 40#L86-1true activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 102#L313-3true assume activate_threads_~tmp___0~1 != 0;~c_dr_st~0 := 0; 88#L313-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96#L283-3true assume ~q_read_ev~0 == 1;~q_read_ev~0 := 2; 92#L283-5true assume ~q_write_ev~0 == 1;~q_write_ev~0 := 2; 103#L288-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 52#L245-1true assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 30#L257-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 108#L258-1true stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 13#L384true assume stop_simulation_~tmp~3 != 0;stop_simulation_~__retres2~0 := 0; 56#L391true stop_simulation_#res := stop_simulation_~__retres2~0; 15#L392true start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 105#L426true assume !(start_simulation_~tmp~4 != 0); 6#L409-3true [2018-10-27 06:09:49,059 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:49,059 INFO L82 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2018-10-27 06:09:49,061 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:49,062 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:49,113 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,113 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:49,113 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:49,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:49,211 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:49,212 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:09:49,216 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:09:49,217 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:49,217 INFO L82 PathProgramCache]: Analyzing trace with hash -965560389, now seen corresponding path program 1 times [2018-10-27 06:09:49,217 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:49,217 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:49,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,219 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:49,219 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:49,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:49,231 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:49,231 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:09:49,232 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:09:49,250 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:09:49,251 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:09:49,253 INFO L87 Difference]: Start difference. First operand 107 states. Second operand 3 states. [2018-10-27 06:09:49,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:49,298 INFO L93 Difference]: Finished difference Result 105 states and 148 transitions. [2018-10-27 06:09:49,299 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:09:49,301 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 148 transitions. [2018-10-27 06:09:49,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2018-10-27 06:09:49,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 99 states and 142 transitions. [2018-10-27 06:09:49,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99 [2018-10-27 06:09:49,313 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99 [2018-10-27 06:09:49,314 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 142 transitions. [2018-10-27 06:09:49,315 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:09:49,315 INFO L705 BuchiCegarLoop]: Abstraction has 99 states and 142 transitions. [2018-10-27 06:09:49,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 142 transitions. [2018-10-27 06:09:49,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2018-10-27 06:09:49,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-10-27 06:09:49,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 142 transitions. [2018-10-27 06:09:49,344 INFO L728 BuchiCegarLoop]: Abstraction has 99 states and 142 transitions. [2018-10-27 06:09:49,344 INFO L608 BuchiCegarLoop]: Abstraction has 99 states and 142 transitions. [2018-10-27 06:09:49,345 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-10-27 06:09:49,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 142 transitions. [2018-10-27 06:09:49,346 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2018-10-27 06:09:49,347 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:49,347 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:49,348 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:49,348 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:49,348 INFO L793 eck$LassoCheckResult]: Stem: 306#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 229#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 230#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 274#L212 assume !(~q_req_up~0 == 1); 293#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 247#L227 assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 241#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 242#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 257#L265 assume !(~q_read_ev~0 == 0); 258#L265-2 assume !(~q_write_ev~0 == 0); 259#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 300#L55 assume !(~p_dw_pc~0 == 1); 270#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 269#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 271#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 272#L305 assume !(activate_threads_~tmp~1 != 0); 317#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 314#L74 assume ~c_dr_pc~0 == 1; 283#L75 assume ~q_write_ev~0 == 1;is_do_read_c_triggered_~__retres1~1 := 1; 284#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 286#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 287#L313 assume !(activate_threads_~tmp___0~1 != 0); 319#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309#L283 assume !(~q_read_ev~0 == 1); 310#L283-2 assume ~q_write_ev~0 == 1;~q_write_ev~0 := 2; 231#L288-1 assume { :end_inline_reset_delta_events } true; 228#L409-3 [2018-10-27 06:09:49,349 INFO L795 eck$LassoCheckResult]: Loop: 228#L409-3 assume true; 221#L409-1 assume !false; 222#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 223#L354 assume true; 224#L329-1 assume !false; 232#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 305#L245 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 249#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 262#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 250#L334 assume !(eval_~tmp___1~0 != 0); 243#L370 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 244#L212-3 assume !(~q_req_up~0 == 1); 291#L212-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 254#L265-3 assume ~q_read_ev~0 == 0;~q_read_ev~0 := 1; 255#L265-5 assume ~q_write_ev~0 == 0;~q_write_ev~0 := 1; 273#L270-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 295#L55-3 assume ~p_dw_pc~0 == 1; 263#L56-1 assume ~q_read_ev~0 == 1;is_do_write_p_triggered_~__retres1~0 := 1; 264#L66-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 266#L67-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 267#L305-3 assume !(activate_threads_~tmp~1 != 0); 308#L305-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 303#L74-3 assume ~c_dr_pc~0 == 1; 277#L75-1 assume ~q_write_ev~0 == 1;is_do_read_c_triggered_~__retres1~1 := 1; 278#L85-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 280#L86-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 281#L313-3 assume activate_threads_~tmp___0~1 != 0;~c_dr_st~0 := 0; 312#L313-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 313#L283-3 assume ~q_read_ev~0 == 1;~q_read_ev~0 := 2; 315#L283-5 assume ~q_write_ev~0 == 1;~q_write_ev~0 := 2; 316#L288-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 296#L245-1 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 246#L257-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 261#L258-1 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 235#L384 assume stop_simulation_~tmp~3 != 0;stop_simulation_~__retres2~0 := 0; 236#L391 stop_simulation_#res := stop_simulation_~__retres2~0; 239#L392 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 240#L426 assume !(start_simulation_~tmp~4 != 0); 228#L409-3 [2018-10-27 06:09:49,349 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:49,349 INFO L82 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2018-10-27 06:09:49,349 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:49,349 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:49,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,350 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:49,351 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:49,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:49,417 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:49,417 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:09:49,417 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:09:49,418 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:49,418 INFO L82 PathProgramCache]: Analyzing trace with hash -21428580, now seen corresponding path program 1 times [2018-10-27 06:09:49,418 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:49,418 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:49,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,419 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:49,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:49,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:49,527 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:49,527 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 06:09:49,527 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:09:49,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:09:49,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:09:49,528 INFO L87 Difference]: Start difference. First operand 99 states and 142 transitions. cyclomatic complexity: 44 Second operand 3 states. [2018-10-27 06:09:49,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:49,579 INFO L93 Difference]: Finished difference Result 162 states and 229 transitions. [2018-10-27 06:09:49,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:09:49,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 162 states and 229 transitions. [2018-10-27 06:09:49,584 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 129 [2018-10-27 06:09:49,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 162 states to 162 states and 229 transitions. [2018-10-27 06:09:49,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 162 [2018-10-27 06:09:49,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 162 [2018-10-27 06:09:49,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 162 states and 229 transitions. [2018-10-27 06:09:49,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:09:49,589 INFO L705 BuchiCegarLoop]: Abstraction has 162 states and 229 transitions. [2018-10-27 06:09:49,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states and 229 transitions. [2018-10-27 06:09:49,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 156. [2018-10-27 06:09:49,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-10-27 06:09:49,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 222 transitions. [2018-10-27 06:09:49,598 INFO L728 BuchiCegarLoop]: Abstraction has 156 states and 222 transitions. [2018-10-27 06:09:49,598 INFO L608 BuchiCegarLoop]: Abstraction has 156 states and 222 transitions. [2018-10-27 06:09:49,599 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-10-27 06:09:49,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156 states and 222 transitions. [2018-10-27 06:09:49,602 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 123 [2018-10-27 06:09:49,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:49,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:49,603 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:49,603 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:49,604 INFO L793 eck$LassoCheckResult]: Stem: 580#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 500#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 546#L212 assume !(~q_req_up~0 == 1); 563#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 518#L227 assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 512#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 513#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 529#L265 assume !(~q_read_ev~0 == 0); 530#L265-2 assume !(~q_write_ev~0 == 0); 531#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 571#L55 assume !(~p_dw_pc~0 == 1); 542#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 541#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 543#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 544#L305 assume !(activate_threads_~tmp~1 != 0); 593#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 588#L74 assume !(~c_dr_pc~0 == 1); 577#L74-2 is_do_read_c_triggered_~__retres1~1 := 0; 578#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 555#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 556#L313 assume !(activate_threads_~tmp___0~1 != 0); 595#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 583#L283 assume !(~q_read_ev~0 == 1); 584#L283-2 assume ~q_write_ev~0 == 1;~q_write_ev~0 := 2; 501#L288-1 assume { :end_inline_reset_delta_events } true; 502#L409-3 [2018-10-27 06:09:49,604 INFO L795 eck$LassoCheckResult]: Loop: 502#L409-3 assume true; 628#L409-1 assume !false; 627#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 601#L354 assume true; 626#L329-1 assume !false; 624#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 619#L245 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 614#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 611#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 608#L334 assume !(eval_~tmp___1~0 != 0); 514#L370 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 515#L212-3 assume !(~q_req_up~0 == 1); 561#L212-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 526#L265-3 assume ~q_read_ev~0 == 0;~q_read_ev~0 := 1; 527#L265-5 assume ~q_write_ev~0 == 0;~q_write_ev~0 := 1; 545#L270-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 565#L55-3 assume ~p_dw_pc~0 == 1; 535#L56-1 assume ~q_read_ev~0 == 1;is_do_write_p_triggered_~__retres1~0 := 1; 536#L66-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 538#L67-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 539#L305-3 assume !(activate_threads_~tmp~1 != 0); 582#L305-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 574#L74-3 assume !(~c_dr_pc~0 == 1); 575#L74-5 is_do_read_c_triggered_~__retres1~1 := 0; 646#L85-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 645#L86-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 644#L313-3 assume activate_threads_~tmp___0~1 != 0;~c_dr_st~0 := 0; 586#L313-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 587#L283-3 assume ~q_read_ev~0 == 1;~q_read_ev~0 := 2; 590#L283-5 assume ~q_write_ev~0 == 1;~q_write_ev~0 := 2; 591#L288-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 566#L245-1 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 517#L257-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 533#L258-1 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 506#L384 assume stop_simulation_~tmp~3 != 0;stop_simulation_~__retres2~0 := 0; 507#L391 stop_simulation_#res := stop_simulation_~__retres2~0; 635#L392 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 634#L426 assume !(start_simulation_~tmp~4 != 0); 502#L409-3 [2018-10-27 06:09:49,604 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:49,604 INFO L82 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2018-10-27 06:09:49,604 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:49,605 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:49,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,605 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:49,606 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:49,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:49,678 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:49,678 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:09:49,678 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:09:49,678 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:49,679 INFO L82 PathProgramCache]: Analyzing trace with hash 1155175739, now seen corresponding path program 1 times [2018-10-27 06:09:49,679 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:49,679 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:49,680 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,680 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:49,680 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:49,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:49,770 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:49,770 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 06:09:49,770 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:09:49,770 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:09:49,771 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:09:49,771 INFO L87 Difference]: Start difference. First operand 156 states and 222 transitions. cyclomatic complexity: 68 Second operand 3 states. [2018-10-27 06:09:49,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:49,881 INFO L93 Difference]: Finished difference Result 307 states and 430 transitions. [2018-10-27 06:09:49,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:09:49,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 307 states and 430 transitions. [2018-10-27 06:09:49,886 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 246 [2018-10-27 06:09:49,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 307 states to 307 states and 430 transitions. [2018-10-27 06:09:49,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 307 [2018-10-27 06:09:49,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 307 [2018-10-27 06:09:49,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 307 states and 430 transitions. [2018-10-27 06:09:49,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:09:49,893 INFO L705 BuchiCegarLoop]: Abstraction has 307 states and 430 transitions. [2018-10-27 06:09:49,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307 states and 430 transitions. [2018-10-27 06:09:49,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307 to 307. [2018-10-27 06:09:49,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 307 states. [2018-10-27 06:09:49,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 430 transitions. [2018-10-27 06:09:49,911 INFO L728 BuchiCegarLoop]: Abstraction has 307 states and 430 transitions. [2018-10-27 06:09:49,912 INFO L608 BuchiCegarLoop]: Abstraction has 307 states and 430 transitions. [2018-10-27 06:09:49,912 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-10-27 06:09:49,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 307 states and 430 transitions. [2018-10-27 06:09:49,916 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 246 [2018-10-27 06:09:49,917 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:49,917 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:49,918 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:49,918 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:49,918 INFO L793 eck$LassoCheckResult]: Stem: 1062#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 971#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 972#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1021#L212 assume !(~q_req_up~0 == 1); 1043#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1260#L227 assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 1259#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 1258#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1257#L265 assume !(~q_read_ev~0 == 0); 1002#L265-2 assume !(~q_write_ev~0 == 0); 1003#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 1051#L55 assume !(~p_dw_pc~0 == 1); 1063#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 1249#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 1248#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 1247#L305 assume !(activate_threads_~tmp~1 != 0); 1246#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 1245#L74 assume !(~c_dr_pc~0 == 1); 1244#L74-2 is_do_read_c_triggered_~__retres1~1 := 0; 1242#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 1240#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1238#L313 assume !(activate_threads_~tmp___0~1 != 0); 1232#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1229#L283 assume !(~q_read_ev~0 == 1); 1227#L283-2 assume !(~q_write_ev~0 == 1); 1081#L288-1 assume { :end_inline_reset_delta_events } true; 1206#L409-3 [2018-10-27 06:09:49,918 INFO L795 eck$LassoCheckResult]: Loop: 1206#L409-3 assume true; 1200#L409-1 assume !false; 1199#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 1100#L354 assume true; 1198#L329-1 assume !false; 1182#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1181#L245 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 1178#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1176#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 1173#L334 assume !(eval_~tmp___1~0 != 0); 1174#L370 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1038#L212-3 assume !(~q_req_up~0 == 1); 1040#L212-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1202#L265-3 assume ~q_read_ev~0 == 0;~q_read_ev~0 := 1; 1019#L265-5 assume !(~q_write_ev~0 == 0); 1020#L270-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 1256#L55-3 assume ~p_dw_pc~0 == 1; 1254#L56-1 assume ~q_read_ev~0 == 1;is_do_write_p_triggered_~__retres1~0 := 1; 1253#L66-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 1252#L67-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 1066#L305-3 assume !(activate_threads_~tmp~1 != 0); 1067#L305-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 1056#L74-3 assume !(~c_dr_pc~0 == 1); 1057#L74-5 is_do_read_c_triggered_~__retres1~1 := 0; 1237#L85-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 1236#L86-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1235#L313-3 assume activate_threads_~tmp___0~1 != 0;~c_dr_st~0 := 0; 1234#L313-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1231#L283-3 assume ~q_read_ev~0 == 1;~q_read_ev~0 := 2; 1224#L283-5 assume !(~q_write_ev~0 == 1); 1221#L288-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1045#L245-1 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 988#L257-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1007#L258-1 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 977#L384 assume stop_simulation_~tmp~3 != 0;stop_simulation_~__retres2~0 := 0; 978#L391 stop_simulation_#res := stop_simulation_~__retres2~0; 981#L392 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 982#L426 assume !(start_simulation_~tmp~4 != 0); 1206#L409-3 [2018-10-27 06:09:49,919 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:49,919 INFO L82 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2018-10-27 06:09:49,919 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:49,919 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:49,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,933 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:49,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:49,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:49,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:49,999 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:50,000 INFO L82 PathProgramCache]: Analyzing trace with hash 1701220603, now seen corresponding path program 1 times [2018-10-27 06:09:50,000 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:50,000 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:50,001 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,001 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:50,001 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:50,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:50,086 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:50,086 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 06:09:50,086 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:09:50,086 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 06:09:50,087 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-27 06:09:50,087 INFO L87 Difference]: Start difference. First operand 307 states and 430 transitions. cyclomatic complexity: 125 Second operand 5 states. [2018-10-27 06:09:50,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:50,280 INFO L93 Difference]: Finished difference Result 471 states and 642 transitions. [2018-10-27 06:09:50,281 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-27 06:09:50,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 471 states and 642 transitions. [2018-10-27 06:09:50,285 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 406 [2018-10-27 06:09:50,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 471 states to 471 states and 642 transitions. [2018-10-27 06:09:50,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 471 [2018-10-27 06:09:50,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 471 [2018-10-27 06:09:50,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 471 states and 642 transitions. [2018-10-27 06:09:50,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:09:50,300 INFO L705 BuchiCegarLoop]: Abstraction has 471 states and 642 transitions. [2018-10-27 06:09:50,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states and 642 transitions. [2018-10-27 06:09:50,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 319. [2018-10-27 06:09:50,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 319 states. [2018-10-27 06:09:50,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 319 states to 319 states and 442 transitions. [2018-10-27 06:09:50,326 INFO L728 BuchiCegarLoop]: Abstraction has 319 states and 442 transitions. [2018-10-27 06:09:50,326 INFO L608 BuchiCegarLoop]: Abstraction has 319 states and 442 transitions. [2018-10-27 06:09:50,326 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-10-27 06:09:50,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 319 states and 442 transitions. [2018-10-27 06:09:50,329 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 258 [2018-10-27 06:09:50,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:50,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:50,333 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:50,336 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:50,338 INFO L793 eck$LassoCheckResult]: Stem: 1860#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1765#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1766#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1817#L212 assume !(~q_req_up~0 == 1); 1834#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1908#L227 assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 1907#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 1795#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1796#L265 assume !(~q_read_ev~0 == 0); 1799#L265-2 assume !(~q_write_ev~0 == 0); 1905#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 1862#L55 assume !(~p_dw_pc~0 == 1); 1812#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 1811#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 1902#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 1879#L305 assume !(activate_threads_~tmp~1 != 0); 1880#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 1874#L74 assume !(~c_dr_pc~0 == 1); 1855#L74-2 is_do_read_c_triggered_~__retres1~1 := 0; 1856#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 1825#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1826#L313 assume !(activate_threads_~tmp___0~1 != 0); 1890#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1891#L283 assume !(~q_read_ev~0 == 1); 1885#L283-2 assume !(~q_write_ev~0 == 1); 1767#L288-1 assume { :end_inline_reset_delta_events } true; 1768#L409-3 [2018-10-27 06:09:50,342 INFO L795 eck$LassoCheckResult]: Loop: 1768#L409-3 assume true; 2068#L409-1 assume !false; 2067#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 1973#L354 assume true; 1971#L329-1 assume !false; 1968#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1966#L245 assume !(~p_dw_st~0 == 0); 1963#L249 assume !(~c_dr_st~0 == 0);exists_runnable_thread_~__retres1~2 := 0; 1959#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1955#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 1953#L334 assume !(eval_~tmp___1~0 != 0); 1952#L370 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1950#L212-3 assume !(~q_req_up~0 == 1); 1948#L212-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1947#L265-3 assume ~q_read_ev~0 == 0;~q_read_ev~0 := 1; 1815#L265-5 assume !(~q_write_ev~0 == 0); 1816#L270-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 1835#L55-3 assume !(~p_dw_pc~0 == 1); 1836#L55-5 is_do_write_p_triggered_~__retres1~0 := 0; 1914#L66-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 1915#L67-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 1910#L305-3 assume !(activate_threads_~tmp~1 != 0); 1911#L305-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 1852#L74-3 assume !(~c_dr_pc~0 == 1); 1853#L74-5 is_do_read_c_triggered_~__retres1~1 := 0; 1857#L85-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 1858#L86-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1892#L313-3 assume activate_threads_~tmp___0~1 != 0;~c_dr_st~0 := 0; 1893#L313-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1883#L283-3 assume ~q_read_ev~0 == 1;~q_read_ev~0 := 2; 1884#L283-5 assume !(~q_write_ev~0 == 1); 1894#L288-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1895#L245-1 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 2074#L257-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 2073#L258-1 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 2072#L384 assume stop_simulation_~tmp~3 != 0;stop_simulation_~__retres2~0 := 0; 2071#L391 stop_simulation_#res := stop_simulation_~__retres2~0; 2070#L392 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 2069#L426 assume !(start_simulation_~tmp~4 != 0); 1768#L409-3 [2018-10-27 06:09:50,342 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:50,342 INFO L82 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2018-10-27 06:09:50,342 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:50,343 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:50,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,343 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:50,344 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:50,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:50,382 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:50,385 INFO L82 PathProgramCache]: Analyzing trace with hash 2001597066, now seen corresponding path program 1 times [2018-10-27 06:09:50,386 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:50,386 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:50,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,387 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:09:50,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:50,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:50,486 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:50,486 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:09:50,487 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:09:50,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:09:50,487 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:09:50,487 INFO L87 Difference]: Start difference. First operand 319 states and 442 transitions. cyclomatic complexity: 125 Second operand 3 states. [2018-10-27 06:09:50,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:50,641 INFO L93 Difference]: Finished difference Result 507 states and 677 transitions. [2018-10-27 06:09:50,642 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:09:50,642 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 507 states and 677 transitions. [2018-10-27 06:09:50,647 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 400 [2018-10-27 06:09:50,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 507 states to 507 states and 677 transitions. [2018-10-27 06:09:50,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 507 [2018-10-27 06:09:50,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 507 [2018-10-27 06:09:50,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 507 states and 677 transitions. [2018-10-27 06:09:50,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:09:50,652 INFO L705 BuchiCegarLoop]: Abstraction has 507 states and 677 transitions. [2018-10-27 06:09:50,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 507 states and 677 transitions. [2018-10-27 06:09:50,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 507 to 507. [2018-10-27 06:09:50,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 507 states. [2018-10-27 06:09:50,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 507 states to 507 states and 677 transitions. [2018-10-27 06:09:50,666 INFO L728 BuchiCegarLoop]: Abstraction has 507 states and 677 transitions. [2018-10-27 06:09:50,666 INFO L608 BuchiCegarLoop]: Abstraction has 507 states and 677 transitions. [2018-10-27 06:09:50,666 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-10-27 06:09:50,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 507 states and 677 transitions. [2018-10-27 06:09:50,670 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 400 [2018-10-27 06:09:50,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:50,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:50,672 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:50,672 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:50,672 INFO L793 eck$LassoCheckResult]: Stem: 2687#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 2597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2598#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2649#L212 assume !(~q_req_up~0 == 1); 2668#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2669#L227 assume !(~p_dw_i~0 == 1);~p_dw_st~0 := 2; 2819#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 2818#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2817#L265 assume !(~q_read_ev~0 == 0); 2815#L265-2 assume !(~q_write_ev~0 == 0); 2813#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 2811#L55 assume !(~p_dw_pc~0 == 1); 2808#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 2806#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 2805#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 2799#L305 assume activate_threads_~tmp~1 != 0;~p_dw_st~0 := 0; 2798#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 2797#L74 assume !(~c_dr_pc~0 == 1); 2796#L74-2 is_do_read_c_triggered_~__retres1~1 := 0; 2795#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 2794#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2793#L313 assume !(activate_threads_~tmp___0~1 != 0); 2792#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2791#L283 assume !(~q_read_ev~0 == 1); 2786#L283-2 assume !(~q_write_ev~0 == 1); 2787#L288-1 assume { :end_inline_reset_delta_events } true; 2997#L409-3 [2018-10-27 06:09:50,672 INFO L795 eck$LassoCheckResult]: Loop: 2997#L409-3 assume true; 2996#L409-1 assume !false; 2729#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 2728#L354 assume true; 2727#L329-1 assume !false; 2726#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 2724#L245 assume !(~p_dw_st~0 == 0); 2725#L249 assume !(~c_dr_st~0 == 0);exists_runnable_thread_~__retres1~2 := 0; 3046#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3045#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 3044#L334 assume !(eval_~tmp___1~0 != 0); 3042#L370 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3039#L212-3 assume !(~q_req_up~0 == 1); 3036#L212-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3033#L265-3 assume ~q_read_ev~0 == 0;~q_read_ev~0 := 1; 3032#L265-5 assume !(~q_write_ev~0 == 0); 3031#L270-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 3030#L55-3 assume ~p_dw_pc~0 == 1; 3028#L56-1 assume ~q_read_ev~0 == 1;is_do_write_p_triggered_~__retres1~0 := 1; 3027#L66-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 3026#L67-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 3025#L305-3 assume activate_threads_~tmp~1 != 0;~p_dw_st~0 := 0; 3024#L305-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 3022#L74-3 assume !(~c_dr_pc~0 == 1); 3020#L74-5 is_do_read_c_triggered_~__retres1~1 := 0; 3018#L85-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 3016#L86-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3014#L313-3 assume activate_threads_~tmp___0~1 != 0;~c_dr_st~0 := 0; 3012#L313-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3010#L283-3 assume ~q_read_ev~0 == 1;~q_read_ev~0 := 2; 3009#L283-5 assume !(~q_write_ev~0 == 1); 3006#L288-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3004#L245-1 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 3003#L257-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3002#L258-1 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 3001#L384 assume stop_simulation_~tmp~3 != 0;stop_simulation_~__retres2~0 := 0; 3000#L391 stop_simulation_#res := stop_simulation_~__retres2~0; 2999#L392 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 2998#L426 assume !(start_simulation_~tmp~4 != 0); 2997#L409-3 [2018-10-27 06:09:50,673 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:50,673 INFO L82 PathProgramCache]: Analyzing trace with hash -1896010065, now seen corresponding path program 1 times [2018-10-27 06:09:50,673 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:50,673 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:50,674 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,674 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:50,674 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:50,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:50,707 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:50,708 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:09:50,708 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:09:50,708 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:50,708 INFO L82 PathProgramCache]: Analyzing trace with hash -185838867, now seen corresponding path program 1 times [2018-10-27 06:09:50,708 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:50,709 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:50,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:50,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:50,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:50,815 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:50,815 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 06:09:50,815 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:09:50,816 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:09:50,816 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:09:50,818 INFO L87 Difference]: Start difference. First operand 507 states and 677 transitions. cyclomatic complexity: 172 Second operand 3 states. [2018-10-27 06:09:50,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:50,832 INFO L93 Difference]: Finished difference Result 465 states and 619 transitions. [2018-10-27 06:09:50,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:09:50,836 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 465 states and 619 transitions. [2018-10-27 06:09:50,840 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 400 [2018-10-27 06:09:50,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 465 states to 465 states and 619 transitions. [2018-10-27 06:09:50,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 465 [2018-10-27 06:09:50,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 465 [2018-10-27 06:09:50,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 465 states and 619 transitions. [2018-10-27 06:09:50,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:09:50,846 INFO L705 BuchiCegarLoop]: Abstraction has 465 states and 619 transitions. [2018-10-27 06:09:50,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 465 states and 619 transitions. [2018-10-27 06:09:50,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 465 to 465. [2018-10-27 06:09:50,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 465 states. [2018-10-27 06:09:50,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 465 states to 465 states and 619 transitions. [2018-10-27 06:09:50,859 INFO L728 BuchiCegarLoop]: Abstraction has 465 states and 619 transitions. [2018-10-27 06:09:50,859 INFO L608 BuchiCegarLoop]: Abstraction has 465 states and 619 transitions. [2018-10-27 06:09:50,859 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-10-27 06:09:50,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 465 states and 619 transitions. [2018-10-27 06:09:50,862 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 400 [2018-10-27 06:09:50,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:50,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:50,863 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:50,863 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:50,866 INFO L793 eck$LassoCheckResult]: Stem: 3667#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3578#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3579#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3632#L212 assume !(~q_req_up~0 == 1); 3647#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3596#L227 assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 3590#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 3591#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3613#L265 assume !(~q_read_ev~0 == 0); 3614#L265-2 assume !(~q_write_ev~0 == 0); 3704#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 3668#L55 assume !(~p_dw_pc~0 == 1); 3628#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 3627#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 3701#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 3688#L305 assume !(activate_threads_~tmp~1 != 0); 3689#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 3683#L74 assume !(~c_dr_pc~0 == 1); 3663#L74-2 is_do_read_c_triggered_~__retres1~1 := 0; 3664#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 3640#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3641#L313 assume !(activate_threads_~tmp___0~1 != 0); 3696#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3697#L283 assume !(~q_read_ev~0 == 1); 3691#L283-2 assume !(~q_write_ev~0 == 1); 3580#L288-1 assume { :end_inline_reset_delta_events } true; 3577#L409-3 [2018-10-27 06:09:50,867 INFO L795 eck$LassoCheckResult]: Loop: 3577#L409-3 assume true; 3570#L409-1 assume !false; 3571#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 3727#L354 assume true; 3725#L329-1 assume !false; 3726#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3781#L245 assume !(~p_dw_st~0 == 0); 3597#L249 assume !(~c_dr_st~0 == 0);exists_runnable_thread_~__retres1~2 := 0; 3599#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 4009#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 4008#L334 assume !(eval_~tmp___1~0 != 0); 3592#L370 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3593#L212-3 assume !(~q_req_up~0 == 1); 3645#L212-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3606#L265-3 assume ~q_read_ev~0 == 0;~q_read_ev~0 := 1; 3607#L265-5 assume !(~q_write_ev~0 == 0); 3631#L270-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 3649#L55-3 assume ~p_dw_pc~0 == 1; 3621#L56-1 assume ~q_read_ev~0 == 1;is_do_write_p_triggered_~__retres1~0 := 1; 3622#L66-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 3624#L67-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 3625#L305-3 assume activate_threads_~tmp~1 != 0;~p_dw_st~0 := 0; 3674#L305-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 3661#L74-3 assume !(~c_dr_pc~0 == 1); 3658#L74-5 is_do_read_c_triggered_~__retres1~1 := 0; 3659#L85-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 3637#L86-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3638#L313-3 assume activate_threads_~tmp___0~1 != 0;~c_dr_st~0 := 0; 3681#L313-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3682#L283-3 assume ~q_read_ev~0 == 1;~q_read_ev~0 := 2; 3686#L283-5 assume !(~q_write_ev~0 == 1); 3687#L288-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3698#L245-1 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 3617#L257-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3618#L258-1 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 3584#L384 assume stop_simulation_~tmp~3 != 0;stop_simulation_~__retres2~0 := 0; 3585#L391 stop_simulation_#res := stop_simulation_~__retres2~0; 3588#L392 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 3589#L426 assume !(start_simulation_~tmp~4 != 0); 3577#L409-3 [2018-10-27 06:09:50,867 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:50,867 INFO L82 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2018-10-27 06:09:50,867 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:50,867 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:50,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,868 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:50,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:50,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:50,891 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:50,891 INFO L82 PathProgramCache]: Analyzing trace with hash -185838867, now seen corresponding path program 2 times [2018-10-27 06:09:50,892 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:50,892 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:50,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,893 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:09:50,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:50,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:51,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:51,065 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:51,065 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 06:09:51,065 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:09:51,065 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 06:09:51,065 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-27 06:09:51,066 INFO L87 Difference]: Start difference. First operand 465 states and 619 transitions. cyclomatic complexity: 156 Second operand 5 states. [2018-10-27 06:09:51,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:51,194 INFO L93 Difference]: Finished difference Result 839 states and 1105 transitions. [2018-10-27 06:09:51,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-27 06:09:51,196 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 839 states and 1105 transitions. [2018-10-27 06:09:51,203 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 774 [2018-10-27 06:09:51,208 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 839 states to 839 states and 1105 transitions. [2018-10-27 06:09:51,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 839 [2018-10-27 06:09:51,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 839 [2018-10-27 06:09:51,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 839 states and 1105 transitions. [2018-10-27 06:09:51,217 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:09:51,217 INFO L705 BuchiCegarLoop]: Abstraction has 839 states and 1105 transitions. [2018-10-27 06:09:51,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 839 states and 1105 transitions. [2018-10-27 06:09:51,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 839 to 471. [2018-10-27 06:09:51,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 471 states. [2018-10-27 06:09:51,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 617 transitions. [2018-10-27 06:09:51,232 INFO L728 BuchiCegarLoop]: Abstraction has 471 states and 617 transitions. [2018-10-27 06:09:51,232 INFO L608 BuchiCegarLoop]: Abstraction has 471 states and 617 transitions. [2018-10-27 06:09:51,232 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-10-27 06:09:51,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 471 states and 617 transitions. [2018-10-27 06:09:51,236 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 406 [2018-10-27 06:09:51,236 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:51,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:51,237 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:51,237 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:51,238 INFO L793 eck$LassoCheckResult]: Stem: 4991#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 4898#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4899#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4951#L212 assume !(~q_req_up~0 == 1); 4967#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4915#L227 assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 4911#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 4912#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4932#L265 assume !(~q_read_ev~0 == 0); 4933#L265-2 assume !(~q_write_ev~0 == 0); 5039#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 4994#L55 assume !(~p_dw_pc~0 == 1); 4946#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 4945#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 5036#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 5015#L305 assume !(activate_threads_~tmp~1 != 0); 5016#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 5009#L74 assume !(~c_dr_pc~0 == 1); 4986#L74-2 is_do_read_c_triggered_~__retres1~1 := 0; 4987#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 4959#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4960#L313 assume !(activate_threads_~tmp___0~1 != 0); 5024#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5025#L283 assume !(~q_read_ev~0 == 1); 5019#L283-2 assume !(~q_write_ev~0 == 1); 4896#L288-1 assume { :end_inline_reset_delta_events } true; 4897#L409-3 [2018-10-27 06:09:51,238 INFO L795 eck$LassoCheckResult]: Loop: 4897#L409-3 assume true; 5142#L409-1 assume !false; 5143#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 5105#L354 assume true; 5106#L329-1 assume !false; 5097#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 5098#L245 assume !(~p_dw_st~0 == 0); 5091#L249 assume !(~c_dr_st~0 == 0);exists_runnable_thread_~__retres1~2 := 0; 5088#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 5086#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 5083#L334 assume !(eval_~tmp___1~0 != 0); 5078#L370 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5073#L212-3 assume !(~q_req_up~0 == 1); 5068#L212-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5066#L265-3 assume ~q_read_ev~0 == 0;~q_read_ev~0 := 1; 5064#L265-5 assume !(~q_write_ev~0 == 0); 5061#L270-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 5058#L55-3 assume !(~p_dw_pc~0 == 1); 5059#L55-5 is_do_write_p_triggered_~__retres1~0 := 0; 5053#L66-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 5054#L67-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 4997#L305-3 assume activate_threads_~tmp~1 != 0;~p_dw_st~0 := 0; 4999#L305-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 5225#L74-3 assume !(~c_dr_pc~0 == 1); 5223#L74-5 is_do_read_c_triggered_~__retres1~1 := 0; 5221#L85-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 5219#L86-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 5217#L313-3 assume !(activate_threads_~tmp___0~1 != 0); 5215#L313-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5213#L283-3 assume ~q_read_ev~0 == 1;~q_read_ev~0 := 2; 5212#L283-5 assume !(~q_write_ev~0 == 1); 5173#L288-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 5209#L245-1 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 5206#L257-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 5204#L258-1 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 5202#L384 assume stop_simulation_~tmp~3 != 0;stop_simulation_~__retres2~0 := 0; 5200#L391 stop_simulation_#res := stop_simulation_~__retres2~0; 5198#L392 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 5194#L426 assume !(start_simulation_~tmp~4 != 0); 4897#L409-3 [2018-10-27 06:09:51,238 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:51,238 INFO L82 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 4 times [2018-10-27 06:09:51,238 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:51,239 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:51,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:51,252 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:09:51,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:51,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:51,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:51,266 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:51,271 INFO L82 PathProgramCache]: Analyzing trace with hash -41060086, now seen corresponding path program 1 times [2018-10-27 06:09:51,271 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:51,271 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:51,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:51,272 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:09:51,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:51,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:51,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:51,669 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:51,669 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 06:09:51,670 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:09:51,670 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 06:09:51,670 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-27 06:09:51,670 INFO L87 Difference]: Start difference. First operand 471 states and 617 transitions. cyclomatic complexity: 148 Second operand 5 states. [2018-10-27 06:09:51,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:51,823 INFO L93 Difference]: Finished difference Result 1102 states and 1444 transitions. [2018-10-27 06:09:51,828 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-27 06:09:51,828 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1102 states and 1444 transitions. [2018-10-27 06:09:51,837 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 939 [2018-10-27 06:09:51,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1102 states to 1102 states and 1444 transitions. [2018-10-27 06:09:51,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1102 [2018-10-27 06:09:51,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1102 [2018-10-27 06:09:51,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1102 states and 1444 transitions. [2018-10-27 06:09:51,847 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:09:51,847 INFO L705 BuchiCegarLoop]: Abstraction has 1102 states and 1444 transitions. [2018-10-27 06:09:51,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1102 states and 1444 transitions. [2018-10-27 06:09:51,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1102 to 489. [2018-10-27 06:09:51,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 489 states. [2018-10-27 06:09:51,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 489 states to 489 states and 635 transitions. [2018-10-27 06:09:51,863 INFO L728 BuchiCegarLoop]: Abstraction has 489 states and 635 transitions. [2018-10-27 06:09:51,863 INFO L608 BuchiCegarLoop]: Abstraction has 489 states and 635 transitions. [2018-10-27 06:09:51,863 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-10-27 06:09:51,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 489 states and 635 transitions. [2018-10-27 06:09:51,866 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 418 [2018-10-27 06:09:51,866 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:51,866 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:51,867 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:51,867 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:51,870 INFO L793 eck$LassoCheckResult]: Stem: 6582#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6482#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6483#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6535#L212 assume !(~q_req_up~0 == 1); 6559#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6501#L227 assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 6502#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 6514#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6515#L265 assume !(~q_read_ev~0 == 0); 6516#L265-2 assume !(~q_write_ev~0 == 0); 6517#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 6566#L55 assume !(~p_dw_pc~0 == 1); 6531#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 6579#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 6532#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 6533#L305 assume !(activate_threads_~tmp~1 != 0); 6612#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 6613#L74 assume !(~c_dr_pc~0 == 1); 6575#L74-2 is_do_read_c_triggered_~__retres1~1 := 0; 6576#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 6543#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6544#L313 assume !(activate_threads_~tmp___0~1 != 0); 6616#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6617#L283 assume !(~q_read_ev~0 == 1); 6610#L283-2 assume !(~q_write_ev~0 == 1); 6611#L288-1 assume { :end_inline_reset_delta_events } true; 6822#L409-3 [2018-10-27 06:09:51,871 INFO L795 eck$LassoCheckResult]: Loop: 6822#L409-3 assume true; 6821#L409-1 assume !false; 6820#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 6799#L354 assume true; 6818#L329-1 assume !false; 6816#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 6814#L245 assume !(~p_dw_st~0 == 0); 6503#L249 assume !(~c_dr_st~0 == 0);exists_runnable_thread_~__retres1~2 := 0; 6505#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 6887#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 6886#L334 assume !(eval_~tmp___1~0 != 0); 6497#L370 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 6498#L212-3 assume !(~q_req_up~0 == 1); 6548#L212-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 6510#L265-3 assume ~q_read_ev~0 == 0;~q_read_ev~0 := 1; 6511#L265-5 assume !(~q_write_ev~0 == 0); 6534#L270-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 6560#L55-3 assume ~p_dw_pc~0 == 1; 6524#L56-1 assume ~q_read_ev~0 == 1;is_do_write_p_triggered_~__retres1~0 := 1; 6525#L66-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 6854#L67-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 6852#L305-3 assume activate_threads_~tmp~1 != 0;~p_dw_st~0 := 0; 6850#L305-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 6848#L74-3 assume !(~c_dr_pc~0 == 1); 6846#L74-5 is_do_read_c_triggered_~__retres1~1 := 0; 6844#L85-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 6842#L86-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6840#L313-3 assume !(activate_threads_~tmp___0~1 != 0); 6838#L313-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6836#L283-3 assume ~q_read_ev~0 == 1;~q_read_ev~0 := 2; 6834#L283-5 assume !(~q_write_ev~0 == 1); 6831#L288-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 6829#L245-1 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 6828#L257-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 6827#L258-1 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 6826#L384 assume stop_simulation_~tmp~3 != 0;stop_simulation_~__retres2~0 := 0; 6825#L391 stop_simulation_#res := stop_simulation_~__retres2~0; 6824#L392 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 6823#L426 assume !(start_simulation_~tmp~4 != 0); 6822#L409-3 [2018-10-27 06:09:51,871 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:51,871 INFO L82 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 5 times [2018-10-27 06:09:51,871 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:51,871 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:51,872 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:51,872 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:51,872 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:51,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:51,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:51,893 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:51,894 INFO L82 PathProgramCache]: Analyzing trace with hash 72326571, now seen corresponding path program 1 times [2018-10-27 06:09:51,894 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:51,894 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:51,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:51,895 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:09:51,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:51,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:51,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:51,916 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:51,916 INFO L82 PathProgramCache]: Analyzing trace with hash 832576701, now seen corresponding path program 1 times [2018-10-27 06:09:51,916 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:51,916 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:51,917 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:51,917 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:51,917 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:51,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:51,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:51,990 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:51,990 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:09:53,625 WARN L179 SmtUtils]: Spent 1.63 s on a formula simplification. DAG size of input: 75 DAG size of output: 68 [2018-10-27 06:09:53,924 WARN L179 SmtUtils]: Spent 289.00 ms on a formula simplification that was a NOOP. DAG size: 58 [2018-10-27 06:09:53,941 INFO L214 LassoAnalysis]: Preferences: [2018-10-27 06:09:53,942 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-10-27 06:09:53,942 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-10-27 06:09:53,942 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-10-27 06:09:53,942 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-10-27 06:09:53,943 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-10-27 06:09:53,943 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-10-27 06:09:53,943 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-10-27 06:09:53,943 INFO L131 ssoRankerPreferences]: Filename of dumped script: pc_sfifo_2_true-unreach-call_false-termination.cil.c_Iteration9_Loop [2018-10-27 06:09:53,943 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-10-27 06:09:53,947 INFO L280 LassoAnalysis]: Starting lasso preprocessing... [2018-10-27 06:09:53,971 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:53,984 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:53,996 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:53,999 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,005 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,050 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,058 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,060 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,092 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,095 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,099 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,108 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,118 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,128 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,130 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,156 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,165 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,176 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,182 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,184 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,194 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,196 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,225 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,585 INFO L298 LassoAnalysis]: Preprocessing complete. [2018-10-27 06:09:54,586 INFO L410 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-10-27 06:09:54,592 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-10-27 06:09:54,592 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-10-27 06:09:54,599 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-10-27 06:09:54,599 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp___0~2=0} Honda state: {ULTIMATE.start_eval_~tmp___0~2=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2018-10-27 06:09:54,642 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-10-27 06:09:54,642 INFO L163 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-10-27 06:09:54,664 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-10-27 06:09:54,664 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2018-10-27 06:09:54,700 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-10-27 06:09:54,700 INFO L163 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-10-27 06:09:54,716 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-10-27 06:09:54,716 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~ret5=0} Honda state: {ULTIMATE.start_eval_#t~ret5=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-10-27 06:09:54,749 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-10-27 06:09:54,749 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-10-27 06:09:54,786 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-10-27 06:09:54,786 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-10-27 06:09:54,807 INFO L450 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-10-27 06:09:54,826 INFO L214 LassoAnalysis]: Preferences: [2018-10-27 06:09:54,826 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-10-27 06:09:54,826 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-10-27 06:09:54,827 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-10-27 06:09:54,827 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-10-27 06:09:54,827 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-10-27 06:09:54,827 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-10-27 06:09:54,827 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-10-27 06:09:54,827 INFO L131 ssoRankerPreferences]: Filename of dumped script: pc_sfifo_2_true-unreach-call_false-termination.cil.c_Iteration9_Loop [2018-10-27 06:09:54,827 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-10-27 06:09:54,827 INFO L280 LassoAnalysis]: Starting lasso preprocessing... [2018-10-27 06:09:54,829 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,864 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,909 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,933 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,958 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,959 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,963 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,966 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,968 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,970 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,973 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:54,979 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:55,005 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:55,009 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:55,013 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:55,015 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:55,017 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:55,018 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:55,097 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:55,212 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:55,244 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:55,280 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:55,288 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-10-27 06:09:55,684 WARN L179 SmtUtils]: Spent 168.00 ms on a formula simplification that was a NOOP. DAG size: 11 [2018-10-27 06:09:55,910 INFO L298 LassoAnalysis]: Preprocessing complete. [2018-10-27 06:09:55,919 INFO L496 LassoAnalysis]: Using template 'affine'. [2018-10-27 06:09:55,922 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-10-27 06:09:55,923 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-10-27 06:09:55,926 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-10-27 06:09:55,927 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-10-27 06:09:55,927 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-10-27 06:09:55,927 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-10-27 06:09:55,929 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-10-27 06:09:55,929 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-10-27 06:09:55,935 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-10-27 06:09:55,935 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-10-27 06:09:55,936 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-10-27 06:09:55,936 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-10-27 06:09:55,936 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-10-27 06:09:55,936 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-10-27 06:09:55,936 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-10-27 06:09:55,937 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-10-27 06:09:55,937 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-10-27 06:09:55,938 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-10-27 06:09:55,938 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-10-27 06:09:55,939 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-10-27 06:09:55,939 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-10-27 06:09:55,939 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-10-27 06:09:55,939 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-10-27 06:09:55,948 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-10-27 06:09:55,949 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-10-27 06:09:55,949 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-10-27 06:09:55,950 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-10-27 06:09:55,950 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-10-27 06:09:55,951 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-10-27 06:09:55,951 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-10-27 06:09:55,951 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-10-27 06:09:55,951 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-10-27 06:09:55,951 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-10-27 06:09:55,952 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-10-27 06:09:55,952 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-10-27 06:09:55,963 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-10-27 06:09:55,965 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-10-27 06:09:55,966 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-10-27 06:09:55,968 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-10-27 06:09:55,968 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-10-27 06:09:55,968 INFO L517 LassoAnalysis]: Proved termination. [2018-10-27 06:09:55,969 INFO L519 LassoAnalysis]: Termination argument consisting of: Ranking function f(~q_read_ev~0) = -1*~q_read_ev~0 + 1 Supporting invariants [] [2018-10-27 06:09:55,970 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-10-27 06:09:56,080 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:56,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:56,100 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 06:09:56,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:56,124 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-10-27 06:09:56,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:56,156 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-10-27 06:09:56,157 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 489 states and 635 transitions. cyclomatic complexity: 148 Second operand 5 states. [2018-10-27 06:09:56,289 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 489 states and 635 transitions. cyclomatic complexity: 148. Second operand 5 states. Result 1369 states and 1785 transitions. Complement of second has 5 states. [2018-10-27 06:09:56,296 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-10-27 06:09:56,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-10-27 06:09:56,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 141 transitions. [2018-10-27 06:09:56,298 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 141 transitions. Stem has 26 letters. Loop has 39 letters. [2018-10-27 06:09:56,304 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-10-27 06:09:56,305 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 141 transitions. Stem has 65 letters. Loop has 39 letters. [2018-10-27 06:09:56,306 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-10-27 06:09:56,310 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 141 transitions. Stem has 26 letters. Loop has 78 letters. [2018-10-27 06:09:56,312 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-10-27 06:09:56,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1369 states and 1785 transitions. [2018-10-27 06:09:56,325 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 836 [2018-10-27 06:09:56,334 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1369 states to 1369 states and 1785 transitions. [2018-10-27 06:09:56,334 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 917 [2018-10-27 06:09:56,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 931 [2018-10-27 06:09:56,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1369 states and 1785 transitions. [2018-10-27 06:09:56,337 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-10-27 06:09:56,337 INFO L705 BuchiCegarLoop]: Abstraction has 1369 states and 1785 transitions. [2018-10-27 06:09:56,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1369 states and 1785 transitions. [2018-10-27 06:09:56,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1369 to 1355. [2018-10-27 06:09:56,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1355 states. [2018-10-27 06:09:56,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1355 states to 1355 states and 1771 transitions. [2018-10-27 06:09:56,365 INFO L728 BuchiCegarLoop]: Abstraction has 1355 states and 1771 transitions. [2018-10-27 06:09:56,366 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:09:56,366 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:09:56,366 INFO L87 Difference]: Start difference. First operand 1355 states and 1771 transitions. Second operand 3 states. [2018-10-27 06:09:56,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:56,500 INFO L93 Difference]: Finished difference Result 1355 states and 1735 transitions. [2018-10-27 06:09:56,501 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:09:56,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1355 states and 1735 transitions. [2018-10-27 06:09:56,511 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 836 [2018-10-27 06:09:56,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1355 states to 1355 states and 1735 transitions. [2018-10-27 06:09:56,520 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 917 [2018-10-27 06:09:56,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 917 [2018-10-27 06:09:56,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1355 states and 1735 transitions. [2018-10-27 06:09:56,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-10-27 06:09:56,521 INFO L705 BuchiCegarLoop]: Abstraction has 1355 states and 1735 transitions. [2018-10-27 06:09:56,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1355 states and 1735 transitions. [2018-10-27 06:09:56,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1355 to 1355. [2018-10-27 06:09:56,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1355 states. [2018-10-27 06:09:56,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1355 states to 1355 states and 1735 transitions. [2018-10-27 06:09:56,548 INFO L728 BuchiCegarLoop]: Abstraction has 1355 states and 1735 transitions. [2018-10-27 06:09:56,548 INFO L608 BuchiCegarLoop]: Abstraction has 1355 states and 1735 transitions. [2018-10-27 06:09:56,548 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-10-27 06:09:56,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1355 states and 1735 transitions. [2018-10-27 06:09:56,556 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 836 [2018-10-27 06:09:56,557 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:56,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:56,559 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:56,559 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:56,560 INFO L793 eck$LassoCheckResult]: Stem: 11450#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 11277#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 11278#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 11367#L212 assume !(~q_req_up~0 == 1); 11411#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11510#L227 assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 11303#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 11304#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11340#L265 assume !(~q_read_ev~0 == 0); 11341#L265-2 assume !(~q_write_ev~0 == 0); 11429#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 11430#L55 assume !(~p_dw_pc~0 == 1); 11362#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 11507#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 11506#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 11505#L305 assume !(activate_threads_~tmp~1 != 0); 11484#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 11485#L74 assume !(~c_dr_pc~0 == 1); 11504#L74-2 is_do_read_c_triggered_~__retres1~1 := 0; 11467#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 11468#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 11486#L313 assume !(activate_threads_~tmp___0~1 != 0); 11487#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11503#L283 assume !(~q_read_ev~0 == 1); 11482#L283-2 assume !(~q_write_ev~0 == 1); 11483#L288-1 assume { :end_inline_reset_delta_events } true; 11727#L409-3 assume true; 11728#L409-1 [2018-10-27 06:09:56,560 INFO L795 eck$LassoCheckResult]: Loop: 11728#L409-1 assume !false; 12169#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 12167#L354 assume true; 12165#L329-1 assume !false; 12163#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 12161#L245 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 12159#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 12157#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 12155#L334 assume eval_~tmp___1~0 != 0; 12153#L334-1 assume ~p_dw_st~0 == 0;eval_~tmp~2 := eval_#t~nondet6;havoc eval_#t~nondet6; 12150#L343 assume eval_~tmp~2 != 0;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet2; 12148#L118 assume ~p_dw_pc~0 == 0; 12144#L129-2 assume true; 12142#L129 assume !false; 12139#L130 assume ~q_free~0 == 0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 12042#L148 assume { :end_inline_do_write_p } true; 11954#L339 assume !(~c_dr_st~0 == 0); 11952#L354 assume true; 11950#L329-1 assume !false; 11947#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 11945#L245 assume !(~p_dw_st~0 == 0); 11942#L249 assume !(~c_dr_st~0 == 0);exists_runnable_thread_~__retres1~2 := 0; 11940#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 11937#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 11934#L334 assume !(eval_~tmp___1~0 != 0); 11932#L370 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 11929#L212-3 assume !(~q_req_up~0 == 1); 11930#L212-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12231#L265-3 assume !(~q_read_ev~0 == 0); 12229#L265-5 assume !(~q_write_ev~0 == 0); 11856#L270-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 12226#L55-3 assume ~p_dw_pc~0 == 1; 12220#L56-1 assume ~q_read_ev~0 == 1;is_do_write_p_triggered_~__retres1~0 := 1; 12218#L66-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 12216#L67-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 12213#L305-3 assume activate_threads_~tmp~1 != 0;~p_dw_st~0 := 0; 12211#L305-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 12209#L74-3 assume !(~c_dr_pc~0 == 1); 12207#L74-5 is_do_read_c_triggered_~__retres1~1 := 0; 12205#L85-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 12203#L86-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 12200#L313-3 assume !(activate_threads_~tmp___0~1 != 0); 12197#L313-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12195#L283-3 assume !(~q_read_ev~0 == 1); 12193#L283-5 assume !(~q_write_ev~0 == 1); 12184#L288-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 12180#L245-1 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 12179#L257-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 12178#L258-1 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 12176#L384 assume stop_simulation_~tmp~3 != 0;stop_simulation_~__retres2~0 := 0; 12175#L391 stop_simulation_#res := stop_simulation_~__retres2~0; 12174#L392 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 12173#L426 assume !(start_simulation_~tmp~4 != 0); 12172#L409-3 assume true; 11728#L409-1 [2018-10-27 06:09:56,560 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:56,560 INFO L82 PathProgramCache]: Analyzing trace with hash 1392540969, now seen corresponding path program 1 times [2018-10-27 06:09:56,560 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:56,560 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:56,568 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:56,568 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:56,568 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:56,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:56,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:56,591 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:56,600 INFO L82 PathProgramCache]: Analyzing trace with hash -1334432163, now seen corresponding path program 1 times [2018-10-27 06:09:56,600 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:56,600 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:56,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:56,601 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:56,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:56,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:56,682 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-27 06:09:56,682 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:56,682 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:09:56,683 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:09:56,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:09:56,683 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:09:56,683 INFO L87 Difference]: Start difference. First operand 1355 states and 1735 transitions. cyclomatic complexity: 386 Second operand 3 states. [2018-10-27 06:09:56,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:56,959 INFO L93 Difference]: Finished difference Result 1578 states and 1967 transitions. [2018-10-27 06:09:56,960 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:09:56,960 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 1967 transitions. [2018-10-27 06:09:56,969 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 796 [2018-10-27 06:09:56,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1464 states and 1835 transitions. [2018-10-27 06:09:56,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 965 [2018-10-27 06:09:56,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 965 [2018-10-27 06:09:56,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1464 states and 1835 transitions. [2018-10-27 06:09:56,983 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-10-27 06:09:56,984 INFO L705 BuchiCegarLoop]: Abstraction has 1464 states and 1835 transitions. [2018-10-27 06:09:56,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1464 states and 1835 transitions. [2018-10-27 06:09:57,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1464 to 1464. [2018-10-27 06:09:57,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1464 states. [2018-10-27 06:09:57,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 1835 transitions. [2018-10-27 06:09:57,012 INFO L728 BuchiCegarLoop]: Abstraction has 1464 states and 1835 transitions. [2018-10-27 06:09:57,012 INFO L608 BuchiCegarLoop]: Abstraction has 1464 states and 1835 transitions. [2018-10-27 06:09:57,012 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-10-27 06:09:57,012 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 1835 transitions. [2018-10-27 06:09:57,020 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 796 [2018-10-27 06:09:57,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:57,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:57,021 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:57,021 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:57,024 INFO L793 eck$LassoCheckResult]: Stem: 14385#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 14215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 14216#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 14305#L212 assume !(~q_req_up~0 == 1); 14336#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14247#L227 assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 14248#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 14274#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14275#L265 assume ~q_read_ev~0 == 0;~q_read_ev~0 := 1; 14491#L265-2 assume !(~q_write_ev~0 == 0); 14488#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 14485#L55 assume !(~p_dw_pc~0 == 1); 14481#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 14477#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 14472#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 14467#L305 assume !(activate_threads_~tmp~1 != 0); 14463#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 14460#L74 assume !(~c_dr_pc~0 == 1); 14457#L74-2 is_do_read_c_triggered_~__retres1~1 := 0; 14454#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 14452#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 14449#L313 assume !(activate_threads_~tmp___0~1 != 0); 14446#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14442#L283 assume ~q_read_ev~0 == 1;~q_read_ev~0 := 2; 14427#L283-2 assume !(~q_write_ev~0 == 1); 14428#L288-1 assume { :end_inline_reset_delta_events } true; 14564#L409-3 assume true; 14565#L409-1 assume !false; 15232#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 15230#L354 [2018-10-27 06:09:57,024 INFO L795 eck$LassoCheckResult]: Loop: 15230#L354 assume true; 15228#L329-1 assume !false; 15226#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 15224#L245 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 15222#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 15220#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 15218#L334 assume eval_~tmp___1~0 != 0; 15215#L334-1 assume ~p_dw_st~0 == 0;eval_~tmp~2 := eval_#t~nondet6;havoc eval_#t~nondet6; 15211#L343 assume !(eval_~tmp~2 != 0); 15212#L339 assume !(~c_dr_st~0 == 0); 15230#L354 [2018-10-27 06:09:57,024 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:57,024 INFO L82 PathProgramCache]: Analyzing trace with hash 2017086059, now seen corresponding path program 1 times [2018-10-27 06:09:57,024 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:57,024 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:57,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,025 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:57,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:57,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:57,101 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:57,101 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:09:57,101 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:09:57,101 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:57,102 INFO L82 PathProgramCache]: Analyzing trace with hash -544530888, now seen corresponding path program 1 times [2018-10-27 06:09:57,102 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:57,102 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:57,102 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,102 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:57,102 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:57,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:57,383 WARN L179 SmtUtils]: Spent 269.00 ms on a formula simplification. DAG size of input: 20 DAG size of output: 18 [2018-10-27 06:09:57,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:09:57,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:09:57,423 INFO L87 Difference]: Start difference. First operand 1464 states and 1835 transitions. cyclomatic complexity: 385 Second operand 3 states. [2018-10-27 06:09:57,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:57,533 INFO L93 Difference]: Finished difference Result 2415 states and 3020 transitions. [2018-10-27 06:09:57,534 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:09:57,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2415 states and 3020 transitions. [2018-10-27 06:09:57,546 INFO L131 ngComponentsAnalysis]: Automaton has 22 accepting balls. 1334 [2018-10-27 06:09:57,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2415 states to 2042 states and 2545 transitions. [2018-10-27 06:09:57,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1583 [2018-10-27 06:09:57,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1709 [2018-10-27 06:09:57,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2042 states and 2545 transitions. [2018-10-27 06:09:57,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-10-27 06:09:57,559 INFO L705 BuchiCegarLoop]: Abstraction has 2042 states and 2545 transitions. [2018-10-27 06:09:57,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2042 states and 2545 transitions. [2018-10-27 06:09:57,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2042 to 1208. [2018-10-27 06:09:57,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1208 states. [2018-10-27 06:09:57,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1208 states to 1208 states and 1509 transitions. [2018-10-27 06:09:57,607 INFO L728 BuchiCegarLoop]: Abstraction has 1208 states and 1509 transitions. [2018-10-27 06:09:57,607 INFO L608 BuchiCegarLoop]: Abstraction has 1208 states and 1509 transitions. [2018-10-27 06:09:57,607 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-10-27 06:09:57,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1208 states and 1509 transitions. [2018-10-27 06:09:57,611 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 716 [2018-10-27 06:09:57,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:57,614 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:57,614 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:57,615 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:57,615 INFO L793 eck$LassoCheckResult]: Stem: 18255#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 18100#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 18101#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 18183#L212 assume !(~q_req_up~0 == 1); 18222#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18132#L227 assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 18126#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 18127#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18156#L265 assume !(~q_read_ev~0 == 0); 18157#L265-2 assume !(~q_write_ev~0 == 0); 18158#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 18239#L55 assume !(~p_dw_pc~0 == 1); 18178#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 18254#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 18179#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 18180#L305 assume !(activate_threads_~tmp~1 != 0); 18281#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 18271#L74 assume !(~c_dr_pc~0 == 1); 18250#L74-2 is_do_read_c_triggered_~__retres1~1 := 0; 18251#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 18202#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 18203#L313 assume !(activate_threads_~tmp___0~1 != 0); 18287#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18260#L283 assume !(~q_read_ev~0 == 1); 18261#L283-2 assume !(~q_write_ev~0 == 1); 18286#L288-1 assume { :end_inline_reset_delta_events } true; 19000#L409-3 [2018-10-27 06:09:57,615 INFO L795 eck$LassoCheckResult]: Loop: 19000#L409-3 assume true; 18528#L409-1 assume !false; 18668#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 18664#L354 assume true; 18663#L329-1 assume !false; 18662#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 18661#L245 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 18660#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 18659#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 18658#L334 assume eval_~tmp___1~0 != 0; 18656#L334-1 assume ~p_dw_st~0 == 0;eval_~tmp~2 := eval_#t~nondet6;havoc eval_#t~nondet6; 18657#L343 assume eval_~tmp~2 != 0;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet2; 18688#L118 assume ~p_dw_pc~0 == 0; 19068#L129-2 assume true; 19067#L129 assume !false; 19065#L130 assume ~q_free~0 == 0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 19057#L148 assume { :end_inline_do_write_p } true; 19038#L339 assume !(~c_dr_st~0 == 0); 19032#L354 assume true; 19029#L329-1 assume !false; 19026#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 19023#L245 assume !(~p_dw_st~0 == 0); 19018#L249 assume !(~c_dr_st~0 == 0);exists_runnable_thread_~__retres1~2 := 0; 19014#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 19011#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 19006#L334 assume !(eval_~tmp___1~0 != 0); 18998#L370 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 18999#L212-3 assume ~q_req_up~0 == 1;assume { :begin_inline_update_fifo_q } true; 18993#L25-3 assume ~q_free~0 == 0;~q_write_ev~0 := 0; 18946#L25-5 assume ~q_free~0 == 1;~q_read_ev~0 := 0; 18944#L30-3 ~q_ev~0 := 0;~q_req_up~0 := 0; 18941#L38-1 assume { :end_inline_update_fifo_q } true; 18940#L212-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 18939#L265-3 assume ~q_read_ev~0 == 0;~q_read_ev~0 := 1; 18596#L265-5 assume ~q_write_ev~0 == 0;~q_write_ev~0 := 1; 19153#L270-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 19149#L55-3 assume ~p_dw_pc~0 == 1; 19147#L56-1 assume ~q_read_ev~0 == 1;is_do_write_p_triggered_~__retres1~0 := 1; 18171#L66-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 19145#L67-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 19141#L305-3 assume activate_threads_~tmp~1 != 0;~p_dw_st~0 := 0; 19139#L305-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 19137#L74-3 assume !(~c_dr_pc~0 == 1); 19135#L74-5 is_do_read_c_triggered_~__retres1~1 := 0; 19133#L85-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 19131#L86-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 19129#L313-3 assume !(activate_threads_~tmp___0~1 != 0); 19127#L313-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19125#L283-3 assume ~q_read_ev~0 == 1;~q_read_ev~0 := 2; 19122#L283-5 assume ~q_write_ev~0 == 1;~q_write_ev~0 := 2; 19121#L288-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 19120#L245-1 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 19119#L257-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 19118#L258-1 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 19117#L384 assume stop_simulation_~tmp~3 != 0;stop_simulation_~__retres2~0 := 0; 19116#L391 stop_simulation_#res := stop_simulation_~__retres2~0; 19115#L392 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 19114#L426 assume !(start_simulation_~tmp~4 != 0); 19000#L409-3 [2018-10-27 06:09:57,615 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:57,615 INFO L82 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 6 times [2018-10-27 06:09:57,616 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:57,616 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:57,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,616 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:57,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:57,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:57,635 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:57,635 INFO L82 PathProgramCache]: Analyzing trace with hash -1205551460, now seen corresponding path program 1 times [2018-10-27 06:09:57,635 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:57,635 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:57,638 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,638 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:09:57,638 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:57,686 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:57,686 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:57,686 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:09:57,686 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:09:57,686 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:09:57,686 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:09:57,687 INFO L87 Difference]: Start difference. First operand 1208 states and 1509 transitions. cyclomatic complexity: 313 Second operand 3 states. [2018-10-27 06:09:57,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:57,831 INFO L93 Difference]: Finished difference Result 1520 states and 1883 transitions. [2018-10-27 06:09:57,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:09:57,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1520 states and 1883 transitions. [2018-10-27 06:09:57,839 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 902 [2018-10-27 06:09:57,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1520 states to 1520 states and 1883 transitions. [2018-10-27 06:09:57,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1116 [2018-10-27 06:09:57,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1116 [2018-10-27 06:09:57,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1520 states and 1883 transitions. [2018-10-27 06:09:57,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-10-27 06:09:57,847 INFO L705 BuchiCegarLoop]: Abstraction has 1520 states and 1883 transitions. [2018-10-27 06:09:57,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1520 states and 1883 transitions. [2018-10-27 06:09:57,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1520 to 1496. [2018-10-27 06:09:57,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1496 states. [2018-10-27 06:09:57,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1496 states to 1496 states and 1859 transitions. [2018-10-27 06:09:57,869 INFO L728 BuchiCegarLoop]: Abstraction has 1496 states and 1859 transitions. [2018-10-27 06:09:57,869 INFO L608 BuchiCegarLoop]: Abstraction has 1496 states and 1859 transitions. [2018-10-27 06:09:57,869 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-10-27 06:09:57,870 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1496 states and 1859 transitions. [2018-10-27 06:09:57,877 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 885 [2018-10-27 06:09:57,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:57,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:57,878 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:57,878 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:57,878 INFO L793 eck$LassoCheckResult]: Stem: 21000#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 20835#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 20836#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 20927#L212 assume !(~q_req_up~0 == 1); 20965#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20868#L227 assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 20869#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 20896#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20897#L265 assume !(~q_read_ev~0 == 0); 20898#L265-2 assume !(~q_write_ev~0 == 0); 20899#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 20982#L55 assume !(~p_dw_pc~0 == 1); 20922#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 20999#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 21001#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 21042#L305 assume !(activate_threads_~tmp~1 != 0); 21043#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 21163#L74 assume !(~c_dr_pc~0 == 1); 21162#L74-2 is_do_read_c_triggered_~__retres1~1 := 0; 21028#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 21029#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 21050#L313 assume !(activate_threads_~tmp___0~1 != 0); 21051#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21161#L283 assume !(~q_read_ev~0 == 1); 21047#L283-2 assume !(~q_write_ev~0 == 1); 21048#L288-1 assume { :end_inline_reset_delta_events } true; 21496#L409-3 assume true; 21098#L409-1 assume !false; 22156#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 21483#L354 [2018-10-27 06:09:57,878 INFO L795 eck$LassoCheckResult]: Loop: 21483#L354 assume true; 21492#L329-1 assume !false; 21491#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 21490#L245 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 21489#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 21488#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 21487#L334 assume eval_~tmp___1~0 != 0; 21486#L334-1 assume ~p_dw_st~0 == 0;eval_~tmp~2 := eval_#t~nondet6;havoc eval_#t~nondet6; 21485#L343 assume !(eval_~tmp~2 != 0); 21484#L339 assume !(~c_dr_st~0 == 0); 21483#L354 [2018-10-27 06:09:57,879 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:57,879 INFO L82 PathProgramCache]: Analyzing trace with hash -1797921109, now seen corresponding path program 1 times [2018-10-27 06:09:57,879 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:57,879 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:57,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,880 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:57,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:57,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:57,896 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:57,896 INFO L82 PathProgramCache]: Analyzing trace with hash -544530888, now seen corresponding path program 2 times [2018-10-27 06:09:57,896 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:57,896 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:57,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,897 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:57,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:57,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:57,905 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:57,905 INFO L82 PathProgramCache]: Analyzing trace with hash -2036844446, now seen corresponding path program 1 times [2018-10-27 06:09:57,905 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:57,905 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:57,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,906 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:09:57,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:57,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:09:57,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:09:57,973 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:09:57,973 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:09:58,334 WARN L179 SmtUtils]: Spent 359.00 ms on a formula simplification. DAG size of input: 20 DAG size of output: 18 [2018-10-27 06:09:58,343 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:09:58,343 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:09:58,343 INFO L87 Difference]: Start difference. First operand 1496 states and 1859 transitions. cyclomatic complexity: 372 Second operand 3 states. [2018-10-27 06:09:58,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:09:58,429 INFO L93 Difference]: Finished difference Result 1643 states and 2000 transitions. [2018-10-27 06:09:58,430 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:09:58,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1643 states and 2000 transitions. [2018-10-27 06:09:58,438 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1091 [2018-10-27 06:09:58,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1643 states to 1643 states and 2000 transitions. [2018-10-27 06:09:58,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1232 [2018-10-27 06:09:58,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1232 [2018-10-27 06:09:58,447 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1643 states and 2000 transitions. [2018-10-27 06:09:58,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-10-27 06:09:58,447 INFO L705 BuchiCegarLoop]: Abstraction has 1643 states and 2000 transitions. [2018-10-27 06:09:58,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1643 states and 2000 transitions. [2018-10-27 06:09:58,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1643 to 1643. [2018-10-27 06:09:58,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1643 states. [2018-10-27 06:09:58,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1643 states to 1643 states and 2000 transitions. [2018-10-27 06:09:58,475 INFO L728 BuchiCegarLoop]: Abstraction has 1643 states and 2000 transitions. [2018-10-27 06:09:58,475 INFO L608 BuchiCegarLoop]: Abstraction has 1643 states and 2000 transitions. [2018-10-27 06:09:58,476 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-10-27 06:09:58,476 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1643 states and 2000 transitions. [2018-10-27 06:09:58,483 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1091 [2018-10-27 06:09:58,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:09:58,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:09:58,483 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:58,483 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:09:58,484 INFO L793 eck$LassoCheckResult]: Stem: 24153#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 23981#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 23982#L452 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 24071#L212 assume !(~q_req_up~0 == 1); 24113#L212-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24014#L227 assume ~p_dw_i~0 == 1;~p_dw_st~0 := 0; 24015#L227-2 assume ~c_dr_i~0 == 1;~c_dr_st~0 := 0; 24038#L232-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24039#L265 assume !(~q_read_ev~0 == 0); 24040#L265-2 assume !(~q_write_ev~0 == 0); 24041#L270-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 24131#L55 assume !(~p_dw_pc~0 == 1); 24064#L55-2 is_do_write_p_triggered_~__retres1~0 := 0; 24154#L66 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 24155#L67 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 24191#L305 assume !(activate_threads_~tmp~1 != 0); 24192#L305-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 24181#L74 assume !(~c_dr_pc~0 == 1); 24145#L74-2 is_do_read_c_triggered_~__retres1~1 := 0; 24146#L85 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 24089#L86 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 24090#L313 assume !(activate_threads_~tmp___0~1 != 0); 24204#L313-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24205#L283 assume !(~q_read_ev~0 == 1); 24198#L283-2 assume !(~q_write_ev~0 == 1); 24199#L288-1 assume { :end_inline_reset_delta_events } true; 24634#L409-3 assume true; 24324#L409-1 assume !false; 24851#L410 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 24722#L354 [2018-10-27 06:09:58,484 INFO L795 eck$LassoCheckResult]: Loop: 24722#L354 assume true; 24832#L329-1 assume !false; 24828#L330 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 24824#L245 assume ~p_dw_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 24820#L257 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 24749#L258 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 24746#L334 assume eval_~tmp___1~0 != 0; 24744#L334-1 assume ~p_dw_st~0 == 0;eval_~tmp~2 := eval_#t~nondet6;havoc eval_#t~nondet6; 24733#L343 assume !(eval_~tmp~2 != 0); 24727#L339 assume ~c_dr_st~0 == 0;eval_~tmp___0~2 := eval_#t~nondet7;havoc eval_#t~nondet7; 24721#L358 assume !(eval_~tmp___0~2 != 0); 24722#L354 [2018-10-27 06:09:58,484 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:58,484 INFO L82 PathProgramCache]: Analyzing trace with hash -1797921109, now seen corresponding path program 2 times [2018-10-27 06:09:58,484 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:58,484 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:58,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:58,485 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:58,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:58,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:58,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:58,509 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:58,509 INFO L82 PathProgramCache]: Analyzing trace with hash 299409972, now seen corresponding path program 1 times [2018-10-27 06:09:58,510 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:58,510 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:58,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:58,510 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:09:58,511 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:58,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:58,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:58,519 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:09:58,519 INFO L82 PathProgramCache]: Analyzing trace with hash 1282329930, now seen corresponding path program 1 times [2018-10-27 06:09:58,519 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:09:58,519 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:09:58,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:58,523 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:09:58,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:09:58,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:58,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:09:59,024 WARN L179 SmtUtils]: Spent 394.00 ms on a formula simplification. DAG size of input: 92 DAG size of output: 76 [2018-10-27 06:09:59,088 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 27.10 06:09:59 BoogieIcfgContainer [2018-10-27 06:09:59,088 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-10-27 06:09:59,089 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-10-27 06:09:59,089 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-10-27 06:09:59,090 INFO L276 PluginConnector]: Witness Printer initialized [2018-10-27 06:09:59,090 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 06:09:48" (3/4) ... [2018-10-27 06:09:59,093 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-10-27 06:09:59,159 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_daeb9472-58ca-4106-9d30-df1a4074ed6c/bin-2019/uautomizer/witness.graphml [2018-10-27 06:09:59,159 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-10-27 06:09:59,160 INFO L168 Benchmark]: Toolchain (without parser) took 11850.84 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 175.6 MB). Free memory was 954.8 MB in the beginning and 1.0 GB in the end (delta: -53.7 MB). Peak memory consumption was 122.0 MB. Max. memory is 11.5 GB. [2018-10-27 06:09:59,161 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-27 06:09:59,161 INFO L168 Benchmark]: CACSL2BoogieTranslator took 285.51 ms. Allocated memory is still 1.0 GB. Free memory was 954.8 MB in the beginning and 940.2 MB in the end (delta: 14.7 MB). Peak memory consumption was 14.7 MB. Max. memory is 11.5 GB. [2018-10-27 06:09:59,162 INFO L168 Benchmark]: Boogie Procedure Inliner took 68.92 ms. Allocated memory is still 1.0 GB. Free memory was 940.2 MB in the beginning and 937.5 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-10-27 06:09:59,162 INFO L168 Benchmark]: Boogie Preprocessor took 62.05 ms. Allocated memory is still 1.0 GB. Free memory was 937.5 MB in the beginning and 934.8 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-10-27 06:09:59,162 INFO L168 Benchmark]: RCFGBuilder took 1145.56 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 137.9 MB). Free memory was 934.8 MB in the beginning and 1.1 GB in the end (delta: -166.7 MB). Peak memory consumption was 15.9 MB. Max. memory is 11.5 GB. [2018-10-27 06:09:59,163 INFO L168 Benchmark]: BuchiAutomizer took 10212.96 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 37.7 MB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 88.3 MB). Peak memory consumption was 126.1 MB. Max. memory is 11.5 GB. [2018-10-27 06:09:59,163 INFO L168 Benchmark]: Witness Printer took 70.27 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 4.7 MB). Peak memory consumption was 4.7 MB. Max. memory is 11.5 GB. [2018-10-27 06:09:59,170 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 285.51 ms. Allocated memory is still 1.0 GB. Free memory was 954.8 MB in the beginning and 940.2 MB in the end (delta: 14.7 MB). Peak memory consumption was 14.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 68.92 ms. Allocated memory is still 1.0 GB. Free memory was 940.2 MB in the beginning and 937.5 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 62.05 ms. Allocated memory is still 1.0 GB. Free memory was 937.5 MB in the beginning and 934.8 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1145.56 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 137.9 MB). Free memory was 934.8 MB in the beginning and 1.1 GB in the end (delta: -166.7 MB). Peak memory consumption was 15.9 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 10212.96 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 37.7 MB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 88.3 MB). Peak memory consumption was 126.1 MB. Max. memory is 11.5 GB. * Witness Printer took 70.27 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 4.7 MB). Peak memory consumption was 4.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 14 terminating modules (13 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * q_read_ev + 1 and consists of 3 locations. 13 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1643 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 10.1s and 14 iterations. TraceHistogramMax:2. Analysis of lassos took 7.3s. Construction of modules took 1.2s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 3. Minimization of det autom 8. Minimization of nondet autom 6. Automata minimization 0.3s AutomataMinimizationTime, 14 MinimizatonAttempts, 2011 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had 1643 states and ocurred in iteration 13. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 2045 SDtfs, 1976 SDslu, 2471 SDs, 0 SdLazy, 205 SolverSat, 67 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.2s Time LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc1 concLT1 SILN1 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital80 mio100 ax100 hnf100 lsp13 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 14ms VariablesStem: 0 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 3 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 329]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {p_last_write=0, c_dr_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@84a99c1=0, c_dr_pc=0, a_t=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4acee8f1=0, \result=0, \result=0, c_num_read=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5c891236=0, c_dr_st=0, kernel_st=1, q_read_ev=2, p_dw_i=1, tmp___1=1, q_req_up=0, tmp___0=0, q_write_ev=2, __retres1=1, p_dw_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2f27052c=0, q_free=1, __retres1=0, p_dw_st=0, \result=0, q_ev=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@e43677b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@71c23fdf=0, c_last_read=0, tmp___0=0, __retres1=0, tmp=0, p_num_write=0, q_buf_0=0, __retres1=0, tmp=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 329]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int q_buf_0 ; [L16] int q_free ; [L17] int q_read_ev ; [L18] int q_write_ev ; [L19] int q_req_up ; [L20] int q_ev ; [L41] int p_num_write ; [L42] int p_last_write ; [L43] int p_dw_st ; [L44] int p_dw_pc ; [L45] int p_dw_i ; [L46] int c_num_read ; [L47] int c_last_read ; [L48] int c_dr_st ; [L49] int c_dr_pc ; [L50] int c_dr_i ; [L154] static int a_t ; [L456] int __retres1 ; [L460] CALL init_model() [L442] q_free = 1 [L443] q_write_ev = 2 [L444] q_read_ev = q_write_ev [L445] p_num_write = 0 [L446] p_dw_pc = 0 [L447] p_dw_i = 1 [L448] c_num_read = 0 [L449] c_dr_pc = 0 [L450] RET c_dr_i = 1 [L460] init_model() [L461] CALL start_simulation() [L396] int kernel_st ; [L397] int tmp ; [L401] kernel_st = 0 [L402] CALL update_channels() [L212] COND FALSE, RET !((int )q_req_up == 1) [L402] update_channels() [L403] CALL init_threads() [L227] COND TRUE (int )p_dw_i == 1 [L228] p_dw_st = 0 [L232] COND TRUE (int )c_dr_i == 1 [L233] RET c_dr_st = 0 [L403] init_threads() [L404] CALL fire_delta_events() [L265] COND FALSE !((int )q_read_ev == 0) [L270] COND FALSE, RET !((int )q_write_ev == 0) [L404] fire_delta_events() [L405] CALL activate_threads() [L298] int tmp ; [L299] int tmp___0 ; [L303] CALL, EXPR is_do_write_p_triggered() [L52] int __retres1 ; [L55] COND FALSE !((int )p_dw_pc == 1) [L65] __retres1 = 0 [L67] RET return (__retres1); [L303] EXPR is_do_write_p_triggered() [L303] tmp = is_do_write_p_triggered() [L305] COND FALSE !(\read(tmp)) [L311] CALL, EXPR is_do_read_c_triggered() [L71] int __retres1 ; [L74] COND FALSE !((int )c_dr_pc == 1) [L84] __retres1 = 0 [L86] RET return (__retres1); [L311] EXPR is_do_read_c_triggered() [L311] tmp___0 = is_do_read_c_triggered() [L313] COND FALSE, RET !(\read(tmp___0)) [L405] activate_threads() [L406] CALL reset_delta_events() [L283] COND FALSE !((int )q_read_ev == 1) [L288] COND FALSE, RET !((int )q_write_ev == 1) [L406] reset_delta_events() [L409] COND TRUE 1 [L412] kernel_st = 1 [L413] CALL eval() [L323] int tmp ; [L324] int tmp___0 ; [L325] int tmp___1 ; Loop: [L329] COND TRUE 1 [L332] CALL, EXPR exists_runnable_thread() [L242] int __retres1 ; [L245] COND TRUE (int )p_dw_st == 0 [L246] __retres1 = 1 [L258] RET return (__retres1); [L332] EXPR exists_runnable_thread() [L332] tmp___1 = exists_runnable_thread() [L334] COND TRUE \read(tmp___1) [L339] COND TRUE (int )p_dw_st == 0 [L341] tmp = __VERIFIER_nondet_int() [L343] COND FALSE !(\read(tmp)) [L354] COND TRUE (int )c_dr_st == 0 [L356] tmp___0 = __VERIFIER_nondet_int() [L358] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...