./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.02_true-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.02_true-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e3d58fadf54daed6107b58402b79d250d23d0301 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-10-27 06:12:16,681 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-27 06:12:16,682 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-27 06:12:16,692 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-27 06:12:16,692 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-27 06:12:16,693 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-27 06:12:16,695 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-27 06:12:16,696 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-27 06:12:16,697 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-27 06:12:16,698 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-27 06:12:16,699 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-27 06:12:16,699 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-27 06:12:16,700 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-27 06:12:16,701 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-27 06:12:16,703 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-27 06:12:16,703 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-27 06:12:16,704 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-27 06:12:16,705 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-27 06:12:16,707 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-27 06:12:16,709 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-27 06:12:16,710 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-27 06:12:16,711 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-27 06:12:16,713 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-27 06:12:16,713 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-27 06:12:16,713 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-27 06:12:16,715 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-27 06:12:16,716 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-27 06:12:16,716 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-27 06:12:16,717 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-27 06:12:16,717 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-27 06:12:16,718 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-27 06:12:16,719 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-27 06:12:16,719 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-27 06:12:16,719 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-27 06:12:16,720 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-27 06:12:16,720 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-27 06:12:16,721 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-10-27 06:12:16,733 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-27 06:12:16,734 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-27 06:12:16,735 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-10-27 06:12:16,735 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-10-27 06:12:16,735 INFO L133 SettingsManager]: * Use SBE=true [2018-10-27 06:12:16,735 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-10-27 06:12:16,735 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-10-27 06:12:16,735 INFO L133 SettingsManager]: * Use old map elimination=false [2018-10-27 06:12:16,736 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-10-27 06:12:16,736 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-10-27 06:12:16,736 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-10-27 06:12:16,736 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-27 06:12:16,736 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-27 06:12:16,736 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-10-27 06:12:16,737 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-27 06:12:16,737 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-27 06:12:16,737 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-27 06:12:16,737 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-10-27 06:12:16,737 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-10-27 06:12:16,737 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-10-27 06:12:16,739 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-27 06:12:16,739 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-27 06:12:16,739 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-10-27 06:12:16,739 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-10-27 06:12:16,740 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-27 06:12:16,740 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-10-27 06:12:16,740 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-10-27 06:12:16,740 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-27 06:12:16,740 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-10-27 06:12:16,740 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-10-27 06:12:16,741 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-10-27 06:12:16,741 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e3d58fadf54daed6107b58402b79d250d23d0301 [2018-10-27 06:12:16,768 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-27 06:12:16,778 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-27 06:12:16,781 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-27 06:12:16,782 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-27 06:12:16,783 INFO L276 PluginConnector]: CDTParser initialized [2018-10-27 06:12:16,783 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.02_true-unreach-call_false-termination.cil.c [2018-10-27 06:12:16,829 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer/data/770d70269/302684f58e414b5b85b753a80631c936/FLAGc1e64b30d [2018-10-27 06:12:17,233 INFO L298 CDTParser]: Found 1 translation units. [2018-10-27 06:12:17,234 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/sv-benchmarks/c/systemc/token_ring.02_true-unreach-call_false-termination.cil.c [2018-10-27 06:12:17,244 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer/data/770d70269/302684f58e414b5b85b753a80631c936/FLAGc1e64b30d [2018-10-27 06:12:17,255 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer/data/770d70269/302684f58e414b5b85b753a80631c936 [2018-10-27 06:12:17,258 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-27 06:12:17,259 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-27 06:12:17,259 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-27 06:12:17,260 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-27 06:12:17,263 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-27 06:12:17,264 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.10 06:12:17" (1/1) ... [2018-10-27 06:12:17,266 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a8c40cb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17, skipping insertion in model container [2018-10-27 06:12:17,267 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.10 06:12:17" (1/1) ... [2018-10-27 06:12:17,276 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-27 06:12:17,309 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-27 06:12:17,469 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-27 06:12:17,473 INFO L189 MainTranslator]: Completed pre-run [2018-10-27 06:12:17,509 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-27 06:12:17,525 INFO L193 MainTranslator]: Completed translation [2018-10-27 06:12:17,526 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17 WrapperNode [2018-10-27 06:12:17,526 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-27 06:12:17,526 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-27 06:12:17,527 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-27 06:12:17,527 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-27 06:12:17,536 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17" (1/1) ... [2018-10-27 06:12:17,542 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17" (1/1) ... [2018-10-27 06:12:17,573 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-27 06:12:17,573 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-27 06:12:17,574 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-27 06:12:17,574 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-27 06:12:17,582 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17" (1/1) ... [2018-10-27 06:12:17,582 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17" (1/1) ... [2018-10-27 06:12:17,585 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17" (1/1) ... [2018-10-27 06:12:17,586 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17" (1/1) ... [2018-10-27 06:12:17,592 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17" (1/1) ... [2018-10-27 06:12:17,668 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17" (1/1) ... [2018-10-27 06:12:17,670 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17" (1/1) ... [2018-10-27 06:12:17,674 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-27 06:12:17,674 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-27 06:12:17,674 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-27 06:12:17,674 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-27 06:12:17,675 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-10-27 06:12:17,755 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-27 06:12:17,756 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-27 06:12:18,900 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-27 06:12:18,900 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 06:12:18 BoogieIcfgContainer [2018-10-27 06:12:18,900 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-27 06:12:18,901 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-10-27 06:12:18,901 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-10-27 06:12:18,913 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-10-27 06:12:18,914 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-10-27 06:12:18,914 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 27.10 06:12:17" (1/3) ... [2018-10-27 06:12:18,915 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@d135e82 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 27.10 06:12:18, skipping insertion in model container [2018-10-27 06:12:18,915 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-10-27 06:12:18,915 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:12:17" (2/3) ... [2018-10-27 06:12:18,916 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@d135e82 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 27.10 06:12:18, skipping insertion in model container [2018-10-27 06:12:18,916 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-10-27 06:12:18,916 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 06:12:18" (3/3) ... [2018-10-27 06:12:18,918 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.02_true-unreach-call_false-termination.cil.c [2018-10-27 06:12:18,980 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-10-27 06:12:18,982 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-10-27 06:12:18,982 INFO L375 BuchiCegarLoop]: Hoare is false [2018-10-27 06:12:18,982 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-10-27 06:12:18,982 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-10-27 06:12:18,983 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-10-27 06:12:18,983 INFO L379 BuchiCegarLoop]: Difference is false [2018-10-27 06:12:18,983 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-10-27 06:12:18,984 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-10-27 06:12:19,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 236 states. [2018-10-27 06:12:19,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 189 [2018-10-27 06:12:19,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:19,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:19,060 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:19,060 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:19,060 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-10-27 06:12:19,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 236 states. [2018-10-27 06:12:19,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 189 [2018-10-27 06:12:19,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:19,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:19,071 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:19,071 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:19,079 INFO L793 eck$LassoCheckResult]: Stem: 56#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 9#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 78#L506true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 90#L214true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 136#L221true assume !(~m_i~0 == 1);~m_st~0 := 2; 134#L221-2true assume ~t1_i~0 == 1;~t1_st~0 := 0; 47#L226-1true assume !(~t2_i~0 == 1);~t2_st~0 := 2; 55#L231-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27#L334true assume !(~M_E~0 == 0); 29#L334-2true assume !(~T1_E~0 == 0); 38#L339-1true assume !(~T2_E~0 == 0); 164#L344-1true assume ~E_M~0 == 0;~E_M~0 := 1; 196#L349-1true assume !(~E_1~0 == 0); 102#L354-1true assume !(~E_2~0 == 0); 130#L359-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 218#L156true assume ~m_pc~0 == 1; 153#L157true assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 219#L167true is_master_triggered_#res := is_master_triggered_~__retres1~0; 154#L168true activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 226#L415true assume !(activate_threads_~tmp~1 != 0); 192#L415-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3#L175true assume !(~t1_pc~0 == 1); 20#L175-2true is_transmit1_triggered_~__retres1~1 := 0; 4#L186true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 54#L187true activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 92#L423true assume !(activate_threads_~tmp___0~0 != 0); 94#L423-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 129#L194true assume ~t2_pc~0 == 1; 202#L195true assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 131#L205true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 204#L206true activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 119#L431true assume !(activate_threads_~tmp___1~0 != 0); 98#L431-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37#L372true assume !(~M_E~0 == 1); 39#L372-2true assume ~T1_E~0 == 1;~T1_E~0 := 2; 163#L377-1true assume !(~T2_E~0 == 1); 193#L382-1true assume !(~E_M~0 == 1); 99#L387-1true assume !(~E_1~0 == 1); 127#L392-1true assume !(~E_2~0 == 1); 140#L397-1true assume { :end_inline_reset_delta_events } true; 32#L543-3true [2018-10-27 06:12:19,080 INFO L795 eck$LassoCheckResult]: Loop: 32#L543-3true assume true; 31#L543-1true assume !false; 8#L544true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 141#L309true assume !true; 79#L324true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 87#L214-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 30#L334-3true assume ~M_E~0 == 0;~M_E~0 := 1; 26#L334-5true assume ~T1_E~0 == 0;~T1_E~0 := 1; 41#L339-3true assume !(~T2_E~0 == 0); 166#L344-3true assume ~E_M~0 == 0;~E_M~0 := 1; 206#L349-3true assume ~E_1~0 == 0;~E_1~0 := 1; 112#L354-3true assume ~E_2~0 == 0;~E_2~0 := 1; 120#L359-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 177#L156-12true assume ~m_pc~0 == 1; 160#L157-4true assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 236#L167-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 161#L168-4true activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 171#L415-12true assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 172#L415-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 93#L175-12true assume !(~t1_pc~0 == 1); 91#L175-14true is_transmit1_triggered_~__retres1~1 := 0; 15#L186-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 62#L187-4true activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 76#L423-12true assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 69#L423-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 115#L194-12true assume !(~t2_pc~0 == 1); 228#L194-14true is_transmit2_triggered_~__retres1~2 := 0; 110#L205-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 185#L206-4true activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 212#L431-12true assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 220#L431-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40#L372-3true assume !(~M_E~0 == 1); 42#L372-5true assume ~T1_E~0 == 1;~T1_E~0 := 2; 165#L377-3true assume ~T2_E~0 == 1;~T2_E~0 := 2; 201#L382-3true assume ~E_M~0 == 1;~E_M~0 := 2; 108#L387-3true assume ~E_1~0 == 1;~E_1~0 := 2; 133#L392-3true assume ~E_2~0 == 1;~E_2~0 := 2; 142#L397-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 223#L244-1true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 208#L261-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 33#L262-1true start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 144#L562true assume !(start_simulation_~tmp~3 == 0); 145#L562-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 221#L244-2true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 203#L261-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 43#L262-2true stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 77#L517true assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 135#L524true stop_simulation_#res := stop_simulation_~__retres2~0; 215#L525true start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 183#L575true assume !(start_simulation_~tmp___0~1 != 0); 32#L543-3true [2018-10-27 06:12:19,085 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:19,085 INFO L82 PathProgramCache]: Analyzing trace with hash 332551043, now seen corresponding path program 1 times [2018-10-27 06:12:19,087 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:19,088 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:19,132 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,133 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:19,133 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:19,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:19,270 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:19,270 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:12:19,277 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:12:19,277 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:19,277 INFO L82 PathProgramCache]: Analyzing trace with hash 294868141, now seen corresponding path program 1 times [2018-10-27 06:12:19,277 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:19,277 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:19,278 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,278 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:19,278 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:19,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:19,296 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:19,297 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:12:19,299 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:12:19,312 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:12:19,313 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:12:19,315 INFO L87 Difference]: Start difference. First operand 236 states. Second operand 3 states. [2018-10-27 06:12:19,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:19,380 INFO L93 Difference]: Finished difference Result 235 states and 345 transitions. [2018-10-27 06:12:19,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:12:19,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 235 states and 345 transitions. [2018-10-27 06:12:19,393 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2018-10-27 06:12:19,403 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 235 states to 230 states and 340 transitions. [2018-10-27 06:12:19,404 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 230 [2018-10-27 06:12:19,405 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 230 [2018-10-27 06:12:19,407 INFO L73 IsDeterministic]: Start isDeterministic. Operand 230 states and 340 transitions. [2018-10-27 06:12:19,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:19,408 INFO L705 BuchiCegarLoop]: Abstraction has 230 states and 340 transitions. [2018-10-27 06:12:19,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states and 340 transitions. [2018-10-27 06:12:19,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 230. [2018-10-27 06:12:19,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-10-27 06:12:19,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 340 transitions. [2018-10-27 06:12:19,442 INFO L728 BuchiCegarLoop]: Abstraction has 230 states and 340 transitions. [2018-10-27 06:12:19,442 INFO L608 BuchiCegarLoop]: Abstraction has 230 states and 340 transitions. [2018-10-27 06:12:19,444 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-10-27 06:12:19,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230 states and 340 transitions. [2018-10-27 06:12:19,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2018-10-27 06:12:19,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:19,446 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:19,448 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:19,448 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:19,448 INFO L793 eck$LassoCheckResult]: Stem: 560#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 493#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 494#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 583#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 594#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 648#L221-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 553#L226-1 assume !(~t2_i~0 == 1);~t2_st~0 := 2; 554#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 524#L334 assume !(~M_E~0 == 0); 525#L334-2 assume !(~T1_E~0 == 0); 527#L339-1 assume !(~T2_E~0 == 0); 540#L344-1 assume ~E_M~0 == 0;~E_M~0 := 1; 687#L349-1 assume !(~E_1~0 == 0); 608#L354-1 assume !(~E_2~0 == 0); 609#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 643#L156 assume ~m_pc~0 == 1; 670#L157 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 671#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 673#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 674#L415 assume !(activate_threads_~tmp~1 != 0); 703#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 480#L175 assume !(~t1_pc~0 == 1); 481#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 483#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 484#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 559#L423 assume !(activate_threads_~tmp___0~0 != 0); 595#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 597#L194 assume ~t2_pc~0 == 1; 642#L195 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 638#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 644#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 631#L431 assume !(activate_threads_~tmp___1~0 != 0); 602#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 538#L372 assume !(~M_E~0 == 1); 539#L372-2 assume ~T1_E~0 == 1;~T1_E~0 := 2; 541#L377-1 assume !(~T2_E~0 == 1); 686#L382-1 assume !(~E_M~0 == 1); 603#L387-1 assume !(~E_1~0 == 1); 604#L392-1 assume !(~E_2~0 == 1); 640#L397-1 assume { :end_inline_reset_delta_events } true; 530#L543-3 [2018-10-27 06:12:19,448 INFO L795 eck$LassoCheckResult]: Loop: 530#L543-3 assume true; 529#L543-1 assume !false; 491#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 492#L309 assume true; 645#L271-1 assume !false; 646#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 697#L244 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 490#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 533#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 534#L276 assume !(eval_~tmp~0 != 0); 584#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 585#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 528#L334-3 assume ~M_E~0 == 0;~M_E~0 := 1; 522#L334-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 523#L339-3 assume !(~T2_E~0 == 0); 544#L344-3 assume ~E_M~0 == 0;~E_M~0 := 1; 689#L349-3 assume ~E_1~0 == 0;~E_1~0 := 1; 623#L354-3 assume ~E_2~0 == 0;~E_2~0 := 1; 624#L359-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 632#L156-12 assume ~m_pc~0 == 1; 680#L157-4 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 681#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 683#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 684#L415-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 695#L415-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 596#L175-12 assume ~t1_pc~0 == 1; 564#L176-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 503#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 504#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 566#L423-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 575#L423-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 576#L194-12 assume ~t2_pc~0 == 1; 625#L195-4 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 619#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 620#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 699#L431-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 707#L431-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 542#L372-3 assume !(~M_E~0 == 1); 543#L372-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 545#L377-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 688#L382-3 assume ~E_M~0 == 1;~E_M~0 := 2; 616#L387-3 assume ~E_1~0 == 1;~E_1~0 := 2; 617#L392-3 assume ~E_2~0 == 1;~E_2~0 := 2; 647#L397-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 651#L244-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 488#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 531#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 532#L562 assume !(start_simulation_~tmp~3 == 0); 593#L562-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 652#L244-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 486#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 546#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 547#L517 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 582#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 649#L525 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 698#L575 assume !(start_simulation_~tmp___0~1 != 0); 530#L543-3 [2018-10-27 06:12:19,449 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:19,449 INFO L82 PathProgramCache]: Analyzing trace with hash 726917829, now seen corresponding path program 1 times [2018-10-27 06:12:19,449 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:19,449 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:19,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,456 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:19,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:19,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:19,504 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:19,504 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:12:19,505 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:12:19,505 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:19,505 INFO L82 PathProgramCache]: Analyzing trace with hash -1818182591, now seen corresponding path program 1 times [2018-10-27 06:12:19,505 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:19,505 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:19,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,507 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:19,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:19,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:19,605 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:19,605 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:12:19,606 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:12:19,606 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:12:19,606 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:12:19,606 INFO L87 Difference]: Start difference. First operand 230 states and 340 transitions. cyclomatic complexity: 111 Second operand 3 states. [2018-10-27 06:12:19,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:19,633 INFO L93 Difference]: Finished difference Result 230 states and 339 transitions. [2018-10-27 06:12:19,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:12:19,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 339 transitions. [2018-10-27 06:12:19,636 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2018-10-27 06:12:19,638 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 230 states and 339 transitions. [2018-10-27 06:12:19,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 230 [2018-10-27 06:12:19,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 230 [2018-10-27 06:12:19,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 230 states and 339 transitions. [2018-10-27 06:12:19,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:19,641 INFO L705 BuchiCegarLoop]: Abstraction has 230 states and 339 transitions. [2018-10-27 06:12:19,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states and 339 transitions. [2018-10-27 06:12:19,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 230. [2018-10-27 06:12:19,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-10-27 06:12:19,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 339 transitions. [2018-10-27 06:12:19,651 INFO L728 BuchiCegarLoop]: Abstraction has 230 states and 339 transitions. [2018-10-27 06:12:19,651 INFO L608 BuchiCegarLoop]: Abstraction has 230 states and 339 transitions. [2018-10-27 06:12:19,651 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-10-27 06:12:19,652 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230 states and 339 transitions. [2018-10-27 06:12:19,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2018-10-27 06:12:19,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:19,654 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:19,656 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:19,657 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:19,657 INFO L793 eck$LassoCheckResult]: Stem: 1027#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 960#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 961#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1050#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1061#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 1115#L221-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 1020#L226-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 1021#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 991#L334 assume !(~M_E~0 == 0); 992#L334-2 assume !(~T1_E~0 == 0); 994#L339-1 assume !(~T2_E~0 == 0); 1007#L344-1 assume ~E_M~0 == 0;~E_M~0 := 1; 1154#L349-1 assume !(~E_1~0 == 0); 1075#L354-1 assume !(~E_2~0 == 0); 1076#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1110#L156 assume ~m_pc~0 == 1; 1137#L157 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 1138#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1140#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1141#L415 assume !(activate_threads_~tmp~1 != 0); 1170#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 947#L175 assume !(~t1_pc~0 == 1); 948#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 950#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 951#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1026#L423 assume !(activate_threads_~tmp___0~0 != 0); 1062#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1064#L194 assume ~t2_pc~0 == 1; 1109#L195 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1105#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1111#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1098#L431 assume !(activate_threads_~tmp___1~0 != 0); 1069#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1005#L372 assume !(~M_E~0 == 1); 1006#L372-2 assume ~T1_E~0 == 1;~T1_E~0 := 2; 1008#L377-1 assume !(~T2_E~0 == 1); 1153#L382-1 assume !(~E_M~0 == 1); 1070#L387-1 assume !(~E_1~0 == 1); 1071#L392-1 assume !(~E_2~0 == 1); 1107#L397-1 assume { :end_inline_reset_delta_events } true; 997#L543-3 [2018-10-27 06:12:19,657 INFO L795 eck$LassoCheckResult]: Loop: 997#L543-3 assume true; 996#L543-1 assume !false; 958#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 959#L309 assume true; 1112#L271-1 assume !false; 1113#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1164#L244 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 957#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1000#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1001#L276 assume !(eval_~tmp~0 != 0); 1051#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1052#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 995#L334-3 assume ~M_E~0 == 0;~M_E~0 := 1; 989#L334-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 990#L339-3 assume !(~T2_E~0 == 0); 1011#L344-3 assume ~E_M~0 == 0;~E_M~0 := 1; 1156#L349-3 assume ~E_1~0 == 0;~E_1~0 := 1; 1090#L354-3 assume ~E_2~0 == 0;~E_2~0 := 1; 1091#L359-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1099#L156-12 assume ~m_pc~0 == 1; 1147#L157-4 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 1148#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1150#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1151#L415-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1162#L415-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1063#L175-12 assume ~t1_pc~0 == 1; 1031#L176-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 970#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 971#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1033#L423-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 1042#L423-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1043#L194-12 assume ~t2_pc~0 == 1; 1092#L195-4 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1086#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1087#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1166#L431-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 1174#L431-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1009#L372-3 assume !(~M_E~0 == 1); 1010#L372-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 1012#L377-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 1155#L382-3 assume ~E_M~0 == 1;~E_M~0 := 2; 1083#L387-3 assume ~E_1~0 == 1;~E_1~0 := 2; 1084#L392-3 assume ~E_2~0 == 1;~E_2~0 := 2; 1114#L397-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1118#L244-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 955#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 998#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 999#L562 assume !(start_simulation_~tmp~3 == 0); 1060#L562-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1119#L244-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 953#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1013#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 1014#L517 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 1049#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 1116#L525 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1165#L575 assume !(start_simulation_~tmp___0~1 != 0); 997#L543-3 [2018-10-27 06:12:19,658 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:19,658 INFO L82 PathProgramCache]: Analyzing trace with hash -1324066169, now seen corresponding path program 1 times [2018-10-27 06:12:19,658 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:19,658 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:19,659 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,659 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:19,659 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:19,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:19,724 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:19,724 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:12:19,725 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:12:19,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:19,725 INFO L82 PathProgramCache]: Analyzing trace with hash -1818182591, now seen corresponding path program 2 times [2018-10-27 06:12:19,725 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:19,725 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:19,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:19,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:19,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:19,789 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:19,789 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:12:19,790 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:12:19,790 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:12:19,790 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:12:19,790 INFO L87 Difference]: Start difference. First operand 230 states and 339 transitions. cyclomatic complexity: 110 Second operand 3 states. [2018-10-27 06:12:19,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:19,883 INFO L93 Difference]: Finished difference Result 230 states and 329 transitions. [2018-10-27 06:12:19,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:12:19,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 329 transitions. [2018-10-27 06:12:19,885 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2018-10-27 06:12:19,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 230 states and 329 transitions. [2018-10-27 06:12:19,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 230 [2018-10-27 06:12:19,888 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 230 [2018-10-27 06:12:19,888 INFO L73 IsDeterministic]: Start isDeterministic. Operand 230 states and 329 transitions. [2018-10-27 06:12:19,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:19,889 INFO L705 BuchiCegarLoop]: Abstraction has 230 states and 329 transitions. [2018-10-27 06:12:19,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states and 329 transitions. [2018-10-27 06:12:19,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 230. [2018-10-27 06:12:19,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-10-27 06:12:19,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 329 transitions. [2018-10-27 06:12:19,898 INFO L728 BuchiCegarLoop]: Abstraction has 230 states and 329 transitions. [2018-10-27 06:12:19,898 INFO L608 BuchiCegarLoop]: Abstraction has 230 states and 329 transitions. [2018-10-27 06:12:19,899 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-10-27 06:12:19,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230 states and 329 transitions. [2018-10-27 06:12:19,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2018-10-27 06:12:19,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:19,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:19,901 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:19,902 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:19,902 INFO L793 eck$LassoCheckResult]: Stem: 1494#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1427#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1428#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1517#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1528#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 1582#L221-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 1487#L226-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 1488#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1458#L334 assume !(~M_E~0 == 0); 1459#L334-2 assume !(~T1_E~0 == 0); 1461#L339-1 assume !(~T2_E~0 == 0); 1474#L344-1 assume !(~E_M~0 == 0); 1616#L349-1 assume !(~E_1~0 == 0); 1542#L354-1 assume !(~E_2~0 == 0); 1543#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1577#L156 assume !(~m_pc~0 == 1); 1603#L156-2 is_master_triggered_~__retres1~0 := 0; 1639#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1604#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1605#L415 assume !(activate_threads_~tmp~1 != 0); 1634#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1414#L175 assume !(~t1_pc~0 == 1); 1415#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 1417#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1418#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1493#L423 assume !(activate_threads_~tmp___0~0 != 0); 1529#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1531#L194 assume ~t2_pc~0 == 1; 1576#L195 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1572#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1578#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1565#L431 assume !(activate_threads_~tmp___1~0 != 0); 1536#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1472#L372 assume !(~M_E~0 == 1); 1473#L372-2 assume ~T1_E~0 == 1;~T1_E~0 := 2; 1475#L377-1 assume !(~T2_E~0 == 1); 1615#L382-1 assume !(~E_M~0 == 1); 1537#L387-1 assume !(~E_1~0 == 1); 1538#L392-1 assume !(~E_2~0 == 1); 1574#L397-1 assume { :end_inline_reset_delta_events } true; 1464#L543-3 [2018-10-27 06:12:19,902 INFO L795 eck$LassoCheckResult]: Loop: 1464#L543-3 assume true; 1463#L543-1 assume !false; 1425#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1426#L309 assume true; 1579#L271-1 assume !false; 1580#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1626#L244 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 1424#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1467#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1468#L276 assume !(eval_~tmp~0 != 0); 1518#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1519#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1462#L334-3 assume ~M_E~0 == 0;~M_E~0 := 1; 1456#L334-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 1457#L339-3 assume !(~T2_E~0 == 0); 1478#L344-3 assume !(~E_M~0 == 0); 1618#L349-3 assume ~E_1~0 == 0;~E_1~0 := 1; 1557#L354-3 assume ~E_2~0 == 0;~E_2~0 := 1; 1558#L359-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1566#L156-12 assume !(~m_pc~0 == 1); 1611#L156-14 is_master_triggered_~__retres1~0 := 0; 1637#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1612#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1613#L415-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1624#L415-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1530#L175-12 assume ~t1_pc~0 == 1; 1498#L176-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 1437#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1438#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1500#L423-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 1509#L423-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1510#L194-12 assume ~t2_pc~0 == 1; 1559#L195-4 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1553#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1554#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1629#L431-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 1640#L431-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1476#L372-3 assume !(~M_E~0 == 1); 1477#L372-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 1479#L377-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 1617#L382-3 assume !(~E_M~0 == 1); 1550#L387-3 assume ~E_1~0 == 1;~E_1~0 := 2; 1551#L392-3 assume ~E_2~0 == 1;~E_2~0 := 2; 1581#L397-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1585#L244-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 1422#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1465#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 1466#L562 assume !(start_simulation_~tmp~3 == 0); 1527#L562-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1586#L244-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 1420#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1480#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 1481#L517 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 1516#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 1583#L525 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1628#L575 assume !(start_simulation_~tmp___0~1 != 0); 1464#L543-3 [2018-10-27 06:12:19,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:19,902 INFO L82 PathProgramCache]: Analyzing trace with hash -1995466806, now seen corresponding path program 1 times [2018-10-27 06:12:19,903 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:19,903 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:19,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,904 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:12:19,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:19,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:19,978 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:19,978 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:12:19,978 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:12:19,978 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:19,979 INFO L82 PathProgramCache]: Analyzing trace with hash -1290344254, now seen corresponding path program 1 times [2018-10-27 06:12:19,979 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:19,979 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:19,980 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,980 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:19,980 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:19,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:20,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:20,093 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:20,093 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:12:20,094 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:12:20,094 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:12:20,094 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:12:20,094 INFO L87 Difference]: Start difference. First operand 230 states and 329 transitions. cyclomatic complexity: 100 Second operand 3 states. [2018-10-27 06:12:20,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:20,359 INFO L93 Difference]: Finished difference Result 388 states and 547 transitions. [2018-10-27 06:12:20,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:12:20,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 388 states and 547 transitions. [2018-10-27 06:12:20,366 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 344 [2018-10-27 06:12:20,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 388 states to 388 states and 547 transitions. [2018-10-27 06:12:20,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 388 [2018-10-27 06:12:20,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 388 [2018-10-27 06:12:20,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 388 states and 547 transitions. [2018-10-27 06:12:20,374 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:20,374 INFO L705 BuchiCegarLoop]: Abstraction has 388 states and 547 transitions. [2018-10-27 06:12:20,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 388 states and 547 transitions. [2018-10-27 06:12:20,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 388 to 385. [2018-10-27 06:12:20,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 385 states. [2018-10-27 06:12:20,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 385 states to 385 states and 544 transitions. [2018-10-27 06:12:20,388 INFO L728 BuchiCegarLoop]: Abstraction has 385 states and 544 transitions. [2018-10-27 06:12:20,388 INFO L608 BuchiCegarLoop]: Abstraction has 385 states and 544 transitions. [2018-10-27 06:12:20,388 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-10-27 06:12:20,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 385 states and 544 transitions. [2018-10-27 06:12:20,390 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 341 [2018-10-27 06:12:20,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:20,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:20,392 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:20,392 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:20,392 INFO L793 eck$LassoCheckResult]: Stem: 2120#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2053#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2146#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2157#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 2209#L221-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 2112#L226-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 2113#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2083#L334 assume !(~M_E~0 == 0); 2084#L334-2 assume !(~T1_E~0 == 0); 2086#L339-1 assume !(~T2_E~0 == 0); 2099#L344-1 assume !(~E_M~0 == 0); 2247#L349-1 assume !(~E_1~0 == 0); 2171#L354-1 assume !(~E_2~0 == 0); 2172#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2204#L156 assume !(~m_pc~0 == 1); 2234#L156-2 is_master_triggered_~__retres1~0 := 0; 2280#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2235#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2236#L415 assume !(activate_threads_~tmp~1 != 0); 2271#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2039#L175 assume !(~t1_pc~0 == 1); 2040#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 2042#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2043#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2119#L423 assume !(activate_threads_~tmp___0~0 != 0); 2158#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2160#L194 assume !(~t2_pc~0 == 1); 2199#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 2200#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2205#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2193#L431 assume !(activate_threads_~tmp___1~0 != 0); 2165#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2097#L372 assume !(~M_E~0 == 1); 2098#L372-2 assume ~T1_E~0 == 1;~T1_E~0 := 2; 2100#L377-1 assume !(~T2_E~0 == 1); 2246#L382-1 assume !(~E_M~0 == 1); 2166#L387-1 assume !(~E_1~0 == 1); 2167#L392-1 assume !(~E_2~0 == 1); 2202#L397-1 assume { :end_inline_reset_delta_events } true; 2213#L543-3 [2018-10-27 06:12:20,392 INFO L795 eck$LassoCheckResult]: Loop: 2213#L543-3 assume true; 2363#L543-1 assume !false; 2360#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2334#L309 assume true; 2357#L271-1 assume !false; 2355#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2351#L244 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 2348#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2345#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2212#L276 assume !(eval_~tmp~0 != 0); 2147#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2148#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2087#L334-3 assume ~M_E~0 == 0;~M_E~0 := 1; 2081#L334-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 2082#L339-3 assume !(~T2_E~0 == 0); 2103#L344-3 assume !(~E_M~0 == 0); 2249#L349-3 assume ~E_1~0 == 0;~E_1~0 := 1; 2186#L354-3 assume ~E_2~0 == 0;~E_2~0 := 1; 2187#L359-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2194#L156-12 assume !(~m_pc~0 == 1); 2242#L156-14 is_master_triggered_~__retres1~0 := 0; 2278#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2243#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2244#L415-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 2256#L415-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2159#L175-12 assume ~t1_pc~0 == 1; 2124#L176-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 2062#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2063#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2126#L423-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 2136#L423-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2137#L194-12 assume !(~t2_pc~0 == 1); 2188#L194-14 is_transmit2_triggered_~__retres1~2 := 0; 2397#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2395#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2393#L431-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 2391#L431-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2389#L372-3 assume !(~M_E~0 == 1); 2387#L372-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 2385#L377-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 2383#L382-3 assume !(~E_M~0 == 1); 2381#L387-3 assume ~E_1~0 == 1;~E_1~0 := 2; 2380#L392-3 assume ~E_2~0 == 1;~E_2~0 := 2; 2376#L397-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2372#L244-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 2369#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2367#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 2365#L562 assume !(start_simulation_~tmp~3 == 0); 2156#L562-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2217#L244-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 2045#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2105#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 2106#L517 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 2370#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 2368#L525 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 2366#L575 assume !(start_simulation_~tmp___0~1 != 0); 2213#L543-3 [2018-10-27 06:12:20,393 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:20,393 INFO L82 PathProgramCache]: Analyzing trace with hash 1020175755, now seen corresponding path program 1 times [2018-10-27 06:12:20,393 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:20,393 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:20,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:20,394 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:20,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:20,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:20,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:20,452 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:20,452 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:12:20,453 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:12:20,453 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:20,453 INFO L82 PathProgramCache]: Analyzing trace with hash 947019011, now seen corresponding path program 1 times [2018-10-27 06:12:20,453 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:20,453 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:20,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:20,454 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:20,454 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:20,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:20,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:20,538 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:20,539 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:12:20,539 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:12:20,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:12:20,539 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:12:20,539 INFO L87 Difference]: Start difference. First operand 385 states and 544 transitions. cyclomatic complexity: 161 Second operand 3 states. [2018-10-27 06:12:20,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:20,637 INFO L93 Difference]: Finished difference Result 385 states and 536 transitions. [2018-10-27 06:12:20,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:12:20,639 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 385 states and 536 transitions. [2018-10-27 06:12:20,641 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 341 [2018-10-27 06:12:20,644 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 385 states to 385 states and 536 transitions. [2018-10-27 06:12:20,644 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 385 [2018-10-27 06:12:20,645 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 385 [2018-10-27 06:12:20,645 INFO L73 IsDeterministic]: Start isDeterministic. Operand 385 states and 536 transitions. [2018-10-27 06:12:20,646 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:20,646 INFO L705 BuchiCegarLoop]: Abstraction has 385 states and 536 transitions. [2018-10-27 06:12:20,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 385 states and 536 transitions. [2018-10-27 06:12:20,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 385 to 385. [2018-10-27 06:12:20,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 385 states. [2018-10-27 06:12:20,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 385 states to 385 states and 536 transitions. [2018-10-27 06:12:20,657 INFO L728 BuchiCegarLoop]: Abstraction has 385 states and 536 transitions. [2018-10-27 06:12:20,658 INFO L608 BuchiCegarLoop]: Abstraction has 385 states and 536 transitions. [2018-10-27 06:12:20,658 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-10-27 06:12:20,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 385 states and 536 transitions. [2018-10-27 06:12:20,660 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 341 [2018-10-27 06:12:20,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:20,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:20,662 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:20,662 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:20,662 INFO L793 eck$LassoCheckResult]: Stem: 2897#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2829#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2830#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2921#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2932#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 2982#L221-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 2890#L226-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 2891#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2860#L334 assume !(~M_E~0 == 0); 2861#L334-2 assume !(~T1_E~0 == 0); 2864#L339-1 assume !(~T2_E~0 == 0); 2877#L344-1 assume !(~E_M~0 == 0); 3018#L349-1 assume !(~E_1~0 == 0); 2945#L354-1 assume !(~E_2~0 == 0); 2946#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2977#L156 assume !(~m_pc~0 == 1); 3005#L156-2 is_master_triggered_~__retres1~0 := 0; 3051#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3006#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3007#L415 assume !(activate_threads_~tmp~1 != 0); 3040#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2816#L175 assume !(~t1_pc~0 == 1); 2817#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 2819#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2820#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2896#L423 assume !(activate_threads_~tmp___0~0 != 0); 2933#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2935#L194 assume !(~t2_pc~0 == 1); 2972#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 2973#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2978#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2967#L431 assume !(activate_threads_~tmp___1~0 != 0); 2940#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2875#L372 assume !(~M_E~0 == 1); 2876#L372-2 assume !(~T1_E~0 == 1); 2878#L377-1 assume !(~T2_E~0 == 1); 3017#L382-1 assume !(~E_M~0 == 1); 2941#L387-1 assume !(~E_1~0 == 1); 2942#L392-1 assume !(~E_2~0 == 1); 2975#L397-1 assume { :end_inline_reset_delta_events } true; 2867#L543-3 [2018-10-27 06:12:20,662 INFO L795 eck$LassoCheckResult]: Loop: 2867#L543-3 assume true; 2866#L543-1 assume !false; 2827#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2828#L309 assume true; 2979#L271-1 assume !false; 2980#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3029#L244 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 2826#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2870#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2871#L276 assume !(eval_~tmp~0 != 0); 2985#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3200#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3199#L334-3 assume ~M_E~0 == 0;~M_E~0 := 1; 3198#L334-5 assume !(~T1_E~0 == 0); 3197#L339-3 assume !(~T2_E~0 == 0); 3196#L344-3 assume !(~E_M~0 == 0); 3195#L349-3 assume ~E_1~0 == 0;~E_1~0 := 1; 3194#L354-3 assume ~E_2~0 == 0;~E_2~0 := 1; 3193#L359-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3191#L156-12 assume !(~m_pc~0 == 1); 3190#L156-14 is_master_triggered_~__retres1~0 := 0; 3189#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3188#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3187#L415-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 3186#L415-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3185#L175-12 assume !(~t1_pc~0 == 1); 3184#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 3182#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3169#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3167#L423-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 2912#L423-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2913#L194-12 assume !(~t2_pc~0 == 1); 2962#L194-14 is_transmit2_triggered_~__retres1~2 := 0; 2956#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2957#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3035#L431-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 3052#L431-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2879#L372-3 assume !(~M_E~0 == 1); 2880#L372-5 assume !(~T1_E~0 == 1); 2882#L377-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 3019#L382-3 assume !(~E_M~0 == 1); 2953#L387-3 assume ~E_1~0 == 1;~E_1~0 := 2; 2954#L392-3 assume ~E_2~0 == 1;~E_2~0 := 2; 2981#L397-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2986#L244-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 2824#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2868#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 2869#L562 assume !(start_simulation_~tmp~3 == 0); 2931#L562-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2988#L244-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 2822#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2883#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 2884#L517 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 2920#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 2983#L525 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 3031#L575 assume !(start_simulation_~tmp___0~1 != 0); 2867#L543-3 [2018-10-27 06:12:20,663 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:20,663 INFO L82 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 1 times [2018-10-27 06:12:20,663 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:20,663 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:20,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:20,664 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:20,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:20,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:20,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:20,696 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:20,696 INFO L82 PathProgramCache]: Analyzing trace with hash 578977348, now seen corresponding path program 1 times [2018-10-27 06:12:20,697 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:20,697 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:20,697 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:20,698 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:20,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:20,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:20,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:20,764 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:20,765 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:12:20,765 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:12:20,765 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:12:20,765 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:12:20,766 INFO L87 Difference]: Start difference. First operand 385 states and 536 transitions. cyclomatic complexity: 153 Second operand 3 states. [2018-10-27 06:12:20,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:20,912 INFO L93 Difference]: Finished difference Result 467 states and 645 transitions. [2018-10-27 06:12:20,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:12:20,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 467 states and 645 transitions. [2018-10-27 06:12:20,916 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 396 [2018-10-27 06:12:20,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 467 states to 467 states and 645 transitions. [2018-10-27 06:12:20,920 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 467 [2018-10-27 06:12:20,921 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 467 [2018-10-27 06:12:20,922 INFO L73 IsDeterministic]: Start isDeterministic. Operand 467 states and 645 transitions. [2018-10-27 06:12:20,923 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:20,923 INFO L705 BuchiCegarLoop]: Abstraction has 467 states and 645 transitions. [2018-10-27 06:12:20,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 467 states and 645 transitions. [2018-10-27 06:12:20,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 467 to 467. [2018-10-27 06:12:20,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 467 states. [2018-10-27 06:12:20,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 467 states to 467 states and 645 transitions. [2018-10-27 06:12:20,939 INFO L728 BuchiCegarLoop]: Abstraction has 467 states and 645 transitions. [2018-10-27 06:12:20,939 INFO L608 BuchiCegarLoop]: Abstraction has 467 states and 645 transitions. [2018-10-27 06:12:20,939 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-10-27 06:12:20,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 467 states and 645 transitions. [2018-10-27 06:12:20,943 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 396 [2018-10-27 06:12:20,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:20,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:20,947 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:20,947 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:20,948 INFO L793 eck$LassoCheckResult]: Stem: 3758#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 3687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3688#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3783#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3794#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 3848#L221-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 3751#L226-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 3752#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3718#L334 assume ~M_E~0 == 0;~M_E~0 := 1; 3719#L334-2 assume !(~T1_E~0 == 0); 4116#L339-1 assume !(~T2_E~0 == 0); 4115#L344-1 assume !(~E_M~0 == 0); 4114#L349-1 assume !(~E_1~0 == 0); 4113#L354-1 assume !(~E_2~0 == 0); 4112#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4111#L156 assume !(~m_pc~0 == 1); 4109#L156-2 is_master_triggered_~__retres1~0 := 0; 4107#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4104#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4102#L415 assume !(activate_threads_~tmp~1 != 0); 3908#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3674#L175 assume !(~t1_pc~0 == 1); 3675#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 3677#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3678#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3757#L423 assume !(activate_threads_~tmp___0~0 != 0); 3795#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3797#L194 assume !(~t2_pc~0 == 1); 3838#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 3839#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3844#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3832#L431 assume !(activate_threads_~tmp___1~0 != 0); 3833#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3736#L372 assume ~M_E~0 == 1;~M_E~0 := 2; 3737#L372-2 assume !(~T1_E~0 == 1); 3739#L377-1 assume !(~T2_E~0 == 1); 3882#L382-1 assume !(~E_M~0 == 1); 3804#L387-1 assume !(~E_1~0 == 1); 3805#L392-1 assume !(~E_2~0 == 1); 3841#L397-1 assume { :end_inline_reset_delta_events } true; 3727#L543-3 [2018-10-27 06:12:20,948 INFO L795 eck$LassoCheckResult]: Loop: 3727#L543-3 assume true; 3726#L543-1 assume !false; 3685#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 3686#L309 assume true; 3845#L271-1 assume !false; 3846#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3897#L244 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 3684#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3730#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3731#L276 assume !(eval_~tmp~0 != 0); 3784#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3785#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3724#L334-3 assume !(~M_E~0 == 0); 3716#L334-5 assume !(~T1_E~0 == 0); 3717#L339-3 assume !(~T2_E~0 == 0); 3742#L344-3 assume !(~E_M~0 == 0); 3885#L349-3 assume ~E_1~0 == 0;~E_1~0 := 1; 3825#L354-3 assume ~E_2~0 == 0;~E_2~0 := 1; 3826#L359-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3834#L156-12 assume !(~m_pc~0 == 1); 3878#L156-14 is_master_triggered_~__retres1~0 := 0; 3932#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3933#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3892#L415-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 3893#L415-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3796#L175-12 assume ~t1_pc~0 == 1; 3762#L176-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 3697#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3698#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3764#L423-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 4129#L423-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4128#L194-12 assume !(~t2_pc~0 == 1); 4127#L194-14 is_transmit2_triggered_~__retres1~2 := 0; 4126#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4125#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4124#L431-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 4123#L431-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4122#L372-3 assume !(~M_E~0 == 1); 3741#L372-5 assume !(~T1_E~0 == 1); 3743#L377-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 3884#L382-3 assume !(~E_M~0 == 1); 3818#L387-3 assume ~E_1~0 == 1;~E_1~0 := 2; 3819#L392-3 assume ~E_2~0 == 1;~E_2~0 := 2; 3847#L397-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3851#L244-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 3682#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3728#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 3729#L562 assume !(start_simulation_~tmp~3 == 0); 3793#L562-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3853#L244-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 3680#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3744#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 3745#L517 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 3782#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 3849#L525 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 3899#L575 assume !(start_simulation_~tmp___0~1 != 0); 3727#L543-3 [2018-10-27 06:12:20,948 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:20,949 INFO L82 PathProgramCache]: Analyzing trace with hash -972332919, now seen corresponding path program 1 times [2018-10-27 06:12:20,949 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:20,949 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:20,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:20,961 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:20,962 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:20,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:21,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:21,012 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:21,012 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:12:21,012 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:12:21,012 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:21,012 INFO L82 PathProgramCache]: Analyzing trace with hash 301060481, now seen corresponding path program 1 times [2018-10-27 06:12:21,012 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:21,013 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:21,013 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:21,013 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:21,013 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:21,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:21,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:21,088 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:21,088 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 06:12:21,089 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:12:21,089 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:12:21,089 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:12:21,089 INFO L87 Difference]: Start difference. First operand 467 states and 645 transitions. cyclomatic complexity: 180 Second operand 3 states. [2018-10-27 06:12:21,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:21,187 INFO L93 Difference]: Finished difference Result 385 states and 528 transitions. [2018-10-27 06:12:21,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:12:21,192 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 385 states and 528 transitions. [2018-10-27 06:12:21,195 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 341 [2018-10-27 06:12:21,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 385 states to 385 states and 528 transitions. [2018-10-27 06:12:21,197 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 385 [2018-10-27 06:12:21,199 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 385 [2018-10-27 06:12:21,199 INFO L73 IsDeterministic]: Start isDeterministic. Operand 385 states and 528 transitions. [2018-10-27 06:12:21,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:21,200 INFO L705 BuchiCegarLoop]: Abstraction has 385 states and 528 transitions. [2018-10-27 06:12:21,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 385 states and 528 transitions. [2018-10-27 06:12:21,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 385 to 385. [2018-10-27 06:12:21,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 385 states. [2018-10-27 06:12:21,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 385 states to 385 states and 528 transitions. [2018-10-27 06:12:21,215 INFO L728 BuchiCegarLoop]: Abstraction has 385 states and 528 transitions. [2018-10-27 06:12:21,215 INFO L608 BuchiCegarLoop]: Abstraction has 385 states and 528 transitions. [2018-10-27 06:12:21,215 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-10-27 06:12:21,215 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 385 states and 528 transitions. [2018-10-27 06:12:21,217 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 341 [2018-10-27 06:12:21,217 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:21,217 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:21,222 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:21,225 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:21,226 INFO L793 eck$LassoCheckResult]: Stem: 4616#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4548#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4549#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4640#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4651#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 4701#L221-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 4609#L226-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 4610#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4579#L334 assume !(~M_E~0 == 0); 4580#L334-2 assume !(~T1_E~0 == 0); 4583#L339-1 assume !(~T2_E~0 == 0); 4596#L344-1 assume !(~E_M~0 == 0); 4737#L349-1 assume !(~E_1~0 == 0); 4664#L354-1 assume !(~E_2~0 == 0); 4665#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4696#L156 assume !(~m_pc~0 == 1); 4724#L156-2 is_master_triggered_~__retres1~0 := 0; 4770#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4725#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4726#L415 assume !(activate_threads_~tmp~1 != 0); 4759#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4535#L175 assume !(~t1_pc~0 == 1); 4536#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 4538#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4539#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4615#L423 assume !(activate_threads_~tmp___0~0 != 0); 4652#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4654#L194 assume !(~t2_pc~0 == 1); 4691#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 4692#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4697#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4686#L431 assume !(activate_threads_~tmp___1~0 != 0); 4659#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4594#L372 assume !(~M_E~0 == 1); 4595#L372-2 assume !(~T1_E~0 == 1); 4597#L377-1 assume !(~T2_E~0 == 1); 4736#L382-1 assume !(~E_M~0 == 1); 4660#L387-1 assume !(~E_1~0 == 1); 4661#L392-1 assume !(~E_2~0 == 1); 4694#L397-1 assume { :end_inline_reset_delta_events } true; 4586#L543-3 [2018-10-27 06:12:21,226 INFO L795 eck$LassoCheckResult]: Loop: 4586#L543-3 assume true; 4585#L543-1 assume !false; 4546#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4547#L309 assume true; 4698#L271-1 assume !false; 4699#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4748#L244 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 4545#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4589#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 4590#L276 assume !(eval_~tmp~0 != 0); 4704#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4919#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4918#L334-3 assume !(~M_E~0 == 0); 4917#L334-5 assume !(~T1_E~0 == 0); 4916#L339-3 assume !(~T2_E~0 == 0); 4915#L344-3 assume !(~E_M~0 == 0); 4914#L349-3 assume ~E_1~0 == 0;~E_1~0 := 1; 4913#L354-3 assume ~E_2~0 == 0;~E_2~0 := 1; 4912#L359-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4910#L156-12 assume !(~m_pc~0 == 1); 4909#L156-14 is_master_triggered_~__retres1~0 := 0; 4908#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4907#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4906#L415-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 4905#L415-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4904#L175-12 assume ~t1_pc~0 == 1; 4902#L176-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 4901#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4888#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4886#L423-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 4631#L423-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4632#L194-12 assume !(~t2_pc~0 == 1); 4681#L194-14 is_transmit2_triggered_~__retres1~2 := 0; 4675#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4676#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4754#L431-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 4771#L431-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4598#L372-3 assume !(~M_E~0 == 1); 4599#L372-5 assume !(~T1_E~0 == 1); 4601#L377-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 4738#L382-3 assume !(~E_M~0 == 1); 4672#L387-3 assume ~E_1~0 == 1;~E_1~0 := 2; 4673#L392-3 assume ~E_2~0 == 1;~E_2~0 := 2; 4700#L397-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4705#L244-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 4543#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4587#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 4588#L562 assume !(start_simulation_~tmp~3 == 0); 4650#L562-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4707#L244-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 4541#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4602#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 4603#L517 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 4639#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 4702#L525 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 4750#L575 assume !(start_simulation_~tmp___0~1 != 0); 4586#L543-3 [2018-10-27 06:12:21,226 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:21,226 INFO L82 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 2 times [2018-10-27 06:12:21,226 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:21,226 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:21,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:21,227 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:21,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:21,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:21,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:21,258 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:21,259 INFO L82 PathProgramCache]: Analyzing trace with hash 301060481, now seen corresponding path program 2 times [2018-10-27 06:12:21,259 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:21,259 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:21,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:21,261 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:12:21,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:21,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:21,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:21,327 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:21,327 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 06:12:21,327 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:12:21,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 06:12:21,328 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-27 06:12:21,328 INFO L87 Difference]: Start difference. First operand 385 states and 528 transitions. cyclomatic complexity: 145 Second operand 5 states. [2018-10-27 06:12:21,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:21,557 INFO L93 Difference]: Finished difference Result 657 states and 890 transitions. [2018-10-27 06:12:21,558 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-27 06:12:21,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 657 states and 890 transitions. [2018-10-27 06:12:21,562 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 611 [2018-10-27 06:12:21,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 657 states to 657 states and 890 transitions. [2018-10-27 06:12:21,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 657 [2018-10-27 06:12:21,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 657 [2018-10-27 06:12:21,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 657 states and 890 transitions. [2018-10-27 06:12:21,569 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:21,569 INFO L705 BuchiCegarLoop]: Abstraction has 657 states and 890 transitions. [2018-10-27 06:12:21,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 657 states and 890 transitions. [2018-10-27 06:12:21,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 657 to 391. [2018-10-27 06:12:21,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 391 states. [2018-10-27 06:12:21,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 391 states and 534 transitions. [2018-10-27 06:12:21,580 INFO L728 BuchiCegarLoop]: Abstraction has 391 states and 534 transitions. [2018-10-27 06:12:21,580 INFO L608 BuchiCegarLoop]: Abstraction has 391 states and 534 transitions. [2018-10-27 06:12:21,580 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-10-27 06:12:21,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 391 states and 534 transitions. [2018-10-27 06:12:21,584 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 347 [2018-10-27 06:12:21,585 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:21,585 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:21,586 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:21,586 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:21,586 INFO L793 eck$LassoCheckResult]: Stem: 5677#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 5607#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5608#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5703#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5714#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 5764#L221-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 5670#L226-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 5671#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5638#L334 assume !(~M_E~0 == 0); 5639#L334-2 assume !(~T1_E~0 == 0); 5642#L339-1 assume !(~T2_E~0 == 0); 5656#L344-1 assume !(~E_M~0 == 0); 5800#L349-1 assume !(~E_1~0 == 0); 5727#L354-1 assume !(~E_2~0 == 0); 5728#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5759#L156 assume !(~m_pc~0 == 1); 5787#L156-2 is_master_triggered_~__retres1~0 := 0; 5840#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5788#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5789#L415 assume !(activate_threads_~tmp~1 != 0); 5826#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5593#L175 assume !(~t1_pc~0 == 1); 5594#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 5598#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5599#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5676#L423 assume !(activate_threads_~tmp___0~0 != 0); 5715#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5717#L194 assume !(~t2_pc~0 == 1); 5754#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 5755#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5760#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5749#L431 assume !(activate_threads_~tmp___1~0 != 0); 5722#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5654#L372 assume !(~M_E~0 == 1); 5655#L372-2 assume !(~T1_E~0 == 1); 5657#L377-1 assume !(~T2_E~0 == 1); 5799#L382-1 assume !(~E_M~0 == 1); 5723#L387-1 assume !(~E_1~0 == 1); 5724#L392-1 assume !(~E_2~0 == 1); 5758#L397-1 assume { :end_inline_reset_delta_events } true; 5645#L543-3 [2018-10-27 06:12:21,586 INFO L795 eck$LassoCheckResult]: Loop: 5645#L543-3 assume true; 5646#L543-1 assume !false; 5967#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 5641#L309 assume true; 5966#L271-1 assume !false; 5923#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5851#L244 assume !(~m_st~0 == 0); 5673#L248 assume !(~t1_st~0 == 0); 5602#L252 assume !(~t2_st~0 == 0);exists_runnable_thread_~__retres1~3 := 0; 5604#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5929#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5885#L276 assume !(eval_~tmp~0 != 0); 5705#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5706#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5643#L334-3 assume !(~M_E~0 == 0); 5636#L334-5 assume !(~T1_E~0 == 0); 5637#L339-3 assume !(~T2_E~0 == 0); 5660#L344-3 assume !(~E_M~0 == 0); 5803#L349-3 assume ~E_1~0 == 0;~E_1~0 := 1; 5742#L354-3 assume ~E_2~0 == 0;~E_2~0 := 1; 5743#L359-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5750#L156-12 assume !(~m_pc~0 == 1); 5795#L156-14 is_master_triggered_~__retres1~0 := 0; 5838#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5796#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5797#L415-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 5810#L415-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5716#L175-12 assume ~t1_pc~0 == 1; 5682#L176-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 5617#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5618#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5684#L423-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 5694#L423-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5695#L194-12 assume !(~t2_pc~0 == 1); 5744#L194-14 is_transmit2_triggered_~__retres1~2 := 0; 5739#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5740#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5841#L431-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 5842#L431-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5658#L372-3 assume !(~M_E~0 == 1); 5659#L372-5 assume !(~T1_E~0 == 1); 5801#L377-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 5802#L382-3 assume !(~E_M~0 == 1); 5735#L387-3 assume ~E_1~0 == 1;~E_1~0 := 2; 5736#L392-3 assume ~E_2~0 == 1;~E_2~0 := 2; 5761#L397-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5849#L244-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 5601#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5647#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 5648#L562 assume !(start_simulation_~tmp~3 == 0); 5769#L562-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5848#L244-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 5597#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5972#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 5971#L517 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 5970#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 5969#L525 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 5816#L575 assume !(start_simulation_~tmp___0~1 != 0); 5645#L543-3 [2018-10-27 06:12:21,587 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:21,587 INFO L82 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 3 times [2018-10-27 06:12:21,587 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:21,587 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:21,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:21,588 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:12:21,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:21,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:21,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:21,613 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:21,613 INFO L82 PathProgramCache]: Analyzing trace with hash 1077289370, now seen corresponding path program 1 times [2018-10-27 06:12:21,613 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:21,613 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:21,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:21,614 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:12:21,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:21,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:21,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:21,919 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:21,920 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 06:12:21,920 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:12:21,920 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 06:12:21,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-27 06:12:21,920 INFO L87 Difference]: Start difference. First operand 391 states and 534 transitions. cyclomatic complexity: 145 Second operand 5 states. [2018-10-27 06:12:22,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:22,059 INFO L93 Difference]: Finished difference Result 520 states and 704 transitions. [2018-10-27 06:12:22,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-27 06:12:22,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 520 states and 704 transitions. [2018-10-27 06:12:22,070 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 476 [2018-10-27 06:12:22,073 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 520 states to 520 states and 704 transitions. [2018-10-27 06:12:22,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 520 [2018-10-27 06:12:22,074 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 520 [2018-10-27 06:12:22,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 520 states and 704 transitions. [2018-10-27 06:12:22,076 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:22,076 INFO L705 BuchiCegarLoop]: Abstraction has 520 states and 704 transitions. [2018-10-27 06:12:22,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 520 states and 704 transitions. [2018-10-27 06:12:22,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 520 to 394. [2018-10-27 06:12:22,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 394 states. [2018-10-27 06:12:22,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 394 states to 394 states and 528 transitions. [2018-10-27 06:12:22,089 INFO L728 BuchiCegarLoop]: Abstraction has 394 states and 528 transitions. [2018-10-27 06:12:22,089 INFO L608 BuchiCegarLoop]: Abstraction has 394 states and 528 transitions. [2018-10-27 06:12:22,089 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-10-27 06:12:22,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 394 states and 528 transitions. [2018-10-27 06:12:22,091 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 350 [2018-10-27 06:12:22,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:22,091 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:22,092 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:22,092 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:22,092 INFO L793 eck$LassoCheckResult]: Stem: 6601#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 6531#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6532#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6630#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6643#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 6700#L221-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 6594#L226-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 6595#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6562#L334 assume !(~M_E~0 == 0); 6563#L334-2 assume !(~T1_E~0 == 0); 6566#L339-1 assume !(~T2_E~0 == 0); 6581#L344-1 assume !(~E_M~0 == 0); 6739#L349-1 assume !(~E_1~0 == 0); 6657#L354-1 assume !(~E_2~0 == 0); 6658#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6695#L156 assume !(~m_pc~0 == 1); 6726#L156-2 is_master_triggered_~__retres1~0 := 0; 6775#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6727#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6728#L415 assume !(activate_threads_~tmp~1 != 0); 6764#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6517#L175 assume !(~t1_pc~0 == 1); 6518#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 6522#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6523#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6600#L423 assume !(activate_threads_~tmp___0~0 != 0); 6644#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6646#L194 assume !(~t2_pc~0 == 1); 6688#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 6689#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6696#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6681#L431 assume !(activate_threads_~tmp___1~0 != 0); 6651#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6579#L372 assume !(~M_E~0 == 1); 6580#L372-2 assume !(~T1_E~0 == 1); 6582#L377-1 assume !(~T2_E~0 == 1); 6738#L382-1 assume !(~E_M~0 == 1); 6652#L387-1 assume !(~E_1~0 == 1); 6653#L392-1 assume !(~E_2~0 == 1); 6694#L397-1 assume { :end_inline_reset_delta_events } true; 6706#L543-3 [2018-10-27 06:12:22,093 INFO L795 eck$LassoCheckResult]: Loop: 6706#L543-3 assume true; 6568#L543-1 assume !false; 6569#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6884#L309 assume true; 6883#L271-1 assume !false; 6882#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6880#L244 assume !(~m_st~0 == 0); 6881#L248 assume !(~t1_st~0 == 0); 6878#L252 assume !(~t2_st~0 == 0);exists_runnable_thread_~__retres1~3 := 0; 6879#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6874#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 6875#L276 assume !(eval_~tmp~0 != 0); 6907#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 6906#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 6905#L334-3 assume !(~M_E~0 == 0); 6904#L334-5 assume !(~T1_E~0 == 0); 6903#L339-3 assume !(~T2_E~0 == 0); 6902#L344-3 assume !(~E_M~0 == 0); 6773#L349-3 assume ~E_1~0 == 0;~E_1~0 := 1; 6673#L354-3 assume ~E_2~0 == 0;~E_2~0 := 1; 6674#L359-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6682#L156-12 assume !(~m_pc~0 == 1); 6862#L156-14 is_master_triggered_~__retres1~0 := 0; 6861#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6860#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6859#L415-12 assume !(activate_threads_~tmp~1 != 0); 6858#L415-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6857#L175-12 assume ~t1_pc~0 == 1; 6855#L176-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 6541#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6542#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6609#L423-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 6621#L423-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6622#L194-12 assume !(~t2_pc~0 == 1); 6675#L194-14 is_transmit2_triggered_~__retres1~2 := 0; 6835#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6834#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6833#L431-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 6832#L431-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6831#L372-3 assume !(~M_E~0 == 1); 6830#L372-5 assume !(~T1_E~0 == 1); 6829#L377-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 6828#L382-3 assume !(~E_M~0 == 1); 6827#L387-3 assume ~E_1~0 == 1;~E_1~0 := 2; 6826#L392-3 assume ~E_2~0 == 1;~E_2~0 := 2; 6825#L397-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6823#L244-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 6821#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6820#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 6819#L562 assume !(start_simulation_~tmp~3 == 0); 6708#L562-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6709#L244-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 6897#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6896#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 6895#L517 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 6701#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 6702#L525 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 6755#L575 assume !(start_simulation_~tmp___0~1 != 0); 6706#L543-3 [2018-10-27 06:12:22,093 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:22,093 INFO L82 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 4 times [2018-10-27 06:12:22,093 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:22,105 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:22,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:22,106 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:22,106 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:22,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:22,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:22,124 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:22,126 INFO L82 PathProgramCache]: Analyzing trace with hash 1004902812, now seen corresponding path program 1 times [2018-10-27 06:12:22,126 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:22,126 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:22,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:22,127 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:12:22,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:22,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:22,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:22,222 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:22,222 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:12:22,223 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:12:22,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:12:22,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:12:22,223 INFO L87 Difference]: Start difference. First operand 394 states and 528 transitions. cyclomatic complexity: 136 Second operand 3 states. [2018-10-27 06:12:22,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:22,360 INFO L93 Difference]: Finished difference Result 512 states and 678 transitions. [2018-10-27 06:12:22,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:12:22,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 512 states and 678 transitions. [2018-10-27 06:12:22,364 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 435 [2018-10-27 06:12:22,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 512 states to 512 states and 678 transitions. [2018-10-27 06:12:22,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 512 [2018-10-27 06:12:22,368 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 512 [2018-10-27 06:12:22,368 INFO L73 IsDeterministic]: Start isDeterministic. Operand 512 states and 678 transitions. [2018-10-27 06:12:22,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:22,369 INFO L705 BuchiCegarLoop]: Abstraction has 512 states and 678 transitions. [2018-10-27 06:12:22,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 512 states and 678 transitions. [2018-10-27 06:12:22,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 512 to 512. [2018-10-27 06:12:22,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 512 states. [2018-10-27 06:12:22,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 512 states to 512 states and 678 transitions. [2018-10-27 06:12:22,381 INFO L728 BuchiCegarLoop]: Abstraction has 512 states and 678 transitions. [2018-10-27 06:12:22,381 INFO L608 BuchiCegarLoop]: Abstraction has 512 states and 678 transitions. [2018-10-27 06:12:22,381 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-10-27 06:12:22,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 512 states and 678 transitions. [2018-10-27 06:12:22,385 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 435 [2018-10-27 06:12:22,385 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:22,385 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:22,386 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:22,386 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:22,386 INFO L793 eck$LassoCheckResult]: Stem: 7515#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 7443#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7444#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7540#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7554#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 7607#L221-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 7506#L226-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 7507#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7474#L334 assume !(~M_E~0 == 0); 7475#L334-2 assume !(~T1_E~0 == 0); 7478#L339-1 assume !(~T2_E~0 == 0); 7493#L344-1 assume !(~E_M~0 == 0); 7646#L349-1 assume !(~E_1~0 == 0); 7567#L354-1 assume !(~E_2~0 == 0); 7568#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7602#L156 assume !(~m_pc~0 == 1); 7633#L156-2 is_master_triggered_~__retres1~0 := 0; 7688#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7634#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 7635#L415 assume !(activate_threads_~tmp~1 != 0); 7676#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7429#L175 assume !(~t1_pc~0 == 1); 7430#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 7434#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7435#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7514#L423 assume !(activate_threads_~tmp___0~0 != 0); 7555#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7557#L194 assume !(~t2_pc~0 == 1); 7597#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 7598#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7603#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7590#L431 assume !(activate_threads_~tmp___1~0 != 0); 7562#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7491#L372 assume !(~M_E~0 == 1); 7492#L372-2 assume !(~T1_E~0 == 1); 7494#L377-1 assume !(~T2_E~0 == 1); 7645#L382-1 assume !(~E_M~0 == 1); 7563#L387-1 assume !(~E_1~0 == 1); 7564#L392-1 assume !(~E_2~0 == 1); 7601#L397-1 assume { :end_inline_reset_delta_events } true; 7612#L543-3 assume true; 7791#L543-1 assume !false; 7786#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 7778#L309 [2018-10-27 06:12:22,386 INFO L795 eck$LassoCheckResult]: Loop: 7778#L309 assume true; 7776#L271-1 assume !false; 7773#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7770#L244 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 7767#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7764#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 7761#L276 assume eval_~tmp~0 != 0; 7759#L276-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 7487#L284 assume !(eval_~tmp_ndt_1~0 != 0); 7489#L281 assume !(~t1_st~0 == 0); 7787#L295 assume !(~t2_st~0 == 0); 7778#L309 [2018-10-27 06:12:22,387 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:22,387 INFO L82 PathProgramCache]: Analyzing trace with hash 1547564041, now seen corresponding path program 1 times [2018-10-27 06:12:22,387 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:22,387 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:22,388 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:22,388 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:22,388 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:22,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:22,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:22,408 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:22,408 INFO L82 PathProgramCache]: Analyzing trace with hash 1117242930, now seen corresponding path program 1 times [2018-10-27 06:12:22,409 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:22,409 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:22,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:22,410 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:22,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:22,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:22,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:22,418 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:22,418 INFO L82 PathProgramCache]: Analyzing trace with hash 1566997802, now seen corresponding path program 1 times [2018-10-27 06:12:22,418 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:22,419 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:22,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:22,419 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:22,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:22,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:22,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:22,494 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:22,494 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:12:23,027 WARN L179 SmtUtils]: Spent 527.00 ms on a formula simplification. DAG size of input: 23 DAG size of output: 21 [2018-10-27 06:12:23,211 WARN L179 SmtUtils]: Spent 183.00 ms on a formula simplification that was a NOOP. DAG size: 21 [2018-10-27 06:12:23,224 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:12:23,224 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:12:23,225 INFO L87 Difference]: Start difference. First operand 512 states and 678 transitions. cyclomatic complexity: 169 Second operand 3 states. [2018-10-27 06:12:23,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:23,389 INFO L93 Difference]: Finished difference Result 890 states and 1161 transitions. [2018-10-27 06:12:23,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:12:23,391 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 890 states and 1161 transitions. [2018-10-27 06:12:23,394 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 742 [2018-10-27 06:12:23,397 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 890 states to 890 states and 1161 transitions. [2018-10-27 06:12:23,397 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 890 [2018-10-27 06:12:23,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 890 [2018-10-27 06:12:23,399 INFO L73 IsDeterministic]: Start isDeterministic. Operand 890 states and 1161 transitions. [2018-10-27 06:12:23,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:23,401 INFO L705 BuchiCegarLoop]: Abstraction has 890 states and 1161 transitions. [2018-10-27 06:12:23,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 890 states and 1161 transitions. [2018-10-27 06:12:23,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 890 to 844. [2018-10-27 06:12:23,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 844 states. [2018-10-27 06:12:23,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 844 states to 844 states and 1107 transitions. [2018-10-27 06:12:23,416 INFO L728 BuchiCegarLoop]: Abstraction has 844 states and 1107 transitions. [2018-10-27 06:12:23,416 INFO L608 BuchiCegarLoop]: Abstraction has 844 states and 1107 transitions. [2018-10-27 06:12:23,416 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-10-27 06:12:23,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 844 states and 1107 transitions. [2018-10-27 06:12:23,421 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 696 [2018-10-27 06:12:23,421 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:23,421 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:23,423 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:23,423 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:23,423 INFO L793 eck$LassoCheckResult]: Stem: 8935#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 8853#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8854#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 8960#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8975#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 9028#L221-2 assume !(~t1_i~0 == 1);~t1_st~0 := 2; 8923#L226-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 8924#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8934#L334 assume !(~M_E~0 == 0); 9320#L334-2 assume !(~T1_E~0 == 0); 8907#L339-1 assume !(~T2_E~0 == 0); 8908#L344-1 assume !(~E_M~0 == 0); 9110#L349-1 assume !(~E_1~0 == 0); 9111#L354-1 assume !(~E_2~0 == 0); 9317#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9315#L156 assume !(~m_pc~0 == 1); 9119#L156-2 is_master_triggered_~__retres1~0 := 0; 9120#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9054#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 9055#L415 assume !(activate_threads_~tmp~1 != 0); 9130#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8839#L175 assume !(~t1_pc~0 == 1); 8840#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 8844#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8845#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 8933#L423 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 8977#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8979#L194 assume !(~t2_pc~0 == 1); 9018#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 9019#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9024#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9013#L431 assume !(activate_threads_~tmp___1~0 != 0); 8984#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8905#L372 assume !(~M_E~0 == 1); 8906#L372-2 assume !(~T1_E~0 == 1); 8909#L377-1 assume !(~T2_E~0 == 1); 9065#L382-1 assume !(~E_M~0 == 1); 8985#L387-1 assume !(~E_1~0 == 1); 8986#L392-1 assume !(~E_2~0 == 1); 9022#L397-1 assume { :end_inline_reset_delta_events } true; 9032#L543-3 assume true; 9313#L543-1 assume !false; 9311#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 9306#L309 [2018-10-27 06:12:23,423 INFO L795 eck$LassoCheckResult]: Loop: 9306#L309 assume true; 9301#L271-1 assume !false; 9300#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9293#L244 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 9292#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9290#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 9288#L276 assume eval_~tmp~0 != 0; 9286#L276-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 9283#L284 assume !(eval_~tmp_ndt_1~0 != 0); 9284#L281 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 9262#L298 assume !(eval_~tmp_ndt_2~0 != 0); 9312#L295 assume !(~t2_st~0 == 0); 9306#L309 [2018-10-27 06:12:23,424 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:23,424 INFO L82 PathProgramCache]: Analyzing trace with hash -1782617847, now seen corresponding path program 1 times [2018-10-27 06:12:23,424 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:23,424 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:23,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:23,424 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:23,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:23,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:23,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:23,491 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:23,491 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:12:23,491 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:12:23,491 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:23,491 INFO L82 PathProgramCache]: Analyzing trace with hash 274684685, now seen corresponding path program 1 times [2018-10-27 06:12:23,492 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:23,492 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:23,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:23,492 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:23,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:23,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:23,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:23,654 WARN L179 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 24 [2018-10-27 06:12:23,783 WARN L179 SmtUtils]: Spent 128.00 ms on a formula simplification that was a NOOP. DAG size: 24 [2018-10-27 06:12:23,785 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:12:23,785 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:12:23,785 INFO L87 Difference]: Start difference. First operand 844 states and 1107 transitions. cyclomatic complexity: 266 Second operand 3 states. [2018-10-27 06:12:23,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:23,796 INFO L93 Difference]: Finished difference Result 805 states and 1056 transitions. [2018-10-27 06:12:23,797 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:12:23,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 805 states and 1056 transitions. [2018-10-27 06:12:23,800 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 696 [2018-10-27 06:12:23,805 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 805 states to 805 states and 1056 transitions. [2018-10-27 06:12:23,805 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 805 [2018-10-27 06:12:23,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 805 [2018-10-27 06:12:23,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 805 states and 1056 transitions. [2018-10-27 06:12:23,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:23,807 INFO L705 BuchiCegarLoop]: Abstraction has 805 states and 1056 transitions. [2018-10-27 06:12:23,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 805 states and 1056 transitions. [2018-10-27 06:12:23,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 805 to 805. [2018-10-27 06:12:23,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 805 states. [2018-10-27 06:12:23,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 805 states to 805 states and 1056 transitions. [2018-10-27 06:12:23,821 INFO L728 BuchiCegarLoop]: Abstraction has 805 states and 1056 transitions. [2018-10-27 06:12:23,821 INFO L608 BuchiCegarLoop]: Abstraction has 805 states and 1056 transitions. [2018-10-27 06:12:23,822 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-10-27 06:12:23,824 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 805 states and 1056 transitions. [2018-10-27 06:12:23,827 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 696 [2018-10-27 06:12:23,827 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:23,827 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:23,828 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:23,828 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:23,828 INFO L793 eck$LassoCheckResult]: Stem: 10583#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 10508#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10509#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 10609#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10622#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 10673#L221-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 10573#L226-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 10574#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10539#L334 assume !(~M_E~0 == 0); 10540#L334-2 assume !(~T1_E~0 == 0); 10543#L339-1 assume !(~T2_E~0 == 0); 10558#L344-1 assume !(~E_M~0 == 0); 10715#L349-1 assume !(~E_1~0 == 0); 10635#L354-1 assume !(~E_2~0 == 0); 10636#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10668#L156 assume !(~m_pc~0 == 1); 10702#L156-2 is_master_triggered_~__retres1~0 := 0; 10756#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10703#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10704#L415 assume !(activate_threads_~tmp~1 != 0); 10745#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10494#L175 assume !(~t1_pc~0 == 1); 10495#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 10499#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10500#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 10582#L423 assume !(activate_threads_~tmp___0~0 != 0); 10623#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10625#L194 assume !(~t2_pc~0 == 1); 10663#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 10664#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10669#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 10658#L431 assume !(activate_threads_~tmp___1~0 != 0); 10630#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10556#L372 assume !(~M_E~0 == 1); 10557#L372-2 assume !(~T1_E~0 == 1); 10559#L377-1 assume !(~T2_E~0 == 1); 10714#L382-1 assume !(~E_M~0 == 1); 10631#L387-1 assume !(~E_1~0 == 1); 10632#L392-1 assume !(~E_2~0 == 1); 10666#L397-1 assume { :end_inline_reset_delta_events } true; 10679#L543-3 assume true; 11281#L543-1 assume !false; 11279#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 11212#L309 [2018-10-27 06:12:23,828 INFO L795 eck$LassoCheckResult]: Loop: 11212#L309 assume true; 11276#L271-1 assume !false; 11274#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11272#L244 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 11271#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10551#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 10552#L276 assume eval_~tmp~0 != 0; 11261#L276-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 10553#L284 assume !(eval_~tmp_ndt_1~0 != 0); 10555#L281 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 10681#L298 assume !(eval_~tmp_ndt_2~0 != 0); 10682#L295 assume !(~t2_st~0 == 0); 11212#L309 [2018-10-27 06:12:23,828 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:23,829 INFO L82 PathProgramCache]: Analyzing trace with hash 1547564041, now seen corresponding path program 2 times [2018-10-27 06:12:23,829 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:23,829 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:23,829 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:23,829 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:23,830 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:23,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:23,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:23,855 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:23,855 INFO L82 PathProgramCache]: Analyzing trace with hash 274684685, now seen corresponding path program 2 times [2018-10-27 06:12:23,855 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:23,855 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:23,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:23,856 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:12:23,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:23,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:23,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:23,865 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:23,865 INFO L82 PathProgramCache]: Analyzing trace with hash 1332183829, now seen corresponding path program 1 times [2018-10-27 06:12:23,865 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:23,865 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:23,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:23,868 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:12:23,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:23,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:12:23,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:12:23,933 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:12:23,933 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:12:24,059 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:12:24,059 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:12:24,059 INFO L87 Difference]: Start difference. First operand 805 states and 1056 transitions. cyclomatic complexity: 254 Second operand 3 states. [2018-10-27 06:12:24,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:12:24,098 INFO L93 Difference]: Finished difference Result 950 states and 1235 transitions. [2018-10-27 06:12:24,099 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:12:24,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 950 states and 1235 transitions. [2018-10-27 06:12:24,103 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 841 [2018-10-27 06:12:24,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 950 states to 950 states and 1235 transitions. [2018-10-27 06:12:24,107 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 950 [2018-10-27 06:12:24,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 950 [2018-10-27 06:12:24,108 INFO L73 IsDeterministic]: Start isDeterministic. Operand 950 states and 1235 transitions. [2018-10-27 06:12:24,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:12:24,111 INFO L705 BuchiCegarLoop]: Abstraction has 950 states and 1235 transitions. [2018-10-27 06:12:24,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 950 states and 1235 transitions. [2018-10-27 06:12:24,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 950 to 930. [2018-10-27 06:12:24,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 930 states. [2018-10-27 06:12:24,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 930 states to 930 states and 1215 transitions. [2018-10-27 06:12:24,126 INFO L728 BuchiCegarLoop]: Abstraction has 930 states and 1215 transitions. [2018-10-27 06:12:24,127 INFO L608 BuchiCegarLoop]: Abstraction has 930 states and 1215 transitions. [2018-10-27 06:12:24,127 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-10-27 06:12:24,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 930 states and 1215 transitions. [2018-10-27 06:12:24,130 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 821 [2018-10-27 06:12:24,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:12:24,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:12:24,131 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:24,131 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:12:24,131 INFO L793 eck$LassoCheckResult]: Stem: 12344#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 12270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12271#L506 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12372#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12384#L221 assume ~m_i~0 == 1;~m_st~0 := 0; 12437#L221-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 12334#L226-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 12335#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12301#L334 assume !(~M_E~0 == 0); 12302#L334-2 assume !(~T1_E~0 == 0); 12305#L339-1 assume !(~T2_E~0 == 0); 12319#L344-1 assume !(~E_M~0 == 0); 12477#L349-1 assume !(~E_1~0 == 0); 12397#L354-1 assume !(~E_2~0 == 0); 12398#L359-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12432#L156 assume !(~m_pc~0 == 1); 12464#L156-2 is_master_triggered_~__retres1~0 := 0; 12511#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12465#L168 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 12466#L415 assume !(activate_threads_~tmp~1 != 0); 12500#L415-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12257#L175 assume !(~t1_pc~0 == 1); 12258#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 12260#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12261#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12343#L423 assume !(activate_threads_~tmp___0~0 != 0); 12385#L423-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12387#L194 assume !(~t2_pc~0 == 1); 12427#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 12428#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12433#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 12422#L431 assume !(activate_threads_~tmp___1~0 != 0); 12392#L431-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12317#L372 assume !(~M_E~0 == 1); 12318#L372-2 assume !(~T1_E~0 == 1); 12320#L377-1 assume !(~T2_E~0 == 1); 12476#L382-1 assume !(~E_M~0 == 1); 12393#L387-1 assume !(~E_1~0 == 1); 12394#L392-1 assume !(~E_2~0 == 1); 12430#L397-1 assume { :end_inline_reset_delta_events } true; 12441#L543-3 assume true; 13090#L543-1 assume !false; 13088#L544 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 12304#L309 [2018-10-27 06:12:24,131 INFO L795 eck$LassoCheckResult]: Loop: 12304#L309 assume true; 13083#L271-1 assume !false; 13081#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13079#L244 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 13078#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13077#L262 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 13076#L276 assume eval_~tmp~0 != 0; 13075#L276-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 13074#L284 assume !(eval_~tmp_ndt_1~0 != 0); 12340#L281 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 12341#L298 assume !(eval_~tmp_ndt_2~0 != 0); 12316#L295 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 12303#L312 assume !(eval_~tmp_ndt_3~0 != 0); 12304#L309 [2018-10-27 06:12:24,131 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:24,132 INFO L82 PathProgramCache]: Analyzing trace with hash 1547564041, now seen corresponding path program 3 times [2018-10-27 06:12:24,132 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:24,132 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:24,132 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:24,132 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:24,133 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:24,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:24,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:24,153 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:24,153 INFO L82 PathProgramCache]: Analyzing trace with hash -74712171, now seen corresponding path program 1 times [2018-10-27 06:12:24,153 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:24,153 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:24,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:24,156 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:12:24,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:24,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:24,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:24,163 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:12:24,164 INFO L82 PathProgramCache]: Analyzing trace with hash -1651977075, now seen corresponding path program 1 times [2018-10-27 06:12:24,164 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:12:24,164 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:12:24,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:24,164 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:12:24,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:12:24,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:24,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:12:24,858 WARN L179 SmtUtils]: Spent 595.00 ms on a formula simplification. DAG size of input: 105 DAG size of output: 72 [2018-10-27 06:12:24,951 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 27.10 06:12:24 BoogieIcfgContainer [2018-10-27 06:12:24,952 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-10-27 06:12:24,952 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-10-27 06:12:24,952 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-10-27 06:12:24,952 INFO L276 PluginConnector]: Witness Printer initialized [2018-10-27 06:12:24,955 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 06:12:18" (3/4) ... [2018-10-27 06:12:24,958 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-10-27 06:12:25,007 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_b9891c4d-430c-4d8b-bfcc-ae64906cf73c/bin-2019/uautomizer/witness.graphml [2018-10-27 06:12:25,007 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-10-27 06:12:25,008 INFO L168 Benchmark]: Toolchain (without parser) took 7749.94 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 248.5 MB). Free memory was 954.4 MB in the beginning and 1.1 GB in the end (delta: -102.3 MB). Peak memory consumption was 146.2 MB. Max. memory is 11.5 GB. [2018-10-27 06:12:25,009 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-27 06:12:25,009 INFO L168 Benchmark]: CACSL2BoogieTranslator took 266.67 ms. Allocated memory is still 1.0 GB. Free memory was 954.4 MB in the beginning and 938.3 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-10-27 06:12:25,009 INFO L168 Benchmark]: Boogie Procedure Inliner took 46.77 ms. Allocated memory is still 1.0 GB. Free memory was 938.3 MB in the beginning and 935.6 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-10-27 06:12:25,009 INFO L168 Benchmark]: Boogie Preprocessor took 100.54 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 191.9 MB). Free memory was 935.6 MB in the beginning and 1.2 GB in the end (delta: -250.3 MB). Peak memory consumption was 19.1 MB. Max. memory is 11.5 GB. [2018-10-27 06:12:25,013 INFO L168 Benchmark]: RCFGBuilder took 1226.30 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 55.5 MB). Peak memory consumption was 55.5 MB. Max. memory is 11.5 GB. [2018-10-27 06:12:25,013 INFO L168 Benchmark]: BuchiAutomizer took 6050.72 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 56.6 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 68.6 MB). Peak memory consumption was 125.3 MB. Max. memory is 11.5 GB. [2018-10-27 06:12:25,014 INFO L168 Benchmark]: Witness Printer took 55.25 ms. Allocated memory is still 1.3 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.1 MB). Peak memory consumption was 5.1 MB. Max. memory is 11.5 GB. [2018-10-27 06:12:25,018 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 266.67 ms. Allocated memory is still 1.0 GB. Free memory was 954.4 MB in the beginning and 938.3 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 46.77 ms. Allocated memory is still 1.0 GB. Free memory was 938.3 MB in the beginning and 935.6 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 100.54 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 191.9 MB). Free memory was 935.6 MB in the beginning and 1.2 GB in the end (delta: -250.3 MB). Peak memory consumption was 19.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1226.30 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 55.5 MB). Peak memory consumption was 55.5 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 6050.72 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 56.6 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 68.6 MB). Peak memory consumption was 125.3 MB. Max. memory is 11.5 GB. * Witness Printer took 55.25 ms. Allocated memory is still 1.3 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.1 MB). Peak memory consumption was 5.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (13 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.13 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 930 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.9s and 14 iterations. TraceHistogramMax:1. Analysis of lassos took 3.8s. Construction of modules took 1.2s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 13. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 13 MinimizatonAttempts, 461 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had 930 states and ocurred in iteration 13. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 4195 SDtfs, 4097 SDslu, 2718 SDs, 0 SdLazy, 186 SolverSat, 98 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.2s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, token=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@9452b26=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@543b260c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@61a30b6b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@23110220=0, T2_E=2, kernel_st=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@150b81d1=0, __retres1=0, tmp___0=0, t2_st=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@27a55e6b=0, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4925b97c=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4c07fdda=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@ead2d33=0, t1_st=0, \result=0, t2_pc=0, local=0, m_st=0, tmp___1=0, E_M=2, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int m_st ; [L18] int t1_st ; [L19] int t2_st ; [L20] int m_i ; [L21] int t1_i ; [L22] int t2_i ; [L23] int M_E = 2; [L24] int T1_E = 2; [L25] int T2_E = 2; [L26] int E_M = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; [L33] int token ; [L35] int local ; [L588] int __retres1 ; [L592] CALL init_model() [L502] m_i = 1 [L503] t1_i = 1 [L504] RET t2_i = 1 [L592] init_model() [L593] CALL start_simulation() [L529] int kernel_st ; [L530] int tmp ; [L531] int tmp___0 ; [L535] kernel_st = 0 [L536] FCALL update_channels() [L537] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 [L231] COND TRUE t2_i == 1 [L232] RET t2_st = 0 [L537] init_threads() [L538] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) [L339] COND FALSE !(T1_E == 0) [L344] COND FALSE !(T2_E == 0) [L349] COND FALSE !(E_M == 0) [L354] COND FALSE !(E_1 == 0) [L359] COND FALSE, RET !(E_2 == 0) [L538] fire_delta_events() [L539] CALL activate_threads() [L407] int tmp ; [L408] int tmp___0 ; [L409] int tmp___1 ; [L413] CALL, EXPR is_master_triggered() [L153] int __retres1 ; [L156] COND FALSE !(m_pc == 1) [L166] __retres1 = 0 [L168] RET return (__retres1); [L413] EXPR is_master_triggered() [L413] tmp = is_master_triggered() [L415] COND FALSE !(\read(tmp)) [L421] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; [L175] COND FALSE !(t1_pc == 1) [L185] __retres1 = 0 [L187] RET return (__retres1); [L421] EXPR is_transmit1_triggered() [L421] tmp___0 = is_transmit1_triggered() [L423] COND FALSE !(\read(tmp___0)) [L429] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; [L194] COND FALSE !(t2_pc == 1) [L204] __retres1 = 0 [L206] RET return (__retres1); [L429] EXPR is_transmit2_triggered() [L429] tmp___1 = is_transmit2_triggered() [L431] COND FALSE, RET !(\read(tmp___1)) [L539] activate_threads() [L540] CALL reset_delta_events() [L372] COND FALSE !(M_E == 1) [L377] COND FALSE !(T1_E == 1) [L382] COND FALSE !(T2_E == 1) [L387] COND FALSE !(E_M == 1) [L392] COND FALSE !(E_1 == 1) [L397] COND FALSE, RET !(E_2 == 1) [L540] reset_delta_events() [L543] COND TRUE 1 [L546] kernel_st = 1 [L547] CALL eval() [L267] int tmp ; Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] RET return (__retres1); [L274] EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...