./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03_true-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03_true-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 460c5a2466ddacef0b654abb4130c31f8265660c ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-10-27 06:06:30,746 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-27 06:06:30,747 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-27 06:06:30,758 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-27 06:06:30,759 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-27 06:06:30,759 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-27 06:06:30,761 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-27 06:06:30,762 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-27 06:06:30,764 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-27 06:06:30,765 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-27 06:06:30,766 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-27 06:06:30,766 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-27 06:06:30,767 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-27 06:06:30,768 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-27 06:06:30,769 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-27 06:06:30,770 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-27 06:06:30,771 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-27 06:06:30,773 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-27 06:06:30,775 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-27 06:06:30,776 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-27 06:06:30,777 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-27 06:06:30,778 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-27 06:06:30,781 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-27 06:06:30,781 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-27 06:06:30,781 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-27 06:06:30,782 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-27 06:06:30,783 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-27 06:06:30,784 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-27 06:06:30,785 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-27 06:06:30,786 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-27 06:06:30,786 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-27 06:06:30,787 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-27 06:06:30,787 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-27 06:06:30,787 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-27 06:06:30,789 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-27 06:06:30,790 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-27 06:06:30,790 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-10-27 06:06:30,804 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-27 06:06:30,804 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-27 06:06:30,805 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-10-27 06:06:30,805 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-10-27 06:06:30,806 INFO L133 SettingsManager]: * Use SBE=true [2018-10-27 06:06:30,806 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-10-27 06:06:30,806 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-10-27 06:06:30,806 INFO L133 SettingsManager]: * Use old map elimination=false [2018-10-27 06:06:30,806 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-10-27 06:06:30,806 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-10-27 06:06:30,807 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-10-27 06:06:30,807 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-27 06:06:30,807 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-27 06:06:30,807 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-10-27 06:06:30,807 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-27 06:06:30,807 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-27 06:06:30,808 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-27 06:06:30,808 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-10-27 06:06:30,808 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-10-27 06:06:30,808 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-10-27 06:06:30,808 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-27 06:06:30,808 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-27 06:06:30,809 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-10-27 06:06:30,809 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-10-27 06:06:30,809 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-27 06:06:30,809 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-10-27 06:06:30,809 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-10-27 06:06:30,809 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-27 06:06:30,809 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-10-27 06:06:30,810 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-10-27 06:06:30,810 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-10-27 06:06:30,811 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 460c5a2466ddacef0b654abb4130c31f8265660c [2018-10-27 06:06:30,838 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-27 06:06:30,850 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-27 06:06:30,853 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-27 06:06:30,854 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-27 06:06:30,855 INFO L276 PluginConnector]: CDTParser initialized [2018-10-27 06:06:30,856 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.03_true-unreach-call_false-termination.cil.c [2018-10-27 06:06:30,912 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer/data/a8e081d33/49e95c5d4aec4d3c9320677fb8ce89d8/FLAGe4b5de0ce [2018-10-27 06:06:31,294 INFO L298 CDTParser]: Found 1 translation units. [2018-10-27 06:06:31,295 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/sv-benchmarks/c/systemc/token_ring.03_true-unreach-call_false-termination.cil.c [2018-10-27 06:06:31,305 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer/data/a8e081d33/49e95c5d4aec4d3c9320677fb8ce89d8/FLAGe4b5de0ce [2018-10-27 06:06:31,320 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer/data/a8e081d33/49e95c5d4aec4d3c9320677fb8ce89d8 [2018-10-27 06:06:31,323 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-27 06:06:31,325 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-27 06:06:31,326 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-27 06:06:31,326 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-27 06:06:31,331 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-27 06:06:31,332 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.10 06:06:31" (1/1) ... [2018-10-27 06:06:31,335 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@41fcdb68 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31, skipping insertion in model container [2018-10-27 06:06:31,335 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.10 06:06:31" (1/1) ... [2018-10-27 06:06:31,345 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-27 06:06:31,382 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-27 06:06:31,568 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-27 06:06:31,574 INFO L189 MainTranslator]: Completed pre-run [2018-10-27 06:06:31,621 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-27 06:06:31,640 INFO L193 MainTranslator]: Completed translation [2018-10-27 06:06:31,640 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31 WrapperNode [2018-10-27 06:06:31,640 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-27 06:06:31,641 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-27 06:06:31,641 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-27 06:06:31,642 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-27 06:06:31,656 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31" (1/1) ... [2018-10-27 06:06:31,663 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31" (1/1) ... [2018-10-27 06:06:31,701 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-27 06:06:31,702 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-27 06:06:31,702 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-27 06:06:31,702 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-27 06:06:31,712 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31" (1/1) ... [2018-10-27 06:06:31,713 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31" (1/1) ... [2018-10-27 06:06:31,717 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31" (1/1) ... [2018-10-27 06:06:31,717 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31" (1/1) ... [2018-10-27 06:06:31,738 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31" (1/1) ... [2018-10-27 06:06:31,838 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31" (1/1) ... [2018-10-27 06:06:31,841 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31" (1/1) ... [2018-10-27 06:06:31,845 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-27 06:06:31,846 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-27 06:06:31,846 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-27 06:06:31,846 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-27 06:06:31,847 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-10-27 06:06:31,935 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-27 06:06:31,935 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-27 06:06:33,580 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-27 06:06:33,580 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 06:06:33 BoogieIcfgContainer [2018-10-27 06:06:33,581 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-27 06:06:33,581 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-10-27 06:06:33,581 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-10-27 06:06:33,586 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-10-27 06:06:33,587 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-10-27 06:06:33,587 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 27.10 06:06:31" (1/3) ... [2018-10-27 06:06:33,589 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@27abe02b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 27.10 06:06:33, skipping insertion in model container [2018-10-27 06:06:33,589 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-10-27 06:06:33,589 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.10 06:06:31" (2/3) ... [2018-10-27 06:06:33,590 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@27abe02b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 27.10 06:06:33, skipping insertion in model container [2018-10-27 06:06:33,590 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-10-27 06:06:33,591 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 06:06:33" (3/3) ... [2018-10-27 06:06:33,593 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.03_true-unreach-call_false-termination.cil.c [2018-10-27 06:06:33,669 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-10-27 06:06:33,670 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-10-27 06:06:33,670 INFO L375 BuchiCegarLoop]: Hoare is false [2018-10-27 06:06:33,670 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-10-27 06:06:33,670 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-10-27 06:06:33,672 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-10-27 06:06:33,672 INFO L379 BuchiCegarLoop]: Difference is false [2018-10-27 06:06:33,672 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-10-27 06:06:33,672 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-10-27 06:06:33,705 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 330 states. [2018-10-27 06:06:33,759 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 271 [2018-10-27 06:06:33,759 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:33,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:33,774 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:33,775 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:33,775 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-10-27 06:06:33,775 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 330 states. [2018-10-27 06:06:33,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 271 [2018-10-27 06:06:33,788 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:33,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:33,795 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:33,795 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:33,806 INFO L793 eck$LassoCheckResult]: Stem: 117#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 5#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 44#L631true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 113#L275true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 174#L282true assume !(~m_i~0 == 1);~m_st~0 := 2; 178#L282-2true assume ~t1_i~0 == 1;~t1_st~0 := 0; 190#L287-1true assume !(~t2_i~0 == 1);~t2_st~0 := 2; 96#L292-1true assume !(~t3_i~0 == 1);~t3_st~0 := 2; 112#L297-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 207#L419true assume !(~M_E~0 == 0); 212#L419-2true assume !(~T1_E~0 == 0); 84#L424-1true assume ~T2_E~0 == 0;~T2_E~0 := 1; 133#L429-1true assume !(~T3_E~0 == 0); 159#L434-1true assume !(~E_M~0 == 0); 15#L439-1true assume !(~E_1~0 == 0); 36#L444-1true assume !(~E_2~0 == 0); 252#L449-1true assume !(~E_3~0 == 0); 285#L454-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 106#L198true assume ~m_pc~0 == 1; 187#L199true assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 107#L209true is_master_triggered_#res := is_master_triggered_~__retres1~0; 188#L210true activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 30#L521true assume !(activate_threads_~tmp~1 != 0); 32#L521-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 308#L217true assume !(~t1_pc~0 == 1); 300#L217-2true is_transmit1_triggered_~__retres1~1 := 0; 309#L228true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40#L229true activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 228#L529true assume !(activate_threads_~tmp___0~0 != 0); 232#L529-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 157#L236true assume ~t2_pc~0 == 1; 91#L237true assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 158#L247true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 92#L248true activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 235#L537true assume !(activate_threads_~tmp___1~0 != 0); 243#L537-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 171#L255true assume !(~t3_pc~0 == 1); 320#L255-2true is_transmit3_triggered_~__retres1~3 := 0; 172#L266true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 281#L267true activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 109#L545true assume !(activate_threads_~tmp___2~0 != 0); 116#L545-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 155#L467true assume !(~M_E~0 == 1); 160#L467-2true assume !(~T1_E~0 == 1); 13#L472-1true assume ~T2_E~0 == 1;~T2_E~0 := 2; 34#L477-1true assume !(~T3_E~0 == 1); 247#L482-1true assume !(~E_M~0 == 1); 283#L487-1true assume !(~E_1~0 == 1); 321#L492-1true assume !(~E_2~0 == 1); 173#L497-1true assume !(~E_3~0 == 1); 191#L502-1true assume { :end_inline_reset_delta_events } true; 312#L668-3true [2018-10-27 06:06:33,807 INFO L795 eck$LassoCheckResult]: Loop: 312#L668-3true assume true; 327#L668-1true assume !false; 258#L669true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 254#L394true assume !true; 163#L409true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 110#L275-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 218#L419-3true assume ~M_E~0 == 0;~M_E~0 := 1; 194#L419-5true assume ~T1_E~0 == 0;~T1_E~0 := 1; 97#L424-3true assume ~T2_E~0 == 0;~T2_E~0 := 1; 142#L429-3true assume ~T3_E~0 == 0;~T3_E~0 := 1; 162#L434-3true assume ~E_M~0 == 0;~E_M~0 := 1; 6#L439-3true assume ~E_1~0 == 0;~E_1~0 := 1; 25#L444-3true assume !(~E_2~0 == 0); 50#L449-3true assume ~E_3~0 == 0;~E_3~0 := 1; 265#L454-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87#L198-15true assume ~m_pc~0 == 1; 199#L199-5true assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 122#L209-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 200#L210-5true activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 23#L521-15true assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 12#L521-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 278#L217-15true assume ~t1_pc~0 == 1; 51#L218-5true assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 292#L228-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52#L229-5true activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 186#L529-15true assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 189#L529-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 111#L236-15true assume !(~t2_pc~0 == 1); 105#L236-17true is_transmit2_triggered_~__retres1~2 := 0; 136#L247-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 219#L248-5true activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 47#L537-15true assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 31#L537-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 287#L255-15true assume ~t3_pc~0 == 1; 240#L256-5true assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 316#L266-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 242#L267-5true activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 226#L545-15true assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 230#L545-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 161#L467-3true assume ~M_E~0 == 1;~M_E~0 := 2; 152#L467-5true assume !(~T1_E~0 == 1); 16#L472-3true assume ~T2_E~0 == 1;~T2_E~0 := 2; 38#L477-3true assume ~T3_E~0 == 1;~T3_E~0 := 2; 257#L482-3true assume ~E_M~0 == 1;~E_M~0 := 2; 262#L487-3true assume ~E_1~0 == 1;~E_1~0 := 2; 293#L492-3true assume ~E_2~0 == 1;~E_2~0 := 2; 164#L497-3true assume ~E_3~0 == 1;~E_3~0 := 2; 176#L502-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 169#L310-1true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 168#L332-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 270#L333-1true start_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 11#L687true assume !(start_simulation_~tmp~3 == 0); 3#L687-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 324#L310-2true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 170#L332-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 272#L333-2true stop_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 43#L642true assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 146#L649true stop_simulation_#res := stop_simulation_~__retres2~0; 76#L650true start_simulation_#t~ret12 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 198#L700true assume !(start_simulation_~tmp___0~1 != 0); 312#L668-3true [2018-10-27 06:06:33,813 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:33,814 INFO L82 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2018-10-27 06:06:33,816 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:33,817 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:33,861 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:33,861 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:33,861 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:33,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:33,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:33,975 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:33,976 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:33,981 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:06:33,981 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:33,981 INFO L82 PathProgramCache]: Analyzing trace with hash -65150788, now seen corresponding path program 1 times [2018-10-27 06:06:33,982 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:33,982 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:33,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:33,983 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:33,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:33,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:34,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:34,002 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:34,003 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:06:34,005 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:06:34,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:34,022 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:34,025 INFO L87 Difference]: Start difference. First operand 330 states. Second operand 3 states. [2018-10-27 06:06:34,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:34,088 INFO L93 Difference]: Finished difference Result 329 states and 487 transitions. [2018-10-27 06:06:34,092 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:34,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 329 states and 487 transitions. [2018-10-27 06:06:34,100 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 269 [2018-10-27 06:06:34,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 329 states to 324 states and 482 transitions. [2018-10-27 06:06:34,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 324 [2018-10-27 06:06:34,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 324 [2018-10-27 06:06:34,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 324 states and 482 transitions. [2018-10-27 06:06:34,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:34,112 INFO L705 BuchiCegarLoop]: Abstraction has 324 states and 482 transitions. [2018-10-27 06:06:34,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324 states and 482 transitions. [2018-10-27 06:06:34,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324 to 324. [2018-10-27 06:06:34,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 324 states. [2018-10-27 06:06:34,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324 states to 324 states and 482 transitions. [2018-10-27 06:06:34,152 INFO L728 BuchiCegarLoop]: Abstraction has 324 states and 482 transitions. [2018-10-27 06:06:34,153 INFO L608 BuchiCegarLoop]: Abstraction has 324 states and 482 transitions. [2018-10-27 06:06:34,153 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-10-27 06:06:34,153 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 324 states and 482 transitions. [2018-10-27 06:06:34,156 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 269 [2018-10-27 06:06:34,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:34,157 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:34,158 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:34,159 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:34,159 INFO L793 eck$LassoCheckResult]: Stem: 877#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 673#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 739#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 873#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 930#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 932#L287-1 assume !(~t2_i~0 == 1);~t2_st~0 := 2; 840#L292-1 assume !(~t3_i~0 == 1);~t3_st~0 := 2; 841#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 871#L419 assume !(~M_E~0 == 0); 942#L419-2 assume !(~T1_E~0 == 0); 817#L424-1 assume ~T2_E~0 == 0;~T2_E~0 := 1; 818#L429-1 assume !(~T3_E~0 == 0); 895#L434-1 assume !(~E_M~0 == 0); 693#L439-1 assume !(~E_1~0 == 0); 694#L444-1 assume !(~E_2~0 == 0); 725#L449-1 assume !(~E_3~0 == 0); 972#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 858#L198 assume ~m_pc~0 == 1; 859#L199 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 863#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 864#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 716#L521 assume !(activate_threads_~tmp~1 != 0); 717#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 722#L217 assume !(~t1_pc~0 == 1); 729#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 730#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 733#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 734#L529 assume !(activate_threads_~tmp___0~0 != 0); 950#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 913#L236 assume ~t2_pc~0 == 1; 830#L237 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 831#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 834#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 835#L537 assume !(activate_threads_~tmp___1~0 != 0); 955#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 923#L255 assume !(~t3_pc~0 == 1); 924#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 926#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 927#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 865#L545 assume !(activate_threads_~tmp___2~0 != 0); 866#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 876#L467 assume !(~M_E~0 == 1); 912#L467-2 assume !(~T1_E~0 == 1); 691#L472-1 assume ~T2_E~0 == 1;~T2_E~0 := 2; 692#L477-1 assume !(~T3_E~0 == 1); 723#L482-1 assume !(~E_M~0 == 1); 967#L487-1 assume !(~E_1~0 == 1); 987#L492-1 assume !(~E_2~0 == 1); 928#L497-1 assume !(~E_3~0 == 1); 929#L502-1 assume { :end_inline_reset_delta_events } true; 935#L668-3 [2018-10-27 06:06:34,159 INFO L795 eck$LassoCheckResult]: Loop: 935#L668-3 assume true; 990#L668-1 assume !false; 979#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 824#L394 assume true; 945#L342-1 assume !false; 917#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 918#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 677#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 919#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 836#L347 assume !(eval_~tmp~0 != 0); 838#L409 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 867#L275-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 868#L419-3 assume ~M_E~0 == 0;~M_E~0 := 1; 937#L419-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 842#L424-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 843#L429-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 907#L434-3 assume ~E_M~0 == 0;~E_M~0 := 1; 674#L439-3 assume ~E_1~0 == 0;~E_1~0 := 1; 675#L444-3 assume !(~E_2~0 == 0); 708#L449-3 assume ~E_3~0 == 0;~E_3~0 := 1; 750#L454-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 825#L198-15 assume !(~m_pc~0 == 1); 808#L198-17 is_master_triggered_~__retres1~0 := 0; 809#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 883#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 705#L521-15 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 687#L521-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 688#L217-15 assume ~t1_pc~0 == 1; 747#L218-5 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 748#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 751#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 752#L529-15 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 934#L529-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 869#L236-15 assume ~t2_pc~0 == 1; 870#L237-5 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 857#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 898#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 742#L537-15 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 718#L537-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 719#L255-15 assume !(~t3_pc~0 == 1); 960#L255-17 is_transmit3_triggered_~__retres1~3 := 0; 959#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 961#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 948#L545-15 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 949#L545-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 914#L467-3 assume ~M_E~0 == 1;~M_E~0 := 2; 911#L467-5 assume !(~T1_E~0 == 1); 695#L472-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 696#L477-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 727#L482-3 assume ~E_M~0 == 1;~E_M~0 := 2; 977#L487-3 assume ~E_1~0 == 1;~E_1~0 := 2; 981#L492-3 assume ~E_2~0 == 1;~E_2~0 := 2; 915#L497-3 assume ~E_3~0 == 1;~E_3~0 := 2; 916#L502-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 921#L310-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 680#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 920#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 685#L687 assume !(start_simulation_~tmp~3 == 0); 668#L687-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 669#L310-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 683#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 922#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 737#L642 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 738#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 798#L650 start_simulation_#t~ret12 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 799#L700 assume !(start_simulation_~tmp___0~1 != 0); 935#L668-3 [2018-10-27 06:06:34,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:34,160 INFO L82 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2018-10-27 06:06:34,160 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:34,160 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:34,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,161 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:34,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:34,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:34,228 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:34,229 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:34,229 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:06:34,229 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:34,229 INFO L82 PathProgramCache]: Analyzing trace with hash 87548038, now seen corresponding path program 1 times [2018-10-27 06:06:34,230 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:34,230 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:34,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,231 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:34,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:34,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:34,398 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:34,399 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:34,399 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:06:34,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:34,400 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:34,400 INFO L87 Difference]: Start difference. First operand 324 states and 482 transitions. cyclomatic complexity: 159 Second operand 3 states. [2018-10-27 06:06:34,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:34,461 INFO L93 Difference]: Finished difference Result 324 states and 481 transitions. [2018-10-27 06:06:34,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:34,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 324 states and 481 transitions. [2018-10-27 06:06:34,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 269 [2018-10-27 06:06:34,473 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 324 states to 324 states and 481 transitions. [2018-10-27 06:06:34,473 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 324 [2018-10-27 06:06:34,474 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 324 [2018-10-27 06:06:34,474 INFO L73 IsDeterministic]: Start isDeterministic. Operand 324 states and 481 transitions. [2018-10-27 06:06:34,475 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:34,476 INFO L705 BuchiCegarLoop]: Abstraction has 324 states and 481 transitions. [2018-10-27 06:06:34,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324 states and 481 transitions. [2018-10-27 06:06:34,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324 to 324. [2018-10-27 06:06:34,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 324 states. [2018-10-27 06:06:34,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324 states to 324 states and 481 transitions. [2018-10-27 06:06:34,499 INFO L728 BuchiCegarLoop]: Abstraction has 324 states and 481 transitions. [2018-10-27 06:06:34,499 INFO L608 BuchiCegarLoop]: Abstraction has 324 states and 481 transitions. [2018-10-27 06:06:34,499 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-10-27 06:06:34,499 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 324 states and 481 transitions. [2018-10-27 06:06:34,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 269 [2018-10-27 06:06:34,501 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:34,501 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:34,505 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:34,505 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:34,505 INFO L793 eck$LassoCheckResult]: Stem: 1534#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1329#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1330#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1394#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1528#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 1585#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 1587#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 1495#L292-1 assume !(~t3_i~0 == 1);~t3_st~0 := 2; 1496#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1526#L419 assume !(~M_E~0 == 0); 1597#L419-2 assume !(~T1_E~0 == 0); 1472#L424-1 assume ~T2_E~0 == 0;~T2_E~0 := 1; 1473#L429-1 assume !(~T3_E~0 == 0); 1552#L434-1 assume !(~E_M~0 == 0); 1348#L439-1 assume !(~E_1~0 == 0); 1349#L444-1 assume !(~E_2~0 == 0); 1380#L449-1 assume !(~E_3~0 == 0); 1627#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1513#L198 assume ~m_pc~0 == 1; 1514#L199 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 1518#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1519#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1371#L521 assume !(activate_threads_~tmp~1 != 0); 1372#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1377#L217 assume !(~t1_pc~0 == 1); 1384#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 1385#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1386#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1387#L529 assume !(activate_threads_~tmp___0~0 != 0); 1605#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1568#L236 assume ~t2_pc~0 == 1; 1485#L237 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1486#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1488#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1489#L537 assume !(activate_threads_~tmp___1~0 != 0); 1607#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1578#L255 assume !(~t3_pc~0 == 1); 1579#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 1581#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1582#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1520#L545 assume !(activate_threads_~tmp___2~0 != 0); 1521#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1531#L467 assume !(~M_E~0 == 1); 1567#L467-2 assume !(~T1_E~0 == 1); 1344#L472-1 assume ~T2_E~0 == 1;~T2_E~0 := 2; 1345#L477-1 assume !(~T3_E~0 == 1); 1378#L482-1 assume !(~E_M~0 == 1); 1622#L487-1 assume !(~E_1~0 == 1); 1642#L492-1 assume !(~E_2~0 == 1); 1583#L497-1 assume !(~E_3~0 == 1); 1584#L502-1 assume { :end_inline_reset_delta_events } true; 1590#L668-3 [2018-10-27 06:06:34,505 INFO L795 eck$LassoCheckResult]: Loop: 1590#L668-3 assume true; 1645#L668-1 assume !false; 1634#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1476#L394 assume true; 1600#L342-1 assume !false; 1572#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1573#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 1332#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1574#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1490#L347 assume !(eval_~tmp~0 != 0); 1492#L409 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1522#L275-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1523#L419-3 assume ~M_E~0 == 0;~M_E~0 := 1; 1592#L419-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 1497#L424-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 1498#L429-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 1561#L434-3 assume ~E_M~0 == 0;~E_M~0 := 1; 1327#L439-3 assume ~E_1~0 == 0;~E_1~0 := 1; 1328#L444-3 assume !(~E_2~0 == 0); 1363#L449-3 assume ~E_3~0 == 0;~E_3~0 := 1; 1402#L454-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1477#L198-15 assume !(~m_pc~0 == 1); 1460#L198-17 is_master_triggered_~__retres1~0 := 0; 1461#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1538#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1360#L521-15 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1342#L521-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1343#L217-15 assume ~t1_pc~0 == 1; 1403#L218-5 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 1404#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1406#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1407#L529-15 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 1589#L529-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1524#L236-15 assume ~t2_pc~0 == 1; 1525#L237-5 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1512#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1553#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1397#L537-15 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 1373#L537-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1374#L255-15 assume ~t3_pc~0 == 1; 1613#L256-5 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 1614#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1617#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1603#L545-15 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 1604#L545-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1569#L467-3 assume ~M_E~0 == 1;~M_E~0 := 2; 1566#L467-5 assume !(~T1_E~0 == 1); 1350#L472-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 1351#L477-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 1382#L482-3 assume ~E_M~0 == 1;~E_M~0 := 2; 1633#L487-3 assume ~E_1~0 == 1;~E_1~0 := 2; 1636#L492-3 assume ~E_2~0 == 1;~E_2~0 := 2; 1570#L497-3 assume ~E_3~0 == 1;~E_3~0 := 2; 1571#L502-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1576#L310-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 1335#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1575#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 1340#L687 assume !(start_simulation_~tmp~3 == 0); 1323#L687-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1324#L310-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 1338#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1577#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 1392#L642 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 1393#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 1453#L650 start_simulation_#t~ret12 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 1454#L700 assume !(start_simulation_~tmp___0~1 != 0); 1590#L668-3 [2018-10-27 06:06:34,506 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:34,506 INFO L82 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2018-10-27 06:06:34,506 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:34,506 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:34,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,507 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:34,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:34,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:34,619 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:34,620 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:34,622 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:06:34,622 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:34,622 INFO L82 PathProgramCache]: Analyzing trace with hash 1760065669, now seen corresponding path program 1 times [2018-10-27 06:06:34,623 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:34,623 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:34,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,624 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:34,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:34,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:34,687 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:34,687 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:34,687 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:06:34,687 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:34,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:34,688 INFO L87 Difference]: Start difference. First operand 324 states and 481 transitions. cyclomatic complexity: 158 Second operand 3 states. [2018-10-27 06:06:34,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:34,698 INFO L93 Difference]: Finished difference Result 324 states and 480 transitions. [2018-10-27 06:06:34,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:34,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 324 states and 480 transitions. [2018-10-27 06:06:34,703 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 269 [2018-10-27 06:06:34,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 324 states to 324 states and 480 transitions. [2018-10-27 06:06:34,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 324 [2018-10-27 06:06:34,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 324 [2018-10-27 06:06:34,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 324 states and 480 transitions. [2018-10-27 06:06:34,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:34,707 INFO L705 BuchiCegarLoop]: Abstraction has 324 states and 480 transitions. [2018-10-27 06:06:34,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324 states and 480 transitions. [2018-10-27 06:06:34,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324 to 324. [2018-10-27 06:06:34,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 324 states. [2018-10-27 06:06:34,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324 states to 324 states and 480 transitions. [2018-10-27 06:06:34,725 INFO L728 BuchiCegarLoop]: Abstraction has 324 states and 480 transitions. [2018-10-27 06:06:34,726 INFO L608 BuchiCegarLoop]: Abstraction has 324 states and 480 transitions. [2018-10-27 06:06:34,726 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-10-27 06:06:34,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 324 states and 480 transitions. [2018-10-27 06:06:34,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 269 [2018-10-27 06:06:34,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:34,740 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:34,742 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:34,742 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:34,742 INFO L793 eck$LassoCheckResult]: Stem: 2187#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1982#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1983#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2049#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2182#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 2240#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 2242#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 2150#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 2151#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2181#L419 assume !(~M_E~0 == 0); 2252#L419-2 assume !(~T1_E~0 == 0); 2124#L424-1 assume ~T2_E~0 == 0;~T2_E~0 := 1; 2125#L429-1 assume !(~T3_E~0 == 0); 2205#L434-1 assume !(~E_M~0 == 0); 2003#L439-1 assume !(~E_1~0 == 0); 2004#L444-1 assume !(~E_2~0 == 0); 2035#L449-1 assume !(~E_3~0 == 0); 2282#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2168#L198 assume ~m_pc~0 == 1; 2169#L199 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 2171#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2172#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2026#L521 assume !(activate_threads_~tmp~1 != 0); 2027#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2030#L217 assume !(~t1_pc~0 == 1); 2039#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 2040#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2041#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2042#L529 assume !(activate_threads_~tmp___0~0 != 0); 2260#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2223#L236 assume ~t2_pc~0 == 1; 2140#L237 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 2141#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2143#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2144#L537 assume !(activate_threads_~tmp___1~0 != 0); 2262#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2233#L255 assume !(~t3_pc~0 == 1); 2234#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 2236#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2237#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2175#L545 assume !(activate_threads_~tmp___2~0 != 0); 2176#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2186#L467 assume !(~M_E~0 == 1); 2222#L467-2 assume !(~T1_E~0 == 1); 1999#L472-1 assume ~T2_E~0 == 1;~T2_E~0 := 2; 2000#L477-1 assume !(~T3_E~0 == 1); 2033#L482-1 assume !(~E_M~0 == 1); 2277#L487-1 assume !(~E_1~0 == 1); 2297#L492-1 assume !(~E_2~0 == 1); 2238#L497-1 assume !(~E_3~0 == 1); 2239#L502-1 assume { :end_inline_reset_delta_events } true; 2245#L668-3 [2018-10-27 06:06:34,743 INFO L795 eck$LassoCheckResult]: Loop: 2245#L668-3 assume true; 2300#L668-1 assume !false; 2289#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2131#L394 assume true; 2255#L342-1 assume !false; 2227#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2228#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 1987#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2229#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2145#L347 assume !(eval_~tmp~0 != 0); 2147#L409 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2177#L275-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2178#L419-3 assume ~M_E~0 == 0;~M_E~0 := 1; 2247#L419-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 2152#L424-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 2153#L429-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 2216#L434-3 assume ~E_M~0 == 0;~E_M~0 := 1; 1984#L439-3 assume ~E_1~0 == 0;~E_1~0 := 1; 1985#L444-3 assume !(~E_2~0 == 0); 2018#L449-3 assume ~E_3~0 == 0;~E_3~0 := 1; 2057#L454-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2132#L198-15 assume !(~m_pc~0 == 1); 2115#L198-17 is_master_triggered_~__retres1~0 := 0; 2116#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2193#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2015#L521-15 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1997#L521-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1998#L217-15 assume ~t1_pc~0 == 1; 2058#L218-5 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 2059#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2061#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2062#L529-15 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 2244#L529-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2179#L236-15 assume ~t2_pc~0 == 1; 2180#L237-5 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 2167#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2208#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2052#L537-15 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 2028#L537-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2029#L255-15 assume ~t3_pc~0 == 1; 2268#L256-5 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 2269#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2272#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2258#L545-15 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 2259#L545-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2224#L467-3 assume ~M_E~0 == 1;~M_E~0 := 2; 2221#L467-5 assume !(~T1_E~0 == 1); 2005#L472-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 2006#L477-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 2037#L482-3 assume ~E_M~0 == 1;~E_M~0 := 2; 2288#L487-3 assume ~E_1~0 == 1;~E_1~0 := 2; 2291#L492-3 assume ~E_2~0 == 1;~E_2~0 := 2; 2225#L497-3 assume ~E_3~0 == 1;~E_3~0 := 2; 2226#L502-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2231#L310-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 1990#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2230#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 1995#L687 assume !(start_simulation_~tmp~3 == 0); 1978#L687-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1979#L310-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 1993#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2232#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 2047#L642 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 2048#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 2108#L650 start_simulation_#t~ret12 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 2109#L700 assume !(start_simulation_~tmp___0~1 != 0); 2245#L668-3 [2018-10-27 06:06:34,743 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:34,743 INFO L82 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2018-10-27 06:06:34,743 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:34,743 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:34,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,757 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:34,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:34,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:34,814 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:34,815 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:06:34,815 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:06:34,815 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:34,815 INFO L82 PathProgramCache]: Analyzing trace with hash 1760065669, now seen corresponding path program 2 times [2018-10-27 06:06:34,816 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:34,820 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:34,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,821 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:34,821 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:34,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:34,904 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:34,904 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:34,905 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:06:34,905 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:34,905 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:34,905 INFO L87 Difference]: Start difference. First operand 324 states and 480 transitions. cyclomatic complexity: 157 Second operand 3 states. [2018-10-27 06:06:34,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:34,942 INFO L93 Difference]: Finished difference Result 324 states and 475 transitions. [2018-10-27 06:06:34,942 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:34,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 324 states and 475 transitions. [2018-10-27 06:06:34,946 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 269 [2018-10-27 06:06:34,948 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 324 states to 324 states and 475 transitions. [2018-10-27 06:06:34,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 324 [2018-10-27 06:06:34,949 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 324 [2018-10-27 06:06:34,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 324 states and 475 transitions. [2018-10-27 06:06:34,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:34,950 INFO L705 BuchiCegarLoop]: Abstraction has 324 states and 475 transitions. [2018-10-27 06:06:34,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324 states and 475 transitions. [2018-10-27 06:06:34,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324 to 324. [2018-10-27 06:06:34,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 324 states. [2018-10-27 06:06:34,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324 states to 324 states and 475 transitions. [2018-10-27 06:06:34,961 INFO L728 BuchiCegarLoop]: Abstraction has 324 states and 475 transitions. [2018-10-27 06:06:34,961 INFO L608 BuchiCegarLoop]: Abstraction has 324 states and 475 transitions. [2018-10-27 06:06:34,961 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-10-27 06:06:34,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 324 states and 475 transitions. [2018-10-27 06:06:34,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 269 [2018-10-27 06:06:34,964 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:34,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:34,967 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:34,967 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:34,967 INFO L793 eck$LassoCheckResult]: Stem: 2842#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2637#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2638#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2704#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2838#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 2895#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 2897#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 2805#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 2806#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2836#L419 assume !(~M_E~0 == 0); 2907#L419-2 assume !(~T1_E~0 == 0); 2779#L424-1 assume !(~T2_E~0 == 0); 2780#L429-1 assume !(~T3_E~0 == 0); 2860#L434-1 assume !(~E_M~0 == 0); 2658#L439-1 assume !(~E_1~0 == 0); 2659#L444-1 assume !(~E_2~0 == 0); 2690#L449-1 assume !(~E_3~0 == 0); 2937#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2823#L198 assume ~m_pc~0 == 1; 2824#L199 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 2828#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2829#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2681#L521 assume !(activate_threads_~tmp~1 != 0); 2682#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2687#L217 assume !(~t1_pc~0 == 1); 2694#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 2695#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2696#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2697#L529 assume !(activate_threads_~tmp___0~0 != 0); 2915#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2878#L236 assume ~t2_pc~0 == 1; 2795#L237 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 2796#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2798#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2799#L537 assume !(activate_threads_~tmp___1~0 != 0); 2920#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2888#L255 assume !(~t3_pc~0 == 1); 2889#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 2891#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2892#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2830#L545 assume !(activate_threads_~tmp___2~0 != 0); 2831#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2841#L467 assume !(~M_E~0 == 1); 2877#L467-2 assume !(~T1_E~0 == 1); 2656#L472-1 assume !(~T2_E~0 == 1); 2657#L477-1 assume !(~T3_E~0 == 1); 2688#L482-1 assume !(~E_M~0 == 1); 2932#L487-1 assume !(~E_1~0 == 1); 2952#L492-1 assume !(~E_2~0 == 1); 2893#L497-1 assume !(~E_3~0 == 1); 2894#L502-1 assume { :end_inline_reset_delta_events } true; 2900#L668-3 [2018-10-27 06:06:34,968 INFO L795 eck$LassoCheckResult]: Loop: 2900#L668-3 assume true; 2955#L668-1 assume !false; 2944#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2786#L394 assume true; 2910#L342-1 assume !false; 2882#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2883#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 2642#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2884#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2800#L347 assume !(eval_~tmp~0 != 0); 2802#L409 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2832#L275-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2833#L419-3 assume ~M_E~0 == 0;~M_E~0 := 1; 2902#L419-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 2807#L424-3 assume !(~T2_E~0 == 0); 2808#L429-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 2871#L434-3 assume ~E_M~0 == 0;~E_M~0 := 1; 2639#L439-3 assume ~E_1~0 == 0;~E_1~0 := 1; 2640#L444-3 assume !(~E_2~0 == 0); 2673#L449-3 assume ~E_3~0 == 0;~E_3~0 := 1; 2712#L454-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2787#L198-15 assume !(~m_pc~0 == 1); 2770#L198-17 is_master_triggered_~__retres1~0 := 0; 2771#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2848#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2670#L521-15 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 2652#L521-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2653#L217-15 assume ~t1_pc~0 == 1; 2713#L218-5 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 2714#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2716#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2717#L529-15 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 2899#L529-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2834#L236-15 assume ~t2_pc~0 == 1; 2835#L237-5 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 2822#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2863#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2707#L537-15 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 2683#L537-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2684#L255-15 assume ~t3_pc~0 == 1; 2923#L256-5 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 2924#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2926#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2912#L545-15 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 2913#L545-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2879#L467-3 assume ~M_E~0 == 1;~M_E~0 := 2; 2876#L467-5 assume !(~T1_E~0 == 1); 2660#L472-3 assume !(~T2_E~0 == 1); 2661#L477-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 2692#L482-3 assume ~E_M~0 == 1;~E_M~0 := 2; 2942#L487-3 assume ~E_1~0 == 1;~E_1~0 := 2; 2946#L492-3 assume ~E_2~0 == 1;~E_2~0 := 2; 2880#L497-3 assume ~E_3~0 == 1;~E_3~0 := 2; 2881#L502-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2886#L310-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 2645#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2885#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 2650#L687 assume !(start_simulation_~tmp~3 == 0); 2633#L687-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2634#L310-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 2648#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2887#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 2702#L642 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 2703#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 2763#L650 start_simulation_#t~ret12 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 2764#L700 assume !(start_simulation_~tmp___0~1 != 0); 2900#L668-3 [2018-10-27 06:06:34,968 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:34,968 INFO L82 PathProgramCache]: Analyzing trace with hash -465084349, now seen corresponding path program 1 times [2018-10-27 06:06:34,968 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:34,969 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:34,969 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,970 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:06:34,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:34,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:35,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:35,019 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:35,019 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:06:35,020 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:06:35,020 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:35,020 INFO L82 PathProgramCache]: Analyzing trace with hash 1609461957, now seen corresponding path program 1 times [2018-10-27 06:06:35,020 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:35,020 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:35,021 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:35,021 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:35,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:35,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:35,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:35,114 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:35,114 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:35,114 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:06:35,115 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:35,115 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:35,115 INFO L87 Difference]: Start difference. First operand 324 states and 475 transitions. cyclomatic complexity: 152 Second operand 3 states. [2018-10-27 06:06:35,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:35,557 INFO L93 Difference]: Finished difference Result 584 states and 844 transitions. [2018-10-27 06:06:35,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:35,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 584 states and 844 transitions. [2018-10-27 06:06:35,563 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 528 [2018-10-27 06:06:35,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 584 states to 584 states and 844 transitions. [2018-10-27 06:06:35,568 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 584 [2018-10-27 06:06:35,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 584 [2018-10-27 06:06:35,569 INFO L73 IsDeterministic]: Start isDeterministic. Operand 584 states and 844 transitions. [2018-10-27 06:06:35,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:35,570 INFO L705 BuchiCegarLoop]: Abstraction has 584 states and 844 transitions. [2018-10-27 06:06:35,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 584 states and 844 transitions. [2018-10-27 06:06:35,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 584 to 557. [2018-10-27 06:06:35,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 557 states. [2018-10-27 06:06:35,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 807 transitions. [2018-10-27 06:06:35,586 INFO L728 BuchiCegarLoop]: Abstraction has 557 states and 807 transitions. [2018-10-27 06:06:35,586 INFO L608 BuchiCegarLoop]: Abstraction has 557 states and 807 transitions. [2018-10-27 06:06:35,586 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-10-27 06:06:35,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 807 transitions. [2018-10-27 06:06:35,592 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 501 [2018-10-27 06:06:35,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:35,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:35,593 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:35,593 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:35,594 INFO L793 eck$LassoCheckResult]: Stem: 3760#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3554#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3555#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3621#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3755#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 3810#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 3812#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 3722#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 3723#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3752#L419 assume !(~M_E~0 == 0); 3836#L419-2 assume !(~T1_E~0 == 0); 3699#L424-1 assume !(~T2_E~0 == 0); 3700#L429-1 assume !(~T3_E~0 == 0); 3777#L434-1 assume !(~E_M~0 == 0); 3574#L439-1 assume !(~E_1~0 == 0); 3575#L444-1 assume !(~E_2~0 == 0); 3607#L449-1 assume !(~E_3~0 == 0); 3878#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3740#L198 assume !(~m_pc~0 == 1); 3741#L198-2 is_master_triggered_~__retres1~0 := 0; 3744#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3745#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3598#L521 assume !(activate_threads_~tmp~1 != 0); 3599#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3604#L217 assume !(~t1_pc~0 == 1); 3611#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 3612#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3615#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3616#L529 assume !(activate_threads_~tmp___0~0 != 0); 3853#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3793#L236 assume ~t2_pc~0 == 1; 3712#L237 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 3713#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3720#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3721#L537 assume !(activate_threads_~tmp___1~0 != 0); 3861#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3803#L255 assume !(~t3_pc~0 == 1); 3804#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 3806#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3807#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3748#L545 assume !(activate_threads_~tmp___2~0 != 0); 3749#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3758#L467 assume !(~M_E~0 == 1); 3792#L467-2 assume !(~T1_E~0 == 1); 3572#L472-1 assume !(~T2_E~0 == 1); 3573#L477-1 assume !(~T3_E~0 == 1); 3605#L482-1 assume !(~E_M~0 == 1); 3873#L487-1 assume !(~E_1~0 == 1); 3900#L492-1 assume !(~E_2~0 == 1); 3808#L497-1 assume !(~E_3~0 == 1); 3809#L502-1 assume { :end_inline_reset_delta_events } true; 3820#L668-3 [2018-10-27 06:06:35,594 INFO L795 eck$LassoCheckResult]: Loop: 3820#L668-3 assume true; 3909#L668-1 assume !false; 3885#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 3708#L394 assume true; 3847#L342-1 assume !false; 3848#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4005#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 4001#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3992#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3717#L347 assume !(eval_~tmp~0 != 0); 3719#L409 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3746#L275-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3747#L419-3 assume ~M_E~0 == 0;~M_E~0 := 1; 3824#L419-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 3825#L424-3 assume !(~T2_E~0 == 0); 3999#L429-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 3998#L434-3 assume ~E_M~0 == 0;~E_M~0 := 1; 3997#L439-3 assume ~E_1~0 == 0;~E_1~0 := 1; 3996#L444-3 assume !(~E_2~0 == 0); 3995#L449-3 assume ~E_3~0 == 0;~E_3~0 := 1; 3994#L454-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3701#L198-15 assume !(~m_pc~0 == 1); 3702#L198-17 is_master_triggered_~__retres1~0 := 0; 4088#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4087#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4086#L521-15 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 4085#L521-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4084#L217-15 assume ~t1_pc~0 == 1; 4082#L218-5 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 4081#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4080#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4079#L529-15 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 4078#L529-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4077#L236-15 assume !(~t2_pc~0 == 1); 4075#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 4074#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4073#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4072#L537-15 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 4071#L537-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4070#L255-15 assume ~t3_pc~0 == 1; 4068#L256-5 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 4067#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4066#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4065#L545-15 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 4064#L545-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4063#L467-3 assume ~M_E~0 == 1;~M_E~0 := 2; 4062#L467-5 assume !(~T1_E~0 == 1); 4058#L472-3 assume !(~T2_E~0 == 1); 4056#L477-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 4054#L482-3 assume ~E_M~0 == 1;~E_M~0 := 2; 4053#L487-3 assume ~E_1~0 == 1;~E_1~0 := 2; 4052#L492-3 assume ~E_2~0 == 1;~E_2~0 := 2; 4051#L497-3 assume ~E_3~0 == 1;~E_3~0 := 2; 4050#L502-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4049#L310-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 4045#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4044#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 4043#L687 assume !(start_simulation_~tmp~3 == 0); 3548#L687-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3549#L310-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 4057#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4055#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 3619#L642 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 3620#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 3680#L650 start_simulation_#t~ret12 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 3681#L700 assume !(start_simulation_~tmp___0~1 != 0); 3820#L668-3 [2018-10-27 06:06:35,594 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:35,595 INFO L82 PathProgramCache]: Analyzing trace with hash -2041642108, now seen corresponding path program 1 times [2018-10-27 06:06:35,595 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:35,595 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:35,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:35,607 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:35,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:35,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:35,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:35,707 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:35,708 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:06:35,708 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:06:35,708 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:35,708 INFO L82 PathProgramCache]: Analyzing trace with hash 32904198, now seen corresponding path program 1 times [2018-10-27 06:06:35,708 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:35,709 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:35,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:35,712 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:35,712 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:35,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:35,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:35,774 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:35,774 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:35,774 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:06:35,774 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:35,774 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:35,775 INFO L87 Difference]: Start difference. First operand 557 states and 807 transitions. cyclomatic complexity: 252 Second operand 3 states. [2018-10-27 06:06:36,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:36,047 INFO L93 Difference]: Finished difference Result 989 states and 1420 transitions. [2018-10-27 06:06:36,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:36,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 989 states and 1420 transitions. [2018-10-27 06:06:36,056 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 928 [2018-10-27 06:06:36,062 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 989 states to 989 states and 1420 transitions. [2018-10-27 06:06:36,062 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 989 [2018-10-27 06:06:36,063 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 989 [2018-10-27 06:06:36,063 INFO L73 IsDeterministic]: Start isDeterministic. Operand 989 states and 1420 transitions. [2018-10-27 06:06:36,066 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:36,066 INFO L705 BuchiCegarLoop]: Abstraction has 989 states and 1420 transitions. [2018-10-27 06:06:36,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 989 states and 1420 transitions. [2018-10-27 06:06:36,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 989 to 983. [2018-10-27 06:06:36,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 983 states. [2018-10-27 06:06:36,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 983 states to 983 states and 1414 transitions. [2018-10-27 06:06:36,090 INFO L728 BuchiCegarLoop]: Abstraction has 983 states and 1414 transitions. [2018-10-27 06:06:36,091 INFO L608 BuchiCegarLoop]: Abstraction has 983 states and 1414 transitions. [2018-10-27 06:06:36,091 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-10-27 06:06:36,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 983 states and 1414 transitions. [2018-10-27 06:06:36,098 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 922 [2018-10-27 06:06:36,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:36,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:36,100 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:36,106 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:36,107 INFO L793 eck$LassoCheckResult]: Stem: 5305#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 5105#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 5106#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5172#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5300#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 5360#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 5362#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 5270#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 5271#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5299#L419 assume !(~M_E~0 == 0); 5384#L419-2 assume !(~T1_E~0 == 0); 5247#L424-1 assume !(~T2_E~0 == 0); 5248#L429-1 assume !(~T3_E~0 == 0); 5321#L434-1 assume !(~E_M~0 == 0); 5126#L439-1 assume !(~E_1~0 == 0); 5127#L444-1 assume !(~E_2~0 == 0); 5158#L449-1 assume !(~E_3~0 == 0); 5420#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5288#L198 assume !(~m_pc~0 == 1); 5289#L198-2 is_master_triggered_~__retres1~0 := 0; 5290#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5291#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5149#L521 assume !(activate_threads_~tmp~1 != 0); 5150#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5153#L217 assume !(~t1_pc~0 == 1); 5162#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 5163#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5164#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5165#L529 assume !(activate_threads_~tmp___0~0 != 0); 5398#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5342#L236 assume !(~t2_pc~0 == 1); 5339#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 5340#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5263#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5264#L537 assume !(activate_threads_~tmp___1~0 != 0); 5400#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5353#L255 assume !(~t3_pc~0 == 1); 5354#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 5356#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5357#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5294#L545 assume !(activate_threads_~tmp___2~0 != 0); 5295#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5304#L467 assume !(~M_E~0 == 1); 5341#L467-2 assume !(~T1_E~0 == 1); 5122#L472-1 assume !(~T2_E~0 == 1); 5123#L477-1 assume !(~T3_E~0 == 1); 5156#L482-1 assume !(~E_M~0 == 1); 5415#L487-1 assume !(~E_1~0 == 1); 5438#L492-1 assume !(~E_2~0 == 1); 5358#L497-1 assume !(~E_3~0 == 1); 5359#L502-1 assume { :end_inline_reset_delta_events } true; 5370#L668-3 [2018-10-27 06:06:36,107 INFO L795 eck$LassoCheckResult]: Loop: 5370#L668-3 assume true; 5677#L668-1 assume !false; 5670#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 5663#L394 assume true; 5658#L342-1 assume !false; 5655#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5648#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 5641#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5636#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5631#L347 assume !(eval_~tmp~0 != 0); 5344#L409 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5296#L275-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5297#L419-3 assume ~M_E~0 == 0;~M_E~0 := 1; 5392#L419-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 5272#L424-3 assume !(~T2_E~0 == 0); 5273#L429-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 5332#L434-3 assume ~E_M~0 == 0;~E_M~0 := 1; 5107#L439-3 assume ~E_1~0 == 0;~E_1~0 := 1; 5108#L444-3 assume !(~E_2~0 == 0); 5141#L449-3 assume ~E_3~0 == 0;~E_3~0 := 1; 5180#L454-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5255#L198-15 assume !(~m_pc~0 == 1); 5256#L198-17 is_master_triggered_~__retres1~0 := 0; 6043#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6042#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5138#L521-15 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 5120#L521-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5121#L217-15 assume ~t1_pc~0 == 1; 5181#L218-5 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 5182#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5184#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5185#L529-15 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 5369#L529-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5298#L236-15 assume !(~t2_pc~0 == 1); 5286#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 5287#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5324#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5175#L537-15 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 5151#L537-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5152#L255-15 assume !(~t3_pc~0 == 1); 5408#L255-17 is_transmit3_triggered_~__retres1~3 := 0; 5407#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5410#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5396#L545-15 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 5397#L545-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5343#L467-3 assume ~M_E~0 == 1;~M_E~0 := 2; 5338#L467-5 assume !(~T1_E~0 == 1); 5128#L472-3 assume !(~T2_E~0 == 1); 5129#L477-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 5160#L482-3 assume ~E_M~0 == 1;~E_M~0 := 2; 5430#L487-3 assume ~E_1~0 == 1;~E_1~0 := 2; 5431#L492-3 assume ~E_2~0 == 1;~E_2~0 := 2; 5345#L497-3 assume ~E_3~0 == 1;~E_3~0 := 2; 5346#L502-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5351#L310-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 5113#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5350#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 5875#L687 assume !(start_simulation_~tmp~3 == 0); 5860#L687-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5854#L310-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 5729#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5725#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 5723#L642 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 5721#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 5719#L650 start_simulation_#t~ret12 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 5715#L700 assume !(start_simulation_~tmp___0~1 != 0); 5370#L668-3 [2018-10-27 06:06:36,107 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:36,108 INFO L82 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2018-10-27 06:06:36,108 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:36,108 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:36,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:36,109 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:36,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:36,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:36,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:36,170 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:36,171 INFO L82 PathProgramCache]: Analyzing trace with hash -1639613433, now seen corresponding path program 1 times [2018-10-27 06:06:36,171 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:36,171 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:36,173 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:36,174 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:36,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:36,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:36,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:36,247 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:36,247 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:36,247 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:06:36,247 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:36,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:36,248 INFO L87 Difference]: Start difference. First operand 983 states and 1414 transitions. cyclomatic complexity: 435 Second operand 3 states. [2018-10-27 06:06:36,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:36,325 INFO L93 Difference]: Finished difference Result 1162 states and 1671 transitions. [2018-10-27 06:06:36,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:36,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1162 states and 1671 transitions. [2018-10-27 06:06:36,343 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1066 [2018-10-27 06:06:36,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1162 states to 1162 states and 1671 transitions. [2018-10-27 06:06:36,349 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1162 [2018-10-27 06:06:36,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1162 [2018-10-27 06:06:36,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1162 states and 1671 transitions. [2018-10-27 06:06:36,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:36,354 INFO L705 BuchiCegarLoop]: Abstraction has 1162 states and 1671 transitions. [2018-10-27 06:06:36,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1162 states and 1671 transitions. [2018-10-27 06:06:36,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1162 to 1162. [2018-10-27 06:06:36,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1162 states. [2018-10-27 06:06:36,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1162 states to 1162 states and 1671 transitions. [2018-10-27 06:06:36,380 INFO L728 BuchiCegarLoop]: Abstraction has 1162 states and 1671 transitions. [2018-10-27 06:06:36,380 INFO L608 BuchiCegarLoop]: Abstraction has 1162 states and 1671 transitions. [2018-10-27 06:06:36,382 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-10-27 06:06:36,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1162 states and 1671 transitions. [2018-10-27 06:06:36,387 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1066 [2018-10-27 06:06:36,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:36,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:36,391 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:36,392 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:36,392 INFO L793 eck$LassoCheckResult]: Stem: 7458#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7258#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7259#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7324#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7453#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 7519#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 7521#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 7421#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 7422#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7451#L419 assume !(~M_E~0 == 0); 7548#L419-2 assume ~T1_E~0 == 0;~T1_E~0 := 1; 7554#L424-1 assume !(~T2_E~0 == 0); 8260#L429-1 assume !(~T3_E~0 == 0); 8259#L434-1 assume !(~E_M~0 == 0); 8258#L439-1 assume !(~E_1~0 == 0); 8257#L444-1 assume !(~E_2~0 == 0); 8256#L449-1 assume !(~E_3~0 == 0); 8255#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8254#L198 assume !(~m_pc~0 == 1); 8253#L198-2 is_master_triggered_~__retres1~0 := 0; 7443#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7444#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7301#L521 assume !(activate_threads_~tmp~1 != 0); 7302#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7307#L217 assume !(~t1_pc~0 == 1); 7314#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 7315#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7318#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7319#L529 assume !(activate_threads_~tmp___0~0 != 0); 7561#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7501#L236 assume !(~t2_pc~0 == 1); 7497#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 7498#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7414#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7415#L537 assume !(activate_threads_~tmp___1~0 != 0); 7563#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7512#L255 assume !(~t3_pc~0 == 1); 7513#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 7515#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7516#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7445#L545 assume !(activate_threads_~tmp___2~0 != 0); 7446#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7456#L467 assume !(~M_E~0 == 1); 7499#L467-2 assume ~T1_E~0 == 1;~T1_E~0 := 2; 7274#L472-1 assume !(~T2_E~0 == 1); 7275#L477-1 assume !(~T3_E~0 == 1); 7308#L482-1 assume !(~E_M~0 == 1); 7578#L487-1 assume !(~E_1~0 == 1); 7601#L492-1 assume !(~E_2~0 == 1); 7517#L497-1 assume !(~E_3~0 == 1); 7518#L502-1 assume { :end_inline_reset_delta_events } true; 7529#L668-3 [2018-10-27 06:06:36,392 INFO L795 eck$LassoCheckResult]: Loop: 7529#L668-3 assume true; 7605#L668-1 assume !false; 7607#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 8263#L394 assume true; 8262#L342-1 assume !false; 8226#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7508#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 7261#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7507#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 7416#L347 assume !(eval_~tmp~0 != 0); 7418#L409 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7447#L275-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 7448#L419-3 assume ~M_E~0 == 0;~M_E~0 := 1; 7531#L419-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 7532#L424-3 assume !(~T2_E~0 == 0); 8410#L429-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 8409#L434-3 assume ~E_M~0 == 0;~E_M~0 := 1; 8408#L439-3 assume ~E_1~0 == 0;~E_1~0 := 1; 8407#L444-3 assume !(~E_2~0 == 0); 8406#L449-3 assume ~E_3~0 == 0;~E_3~0 := 1; 8405#L454-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8404#L198-15 assume !(~m_pc~0 == 1); 8403#L198-17 is_master_triggered_~__retres1~0 := 0; 8402#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8225#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7290#L521-15 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 7272#L521-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7273#L217-15 assume ~t1_pc~0 == 1; 7333#L218-5 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 7334#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7336#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7337#L529-15 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 7528#L529-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7449#L236-15 assume !(~t2_pc~0 == 1); 7450#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 8338#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8336#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8334#L537-15 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 8331#L537-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8329#L255-15 assume ~t3_pc~0 == 1; 8326#L256-5 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 8324#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8322#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8320#L545-15 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 8319#L545-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8318#L467-3 assume ~M_E~0 == 1;~M_E~0 := 2; 8317#L467-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 8315#L472-3 assume !(~T2_E~0 == 1); 8314#L477-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 8313#L482-3 assume ~E_M~0 == 1;~E_M~0 := 2; 8312#L487-3 assume ~E_1~0 == 1;~E_1~0 := 2; 8311#L492-3 assume ~E_2~0 == 1;~E_2~0 := 2; 8310#L497-3 assume ~E_3~0 == 1;~E_3~0 := 2; 8309#L502-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8308#L310-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 8304#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8303#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 8301#L687 assume !(start_simulation_~tmp~3 == 0); 7252#L687-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7253#L310-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 7267#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7511#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 7322#L642 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 7323#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 7383#L650 start_simulation_#t~ret12 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 7384#L700 assume !(start_simulation_~tmp___0~1 != 0); 7529#L668-3 [2018-10-27 06:06:36,393 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:36,393 INFO L82 PathProgramCache]: Analyzing trace with hash 1665536133, now seen corresponding path program 1 times [2018-10-27 06:06:36,393 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:36,393 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:36,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:36,404 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:36,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:36,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:36,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:36,466 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:36,467 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:06:36,467 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:06:36,467 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:36,467 INFO L82 PathProgramCache]: Analyzing trace with hash 850552648, now seen corresponding path program 1 times [2018-10-27 06:06:36,467 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:36,467 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:36,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:36,471 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:36,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:36,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:36,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:36,730 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:36,731 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 06:06:36,731 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:06:36,731 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:36,731 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:36,731 INFO L87 Difference]: Start difference. First operand 1162 states and 1671 transitions. cyclomatic complexity: 513 Second operand 3 states. [2018-10-27 06:06:36,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:36,857 INFO L93 Difference]: Finished difference Result 983 states and 1400 transitions. [2018-10-27 06:06:36,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:36,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 983 states and 1400 transitions. [2018-10-27 06:06:36,863 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 922 [2018-10-27 06:06:36,870 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 983 states to 983 states and 1400 transitions. [2018-10-27 06:06:36,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 983 [2018-10-27 06:06:36,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 983 [2018-10-27 06:06:36,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 983 states and 1400 transitions. [2018-10-27 06:06:36,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:36,874 INFO L705 BuchiCegarLoop]: Abstraction has 983 states and 1400 transitions. [2018-10-27 06:06:36,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 983 states and 1400 transitions. [2018-10-27 06:06:36,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 983 to 983. [2018-10-27 06:06:36,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 983 states. [2018-10-27 06:06:36,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 983 states to 983 states and 1400 transitions. [2018-10-27 06:06:36,894 INFO L728 BuchiCegarLoop]: Abstraction has 983 states and 1400 transitions. [2018-10-27 06:06:36,894 INFO L608 BuchiCegarLoop]: Abstraction has 983 states and 1400 transitions. [2018-10-27 06:06:36,894 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-10-27 06:06:36,894 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 983 states and 1400 transitions. [2018-10-27 06:06:36,898 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 922 [2018-10-27 06:06:36,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:36,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:36,899 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:36,899 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:36,899 INFO L793 eck$LassoCheckResult]: Stem: 9609#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 9410#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 9411#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9478#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9604#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 9668#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 9670#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 9575#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 9576#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9603#L419 assume !(~M_E~0 == 0); 9689#L419-2 assume !(~T1_E~0 == 0); 9553#L424-1 assume !(~T2_E~0 == 0); 9554#L429-1 assume !(~T3_E~0 == 0); 9626#L434-1 assume !(~E_M~0 == 0); 9431#L439-1 assume !(~E_1~0 == 0); 9432#L444-1 assume !(~E_2~0 == 0); 9464#L449-1 assume !(~E_3~0 == 0); 9729#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9592#L198 assume !(~m_pc~0 == 1); 9593#L198-2 is_master_triggered_~__retres1~0 := 0; 9594#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9595#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 9455#L521 assume !(activate_threads_~tmp~1 != 0); 9456#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9459#L217 assume !(~t1_pc~0 == 1); 9468#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 9469#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9470#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9471#L529 assume !(activate_threads_~tmp___0~0 != 0); 9707#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9649#L236 assume !(~t2_pc~0 == 1); 9646#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 9647#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9568#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9569#L537 assume !(activate_threads_~tmp___1~0 != 0); 9709#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9661#L255 assume !(~t3_pc~0 == 1); 9662#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 9664#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9665#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9598#L545 assume !(activate_threads_~tmp___2~0 != 0); 9599#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9608#L467 assume !(~M_E~0 == 1); 9648#L467-2 assume !(~T1_E~0 == 1); 9427#L472-1 assume !(~T2_E~0 == 1); 9428#L477-1 assume !(~T3_E~0 == 1); 9462#L482-1 assume !(~E_M~0 == 1); 9724#L487-1 assume !(~E_1~0 == 1); 9747#L492-1 assume !(~E_2~0 == 1); 9666#L497-1 assume !(~E_3~0 == 1); 9667#L502-1 assume { :end_inline_reset_delta_events } true; 9676#L668-3 [2018-10-27 06:06:36,899 INFO L795 eck$LassoCheckResult]: Loop: 9676#L668-3 assume true; 9750#L668-1 assume !false; 9863#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 9854#L394 assume true; 9848#L342-1 assume !false; 9844#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 9825#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 9818#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 9811#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 9804#L347 assume !(eval_~tmp~0 != 0); 9805#L409 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 10388#L275-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 10387#L419-3 assume ~M_E~0 == 0;~M_E~0 := 1; 10386#L419-5 assume !(~T1_E~0 == 0); 10385#L424-3 assume !(~T2_E~0 == 0); 9637#L429-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 9638#L434-3 assume ~E_M~0 == 0;~E_M~0 := 1; 9412#L439-3 assume ~E_1~0 == 0;~E_1~0 := 1; 9413#L444-3 assume !(~E_2~0 == 0); 9447#L449-3 assume ~E_3~0 == 0;~E_3~0 := 1; 9486#L454-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9561#L198-15 assume !(~m_pc~0 == 1); 9544#L198-17 is_master_triggered_~__retres1~0 := 0; 9545#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9616#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 9444#L521-15 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 9425#L521-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9426#L217-15 assume !(~t1_pc~0 == 1); 9489#L217-17 is_transmit1_triggered_~__retres1~1 := 0; 9488#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9490#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9491#L529-15 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 9675#L529-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9602#L236-15 assume !(~t2_pc~0 == 1); 9590#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 9591#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9629#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9481#L537-15 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 9457#L537-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9458#L255-15 assume ~t3_pc~0 == 1; 9715#L256-5 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 9716#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9719#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9705#L545-15 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 9706#L545-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9650#L467-3 assume ~M_E~0 == 1;~M_E~0 := 2; 9645#L467-5 assume !(~T1_E~0 == 1); 9433#L472-3 assume !(~T2_E~0 == 1); 9434#L477-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 9466#L482-3 assume ~E_M~0 == 1;~E_M~0 := 2; 9736#L487-3 assume ~E_1~0 == 1;~E_1~0 := 2; 9739#L492-3 assume ~E_2~0 == 1;~E_2~0 := 2; 9652#L497-3 assume ~E_3~0 == 1;~E_3~0 := 2; 9653#L502-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 9659#L310-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 9418#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10239#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 9423#L687 assume !(start_simulation_~tmp~3 == 0); 9406#L687-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 9407#L310-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 9421#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 9660#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 9476#L642 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 9477#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 9537#L650 start_simulation_#t~ret12 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 9538#L700 assume !(start_simulation_~tmp___0~1 != 0); 9676#L668-3 [2018-10-27 06:06:36,900 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:36,912 INFO L82 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2018-10-27 06:06:36,912 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:36,913 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:36,913 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:36,913 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:36,913 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:36,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:36,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:36,939 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:36,940 INFO L82 PathProgramCache]: Analyzing trace with hash -480123511, now seen corresponding path program 1 times [2018-10-27 06:06:36,940 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:36,940 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:36,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:36,941 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:06:36,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:36,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:37,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:37,187 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:37,187 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 06:06:37,187 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:06:37,188 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 06:06:37,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-27 06:06:37,191 INFO L87 Difference]: Start difference. First operand 983 states and 1400 transitions. cyclomatic complexity: 421 Second operand 5 states. [2018-10-27 06:06:38,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:38,311 INFO L93 Difference]: Finished difference Result 1721 states and 2410 transitions. [2018-10-27 06:06:38,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-10-27 06:06:38,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1721 states and 2410 transitions. [2018-10-27 06:06:38,324 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1652 [2018-10-27 06:06:38,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1721 states to 1721 states and 2410 transitions. [2018-10-27 06:06:38,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1721 [2018-10-27 06:06:38,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1721 [2018-10-27 06:06:38,336 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1721 states and 2410 transitions. [2018-10-27 06:06:38,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:38,340 INFO L705 BuchiCegarLoop]: Abstraction has 1721 states and 2410 transitions. [2018-10-27 06:06:38,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1721 states and 2410 transitions. [2018-10-27 06:06:38,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1721 to 995. [2018-10-27 06:06:38,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 995 states. [2018-10-27 06:06:38,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 995 states to 995 states and 1412 transitions. [2018-10-27 06:06:38,365 INFO L728 BuchiCegarLoop]: Abstraction has 995 states and 1412 transitions. [2018-10-27 06:06:38,365 INFO L608 BuchiCegarLoop]: Abstraction has 995 states and 1412 transitions. [2018-10-27 06:06:38,365 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-10-27 06:06:38,365 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 995 states and 1412 transitions. [2018-10-27 06:06:38,370 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 934 [2018-10-27 06:06:38,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:38,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:38,374 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:38,375 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:38,375 INFO L793 eck$LassoCheckResult]: Stem: 12332#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 12130#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12131#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12199#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12327#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 12393#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 12397#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 12297#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 12298#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12326#L419 assume !(~M_E~0 == 0); 12421#L419-2 assume !(~T1_E~0 == 0); 12274#L424-1 assume !(~T2_E~0 == 0); 12275#L429-1 assume !(~T3_E~0 == 0); 12349#L434-1 assume !(~E_M~0 == 0); 12151#L439-1 assume !(~E_1~0 == 0); 12152#L444-1 assume !(~E_2~0 == 0); 12184#L449-1 assume !(~E_3~0 == 0); 12464#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12315#L198 assume !(~m_pc~0 == 1); 12316#L198-2 is_master_triggered_~__retres1~0 := 0; 12317#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12318#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12175#L521 assume !(activate_threads_~tmp~1 != 0); 12176#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12179#L217 assume !(~t1_pc~0 == 1); 12189#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 12190#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12191#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 12192#L529 assume !(activate_threads_~tmp___0~0 != 0); 12438#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12373#L236 assume !(~t2_pc~0 == 1); 12370#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 12371#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12290#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12291#L537 assume !(activate_threads_~tmp___1~0 != 0); 12443#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12386#L255 assume !(~t3_pc~0 == 1); 12387#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 12389#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12390#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12321#L545 assume !(activate_threads_~tmp___2~0 != 0); 12322#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12331#L467 assume !(~M_E~0 == 1); 12372#L467-2 assume !(~T1_E~0 == 1); 12147#L472-1 assume !(~T2_E~0 == 1); 12148#L477-1 assume !(~T3_E~0 == 1); 12182#L482-1 assume !(~E_M~0 == 1); 12459#L487-1 assume !(~E_1~0 == 1); 12483#L492-1 assume !(~E_2~0 == 1); 12391#L497-1 assume !(~E_3~0 == 1); 12392#L502-1 assume { :end_inline_reset_delta_events } true; 12405#L668-3 [2018-10-27 06:06:38,376 INFO L795 eck$LassoCheckResult]: Loop: 12405#L668-3 assume true; 13053#L668-1 assume !false; 13052#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 12281#L394 assume true; 12432#L342-1 assume !false; 12379#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12380#L310 assume !(~m_st~0 == 0); 12301#L314 assume !(~t1_st~0 == 0); 12134#L318 assume !(~t2_st~0 == 0); 12136#L322 assume !(~t3_st~0 == 0);exists_runnable_thread_~__retres1~4 := 0; 12381#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12382#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 12655#L347 assume !(eval_~tmp~0 != 0); 12376#L409 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 12323#L275-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12324#L419-3 assume ~M_E~0 == 0;~M_E~0 := 1; 12407#L419-5 assume !(~T1_E~0 == 0); 12299#L424-3 assume !(~T2_E~0 == 0); 12300#L429-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 12362#L434-3 assume ~E_M~0 == 0;~E_M~0 := 1; 12132#L439-3 assume ~E_1~0 == 0;~E_1~0 := 1; 12133#L444-3 assume !(~E_2~0 == 0); 12167#L449-3 assume ~E_3~0 == 0;~E_3~0 := 1; 12208#L454-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12282#L198-15 assume !(~m_pc~0 == 1); 12283#L198-17 is_master_triggered_~__retres1~0 := 0; 12786#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12785#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12163#L521-15 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 12164#L521-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12481#L217-15 assume ~t1_pc~0 == 1; 12209#L218-5 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 12210#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12214#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 12215#L529-15 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 12404#L529-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12325#L236-15 assume !(~t2_pc~0 == 1); 12313#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 12314#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12430#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12431#L537-15 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 12177#L537-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12178#L255-15 assume ~t3_pc~0 == 1; 12449#L256-5 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 12450#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12453#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12454#L545-15 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 12439#L545-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12440#L467-3 assume ~M_E~0 == 1;~M_E~0 := 2; 12368#L467-5 assume !(~T1_E~0 == 1); 12369#L472-3 assume !(~T2_E~0 == 1); 12186#L477-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 12187#L482-3 assume ~E_M~0 == 1;~E_M~0 := 2; 12474#L487-3 assume ~E_1~0 == 1;~E_1~0 := 2; 12475#L492-3 assume ~E_2~0 == 1;~E_2~0 := 2; 12377#L497-3 assume ~E_3~0 == 1;~E_3~0 := 2; 12378#L502-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12384#L310-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 12138#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12383#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 12143#L687 assume !(start_simulation_~tmp~3 == 0); 12126#L687-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12127#L310-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 13063#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 13062#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 13061#L642 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 13060#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 13059#L650 start_simulation_#t~ret12 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 13057#L700 assume !(start_simulation_~tmp___0~1 != 0); 12405#L668-3 [2018-10-27 06:06:38,380 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:38,380 INFO L82 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2018-10-27 06:06:38,381 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:38,381 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:38,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:38,381 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:38,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:38,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:38,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:38,409 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:38,409 INFO L82 PathProgramCache]: Analyzing trace with hash -1833827648, now seen corresponding path program 1 times [2018-10-27 06:06:38,409 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:38,409 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:38,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:38,410 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:06:38,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:38,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:38,949 WARN L179 SmtUtils]: Spent 252.00 ms on a formula simplification. DAG size of input: 11 DAG size of output: 5 [2018-10-27 06:06:38,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:38,957 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:38,957 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-10-27 06:06:38,957 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:06:38,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-10-27 06:06:38,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-10-27 06:06:38,958 INFO L87 Difference]: Start difference. First operand 995 states and 1412 transitions. cyclomatic complexity: 421 Second operand 5 states. [2018-10-27 06:06:39,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:39,603 INFO L93 Difference]: Finished difference Result 1918 states and 2697 transitions. [2018-10-27 06:06:39,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-10-27 06:06:39,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1918 states and 2697 transitions. [2018-10-27 06:06:39,616 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1853 [2018-10-27 06:06:39,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1918 states to 1918 states and 2697 transitions. [2018-10-27 06:06:39,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1918 [2018-10-27 06:06:39,629 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1918 [2018-10-27 06:06:39,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1918 states and 2697 transitions. [2018-10-27 06:06:39,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:39,633 INFO L705 BuchiCegarLoop]: Abstraction has 1918 states and 2697 transitions. [2018-10-27 06:06:39,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1918 states and 2697 transitions. [2018-10-27 06:06:39,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1918 to 1028. [2018-10-27 06:06:39,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1028 states. [2018-10-27 06:06:39,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1028 states to 1028 states and 1435 transitions. [2018-10-27 06:06:39,658 INFO L728 BuchiCegarLoop]: Abstraction has 1028 states and 1435 transitions. [2018-10-27 06:06:39,658 INFO L608 BuchiCegarLoop]: Abstraction has 1028 states and 1435 transitions. [2018-10-27 06:06:39,658 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-10-27 06:06:39,659 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1028 states and 1435 transitions. [2018-10-27 06:06:39,663 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 967 [2018-10-27 06:06:39,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:39,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:39,667 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:39,667 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:39,668 INFO L793 eck$LassoCheckResult]: Stem: 15258#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 15056#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 15057#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 15124#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15253#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 15317#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 15320#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 15223#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 15224#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15252#L419 assume !(~M_E~0 == 0); 15352#L419-2 assume !(~T1_E~0 == 0); 15200#L424-1 assume !(~T2_E~0 == 0); 15201#L429-1 assume !(~T3_E~0 == 0); 15277#L434-1 assume !(~E_M~0 == 0); 15077#L439-1 assume !(~E_1~0 == 0); 15078#L444-1 assume !(~E_2~0 == 0); 15110#L449-1 assume !(~E_3~0 == 0); 15393#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15240#L198 assume !(~m_pc~0 == 1); 15241#L198-2 is_master_triggered_~__retres1~0 := 0; 15242#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15243#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 15101#L521 assume !(activate_threads_~tmp~1 != 0); 15102#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15105#L217 assume !(~t1_pc~0 == 1); 15114#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 15115#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15116#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15117#L529 assume !(activate_threads_~tmp___0~0 != 0); 15371#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15298#L236 assume !(~t2_pc~0 == 1); 15295#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 15296#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15216#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15217#L537 assume !(activate_threads_~tmp___1~0 != 0); 15373#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15310#L255 assume !(~t3_pc~0 == 1); 15311#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 15313#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15314#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 15246#L545 assume !(activate_threads_~tmp___2~0 != 0); 15247#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15257#L467 assume !(~M_E~0 == 1); 15297#L467-2 assume !(~T1_E~0 == 1); 15073#L472-1 assume !(~T2_E~0 == 1); 15074#L477-1 assume !(~T3_E~0 == 1); 15108#L482-1 assume !(~E_M~0 == 1); 15388#L487-1 assume !(~E_1~0 == 1); 15412#L492-1 assume !(~E_2~0 == 1); 15315#L497-1 assume !(~E_3~0 == 1); 15316#L502-1 assume { :end_inline_reset_delta_events } true; 15333#L668-3 [2018-10-27 06:06:39,668 INFO L795 eck$LassoCheckResult]: Loop: 15333#L668-3 assume true; 15726#L668-1 assume !false; 15724#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 15720#L394 assume true; 15719#L342-1 assume !false; 15718#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 15717#L310 assume !(~m_st~0 == 0); 15713#L314 assume !(~t1_st~0 == 0); 15714#L318 assume !(~t2_st~0 == 0); 15715#L322 assume !(~t3_st~0 == 0);exists_runnable_thread_~__retres1~4 := 0; 15716#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 15705#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 15706#L347 assume !(eval_~tmp~0 != 0); 15848#L409 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 15847#L275-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 15846#L419-3 assume ~M_E~0 == 0;~M_E~0 := 1; 15845#L419-5 assume !(~T1_E~0 == 0); 15844#L424-3 assume !(~T2_E~0 == 0); 15843#L429-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 15842#L434-3 assume ~E_M~0 == 0;~E_M~0 := 1; 15841#L439-3 assume ~E_1~0 == 0;~E_1~0 := 1; 15840#L444-3 assume !(~E_2~0 == 0); 15839#L449-3 assume ~E_3~0 == 0;~E_3~0 := 1; 15405#L454-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15208#L198-15 assume !(~m_pc~0 == 1); 15209#L198-17 is_master_triggered_~__retres1~0 := 0; 15838#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15837#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 15836#L521-15 assume !(activate_threads_~tmp~1 != 0); 15835#L521-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15834#L217-15 assume ~t1_pc~0 == 1; 15831#L218-5 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 15829#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15827#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15825#L529-15 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 15823#L529-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15820#L236-15 assume !(~t2_pc~0 == 1); 15818#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 15816#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15814#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15812#L537-15 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 15810#L537-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15808#L255-15 assume ~t3_pc~0 == 1; 15805#L256-5 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 15803#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15801#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 15798#L545-15 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 15795#L545-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15791#L467-3 assume ~M_E~0 == 1;~M_E~0 := 2; 15788#L467-5 assume !(~T1_E~0 == 1); 15785#L472-3 assume !(~T2_E~0 == 1); 15781#L477-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 15778#L482-3 assume ~E_M~0 == 1;~E_M~0 := 2; 15775#L487-3 assume ~E_1~0 == 1;~E_1~0 := 2; 15772#L492-3 assume ~E_2~0 == 1;~E_2~0 := 2; 15769#L497-3 assume ~E_3~0 == 1;~E_3~0 := 2; 15766#L502-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 15763#L310-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 15757#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 15754#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 15751#L687 assume !(start_simulation_~tmp~3 == 0); 15748#L687-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 15746#L310-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 15740#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 15738#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 15736#L642 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 15734#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 15732#L650 start_simulation_#t~ret12 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 15729#L700 assume !(start_simulation_~tmp___0~1 != 0); 15333#L668-3 [2018-10-27 06:06:39,679 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:39,679 INFO L82 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 4 times [2018-10-27 06:06:39,679 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:39,679 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:39,680 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:39,680 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:39,680 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:39,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:39,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:39,702 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:39,706 INFO L82 PathProgramCache]: Analyzing trace with hash -1410180926, now seen corresponding path program 1 times [2018-10-27 06:06:39,707 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:39,707 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:39,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:39,709 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:06:39,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:39,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:39,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:39,786 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:39,787 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:39,787 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-10-27 06:06:39,787 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:39,787 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:39,787 INFO L87 Difference]: Start difference. First operand 1028 states and 1435 transitions. cyclomatic complexity: 411 Second operand 3 states. [2018-10-27 06:06:40,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:40,048 INFO L93 Difference]: Finished difference Result 1674 states and 2302 transitions. [2018-10-27 06:06:40,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:40,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1674 states and 2302 transitions. [2018-10-27 06:06:40,054 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1606 [2018-10-27 06:06:40,062 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1674 states to 1674 states and 2302 transitions. [2018-10-27 06:06:40,062 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1674 [2018-10-27 06:06:40,064 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1674 [2018-10-27 06:06:40,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1674 states and 2302 transitions. [2018-10-27 06:06:40,067 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:40,067 INFO L705 BuchiCegarLoop]: Abstraction has 1674 states and 2302 transitions. [2018-10-27 06:06:40,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1674 states and 2302 transitions. [2018-10-27 06:06:40,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1674 to 1629. [2018-10-27 06:06:40,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1629 states. [2018-10-27 06:06:40,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1629 states to 1629 states and 2241 transitions. [2018-10-27 06:06:40,097 INFO L728 BuchiCegarLoop]: Abstraction has 1629 states and 2241 transitions. [2018-10-27 06:06:40,097 INFO L608 BuchiCegarLoop]: Abstraction has 1629 states and 2241 transitions. [2018-10-27 06:06:40,097 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-10-27 06:06:40,097 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1629 states and 2241 transitions. [2018-10-27 06:06:40,105 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1561 [2018-10-27 06:06:40,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:40,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:40,106 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:40,106 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:40,106 INFO L793 eck$LassoCheckResult]: Stem: 17963#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 17766#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 17767#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 17833#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17958#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 18020#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 18024#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 17929#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 17930#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17956#L419 assume !(~M_E~0 == 0); 18053#L419-2 assume !(~T1_E~0 == 0); 17909#L424-1 assume !(~T2_E~0 == 0); 17910#L429-1 assume !(~T3_E~0 == 0); 17983#L434-1 assume !(~E_M~0 == 0); 17786#L439-1 assume !(~E_1~0 == 0); 17787#L444-1 assume !(~E_2~0 == 0); 17819#L449-1 assume !(~E_3~0 == 0); 18096#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17945#L198 assume !(~m_pc~0 == 1); 17946#L198-2 is_master_triggered_~__retres1~0 := 0; 17949#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17950#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 17810#L521 assume !(activate_threads_~tmp~1 != 0); 17811#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17816#L217 assume !(~t1_pc~0 == 1); 17823#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 17824#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17827#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 17828#L529 assume !(activate_threads_~tmp___0~0 != 0); 18071#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18001#L236 assume !(~t2_pc~0 == 1); 17998#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 17999#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17927#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 17928#L537 assume !(activate_threads_~tmp___1~0 != 0); 18077#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18013#L255 assume !(~t3_pc~0 == 1); 18014#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 18016#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18017#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 17953#L545 assume !(activate_threads_~tmp___2~0 != 0); 17954#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17961#L467 assume !(~M_E~0 == 1); 18000#L467-2 assume !(~T1_E~0 == 1); 17784#L472-1 assume !(~T2_E~0 == 1); 17785#L477-1 assume !(~T3_E~0 == 1); 17817#L482-1 assume !(~E_M~0 == 1); 18090#L487-1 assume !(~E_1~0 == 1); 18115#L492-1 assume !(~E_2~0 == 1); 18018#L497-1 assume !(~E_3~0 == 1); 18019#L502-1 assume { :end_inline_reset_delta_events } true; 18034#L668-3 assume true; 18253#L668-1 assume !false; 18220#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 18210#L394 [2018-10-27 06:06:40,106 INFO L795 eck$LassoCheckResult]: Loop: 18210#L394 assume true; 18206#L342-1 assume !false; 18202#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 18196#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 18191#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 18187#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 18183#L347 assume eval_~tmp~0 != 0; 18180#L347-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 18107#L355 assume !(eval_~tmp_ndt_1~0 != 0); 18108#L352 assume !(~t1_st~0 == 0); 18297#L366 assume !(~t2_st~0 == 0); 18221#L380 assume !(~t3_st~0 == 0); 18210#L394 [2018-10-27 06:06:40,106 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:40,106 INFO L82 PathProgramCache]: Analyzing trace with hash 1176639138, now seen corresponding path program 1 times [2018-10-27 06:06:40,106 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:40,107 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:40,107 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:40,107 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:40,107 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:40,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:40,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:40,135 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:40,135 INFO L82 PathProgramCache]: Analyzing trace with hash -1403056411, now seen corresponding path program 1 times [2018-10-27 06:06:40,135 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:40,135 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:40,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:40,138 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:40,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:40,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:40,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:40,147 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:40,148 INFO L82 PathProgramCache]: Analyzing trace with hash 309804038, now seen corresponding path program 1 times [2018-10-27 06:06:40,148 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:40,148 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:40,149 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:40,149 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:40,149 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:40,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:40,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:40,225 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:40,225 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:40,398 WARN L179 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 24 [2018-10-27 06:06:40,417 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:40,417 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:40,418 INFO L87 Difference]: Start difference. First operand 1629 states and 2241 transitions. cyclomatic complexity: 618 Second operand 3 states. [2018-10-27 06:06:40,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:40,620 INFO L93 Difference]: Finished difference Result 2950 states and 4017 transitions. [2018-10-27 06:06:40,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:40,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2950 states and 4017 transitions. [2018-10-27 06:06:40,636 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2820 [2018-10-27 06:06:40,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2950 states to 2950 states and 4017 transitions. [2018-10-27 06:06:40,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2950 [2018-10-27 06:06:40,653 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2950 [2018-10-27 06:06:40,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2950 states and 4017 transitions. [2018-10-27 06:06:40,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:40,659 INFO L705 BuchiCegarLoop]: Abstraction has 2950 states and 4017 transitions. [2018-10-27 06:06:40,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2950 states and 4017 transitions. [2018-10-27 06:06:40,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2950 to 2802. [2018-10-27 06:06:40,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2802 states. [2018-10-27 06:06:40,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2802 states to 2802 states and 3829 transitions. [2018-10-27 06:06:40,707 INFO L728 BuchiCegarLoop]: Abstraction has 2802 states and 3829 transitions. [2018-10-27 06:06:40,707 INFO L608 BuchiCegarLoop]: Abstraction has 2802 states and 3829 transitions. [2018-10-27 06:06:40,707 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-10-27 06:06:40,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2802 states and 3829 transitions. [2018-10-27 06:06:40,718 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2672 [2018-10-27 06:06:40,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:40,718 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:40,718 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:40,719 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:40,719 INFO L793 eck$LassoCheckResult]: Stem: 22563#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 22353#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 22354#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 22425#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22556#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 22636#L282-2 assume !(~t1_i~0 == 1);~t1_st~0 := 2; 22638#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 22653#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 22553#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22554#L419 assume !(~M_E~0 == 0); 22684#L419-2 assume !(~T1_E~0 == 0); 22685#L424-1 assume !(~T2_E~0 == 0); 22584#L429-1 assume !(~T3_E~0 == 0); 22585#L434-1 assume !(~E_M~0 == 0); 22372#L439-1 assume !(~E_1~0 == 0); 22373#L444-1 assume !(~E_2~0 == 0); 22728#L449-1 assume !(~E_3~0 == 0); 22729#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22541#L198 assume !(~m_pc~0 == 1); 22542#L198-2 is_master_triggered_~__retres1~0 := 0; 22545#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22546#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 22397#L521 assume !(activate_threads_~tmp~1 != 0); 22398#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22774#L217 assume !(~t1_pc~0 == 1); 22775#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 22777#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22778#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 22697#L529 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 22698#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22702#L236 assume !(~t2_pc~0 == 1); 22604#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 22605#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22519#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 22520#L537 assume !(activate_threads_~tmp___1~0 != 0); 22719#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22720#L255 assume !(~t3_pc~0 == 1); 22756#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 22755#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22757#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22758#L545 assume !(activate_threads_~tmp___2~0 != 0); 22559#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22560#L467 assume !(~M_E~0 == 1); 22616#L467-2 assume !(~T1_E~0 == 1); 22617#L472-1 assume !(~T2_E~0 == 1); 22405#L477-1 assume !(~T3_E~0 == 1); 22406#L482-1 assume !(~E_M~0 == 1); 22759#L487-1 assume !(~E_1~0 == 1); 22760#L492-1 assume !(~E_2~0 == 1); 22634#L497-1 assume !(~E_3~0 == 1); 22635#L502-1 assume { :end_inline_reset_delta_events } true; 22946#L668-3 assume true; 22936#L668-1 assume !false; 22928#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 22923#L394 [2018-10-27 06:06:40,719 INFO L795 eck$LassoCheckResult]: Loop: 22923#L394 assume true; 22914#L342-1 assume !false; 22915#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 22897#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 22898#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 22965#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 22964#L347 assume eval_~tmp~0 != 0; 22962#L347-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 22858#L355 assume !(eval_~tmp_ndt_1~0 != 0); 22859#L352 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 22947#L369 assume !(eval_~tmp_ndt_2~0 != 0); 22939#L366 assume !(~t2_st~0 == 0); 22929#L380 assume !(~t3_st~0 == 0); 22923#L394 [2018-10-27 06:06:40,719 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:40,719 INFO L82 PathProgramCache]: Analyzing trace with hash 1099080806, now seen corresponding path program 1 times [2018-10-27 06:06:40,719 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:40,720 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:40,730 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:40,730 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:40,730 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:40,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:40,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:40,786 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:40,786 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:40,787 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-10-27 06:06:40,787 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:40,787 INFO L82 PathProgramCache]: Analyzing trace with hash -549145157, now seen corresponding path program 1 times [2018-10-27 06:06:40,787 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:40,787 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:40,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:40,788 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:40,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:40,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:40,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:41,015 WARN L179 SmtUtils]: Spent 214.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 27 [2018-10-27 06:06:41,121 WARN L179 SmtUtils]: Spent 105.00 ms on a formula simplification that was a NOOP. DAG size: 27 [2018-10-27 06:06:41,142 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:41,142 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:41,142 INFO L87 Difference]: Start difference. First operand 2802 states and 3829 transitions. cyclomatic complexity: 1033 Second operand 3 states. [2018-10-27 06:06:41,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:41,173 INFO L93 Difference]: Finished difference Result 2752 states and 3759 transitions. [2018-10-27 06:06:41,174 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:41,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2752 states and 3759 transitions. [2018-10-27 06:06:41,186 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2672 [2018-10-27 06:06:41,198 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2752 states to 2752 states and 3759 transitions. [2018-10-27 06:06:41,199 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2752 [2018-10-27 06:06:41,200 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2752 [2018-10-27 06:06:41,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2752 states and 3759 transitions. [2018-10-27 06:06:41,203 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:41,203 INFO L705 BuchiCegarLoop]: Abstraction has 2752 states and 3759 transitions. [2018-10-27 06:06:41,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2752 states and 3759 transitions. [2018-10-27 06:06:41,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2752 to 2752. [2018-10-27 06:06:41,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2752 states. [2018-10-27 06:06:41,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2752 states to 2752 states and 3759 transitions. [2018-10-27 06:06:41,250 INFO L728 BuchiCegarLoop]: Abstraction has 2752 states and 3759 transitions. [2018-10-27 06:06:41,250 INFO L608 BuchiCegarLoop]: Abstraction has 2752 states and 3759 transitions. [2018-10-27 06:06:41,250 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-10-27 06:06:41,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2752 states and 3759 transitions. [2018-10-27 06:06:41,260 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2672 [2018-10-27 06:06:41,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:41,260 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:41,261 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:41,261 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:41,261 INFO L793 eck$LassoCheckResult]: Stem: 28118#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 27911#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 27912#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 27981#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28113#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 28185#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 28187#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 28081#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 28082#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28112#L419 assume !(~M_E~0 == 0); 28225#L419-2 assume !(~T1_E~0 == 0); 28059#L424-1 assume !(~T2_E~0 == 0); 28060#L429-1 assume !(~T3_E~0 == 0); 28135#L434-1 assume !(~E_M~0 == 0); 27932#L439-1 assume !(~E_1~0 == 0); 27933#L444-1 assume !(~E_2~0 == 0); 27967#L449-1 assume !(~E_3~0 == 0); 28272#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28100#L198 assume !(~m_pc~0 == 1); 28101#L198-2 is_master_triggered_~__retres1~0 := 0; 28102#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28103#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 27958#L521 assume !(activate_threads_~tmp~1 != 0); 27959#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27962#L217 assume !(~t1_pc~0 == 1); 27971#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 27972#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27973#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 27974#L529 assume !(activate_threads_~tmp___0~0 != 0); 28247#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28163#L236 assume !(~t2_pc~0 == 1); 28160#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 28161#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28075#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 28076#L537 assume !(activate_threads_~tmp___1~0 != 0); 28250#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28178#L255 assume !(~t3_pc~0 == 1); 28179#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 28181#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28182#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 28106#L545 assume !(activate_threads_~tmp___2~0 != 0); 28107#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28117#L467 assume !(~M_E~0 == 1); 28162#L467-2 assume !(~T1_E~0 == 1); 27928#L472-1 assume !(~T2_E~0 == 1); 27929#L477-1 assume !(~T3_E~0 == 1); 27965#L482-1 assume !(~E_M~0 == 1); 28267#L487-1 assume !(~E_1~0 == 1); 28303#L492-1 assume !(~E_2~0 == 1); 28183#L497-1 assume !(~E_3~0 == 1); 28184#L502-1 assume { :end_inline_reset_delta_events } true; 28202#L668-3 assume true; 28446#L668-1 assume !false; 28439#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 28431#L394 [2018-10-27 06:06:41,261 INFO L795 eck$LassoCheckResult]: Loop: 28431#L394 assume true; 28429#L342-1 assume !false; 28427#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28425#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 28420#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28421#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 28411#L347 assume eval_~tmp~0 != 0; 28412#L347-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 28396#L355 assume !(eval_~tmp_ndt_1~0 != 0); 28397#L352 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 28453#L369 assume !(eval_~tmp_ndt_2~0 != 0); 28449#L366 assume !(~t2_st~0 == 0); 28440#L380 assume !(~t3_st~0 == 0); 28431#L394 [2018-10-27 06:06:41,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:41,271 INFO L82 PathProgramCache]: Analyzing trace with hash 1176639138, now seen corresponding path program 2 times [2018-10-27 06:06:41,271 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:41,271 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:41,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:41,272 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:41,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:41,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:41,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:41,293 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:41,293 INFO L82 PathProgramCache]: Analyzing trace with hash -549145157, now seen corresponding path program 2 times [2018-10-27 06:06:41,293 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:41,293 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:41,296 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:41,296 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:06:41,297 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:41,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:41,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:41,304 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:41,305 INFO L82 PathProgramCache]: Analyzing trace with hash 1009921210, now seen corresponding path program 1 times [2018-10-27 06:06:41,305 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:41,305 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:41,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:41,306 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:06:41,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:41,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:41,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:41,384 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:41,384 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-10-27 06:06:41,530 WARN L179 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 27 [2018-10-27 06:06:41,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:41,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:41,553 INFO L87 Difference]: Start difference. First operand 2752 states and 3759 transitions. cyclomatic complexity: 1013 Second operand 3 states. [2018-10-27 06:06:41,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:41,604 INFO L93 Difference]: Finished difference Result 3393 states and 4602 transitions. [2018-10-27 06:06:41,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:41,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3393 states and 4602 transitions. [2018-10-27 06:06:41,614 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3309 [2018-10-27 06:06:41,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3393 states to 3393 states and 4602 transitions. [2018-10-27 06:06:41,629 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3393 [2018-10-27 06:06:41,631 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3393 [2018-10-27 06:06:41,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3393 states and 4602 transitions. [2018-10-27 06:06:41,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:41,637 INFO L705 BuchiCegarLoop]: Abstraction has 3393 states and 4602 transitions. [2018-10-27 06:06:41,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3393 states and 4602 transitions. [2018-10-27 06:06:41,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3393 to 3297. [2018-10-27 06:06:41,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3297 states. [2018-10-27 06:06:41,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3297 states to 3297 states and 4482 transitions. [2018-10-27 06:06:41,690 INFO L728 BuchiCegarLoop]: Abstraction has 3297 states and 4482 transitions. [2018-10-27 06:06:41,690 INFO L608 BuchiCegarLoop]: Abstraction has 3297 states and 4482 transitions. [2018-10-27 06:06:41,690 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-10-27 06:06:41,691 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3297 states and 4482 transitions. [2018-10-27 06:06:41,702 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3213 [2018-10-27 06:06:41,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:41,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:41,703 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:41,703 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:41,704 INFO L793 eck$LassoCheckResult]: Stem: 34279#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 34064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 34065#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 34132#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34272#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 34344#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 34346#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 34238#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 34239#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34269#L419 assume !(~M_E~0 == 0); 34374#L419-2 assume !(~T1_E~0 == 0); 34215#L424-1 assume !(~T2_E~0 == 0); 34216#L429-1 assume !(~T3_E~0 == 0); 34298#L434-1 assume !(~E_M~0 == 0); 34082#L439-1 assume !(~E_1~0 == 0); 34083#L444-1 assume !(~E_2~0 == 0); 34118#L449-1 assume !(~E_3~0 == 0); 34420#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34257#L198 assume !(~m_pc~0 == 1); 34258#L198-2 is_master_triggered_~__retres1~0 := 0; 34261#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34262#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 34109#L521 assume !(activate_threads_~tmp~1 != 0); 34110#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34115#L217 assume !(~t1_pc~0 == 1); 34122#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 34123#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34126#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 34127#L529 assume !(activate_threads_~tmp___0~0 != 0); 34392#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34323#L236 assume !(~t2_pc~0 == 1); 34319#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 34320#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34236#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 34237#L537 assume !(activate_threads_~tmp___1~0 != 0); 34399#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34337#L255 assume !(~t3_pc~0 == 1); 34338#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 34340#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34341#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 34263#L545 assume !(activate_threads_~tmp___2~0 != 0); 34264#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34275#L467 assume !(~M_E~0 == 1); 34322#L467-2 assume !(~T1_E~0 == 1); 34080#L472-1 assume !(~T2_E~0 == 1); 34081#L477-1 assume !(~T3_E~0 == 1); 34116#L482-1 assume !(~E_M~0 == 1); 34415#L487-1 assume !(~E_1~0 == 1); 34454#L492-1 assume !(~E_2~0 == 1); 34342#L497-1 assume !(~E_3~0 == 1); 34343#L502-1 assume { :end_inline_reset_delta_events } true; 34354#L668-3 assume true; 35979#L668-1 assume !false; 35793#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 35783#L394 [2018-10-27 06:06:41,712 INFO L795 eck$LassoCheckResult]: Loop: 35783#L394 assume true; 35781#L342-1 assume !false; 35779#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 35776#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 35774#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 35772#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 35770#L347 assume eval_~tmp~0 != 0; 35769#L347-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 35766#L355 assume !(eval_~tmp_ndt_1~0 != 0); 35767#L352 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 35929#L369 assume !(eval_~tmp_ndt_2~0 != 0); 35930#L366 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 35756#L383 assume !(eval_~tmp_ndt_3~0 != 0); 35757#L380 assume !(~t3_st~0 == 0); 35783#L394 [2018-10-27 06:06:41,712 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:41,712 INFO L82 PathProgramCache]: Analyzing trace with hash 1176639138, now seen corresponding path program 3 times [2018-10-27 06:06:41,712 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:41,712 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:41,713 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:41,713 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:41,713 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:41,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:41,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:41,736 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:41,736 INFO L82 PathProgramCache]: Analyzing trace with hash 156238987, now seen corresponding path program 1 times [2018-10-27 06:06:41,736 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:41,737 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:41,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:41,737 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:06:41,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:41,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:41,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:41,748 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:41,748 INFO L82 PathProgramCache]: Analyzing trace with hash 1242656108, now seen corresponding path program 1 times [2018-10-27 06:06:41,748 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:41,748 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:41,749 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:41,749 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:41,749 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:41,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-27 06:06:41,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-27 06:06:41,836 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-10-27 06:06:41,836 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-10-27 06:06:42,001 WARN L179 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 30 [2018-10-27 06:06:42,149 WARN L179 SmtUtils]: Spent 147.00 ms on a formula simplification that was a NOOP. DAG size: 30 [2018-10-27 06:06:42,163 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-10-27 06:06:42,163 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-10-27 06:06:42,163 INFO L87 Difference]: Start difference. First operand 3297 states and 4482 transitions. cyclomatic complexity: 1191 Second operand 3 states. [2018-10-27 06:06:42,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-10-27 06:06:42,536 INFO L93 Difference]: Finished difference Result 5559 states and 7492 transitions. [2018-10-27 06:06:42,537 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-10-27 06:06:42,538 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5559 states and 7492 transitions. [2018-10-27 06:06:42,555 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5447 [2018-10-27 06:06:42,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5559 states to 5559 states and 7492 transitions. [2018-10-27 06:06:42,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5559 [2018-10-27 06:06:42,582 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5559 [2018-10-27 06:06:42,582 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5559 states and 7492 transitions. [2018-10-27 06:06:42,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-10-27 06:06:42,589 INFO L705 BuchiCegarLoop]: Abstraction has 5559 states and 7492 transitions. [2018-10-27 06:06:42,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5559 states and 7492 transitions. [2018-10-27 06:06:42,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5559 to 5439. [2018-10-27 06:06:42,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5439 states. [2018-10-27 06:06:42,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5439 states to 5439 states and 7372 transitions. [2018-10-27 06:06:42,668 INFO L728 BuchiCegarLoop]: Abstraction has 5439 states and 7372 transitions. [2018-10-27 06:06:42,669 INFO L608 BuchiCegarLoop]: Abstraction has 5439 states and 7372 transitions. [2018-10-27 06:06:42,669 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-10-27 06:06:42,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5439 states and 7372 transitions. [2018-10-27 06:06:42,686 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5327 [2018-10-27 06:06:42,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-10-27 06:06:42,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-10-27 06:06:42,687 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:42,687 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-10-27 06:06:42,687 INFO L793 eck$LassoCheckResult]: Stem: 43137#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 42928#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 42929#L631 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 42992#L275 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43130#L282 assume ~m_i~0 == 1;~m_st~0 := 0; 43202#L282-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 43204#L287-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 43097#L292-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 43098#L297-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43128#L419 assume !(~M_E~0 == 0); 43232#L419-2 assume !(~T1_E~0 == 0); 43075#L424-1 assume !(~T2_E~0 == 0); 43076#L429-1 assume !(~T3_E~0 == 0); 43157#L434-1 assume !(~E_M~0 == 0); 42946#L439-1 assume !(~E_1~0 == 0); 42947#L444-1 assume !(~E_2~0 == 0); 42978#L449-1 assume !(~E_3~0 == 0); 43275#L454-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43116#L198 assume !(~m_pc~0 == 1); 43117#L198-2 is_master_triggered_~__retres1~0 := 0; 43120#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43121#L210 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 42969#L521 assume !(activate_threads_~tmp~1 != 0); 42970#L521-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42975#L217 assume !(~t1_pc~0 == 1); 42982#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 42983#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42986#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 42987#L529 assume !(activate_threads_~tmp___0~0 != 0); 43249#L529-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43182#L236 assume !(~t2_pc~0 == 1); 43179#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 43180#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43095#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 43096#L537 assume !(activate_threads_~tmp___1~0 != 0); 43259#L537-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43195#L255 assume !(~t3_pc~0 == 1); 43196#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 43198#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43199#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 43122#L545 assume !(activate_threads_~tmp___2~0 != 0); 43123#L545-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43133#L467 assume !(~M_E~0 == 1); 43181#L467-2 assume !(~T1_E~0 == 1); 42944#L472-1 assume !(~T2_E~0 == 1); 42945#L477-1 assume !(~T3_E~0 == 1); 42976#L482-1 assume !(~E_M~0 == 1); 43270#L487-1 assume !(~E_1~0 == 1); 43302#L492-1 assume !(~E_2~0 == 1); 43200#L497-1 assume !(~E_3~0 == 1); 43201#L502-1 assume { :end_inline_reset_delta_events } true; 43212#L668-3 assume true; 44818#L668-1 assume !false; 44816#L669 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 43880#L394 [2018-10-27 06:06:42,687 INFO L795 eck$LassoCheckResult]: Loop: 43880#L394 assume true; 44813#L342-1 assume !false; 44811#L343 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 44800#L310 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 44794#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44784#L333 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 44779#L347 assume eval_~tmp~0 != 0; 44770#L347-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 44762#L355 assume !(eval_~tmp_ndt_1~0 != 0); 43867#L352 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 43865#L369 assume !(eval_~tmp_ndt_2~0 != 0); 43863#L366 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 43860#L383 assume !(eval_~tmp_ndt_3~0 != 0); 43861#L380 assume ~t3_st~0 == 0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 43769#L397 assume !(eval_~tmp_ndt_4~0 != 0); 43880#L394 [2018-10-27 06:06:42,687 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:42,688 INFO L82 PathProgramCache]: Analyzing trace with hash 1176639138, now seen corresponding path program 4 times [2018-10-27 06:06:42,697 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:42,697 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:42,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:42,698 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:42,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:42,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:42,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:42,717 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:42,717 INFO L82 PathProgramCache]: Analyzing trace with hash 548438037, now seen corresponding path program 1 times [2018-10-27 06:06:42,717 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:42,717 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:42,718 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:42,718 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-10-27 06:06:42,718 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:42,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:42,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:42,727 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-27 06:06:42,727 INFO L82 PathProgramCache]: Analyzing trace with hash -132369580, now seen corresponding path program 1 times [2018-10-27 06:06:42,727 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-10-27 06:06:42,727 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-10-27 06:06:42,731 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:42,732 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-10-27 06:06:42,732 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-10-27 06:06:42,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:42,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-27 06:06:43,303 WARN L179 SmtUtils]: Spent 549.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 33 [2018-10-27 06:06:43,931 WARN L179 SmtUtils]: Spent 567.00 ms on a formula simplification. DAG size of input: 136 DAG size of output: 92 [2018-10-27 06:06:44,034 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 27.10 06:06:44 BoogieIcfgContainer [2018-10-27 06:06:44,034 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-10-27 06:06:44,034 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-10-27 06:06:44,034 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-10-27 06:06:44,034 INFO L276 PluginConnector]: Witness Printer initialized [2018-10-27 06:06:44,035 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.10 06:06:33" (3/4) ... [2018-10-27 06:06:44,042 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-10-27 06:06:44,107 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_2d459981-1862-47c2-8827-a7067cf7c9ff/bin-2019/uautomizer/witness.graphml [2018-10-27 06:06:44,107 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-10-27 06:06:44,110 INFO L168 Benchmark]: Toolchain (without parser) took 12785.94 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 197.1 MB). Free memory was 959.6 MB in the beginning and 1.2 GB in the end (delta: -191.8 MB). Peak memory consumption was 5.3 MB. Max. memory is 11.5 GB. [2018-10-27 06:06:44,111 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-27 06:06:44,111 INFO L168 Benchmark]: CACSL2BoogieTranslator took 314.54 ms. Allocated memory is still 1.0 GB. Free memory was 959.6 MB in the beginning and 943.4 MB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 11.5 GB. [2018-10-27 06:06:44,111 INFO L168 Benchmark]: Boogie Procedure Inliner took 60.29 ms. Allocated memory is still 1.0 GB. Free memory was 943.4 MB in the beginning and 938.0 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-10-27 06:06:44,112 INFO L168 Benchmark]: Boogie Preprocessor took 143.64 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.4 MB). Free memory was 938.0 MB in the beginning and 1.2 GB in the end (delta: -217.1 MB). Peak memory consumption was 17.7 MB. Max. memory is 11.5 GB. [2018-10-27 06:06:44,112 INFO L168 Benchmark]: RCFGBuilder took 1734.99 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 73.0 MB). Peak memory consumption was 73.0 MB. Max. memory is 11.5 GB. [2018-10-27 06:06:44,112 INFO L168 Benchmark]: BuchiAutomizer took 10452.57 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 37.7 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -75.3 MB). Peak memory consumption was 236.8 MB. Max. memory is 11.5 GB. [2018-10-27 06:06:44,113 INFO L168 Benchmark]: Witness Printer took 73.47 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 841.0 kB). Peak memory consumption was 841.0 kB. Max. memory is 11.5 GB. [2018-10-27 06:06:44,115 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 314.54 ms. Allocated memory is still 1.0 GB. Free memory was 959.6 MB in the beginning and 943.4 MB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 60.29 ms. Allocated memory is still 1.0 GB. Free memory was 943.4 MB in the beginning and 938.0 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 143.64 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.4 MB). Free memory was 938.0 MB in the beginning and 1.2 GB in the end (delta: -217.1 MB). Peak memory consumption was 17.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1734.99 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 73.0 MB). Peak memory consumption was 73.0 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 10452.57 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 37.7 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -75.3 MB). Peak memory consumption was 236.8 MB. Max. memory is 11.5 GB. * Witness Printer took 73.47 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 841.0 kB). Peak memory consumption was 841.0 kB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (15 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 5439 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 10.3s and 16 iterations. TraceHistogramMax:1. Analysis of lassos took 5.3s. Construction of modules took 2.9s. Büchi inclusion checks took 0.8s. Highest rank in rank-based complementation 0. Minimization of det autom 15. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 15 MinimizatonAttempts, 2058 StatesRemovedByMinimization, 8 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had 5439 states and ocurred in iteration 15. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 7127 SDtfs, 7225 SDslu, 5983 SDs, 0 SdLazy, 260 SolverSat, 132 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.9s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 342]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5ddc3f7d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@536932f7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3541530d=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@758da4f2=0, __retres1=0, kernel_st=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3e514eef=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6c8cf0d1=0, E_3=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, m_pc=0, \result=0, __retres1=0, \result=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2dced348=0, tmp___0=0, t1_pc=0, E_2=2, T1_E=2, __retres1=1, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@117ea7e2=0, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7f6e89e8=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6e0685c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1ba0c1e7=0, t1_st=0, local=0, t2_pc=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 342]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int t3_st ; [L22] int m_i ; [L23] int t1_i ; [L24] int t2_i ; [L25] int t3_i ; [L26] int M_E = 2; [L27] int T1_E = 2; [L28] int T2_E = 2; [L29] int T3_E = 2; [L30] int E_M = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; [L39] int token ; [L41] int local ; [L713] int __retres1 ; [L717] CALL init_model() [L626] m_i = 1 [L627] t1_i = 1 [L628] t2_i = 1 [L629] RET t3_i = 1 [L717] init_model() [L718] CALL start_simulation() [L654] int kernel_st ; [L655] int tmp ; [L656] int tmp___0 ; [L660] kernel_st = 0 [L661] FCALL update_channels() [L662] CALL init_threads() [L282] COND TRUE m_i == 1 [L283] m_st = 0 [L287] COND TRUE t1_i == 1 [L288] t1_st = 0 [L292] COND TRUE t2_i == 1 [L293] t2_st = 0 [L297] COND TRUE t3_i == 1 [L298] RET t3_st = 0 [L662] init_threads() [L663] CALL fire_delta_events() [L419] COND FALSE !(M_E == 0) [L424] COND FALSE !(T1_E == 0) [L429] COND FALSE !(T2_E == 0) [L434] COND FALSE !(T3_E == 0) [L439] COND FALSE !(E_M == 0) [L444] COND FALSE !(E_1 == 0) [L449] COND FALSE !(E_2 == 0) [L454] COND FALSE, RET !(E_3 == 0) [L663] fire_delta_events() [L664] CALL activate_threads() [L512] int tmp ; [L513] int tmp___0 ; [L514] int tmp___1 ; [L515] int tmp___2 ; [L519] CALL, EXPR is_master_triggered() [L195] int __retres1 ; [L198] COND FALSE !(m_pc == 1) [L208] __retres1 = 0 [L210] RET return (__retres1); [L519] EXPR is_master_triggered() [L519] tmp = is_master_triggered() [L521] COND FALSE !(\read(tmp)) [L527] CALL, EXPR is_transmit1_triggered() [L214] int __retres1 ; [L217] COND FALSE !(t1_pc == 1) [L227] __retres1 = 0 [L229] RET return (__retres1); [L527] EXPR is_transmit1_triggered() [L527] tmp___0 = is_transmit1_triggered() [L529] COND FALSE !(\read(tmp___0)) [L535] CALL, EXPR is_transmit2_triggered() [L233] int __retres1 ; [L236] COND FALSE !(t2_pc == 1) [L246] __retres1 = 0 [L248] RET return (__retres1); [L535] EXPR is_transmit2_triggered() [L535] tmp___1 = is_transmit2_triggered() [L537] COND FALSE !(\read(tmp___1)) [L543] CALL, EXPR is_transmit3_triggered() [L252] int __retres1 ; [L255] COND FALSE !(t3_pc == 1) [L265] __retres1 = 0 [L267] RET return (__retres1); [L543] EXPR is_transmit3_triggered() [L543] tmp___2 = is_transmit3_triggered() [L545] COND FALSE, RET !(\read(tmp___2)) [L664] activate_threads() [L665] CALL reset_delta_events() [L467] COND FALSE !(M_E == 1) [L472] COND FALSE !(T1_E == 1) [L477] COND FALSE !(T2_E == 1) [L482] COND FALSE !(T3_E == 1) [L487] COND FALSE !(E_M == 1) [L492] COND FALSE !(E_1 == 1) [L497] COND FALSE !(E_2 == 1) [L502] COND FALSE, RET !(E_3 == 1) [L665] reset_delta_events() [L668] COND TRUE 1 [L671] kernel_st = 1 [L672] CALL eval() [L338] int tmp ; Loop: [L342] COND TRUE 1 [L345] CALL, EXPR exists_runnable_thread() [L307] int __retres1 ; [L310] COND TRUE m_st == 0 [L311] __retres1 = 1 [L333] RET return (__retres1); [L345] EXPR exists_runnable_thread() [L345] tmp = exists_runnable_thread() [L347] COND TRUE \read(tmp) [L352] COND TRUE m_st == 0 [L353] int tmp_ndt_1; [L354] tmp_ndt_1 = __VERIFIER_nondet_int() [L355] COND FALSE !(\read(tmp_ndt_1)) [L366] COND TRUE t1_st == 0 [L367] int tmp_ndt_2; [L368] tmp_ndt_2 = __VERIFIER_nondet_int() [L369] COND FALSE !(\read(tmp_ndt_2)) [L380] COND TRUE t2_st == 0 [L381] int tmp_ndt_3; [L382] tmp_ndt_3 = __VERIFIER_nondet_int() [L383] COND FALSE !(\read(tmp_ndt_3)) [L394] COND TRUE t3_st == 0 [L395] int tmp_ndt_4; [L396] tmp_ndt_4 = __VERIFIER_nondet_int() [L397] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...